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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[mirror_ubuntu-artful-kernel.git] / drivers / pci / pci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * PCI Bus Services, see include/linux/pci.h for further explanation.
3 *
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
5 * David Mosberger-Tang
6 *
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
8 */
9
10#include <linux/kernel.h>
11#include <linux/delay.h>
12#include <linux/init.h>
13#include <linux/pci.h>
075c1771 14#include <linux/pm.h>
5a0e3ad6 15#include <linux/slab.h>
1da177e4
LT		 16#include <linux/module.h>
17#include <linux/spinlock.h>
4e57b681 18#include <linux/string.h>
229f5afd 19#include <linux/log2.h>
7d715a6c 20#include <linux/pci-aspm.h>
c300bd2f 21#include <linux/pm_wakeup.h>
8dd7f803 22#include <linux/interrupt.h>
32a9a682 23#include <linux/device.h>
b67ea761 24#include <linux/pm_runtime.h>
32a9a682 25#include <asm/setup.h>
bc56b9e0 26#include "pci.h"
1da177e4 27
00240c38
AS		 28const char *pci_power_names[] = {
29 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
30};
31EXPORT_SYMBOL_GPL(pci_power_names);
32
93177a74
RW		 33int isa_dma_bridge_buggy;
34EXPORT_SYMBOL(isa_dma_bridge_buggy);
35
36int pci_pci_problems;
37EXPORT_SYMBOL(pci_pci_problems);
38
1ae861e6
RW		 39unsigned int pci_pm_d3_delay;
40
41static void pci_dev_d3_sleep(struct pci_dev *dev)
42{
43 unsigned int delay = dev->d3_delay;
44
45 if (delay < pci_pm_d3_delay)
46 delay = pci_pm_d3_delay;
47
48 msleep(delay);
49}
1da177e4 50
32a2eea7
JG		 51#ifdef CONFIG_PCI_DOMAINS
52int pci_domains_supported = 1;
53#endif
54
4516a618
AN		 55#define DEFAULT_CARDBUS_IO_SIZE (256)
56#define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
57/* pci=cbmemsize=nnM,cbiosize=nn can override this */
58unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
59unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
60
28760489
EB		 61#define DEFAULT_HOTPLUG_IO_SIZE (256)
62#define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
63/* pci=hpmemsize=nnM,hpiosize=nn can override this */
64unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
65unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
66
ac1aa47b
JB		 67/*
68 * The default CLS is used if arch didn't set CLS explicitly and not
69 * all pci devices agree on the same value. Arch can override either
70 * the dfl or actual value as it sees fit. Don't forget this is
71 * measured in 32-bit words, not bytes.
72 */
98e724c7 73u8 pci_dfl_cache_line_size __devinitdata = L1_CACHE_BYTES >> 2;
ac1aa47b
JB		 74u8 pci_cache_line_size;
75
1da177e4
LT		 76/**
77 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
78 * @bus: pointer to PCI bus structure to search
79 *
80 * Given a PCI bus, returns the highest PCI bus number present in the set
81 * including the given PCI bus and its list of child PCI buses.
82 */
96bde06a 83unsigned char pci_bus_max_busnr(struct pci_bus* bus)
1da177e4
LT		 84{
85 struct list_head *tmp;
86 unsigned char max, n;
87
b82db5ce 88 max = bus->subordinate;
1da177e4
LT		 89 list_for_each(tmp, &bus->children) {
90 n = pci_bus_max_busnr(pci_bus_b(tmp));
91 if(n > max)
92 max = n;
93 }
94 return max;
95}
b82db5ce 96EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
1da177e4 97
1684f5dd
AM		 98#ifdef CONFIG_HAS_IOMEM
99void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
100{
101 /*
102 * Make sure the BAR is actually a memory resource, not an IO resource
103 */
104 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
105 WARN_ON(1);
106 return NULL;
107 }
108 return ioremap_nocache(pci_resource_start(pdev, bar),
109 pci_resource_len(pdev, bar));
110}
111EXPORT_SYMBOL_GPL(pci_ioremap_bar);
112#endif
113
b82db5ce 114#if 0
1da177e4
LT		 115/**
116 * pci_max_busnr - returns maximum PCI bus number
117 *
118 * Returns the highest PCI bus number present in the system global list of
119 * PCI buses.
120 */
121unsigned char __devinit
122pci_max_busnr(void)
123{
124 struct pci_bus *bus = NULL;
125 unsigned char max, n;
126
127 max = 0;
128 while ((bus = pci_find_next_bus(bus)) != NULL) {
129 n = pci_bus_max_busnr(bus);
130 if(n > max)
131 max = n;
132 }
133 return max;
134}
135
54c762fe
AB		 136#endif /* 0 */
137
687d5fe3
ME		 138#define PCI_FIND_CAP_TTL 48
139
140static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
141 u8 pos, int cap, int *ttl)
24a4e377
RD		 142{
143 u8 id;
24a4e377 144
687d5fe3 145 while ((*ttl)--) {
24a4e377
RD		 146 pci_bus_read_config_byte(bus, devfn, pos, &pos);
147 if (pos < 0x40)
148 break;
149 pos &= ~3;
150 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
151 &id);
152 if (id == 0xff)
153 break;
154 if (id == cap)
155 return pos;
156 pos += PCI_CAP_LIST_NEXT;
157 }
158 return 0;
159}
160
687d5fe3
ME		 161static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
162 u8 pos, int cap)
163{
164 int ttl = PCI_FIND_CAP_TTL;
165
166 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
167}
168
24a4e377
RD		 169int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
170{
171 return __pci_find_next_cap(dev->bus, dev->devfn,
172 pos + PCI_CAP_LIST_NEXT, cap);
173}
174EXPORT_SYMBOL_GPL(pci_find_next_capability);
175
d3bac118
ME		 176static int __pci_bus_find_cap_start(struct pci_bus *bus,
177 unsigned int devfn, u8 hdr_type)
1da177e4
LT		 178{
179 u16 status;
1da177e4
LT		 180
181 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
182 if (!(status & PCI_STATUS_CAP_LIST))
183 return 0;
184
185 switch (hdr_type) {
186 case PCI_HEADER_TYPE_NORMAL:
187 case PCI_HEADER_TYPE_BRIDGE:
d3bac118 188 return PCI_CAPABILITY_LIST;
1da177e4 189 case PCI_HEADER_TYPE_CARDBUS:
d3bac118 190 return PCI_CB_CAPABILITY_LIST;
1da177e4
LT		 191 default:
192 return 0;
193 }
d3bac118
ME		 194
195 return 0;
1da177e4
LT		 196}
197
198/**
199 * pci_find_capability - query for devices' capabilities
200 * @dev: PCI device to query
201 * @cap: capability code
202 *
203 * Tell if a device supports a given PCI capability.
204 * Returns the address of the requested capability structure within the
205 * device's PCI configuration space or 0 in case the device does not
206 * support it. Possible values for @cap:
207 *
208 * %PCI_CAP_ID_PM Power Management
209 * %PCI_CAP_ID_AGP Accelerated Graphics Port
210 * %PCI_CAP_ID_VPD Vital Product Data
211 * %PCI_CAP_ID_SLOTID Slot Identification
212 * %PCI_CAP_ID_MSI Message Signalled Interrupts
213 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
214 * %PCI_CAP_ID_PCIX PCI-X
215 * %PCI_CAP_ID_EXP PCI Express
216 */
217int pci_find_capability(struct pci_dev *dev, int cap)
218{
d3bac118
ME		 219 int pos;
220
221 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
222 if (pos)
223 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
224
225 return pos;
1da177e4
LT		 226}
227
228/**
229 * pci_bus_find_capability - query for devices' capabilities
230 * @bus: the PCI bus to query
231 * @devfn: PCI device to query
232 * @cap: capability code
233 *
234 * Like pci_find_capability() but works for pci devices that do not have a
235 * pci_dev structure set up yet.
236 *
237 * Returns the address of the requested capability structure within the
238 * device's PCI configuration space or 0 in case the device does not
239 * support it.
240 */
241int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
242{
d3bac118 243 int pos;
1da177e4
LT		 244 u8 hdr_type;
245
246 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
247
d3bac118
ME		 248 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
249 if (pos)
250 pos = __pci_find_next_cap(bus, devfn, pos, cap);
251
252 return pos;
1da177e4
LT		 253}
254
255/**
256 * pci_find_ext_capability - Find an extended capability
257 * @dev: PCI device to query
258 * @cap: capability code
259 *
260 * Returns the address of the requested extended capability structure
261 * within the device's PCI configuration space or 0 if the device does
262 * not support it. Possible values for @cap:
263 *
264 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
265 * %PCI_EXT_CAP_ID_VC Virtual Channel
266 * %PCI_EXT_CAP_ID_DSN Device Serial Number
267 * %PCI_EXT_CAP_ID_PWR Power Budgeting
268 */
269int pci_find_ext_capability(struct pci_dev *dev, int cap)
270{
271 u32 header;
557848c3
ZY		 272 int ttl;
273 int pos = PCI_CFG_SPACE_SIZE;
1da177e4 274
557848c3
ZY		 275 /* minimum 8 bytes per capability */
276 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
277
278 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
1da177e4
LT		 279 return 0;
280
281 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
282 return 0;
283
284 /*
285 * If we have no capabilities, this is indicated by cap ID,
286 * cap version and next pointer all being 0.
287 */
288 if (header == 0)
289 return 0;
290
291 while (ttl-- > 0) {
292 if (PCI_EXT_CAP_ID(header) == cap)
293 return pos;
294
295 pos = PCI_EXT_CAP_NEXT(header);
557848c3 296 if (pos < PCI_CFG_SPACE_SIZE)
1da177e4
LT		 297 break;
298
299 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
300 break;
301 }
302
303 return 0;
304}
3a720d72 305EXPORT_SYMBOL_GPL(pci_find_ext_capability);
1da177e4 306
cf4c43dd
JB		 307/**
308 * pci_bus_find_ext_capability - find an extended capability
309 * @bus: the PCI bus to query
310 * @devfn: PCI device to query
311 * @cap: capability code
312 *
313 * Like pci_find_ext_capability() but works for pci devices that do not have a
314 * pci_dev structure set up yet.
315 *
316 * Returns the address of the requested capability structure within the
317 * device's PCI configuration space or 0 in case the device does not
318 * support it.
319 */
320int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
321 int cap)
322{
323 u32 header;
324 int ttl;
325 int pos = PCI_CFG_SPACE_SIZE;
326
327 /* minimum 8 bytes per capability */
328 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
329
330 if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
331 return 0;
332 if (header == 0xffffffff || header == 0)
333 return 0;
334
335 while (ttl-- > 0) {
336 if (PCI_EXT_CAP_ID(header) == cap)
337 return pos;
338
339 pos = PCI_EXT_CAP_NEXT(header);
340 if (pos < PCI_CFG_SPACE_SIZE)
341 break;
342
343 if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
344 break;
345 }
346
347 return 0;
348}
349
687d5fe3
ME		 350static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
351{
352 int rc, ttl = PCI_FIND_CAP_TTL;
353 u8 cap, mask;
354
355 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
356 mask = HT_3BIT_CAP_MASK;
357 else
358 mask = HT_5BIT_CAP_MASK;
359
360 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
361 PCI_CAP_ID_HT, &ttl);
362 while (pos) {
363 rc = pci_read_config_byte(dev, pos + 3, &cap);
364 if (rc != PCIBIOS_SUCCESSFUL)
365 return 0;
366
367 if ((cap & mask) == ht_cap)
368 return pos;
369
47a4d5be
BG		 370 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
371 pos + PCI_CAP_LIST_NEXT,
687d5fe3
ME		 372 PCI_CAP_ID_HT, &ttl);
373 }
374
375 return 0;
376}
377/**
378 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
379 * @dev: PCI device to query
380 * @pos: Position from which to continue searching
381 * @ht_cap: Hypertransport capability code
382 *
383 * To be used in conjunction with pci_find_ht_capability() to search for
384 * all capabilities matching @ht_cap. @pos should always be a value returned
385 * from pci_find_ht_capability().
386 *
387 * NB. To be 100% safe against broken PCI devices, the caller should take
388 * steps to avoid an infinite loop.
389 */
390int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
391{
392 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
393}
394EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
395
396/**
397 * pci_find_ht_capability - query a device's Hypertransport capabilities
398 * @dev: PCI device to query
399 * @ht_cap: Hypertransport capability code
400 *
401 * Tell if a device supports a given Hypertransport capability.
402 * Returns an address within the device's PCI configuration space
403 * or 0 in case the device does not support the request capability.
404 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
405 * which has a Hypertransport capability matching @ht_cap.
406 */
407int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
408{
409 int pos;
410
411 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
412 if (pos)
413 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
414
415 return pos;
416}
417EXPORT_SYMBOL_GPL(pci_find_ht_capability);
418
1da177e4
LT		 419/**
420 * pci_find_parent_resource - return resource region of parent bus of given region
421 * @dev: PCI device structure contains resources to be searched
422 * @res: child resource record for which parent is sought
423 *
424 * For given resource region of given device, return the resource
425 * region of parent bus the given region is contained in or where
426 * it should be allocated from.
427 */
428struct resource *
429pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
430{
431 const struct pci_bus *bus = dev->bus;
432 int i;
89a74ecc 433 struct resource *best = NULL, *r;
1da177e4 434
89a74ecc 435 pci_bus_for_each_resource(bus, r, i) {
1da177e4
LT		 436 if (!r)
437 continue;
438 if (res->start && !(res->start >= r->start && res->end <= r->end))
439 continue; /* Not contained */
440 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
441 continue; /* Wrong type */
442 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
443 return r; /* Exact match */
8c8def26
LT		 444 /* We can't insert a non-prefetch resource inside a prefetchable parent .. */
445 if (r->flags & IORESOURCE_PREFETCH)
446 continue;
447 /* .. but we can put a prefetchable resource inside a non-prefetchable one */
448 if (!best)
449 best = r;
1da177e4
LT		 450 }
451 return best;
452}
453
064b53db
JL		 454/**
455 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
456 * @dev: PCI device to have its BARs restored
457 *
458 * Restore the BAR values for a given device, so as to make it
459 * accessible by its driver.
460 */
ad668599 461static void
064b53db
JL		 462pci_restore_bars(struct pci_dev *dev)
463{
bc5f5a82 464 int i;
064b53db 465
bc5f5a82 466 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
14add80b 467 pci_update_resource(dev, i);
064b53db
JL		 468}
469
961d9120
RW		 470static struct pci_platform_pm_ops *pci_platform_pm;
471
472int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
473{
eb9d0fe4
RW		 474 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
475 || !ops->sleep_wake || !ops->can_wakeup)
961d9120
RW		 476 return -EINVAL;
477 pci_platform_pm = ops;
478 return 0;
479}
480
481static inline bool platform_pci_power_manageable(struct pci_dev *dev)
482{
483 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
484}
485
486static inline int platform_pci_set_power_state(struct pci_dev *dev,
487 pci_power_t t)
488{
489 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
490}
491
492static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
493{
494 return pci_platform_pm ?
495 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
496}
8f7020d3 497
eb9d0fe4
RW		 498static inline bool platform_pci_can_wakeup(struct pci_dev *dev)
499{
500 return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false;
501}
502
503static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
504{
505 return pci_platform_pm ?
506 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
507}
508
b67ea761
RW		 509static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
510{
511 return pci_platform_pm ?
512 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
513}
514
1da177e4 515/**
44e4e66e
RW		 516 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
517 * given PCI device
518 * @dev: PCI device to handle.
44e4e66e 519 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
1da177e4 520 *
44e4e66e
RW		 521 * RETURN VALUE:
522 * -EINVAL if the requested state is invalid.
523 * -EIO if device does not support PCI PM or its PM capabilities register has a
524 * wrong version, or device doesn't support the requested state.
525 * 0 if device already is in the requested state.
526 * 0 if device's power state has been successfully changed.
1da177e4 527 */
f00a20ef 528static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
1da177e4 529{
337001b6 530 u16 pmcsr;
44e4e66e 531 bool need_restore = false;
1da177e4 532
4a865905
RW		 533 /* Check if we're already there */
534 if (dev->current_state == state)
535 return 0;
536
337001b6 537 if (!dev->pm_cap)
cca03dec
AL		 538 return -EIO;
539
44e4e66e
RW		 540 if (state < PCI_D0 || state > PCI_D3hot)
541 return -EINVAL;
542
1da177e4
LT		 543 /* Validate current state:
544 * Can enter D0 from any state, but if we can only go deeper
545 * to sleep if we're already in a low power state
546 */
4a865905 547 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
44e4e66e 548 && dev->current_state > state) {
80ccba11
BH		 549 dev_err(&dev->dev, "invalid power transition "
550 "(from state %d to %d)\n", dev->current_state, state);
1da177e4 551 return -EINVAL;
44e4e66e 552 }
1da177e4 553
1da177e4 554 /* check if this device supports the desired state */
337001b6
RW		 555 if ((state == PCI_D1 && !dev->d1_support)
556 || (state == PCI_D2 && !dev->d2_support))
3fe9d19f 557 return -EIO;
1da177e4 558
337001b6 559 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
064b53db 560
32a36585 561 /* If we're (effectively) in D3, force entire word to 0.
1da177e4
LT		 562 * This doesn't affect PME_Status, disables PME_En, and
563 * sets PowerState to 0.
564 */
32a36585 565 switch (dev->current_state) {
d3535fbb
JL		 566 case PCI_D0:
567 case PCI_D1:
568 case PCI_D2:
569 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
570 pmcsr |= state;
571 break;
f62795f1
RW		 572 case PCI_D3hot:
573 case PCI_D3cold:
32a36585
JL		 574 case PCI_UNKNOWN: /* Boot-up */
575 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
f00a20ef 576 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
44e4e66e 577 need_restore = true;
32a36585 578 /* Fall-through: force to D0 */
32a36585 579 default:
d3535fbb 580 pmcsr = 0;
32a36585 581 break;
1da177e4
LT		 582 }
583
584 /* enter specified state */
337001b6 585 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1da177e4
LT		 586
587 /* Mandatory power management transition delays */
588 /* see PCI PM 1.1 5.6.1 table 18 */
589 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
1ae861e6 590 pci_dev_d3_sleep(dev);
1da177e4 591 else if (state == PCI_D2 || dev->current_state == PCI_D2)
aa8c6c93 592 udelay(PCI_PM_D2_DELAY);
1da177e4 593
e13cdbd7
RW		 594 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
595 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
596 if (dev->current_state != state && printk_ratelimit())
597 dev_info(&dev->dev, "Refused to change power state, "
598 "currently in D%d\n", dev->current_state);
064b53db
JL		 599
600 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
601 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
602 * from D3hot to D0 _may_ perform an internal reset, thereby
603 * going to "D0 Uninitialized" rather than "D0 Initialized".
604 * For example, at least some versions of the 3c905B and the
605 * 3c556B exhibit this behaviour.
606 *
607 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
608 * devices in a D3hot state at boot. Consequently, we need to
609 * restore at least the BARs so that the device will be
610 * accessible to its driver.
611 */
612 if (need_restore)
613 pci_restore_bars(dev);
614
f00a20ef 615 if (dev->bus->self)
7d715a6c
SL		 616 pcie_aspm_pm_state_change(dev->bus->self);
617
1da177e4
LT		 618 return 0;
619}
620
44e4e66e
RW		 621/**
622 * pci_update_current_state - Read PCI power state of given device from its
623 * PCI PM registers and cache it
624 * @dev: PCI device to handle.
f06fc0b6 625 * @state: State to cache in case the device doesn't have the PM capability
44e4e66e 626 */
73410429 627void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
44e4e66e 628{
337001b6 629 if (dev->pm_cap) {
44e4e66e
RW		 630 u16 pmcsr;
631
337001b6 632 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
44e4e66e 633 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
f06fc0b6
RW		 634 } else {
635 dev->current_state = state;
44e4e66e
RW		 636 }
637}
638
0e5dd46b
RW		 639/**
640 * pci_platform_power_transition - Use platform to change device power state
641 * @dev: PCI device to handle.
642 * @state: State to put the device into.
643 */
644static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
645{
646 int error;
647
648 if (platform_pci_power_manageable(dev)) {
649 error = platform_pci_set_power_state(dev, state);
650 if (!error)
651 pci_update_current_state(dev, state);
652 } else {
653 error = -ENODEV;
654 /* Fall back to PCI_D0 if native PM is not supported */
b3bad72e
RW		 655 if (!dev->pm_cap)
656 dev->current_state = PCI_D0;
0e5dd46b
RW		 657 }
658
659 return error;
660}
661
662/**
663 * __pci_start_power_transition - Start power transition of a PCI device
664 * @dev: PCI device to handle.
665 * @state: State to put the device into.
666 */
667static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
668{
669 if (state == PCI_D0)
670 pci_platform_power_transition(dev, PCI_D0);
671}
672
673/**
674 * __pci_complete_power_transition - Complete power transition of a PCI device
675 * @dev: PCI device to handle.
676 * @state: State to put the device into.
677 *
678 * This function should not be called directly by device drivers.
679 */
680int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
681{
682 return state > PCI_D0 ?
683 pci_platform_power_transition(dev, state) : -EINVAL;
684}
685EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
686
44e4e66e
RW		 687/**
688 * pci_set_power_state - Set the power state of a PCI device
689 * @dev: PCI device to handle.
690 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
691 *
877d0310 692 * Transition a device to a new power state, using the platform firmware and/or
44e4e66e
RW		 693 * the device's PCI PM registers.
694 *
695 * RETURN VALUE:
696 * -EINVAL if the requested state is invalid.
697 * -EIO if device does not support PCI PM or its PM capabilities register has a
698 * wrong version, or device doesn't support the requested state.
699 * 0 if device already is in the requested state.
700 * 0 if device's power state has been successfully changed.
701 */
702int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
703{
337001b6 704 int error;
44e4e66e
RW		 705
706 /* bound the state we're entering */
707 if (state > PCI_D3hot)
708 state = PCI_D3hot;
709 else if (state < PCI_D0)
710 state = PCI_D0;
711 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
712 /*
713 * If the device or the parent bridge do not support PCI PM,
714 * ignore the request if we're doing anything other than putting
715 * it into D0 (which would only happen on boot).
716 */
717 return 0;
718
4a865905
RW		 719 /* Check if we're already there */
720 if (dev->current_state == state)
721 return 0;
722
0e5dd46b
RW		 723 __pci_start_power_transition(dev, state);
724
979b1791
AC		 725 /* This device is quirked not to be put into D3, so
726 don't put it in D3 */
727 if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
728 return 0;
44e4e66e 729
f00a20ef 730 error = pci_raw_set_power_state(dev, state);
44e4e66e 731
0e5dd46b
RW		 732 if (!__pci_complete_power_transition(dev, state))
733 error = 0;
44e4e66e
RW		 734
735 return error;
736}
737
1da177e4
LT		 738/**
739 * pci_choose_state - Choose the power state of a PCI device
740 * @dev: PCI device to be suspended
741 * @state: target sleep state for the whole system. This is the value
742 * that is passed to suspend() function.
743 *
744 * Returns PCI power state suitable for given device and given system
745 * message.
746 */
747
748pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
749{
ab826ca4 750 pci_power_t ret;
0f64474b 751
1da177e4
LT		 752 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
753 return PCI_D0;
754
961d9120
RW		 755 ret = platform_pci_choose_state(dev);
756 if (ret != PCI_POWER_ERROR)
757 return ret;
ca078bae
PM		 758
759 switch (state.event) {
760 case PM_EVENT_ON:
761 return PCI_D0;
762 case PM_EVENT_FREEZE:
b887d2e6
DB		 763 case PM_EVENT_PRETHAW:
764 /* REVISIT both freeze and pre-thaw "should" use D0 */
ca078bae 765 case PM_EVENT_SUSPEND:
3a2d5b70 766 case PM_EVENT_HIBERNATE:
ca078bae 767 return PCI_D3hot;
1da177e4 768 default:
80ccba11
BH		 769 dev_info(&dev->dev, "unrecognized suspend event %d\n",
770 state.event);
1da177e4
LT		 771 BUG();
772 }
773 return PCI_D0;
774}
775
776EXPORT_SYMBOL(pci_choose_state);
777
89858517
YZ		 778#define PCI_EXP_SAVE_REGS 7
779
1b6b8ce2
YZ		 780#define pcie_cap_has_devctl(type, flags) 1
781#define pcie_cap_has_lnkctl(type, flags) \
782 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
783 (type == PCI_EXP_TYPE_ROOT_PORT || \
784 type == PCI_EXP_TYPE_ENDPOINT || \
785 type == PCI_EXP_TYPE_LEG_END))
786#define pcie_cap_has_sltctl(type, flags) \
787 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
788 ((type == PCI_EXP_TYPE_ROOT_PORT) || \
789 (type == PCI_EXP_TYPE_DOWNSTREAM && \
790 (flags & PCI_EXP_FLAGS_SLOT))))
791#define pcie_cap_has_rtctl(type, flags) \
792 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
793 (type == PCI_EXP_TYPE_ROOT_PORT || \
794 type == PCI_EXP_TYPE_RC_EC))
795#define pcie_cap_has_devctl2(type, flags) \
796 ((flags & PCI_EXP_FLAGS_VERS) > 1)
797#define pcie_cap_has_lnkctl2(type, flags) \
798 ((flags & PCI_EXP_FLAGS_VERS) > 1)
799#define pcie_cap_has_sltctl2(type, flags) \
800 ((flags & PCI_EXP_FLAGS_VERS) > 1)
801
b56a5a23
MT		 802static int pci_save_pcie_state(struct pci_dev *dev)
803{
804 int pos, i = 0;
805 struct pci_cap_saved_state *save_state;
806 u16 *cap;
1b6b8ce2 807 u16 flags;
b56a5a23 808
06a1cbaf
KK		 809 pos = pci_pcie_cap(dev);
810 if (!pos)
b56a5a23
MT		 811 return 0;
812
9f35575d 813 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
b56a5a23 814 if (!save_state) {
e496b617 815 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
b56a5a23
MT		 816 return -ENOMEM;
817 }
818 cap = (u16 *)&save_state->data[0];
819
1b6b8ce2
YZ		 820 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
821
822 if (pcie_cap_has_devctl(dev->pcie_type, flags))
823 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
824 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
825 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
826 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
827 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
828 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
829 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
830 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
831 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
832 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
833 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
834 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
835 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);
63f4898a 836
b56a5a23
MT		 837 return 0;
838}
839
840static void pci_restore_pcie_state(struct pci_dev *dev)
841{
842 int i = 0, pos;
843 struct pci_cap_saved_state *save_state;
844 u16 *cap;
1b6b8ce2 845 u16 flags;
b56a5a23
MT		 846
847 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
848 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
849 if (!save_state || pos <= 0)
850 return;
851 cap = (u16 *)&save_state->data[0];
852
1b6b8ce2
YZ		 853 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
854
855 if (pcie_cap_has_devctl(dev->pcie_type, flags))
856 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
857 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
858 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
859 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
860 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
861 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
862 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
863 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
864 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]);
865 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
866 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]);
867 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
868 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]);
b56a5a23
MT		 869}
870
cc692a5f
SH		 871
872static int pci_save_pcix_state(struct pci_dev *dev)
873{
63f4898a 874 int pos;
cc692a5f 875 struct pci_cap_saved_state *save_state;
cc692a5f
SH		 876
877 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
878 if (pos <= 0)
879 return 0;
880
f34303de 881 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
cc692a5f 882 if (!save_state) {
e496b617 883 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
cc692a5f
SH		 884 return -ENOMEM;
885 }
cc692a5f 886
63f4898a
RW		 887 pci_read_config_word(dev, pos + PCI_X_CMD, (u16 *)save_state->data);
888
cc692a5f
SH		 889 return 0;
890}
891
892static void pci_restore_pcix_state(struct pci_dev *dev)
893{
894 int i = 0, pos;
895 struct pci_cap_saved_state *save_state;
896 u16 *cap;
897
898 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
899 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
900 if (!save_state || pos <= 0)
901 return;
902 cap = (u16 *)&save_state->data[0];
903
904 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
cc692a5f
SH		 905}
906
907
1da177e4
LT		 908/**
909 * pci_save_state - save the PCI configuration space of a device before suspending
910 * @dev: - PCI device that we're dealing with
1da177e4
LT		 911 */
912int
913pci_save_state(struct pci_dev *dev)
914{
915 int i;
916 /* XXX: 100% dword access ok here? */
917 for (i = 0; i < 16; i++)
9e0b5b2c 918 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
aa8c6c93 919 dev->state_saved = true;
b56a5a23
MT		 920 if ((i = pci_save_pcie_state(dev)) != 0)
921 return i;
cc692a5f
SH		 922 if ((i = pci_save_pcix_state(dev)) != 0)
923 return i;
1da177e4
LT		 924 return 0;
925}
926
927/**
928 * pci_restore_state - Restore the saved state of a PCI device
929 * @dev: - PCI device that we're dealing with
1da177e4
LT		 930 */
931int
932pci_restore_state(struct pci_dev *dev)
933{
934 int i;
b4482a4b 935 u32 val;
1da177e4 936
c82f63e4
AD		 937 if (!dev->state_saved)
938 return 0;
4b77b0a2 939
b56a5a23
MT		 940 /* PCI Express register must be restored first */
941 pci_restore_pcie_state(dev);
942
8b8c8d28
YL		 943 /*
944 * The Base Address register should be programmed before the command
945 * register(s)
946 */
947 for (i = 15; i >= 0; i--) {
04d9c1a1
DJ		 948 pci_read_config_dword(dev, i * 4, &val);
949 if (val != dev->saved_config_space[i]) {
80ccba11
BH		 950 dev_printk(KERN_DEBUG, &dev->dev, "restoring config "
951 "space at offset %#x (was %#x, writing %#x)\n",
952 i, val, (int)dev->saved_config_space[i]);
04d9c1a1
DJ		 953 pci_write_config_dword(dev,i * 4,
954 dev->saved_config_space[i]);
955 }
956 }
cc692a5f 957 pci_restore_pcix_state(dev);
41017f0c 958 pci_restore_msi_state(dev);
8c5cdb6a 959 pci_restore_iov_state(dev);
8fed4b65 960
4b77b0a2
RW		 961 dev->state_saved = false;
962
1da177e4
LT		 963 return 0;
964}
965
38cc1302
HS		 966static int do_pci_enable_device(struct pci_dev *dev, int bars)
967{
968 int err;
969
970 err = pci_set_power_state(dev, PCI_D0);
971 if (err < 0 && err != -EIO)
972 return err;
973 err = pcibios_enable_device(dev, bars);
974 if (err < 0)
975 return err;
976 pci_fixup_device(pci_fixup_enable, dev);
977
978 return 0;
979}
980
981/**
0b62e13b 982 * pci_reenable_device - Resume abandoned device
38cc1302
HS		 983 * @dev: PCI device to be resumed
984 *
985 * Note this function is a backend of pci_default_resume and is not supposed
986 * to be called by normal code, write proper resume handler and use it instead.
987 */
0b62e13b 988int pci_reenable_device(struct pci_dev *dev)
38cc1302 989{
296ccb08 990 if (pci_is_enabled(dev))
38cc1302
HS		 991 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
992 return 0;
993}
994
b718989d
BH		 995static int __pci_enable_device_flags(struct pci_dev *dev,
996 resource_size_t flags)
1da177e4
LT		 997{
998 int err;
b718989d 999 int i, bars = 0;
1da177e4 1000
9fb625c3
HS		 1001 if (atomic_add_return(1, &dev->enable_cnt) > 1)
1002 return 0; /* already enabled */
1003
b718989d
BH		 1004 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1005 if (dev->resource[i].flags & flags)
1006 bars |= (1 << i);
1007
38cc1302 1008 err = do_pci_enable_device(dev, bars);
95a62965 1009 if (err < 0)
38cc1302 1010 atomic_dec(&dev->enable_cnt);
9fb625c3 1011 return err;
1da177e4
LT		 1012}
1013
b718989d
BH		 1014/**
1015 * pci_enable_device_io - Initialize a device for use with IO space
1016 * @dev: PCI device to be initialized
1017 *
1018 * Initialize device before it's used by a driver. Ask low-level code
1019 * to enable I/O resources. Wake up the device if it was suspended.
1020 * Beware, this function can fail.
1021 */
1022int pci_enable_device_io(struct pci_dev *dev)
1023{
1024 return __pci_enable_device_flags(dev, IORESOURCE_IO);
1025}
1026
1027/**
1028 * pci_enable_device_mem - Initialize a device for use with Memory space
1029 * @dev: PCI device to be initialized
1030 *
1031 * Initialize device before it's used by a driver. Ask low-level code
1032 * to enable Memory resources. Wake up the device if it was suspended.
1033 * Beware, this function can fail.
1034 */
1035int pci_enable_device_mem(struct pci_dev *dev)
1036{
1037 return __pci_enable_device_flags(dev, IORESOURCE_MEM);
1038}
1039
bae94d02
IPG		 1040/**
1041 * pci_enable_device - Initialize device before it's used by a driver.
1042 * @dev: PCI device to be initialized
1043 *
1044 * Initialize device before it's used by a driver. Ask low-level code
1045 * to enable I/O and memory. Wake up the device if it was suspended.
1046 * Beware, this function can fail.
1047 *
1048 * Note we don't actually enable the device many times if we call
1049 * this function repeatedly (we just increment the count).
1050 */
1051int pci_enable_device(struct pci_dev *dev)
1052{
b718989d 1053 return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
bae94d02
IPG		 1054}
1055
9ac7849e
TH		 1056/*
1057 * Managed PCI resources. This manages device on/off, intx/msi/msix
1058 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1059 * there's no need to track it separately. pci_devres is initialized
1060 * when a device is enabled using managed PCI device enable interface.
1061 */
1062struct pci_devres {
7f375f32
TH		 1063 unsigned int enabled:1;
1064 unsigned int pinned:1;
9ac7849e
TH		 1065 unsigned int orig_intx:1;
1066 unsigned int restore_intx:1;
1067 u32 region_mask;
1068};
1069
1070static void pcim_release(struct device *gendev, void *res)
1071{
1072 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
1073 struct pci_devres *this = res;
1074 int i;
1075
1076 if (dev->msi_enabled)
1077 pci_disable_msi(dev);
1078 if (dev->msix_enabled)
1079 pci_disable_msix(dev);
1080
1081 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1082 if (this->region_mask & (1 << i))
1083 pci_release_region(dev, i);
1084
1085 if (this->restore_intx)
1086 pci_intx(dev, this->orig_intx);
1087
7f375f32 1088 if (this->enabled && !this->pinned)
9ac7849e
TH		 1089 pci_disable_device(dev);
1090}
1091
1092static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
1093{
1094 struct pci_devres *dr, *new_dr;
1095
1096 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1097 if (dr)
1098 return dr;
1099
1100 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1101 if (!new_dr)
1102 return NULL;
1103 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1104}
1105
1106static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
1107{
1108 if (pci_is_managed(pdev))
1109 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1110 return NULL;
1111}
1112
1113/**
1114 * pcim_enable_device - Managed pci_enable_device()
1115 * @pdev: PCI device to be initialized
1116 *
1117 * Managed pci_enable_device().
1118 */
1119int pcim_enable_device(struct pci_dev *pdev)
1120{
1121 struct pci_devres *dr;
1122 int rc;
1123
1124 dr = get_pci_dr(pdev);
1125 if (unlikely(!dr))
1126 return -ENOMEM;
b95d58ea
TH		 1127 if (dr->enabled)
1128 return 0;
9ac7849e
TH		 1129
1130 rc = pci_enable_device(pdev);
1131 if (!rc) {
1132 pdev->is_managed = 1;
7f375f32 1133 dr->enabled = 1;
9ac7849e
TH		 1134 }
1135 return rc;
1136}
1137
1138/**
1139 * pcim_pin_device - Pin managed PCI device
1140 * @pdev: PCI device to pin
1141 *
1142 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1143 * driver detach. @pdev must have been enabled with
1144 * pcim_enable_device().
1145 */
1146void pcim_pin_device(struct pci_dev *pdev)
1147{
1148 struct pci_devres *dr;
1149
1150 dr = find_pci_dr(pdev);
7f375f32 1151 WARN_ON(!dr || !dr->enabled);
9ac7849e 1152 if (dr)
7f375f32 1153 dr->pinned = 1;
9ac7849e
TH		 1154}
1155
1da177e4
LT		 1156/**
1157 * pcibios_disable_device - disable arch specific PCI resources for device dev
1158 * @dev: the PCI device to disable
1159 *
1160 * Disables architecture specific PCI resources for the device. This
1161 * is the default implementation. Architecture implementations can
1162 * override this.
1163 */
1164void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
1165
fa58d305
RW		 1166static void do_pci_disable_device(struct pci_dev *dev)
1167{
1168 u16 pci_command;
1169
1170 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1171 if (pci_command & PCI_COMMAND_MASTER) {
1172 pci_command &= ~PCI_COMMAND_MASTER;
1173 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1174 }
1175
1176 pcibios_disable_device(dev);
1177}
1178
1179/**
1180 * pci_disable_enabled_device - Disable device without updating enable_cnt
1181 * @dev: PCI device to disable
1182 *
1183 * NOTE: This function is a backend of PCI power management routines and is
1184 * not supposed to be called drivers.
1185 */
1186void pci_disable_enabled_device(struct pci_dev *dev)
1187{
296ccb08 1188 if (pci_is_enabled(dev))
fa58d305
RW		 1189 do_pci_disable_device(dev);
1190}
1191
1da177e4
LT		 1192/**
1193 * pci_disable_device - Disable PCI device after use
1194 * @dev: PCI device to be disabled
1195 *
1196 * Signal to the system that the PCI device is not in use by the system
1197 * anymore. This only involves disabling PCI bus-mastering, if active.
bae94d02
IPG		 1198 *
1199 * Note we don't actually disable the device until all callers of
1200 * pci_device_enable() have called pci_device_disable().
1da177e4
LT		 1201 */
1202void
1203pci_disable_device(struct pci_dev *dev)
1204{
9ac7849e 1205 struct pci_devres *dr;
99dc804d 1206
9ac7849e
TH		 1207 dr = find_pci_dr(dev);
1208 if (dr)
7f375f32 1209 dr->enabled = 0;
9ac7849e 1210
bae94d02
IPG		 1211 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
1212 return;
1213
fa58d305 1214 do_pci_disable_device(dev);
1da177e4 1215
fa58d305 1216 dev->is_busmaster = 0;
1da177e4
LT		 1217}
1218
f7bdd12d
BK		 1219/**
1220 * pcibios_set_pcie_reset_state - set reset state for device dev
45e829ea 1221 * @dev: the PCIe device reset
f7bdd12d
BK		 1222 * @state: Reset state to enter into
1223 *
1224 *
45e829ea 1225 * Sets the PCIe reset state for the device. This is the default
f7bdd12d
BK		 1226 * implementation. Architecture implementations can override this.
1227 */
1228int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
1229 enum pcie_reset_state state)
1230{
1231 return -EINVAL;
1232}
1233
1234/**
1235 * pci_set_pcie_reset_state - set reset state for device dev
45e829ea 1236 * @dev: the PCIe device reset
f7bdd12d
BK		 1237 * @state: Reset state to enter into
1238 *
1239 *
1240 * Sets the PCI reset state for the device.
1241 */
1242int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1243{
1244 return pcibios_set_pcie_reset_state(dev, state);
1245}
1246
58ff4633
RW		 1247/**
1248 * pci_check_pme_status - Check if given device has generated PME.
1249 * @dev: Device to check.
1250 *
1251 * Check the PME status of the device and if set, clear it and clear PME enable
1252 * (if set). Return 'true' if PME status and PME enable were both set or
1253 * 'false' otherwise.
1254 */
1255bool pci_check_pme_status(struct pci_dev *dev)
1256{
1257 int pmcsr_pos;
1258 u16 pmcsr;
1259 bool ret = false;
1260
1261 if (!dev->pm_cap)
1262 return false;
1263
1264 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1265 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1266 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1267 return false;
1268
1269 /* Clear PME status. */
1270 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1271 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1272 /* Disable PME to avoid interrupt flood. */
1273 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1274 ret = true;
1275 }
1276
1277 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1278
1279 return ret;
1280}
1281
b67ea761
RW		 1282/**
1283 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1284 * @dev: Device to handle.
1285 * @ign: Ignored.
1286 *
1287 * Check if @dev has generated PME and queue a resume request for it in that
1288 * case.
1289 */
1290static int pci_pme_wakeup(struct pci_dev *dev, void *ign)
1291{
1292 if (pci_check_pme_status(dev))
1293 pm_request_resume(&dev->dev);
1294 return 0;
1295}
1296
1297/**
1298 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1299 * @bus: Top bus of the subtree to walk.
1300 */
1301void pci_pme_wakeup_bus(struct pci_bus *bus)
1302{
1303 if (bus)
1304 pci_walk_bus(bus, pci_pme_wakeup, NULL);
1305}
1306
eb9d0fe4
RW		 1307/**
1308 * pci_pme_capable - check the capability of PCI device to generate PME#
1309 * @dev: PCI device to handle.
eb9d0fe4
RW		 1310 * @state: PCI state from which device will issue PME#.
1311 */
e5899e1b 1312bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
eb9d0fe4 1313{
337001b6 1314 if (!dev->pm_cap)
eb9d0fe4
RW		 1315 return false;
1316
337001b6 1317 return !!(dev->pme_support & (1 << state));
eb9d0fe4
RW		 1318}
1319
1320/**
1321 * pci_pme_active - enable or disable PCI device's PME# function
1322 * @dev: PCI device to handle.
eb9d0fe4
RW		 1323 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1324 *
1325 * The caller must verify that the device is capable of generating PME# before
1326 * calling this function with @enable equal to 'true'.
1327 */
5a6c9b60 1328void pci_pme_active(struct pci_dev *dev, bool enable)
eb9d0fe4
RW		 1329{
1330 u16 pmcsr;
1331
337001b6 1332 if (!dev->pm_cap)
eb9d0fe4
RW		 1333 return;
1334
337001b6 1335 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
eb9d0fe4
RW		 1336 /* Clear PME_Status by writing 1 to it and enable PME# */
1337 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1338 if (!enable)
1339 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1340
337001b6 1341 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
eb9d0fe4 1342
10c3d71d 1343 dev_printk(KERN_DEBUG, &dev->dev, "PME# %s\n",
eb9d0fe4
RW		 1344 enable ? "enabled" : "disabled");
1345}
1346
1da177e4 1347/**
6cbf8214 1348 * __pci_enable_wake - enable PCI device as wakeup event source
075c1771
DB		 1349 * @dev: PCI device affected
1350 * @state: PCI state from which device will issue wakeup events
6cbf8214 1351 * @runtime: True if the events are to be generated at run time
075c1771
DB		 1352 * @enable: True to enable event generation; false to disable
1353 *
1354 * This enables the device as a wakeup event source, or disables it.
1355 * When such events involves platform-specific hooks, those hooks are
1356 * called automatically by this routine.
1357 *
1358 * Devices with legacy power management (no standard PCI PM capabilities)
eb9d0fe4 1359 * always require such platform hooks.
075c1771 1360 *
eb9d0fe4
RW		 1361 * RETURN VALUE:
1362 * 0 is returned on success
1363 * -EINVAL is returned if device is not supposed to wake up the system
1364 * Error code depending on the platform is returned if both the platform and
1365 * the native mechanism fail to enable the generation of wake-up events
1da177e4 1366 */
6cbf8214
RW		 1367int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1368 bool runtime, bool enable)
1da177e4 1369{
5bcc2fb4 1370 int ret = 0;
075c1771 1371
6cbf8214 1372 if (enable && !runtime && !device_may_wakeup(&dev->dev))
eb9d0fe4 1373 return -EINVAL;
1da177e4 1374
e80bb09d
RW		 1375 /* Don't do the same thing twice in a row for one device. */
1376 if (!!enable == !!dev->wakeup_prepared)
1377 return 0;
1378
eb9d0fe4
RW		 1379 /*
1380 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1381 * Anderson we should be doing PME# wake enable followed by ACPI wake
1382 * enable. To disable wake-up we call the platform first, for symmetry.
075c1771 1383 */
1da177e4 1384
5bcc2fb4
RW		 1385 if (enable) {
1386 int error;
1da177e4 1387
5bcc2fb4
RW		 1388 if (pci_pme_capable(dev, state))
1389 pci_pme_active(dev, true);
1390 else
1391 ret = 1;
6cbf8214
RW		 1392 error = runtime ? platform_pci_run_wake(dev, true) :
1393 platform_pci_sleep_wake(dev, true);
5bcc2fb4
RW		 1394 if (ret)
1395 ret = error;
e80bb09d
RW		 1396 if (!ret)
1397 dev->wakeup_prepared = true;
5bcc2fb4 1398 } else {
6cbf8214
RW		 1399 if (runtime)
1400 platform_pci_run_wake(dev, false);
1401 else
1402 platform_pci_sleep_wake(dev, false);
5bcc2fb4 1403 pci_pme_active(dev, false);
e80bb09d 1404 dev->wakeup_prepared = false;
5bcc2fb4 1405 }
1da177e4 1406
5bcc2fb4 1407 return ret;
eb9d0fe4 1408}
6cbf8214 1409EXPORT_SYMBOL(__pci_enable_wake);
1da177e4 1410
0235c4fc
RW		 1411/**
1412 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1413 * @dev: PCI device to prepare
1414 * @enable: True to enable wake-up event generation; false to disable
1415 *
1416 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1417 * and this function allows them to set that up cleanly - pci_enable_wake()
1418 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1419 * ordering constraints.
1420 *
1421 * This function only returns error code if the device is not capable of
1422 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1423 * enable wake-up power for it.
1424 */
1425int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1426{
1427 return pci_pme_capable(dev, PCI_D3cold) ?
1428 pci_enable_wake(dev, PCI_D3cold, enable) :
1429 pci_enable_wake(dev, PCI_D3hot, enable);
1430}
1431
404cc2d8 1432/**
37139074
JB		 1433 * pci_target_state - find an appropriate low power state for a given PCI dev
1434 * @dev: PCI device
1435 *
1436 * Use underlying platform code to find a supported low power state for @dev.
1437 * If the platform can't manage @dev, return the deepest state from which it
1438 * can generate wake events, based on any available PME info.
404cc2d8 1439 */
e5899e1b 1440pci_power_t pci_target_state(struct pci_dev *dev)
404cc2d8
RW		 1441{
1442 pci_power_t target_state = PCI_D3hot;
404cc2d8
RW		 1443
1444 if (platform_pci_power_manageable(dev)) {
1445 /*
1446 * Call the platform to choose the target state of the device
1447 * and enable wake-up from this state if supported.
1448 */
1449 pci_power_t state = platform_pci_choose_state(dev);
1450
1451 switch (state) {
1452 case PCI_POWER_ERROR:
1453 case PCI_UNKNOWN:
1454 break;
1455 case PCI_D1:
1456 case PCI_D2:
1457 if (pci_no_d1d2(dev))
1458 break;
1459 default:
1460 target_state = state;
404cc2d8 1461 }
d2abdf62
RW		 1462 } else if (!dev->pm_cap) {
1463 target_state = PCI_D0;
404cc2d8
RW		 1464 } else if (device_may_wakeup(&dev->dev)) {
1465 /*
1466 * Find the deepest state from which the device can generate
1467 * wake-up events, make it the target state and enable device
1468 * to generate PME#.
1469 */
337001b6
RW		 1470 if (dev->pme_support) {
1471 while (target_state
1472 && !(dev->pme_support & (1 << target_state)))
1473 target_state--;
404cc2d8
RW		 1474 }
1475 }
1476
e5899e1b
RW		 1477 return target_state;
1478}
1479
1480/**
1481 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1482 * @dev: Device to handle.
1483 *
1484 * Choose the power state appropriate for the device depending on whether
1485 * it can wake up the system and/or is power manageable by the platform
1486 * (PCI_D3hot is the default) and put the device into that state.
1487 */
1488int pci_prepare_to_sleep(struct pci_dev *dev)
1489{
1490 pci_power_t target_state = pci_target_state(dev);
1491 int error;
1492
1493 if (target_state == PCI_POWER_ERROR)
1494 return -EIO;
1495
8efb8c76 1496 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
c157dfa3 1497
404cc2d8
RW		 1498 error = pci_set_power_state(dev, target_state);
1499
1500 if (error)
1501 pci_enable_wake(dev, target_state, false);
1502
1503 return error;
1504}
1505
1506/**
443bd1c4 1507 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
404cc2d8
RW		 1508 * @dev: Device to handle.
1509 *
1510 * Disable device's sytem wake-up capability and put it into D0.
1511 */
1512int pci_back_from_sleep(struct pci_dev *dev)
1513{
1514 pci_enable_wake(dev, PCI_D0, false);
1515 return pci_set_power_state(dev, PCI_D0);
1516}
1517
6cbf8214
RW		 1518/**
1519 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
1520 * @dev: PCI device being suspended.
1521 *
1522 * Prepare @dev to generate wake-up events at run time and put it into a low
1523 * power state.
1524 */
1525int pci_finish_runtime_suspend(struct pci_dev *dev)
1526{
1527 pci_power_t target_state = pci_target_state(dev);
1528 int error;
1529
1530 if (target_state == PCI_POWER_ERROR)
1531 return -EIO;
1532
1533 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
1534
1535 error = pci_set_power_state(dev, target_state);
1536
1537 if (error)
1538 __pci_enable_wake(dev, target_state, true, false);
1539
1540 return error;
1541}
1542
b67ea761
RW		 1543/**
1544 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
1545 * @dev: Device to check.
1546 *
1547 * Return true if the device itself is cabable of generating wake-up events
1548 * (through the platform or using the native PCIe PME) or if the device supports
1549 * PME and one of its upstream bridges can generate wake-up events.
1550 */
1551bool pci_dev_run_wake(struct pci_dev *dev)
1552{
1553 struct pci_bus *bus = dev->bus;
1554
1555 if (device_run_wake(&dev->dev))
1556 return true;
1557
1558 if (!dev->pme_support)
1559 return false;
1560
1561 while (bus->parent) {
1562 struct pci_dev *bridge = bus->self;
1563
1564 if (device_run_wake(&bridge->dev))
1565 return true;
1566
1567 bus = bus->parent;
1568 }
1569
1570 /* We have reached the root bus. */
1571 if (bus->bridge)
1572 return device_run_wake(bus->bridge);
1573
1574 return false;
1575}
1576EXPORT_SYMBOL_GPL(pci_dev_run_wake);
1577
eb9d0fe4
RW		 1578/**
1579 * pci_pm_init - Initialize PM functions of given PCI device
1580 * @dev: PCI device to handle.
1581 */
1582void pci_pm_init(struct pci_dev *dev)
1583{
1584 int pm;
1585 u16 pmc;
1da177e4 1586
bb910a70 1587 pm_runtime_forbid(&dev->dev);
a1e4d72c 1588 device_enable_async_suspend(&dev->dev);
e80bb09d 1589 dev->wakeup_prepared = false;
bb910a70 1590
337001b6
RW		 1591 dev->pm_cap = 0;
1592
eb9d0fe4
RW		 1593 /* find PCI PM capability in list */
1594 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1595 if (!pm)
50246dd4 1596 return;
eb9d0fe4
RW		 1597 /* Check device's ability to generate PME# */
1598 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
075c1771 1599
eb9d0fe4
RW		 1600 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
1601 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
1602 pmc & PCI_PM_CAP_VER_MASK);
50246dd4 1603 return;
eb9d0fe4
RW		 1604 }
1605
337001b6 1606 dev->pm_cap = pm;
1ae861e6 1607 dev->d3_delay = PCI_PM_D3_WAIT;
337001b6
RW		 1608
1609 dev->d1_support = false;
1610 dev->d2_support = false;
1611 if (!pci_no_d1d2(dev)) {
c9ed77ee 1612 if (pmc & PCI_PM_CAP_D1)
337001b6 1613 dev->d1_support = true;
c9ed77ee 1614 if (pmc & PCI_PM_CAP_D2)
337001b6 1615 dev->d2_support = true;
c9ed77ee
BH		 1616
1617 if (dev->d1_support || dev->d2_support)
1618 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
ec84f126
JB		 1619 dev->d1_support ? " D1" : "",
1620 dev->d2_support ? " D2" : "");
337001b6
RW		 1621 }
1622
1623 pmc &= PCI_PM_CAP_PME_MASK;
1624 if (pmc) {
10c3d71d
BH		 1625 dev_printk(KERN_DEBUG, &dev->dev,
1626 "PME# supported from%s%s%s%s%s\n",
c9ed77ee
BH		 1627 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
1628 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
1629 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
1630 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
1631 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
337001b6 1632 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
eb9d0fe4
RW		 1633 /*
1634 * Make device's PM flags reflect the wake-up capability, but
1635 * let the user space enable it to wake up the system as needed.
1636 */
1637 device_set_wakeup_capable(&dev->dev, true);
1638 device_set_wakeup_enable(&dev->dev, false);
1639 /* Disable the PME# generation functionality */
337001b6
RW		 1640 pci_pme_active(dev, false);
1641 } else {
1642 dev->pme_support = 0;
eb9d0fe4 1643 }
1da177e4
LT		 1644}
1645
eb9c39d0
JB		 1646/**
1647 * platform_pci_wakeup_init - init platform wakeup if present
1648 * @dev: PCI device
1649 *
1650 * Some devices don't have PCI PM caps but can still generate wakeup
1651 * events through platform methods (like ACPI events). If @dev supports
1652 * platform wakeup events, set the device flag to indicate as much. This
1653 * may be redundant if the device also supports PCI PM caps, but double
1654 * initialization should be safe in that case.
1655 */
1656void platform_pci_wakeup_init(struct pci_dev *dev)
1657{
1658 if (!platform_pci_can_wakeup(dev))
1659 return;
1660
1661 device_set_wakeup_capable(&dev->dev, true);
1662 device_set_wakeup_enable(&dev->dev, false);
1663 platform_pci_sleep_wake(dev, false);
1664}
1665
63f4898a
RW		 1666/**
1667 * pci_add_save_buffer - allocate buffer for saving given capability registers
1668 * @dev: the PCI device
1669 * @cap: the capability to allocate the buffer for
1670 * @size: requested size of the buffer
1671 */
1672static int pci_add_cap_save_buffer(
1673 struct pci_dev *dev, char cap, unsigned int size)
1674{
1675 int pos;
1676 struct pci_cap_saved_state *save_state;
1677
1678 pos = pci_find_capability(dev, cap);
1679 if (pos <= 0)
1680 return 0;
1681
1682 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
1683 if (!save_state)
1684 return -ENOMEM;
1685
1686 save_state->cap_nr = cap;
1687 pci_add_saved_cap(dev, save_state);
1688
1689 return 0;
1690}
1691
1692/**
1693 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
1694 * @dev: the PCI device
1695 */
1696void pci_allocate_cap_save_buffers(struct pci_dev *dev)
1697{
1698 int error;
1699
89858517
YZ		 1700 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
1701 PCI_EXP_SAVE_REGS * sizeof(u16));
63f4898a
RW		 1702 if (error)
1703 dev_err(&dev->dev,
1704 "unable to preallocate PCI Express save buffer\n");
1705
1706 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
1707 if (error)
1708 dev_err(&dev->dev,
1709 "unable to preallocate PCI-X save buffer\n");
1710}
1711
58c3a727
YZ		 1712/**
1713 * pci_enable_ari - enable ARI forwarding if hardware support it
1714 * @dev: the PCI device
1715 */
1716void pci_enable_ari(struct pci_dev *dev)
1717{
1718 int pos;
1719 u32 cap;
1720 u16 ctrl;
8113587c 1721 struct pci_dev *bridge;
58c3a727 1722
5f4d91a1 1723 if (!pci_is_pcie(dev) || dev->devfn)
58c3a727
YZ		 1724 return;
1725
8113587c
ZY		 1726 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1727 if (!pos)
58c3a727
YZ		 1728 return;
1729
8113587c 1730 bridge = dev->bus->self;
5f4d91a1 1731 if (!bridge || !pci_is_pcie(bridge))
8113587c
ZY		 1732 return;
1733
06a1cbaf 1734 pos = pci_pcie_cap(bridge);
58c3a727
YZ		 1735 if (!pos)
1736 return;
1737
8113587c 1738 pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);
58c3a727
YZ		 1739 if (!(cap & PCI_EXP_DEVCAP2_ARI))
1740 return;
1741
8113587c 1742 pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl);
58c3a727 1743 ctrl |= PCI_EXP_DEVCTL2_ARI;
8113587c 1744 pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl);
58c3a727 1745
8113587c 1746 bridge->ari_enabled = 1;
58c3a727
YZ		 1747}
1748
5d990b62
CW		 1749static int pci_acs_enable;
1750
1751/**
1752 * pci_request_acs - ask for ACS to be enabled if supported
1753 */
1754void pci_request_acs(void)
1755{
1756 pci_acs_enable = 1;
1757}
1758
ae21ee65
AK		 1759/**
1760 * pci_enable_acs - enable ACS if hardware support it
1761 * @dev: the PCI device
1762 */
1763void pci_enable_acs(struct pci_dev *dev)
1764{
1765 int pos;
1766 u16 cap;
1767 u16 ctrl;
1768
5d990b62
CW		 1769 if (!pci_acs_enable)
1770 return;
1771
5f4d91a1 1772 if (!pci_is_pcie(dev))
ae21ee65
AK		 1773 return;
1774
1775 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
1776 if (!pos)
1777 return;
1778
1779 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
1780 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
1781
1782 /* Source Validation */
1783 ctrl |= (cap & PCI_ACS_SV);
1784
1785 /* P2P Request Redirect */
1786 ctrl |= (cap & PCI_ACS_RR);
1787
1788 /* P2P Completion Redirect */
1789 ctrl |= (cap & PCI_ACS_CR);
1790
1791 /* Upstream Forwarding */
1792 ctrl |= (cap & PCI_ACS_UF);
1793
1794 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
1795}
1796
57c2cf71
BH		 1797/**
1798 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
1799 * @dev: the PCI device
1800 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1801 *
1802 * Perform INTx swizzling for a device behind one level of bridge. This is
1803 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
46b952a3
MW		 1804 * behind bridges on add-in cards. For devices with ARI enabled, the slot
1805 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
1806 * the PCI Express Base Specification, Revision 2.1)
57c2cf71
BH		 1807 */
1808u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin)
1809{
46b952a3
MW		 1810 int slot;
1811
1812 if (pci_ari_enabled(dev->bus))
1813 slot = 0;
1814 else
1815 slot = PCI_SLOT(dev->devfn);
1816
1817 return (((pin - 1) + slot) % 4) + 1;
57c2cf71
BH		 1818}
1819
1da177e4
LT		 1820int
1821pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
1822{
1823 u8 pin;
1824
514d207d 1825 pin = dev->pin;
1da177e4
LT		 1826 if (!pin)
1827 return -1;
878f2e50 1828
8784fd4d 1829 while (!pci_is_root_bus(dev->bus)) {
57c2cf71 1830 pin = pci_swizzle_interrupt_pin(dev, pin);
1da177e4
LT		 1831 dev = dev->bus->self;
1832 }
1833 *bridge = dev;
1834 return pin;
1835}
1836
68feac87
BH		 1837/**
1838 * pci_common_swizzle - swizzle INTx all the way to root bridge
1839 * @dev: the PCI device
1840 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1841 *
1842 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
1843 * bridges all the way up to a PCI root bus.
1844 */
1845u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
1846{
1847 u8 pin = *pinp;
1848
1eb39487 1849 while (!pci_is_root_bus(dev->bus)) {
68feac87
BH		 1850 pin = pci_swizzle_interrupt_pin(dev, pin);
1851 dev = dev->bus->self;
1852 }
1853 *pinp = pin;
1854 return PCI_SLOT(dev->devfn);
1855}
1856
1da177e4
LT		 1857/**
1858 * pci_release_region - Release a PCI bar
1859 * @pdev: PCI device whose resources were previously reserved by pci_request_region
1860 * @bar: BAR to release
1861 *
1862 * Releases the PCI I/O and memory resources previously reserved by a
1863 * successful call to pci_request_region. Call this function only
1864 * after all use of the PCI regions has ceased.
1865 */
1866void pci_release_region(struct pci_dev *pdev, int bar)
1867{
9ac7849e
TH		 1868 struct pci_devres *dr;
1869
1da177e4
LT		 1870 if (pci_resource_len(pdev, bar) == 0)
1871 return;
1872 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
1873 release_region(pci_resource_start(pdev, bar),
1874 pci_resource_len(pdev, bar));
1875 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
1876 release_mem_region(pci_resource_start(pdev, bar),
1877 pci_resource_len(pdev, bar));
9ac7849e
TH		 1878
1879 dr = find_pci_dr(pdev);
1880 if (dr)
1881 dr->region_mask &= ~(1 << bar);
1da177e4
LT		 1882}
1883
1884/**
f5ddcac4 1885 * __pci_request_region - Reserved PCI I/O and memory resource
1da177e4
LT		 1886 * @pdev: PCI device whose resources are to be reserved
1887 * @bar: BAR to be reserved
1888 * @res_name: Name to be associated with resource.
f5ddcac4 1889 * @exclusive: whether the region access is exclusive or not
1da177e4
LT		 1890 *
1891 * Mark the PCI region associated with PCI device @pdev BR @bar as
1892 * being reserved by owner @res_name. Do not access any
1893 * address inside the PCI regions unless this call returns
1894 * successfully.
1895 *
f5ddcac4
RD		 1896 * If @exclusive is set, then the region is marked so that userspace
1897 * is explicitly not allowed to map the resource via /dev/mem or
1898 * sysfs MMIO access.
1899 *
1da177e4
LT		 1900 * Returns 0 on success, or %EBUSY on error. A warning
1901 * message is also printed on failure.
1902 */
e8de1481
AV		 1903static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
1904 int exclusive)
1da177e4 1905{
9ac7849e
TH		 1906 struct pci_devres *dr;
1907
1da177e4
LT		 1908 if (pci_resource_len(pdev, bar) == 0)
1909 return 0;
1910
1911 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
1912 if (!request_region(pci_resource_start(pdev, bar),
1913 pci_resource_len(pdev, bar), res_name))
1914 goto err_out;
1915 }
1916 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
e8de1481
AV		 1917 if (!__request_mem_region(pci_resource_start(pdev, bar),
1918 pci_resource_len(pdev, bar), res_name,
1919 exclusive))
1da177e4
LT		 1920 goto err_out;
1921 }
9ac7849e
TH		 1922
1923 dr = find_pci_dr(pdev);
1924 if (dr)
1925 dr->region_mask |= 1 << bar;
1926
1da177e4
LT		 1927 return 0;
1928
1929err_out:
c7dabef8 1930 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
096e6f67 1931 &pdev->resource[bar]);
1da177e4
LT		 1932 return -EBUSY;
1933}
1934
e8de1481 1935/**
f5ddcac4 1936 * pci_request_region - Reserve PCI I/O and memory resource
e8de1481
AV		 1937 * @pdev: PCI device whose resources are to be reserved
1938 * @bar: BAR to be reserved
f5ddcac4 1939 * @res_name: Name to be associated with resource
e8de1481 1940 *
f5ddcac4 1941 * Mark the PCI region associated with PCI device @pdev BAR @bar as
e8de1481
AV		 1942 * being reserved by owner @res_name. Do not access any
1943 * address inside the PCI regions unless this call returns
1944 * successfully.
1945 *
1946 * Returns 0 on success, or %EBUSY on error. A warning
1947 * message is also printed on failure.
1948 */
1949int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
1950{
1951 return __pci_request_region(pdev, bar, res_name, 0);
1952}
1953
1954/**
1955 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
1956 * @pdev: PCI device whose resources are to be reserved
1957 * @bar: BAR to be reserved
1958 * @res_name: Name to be associated with resource.
1959 *
1960 * Mark the PCI region associated with PCI device @pdev BR @bar as
1961 * being reserved by owner @res_name. Do not access any
1962 * address inside the PCI regions unless this call returns
1963 * successfully.
1964 *
1965 * Returns 0 on success, or %EBUSY on error. A warning
1966 * message is also printed on failure.
1967 *
1968 * The key difference that _exclusive makes it that userspace is
1969 * explicitly not allowed to map the resource via /dev/mem or
1970 * sysfs.
1971 */
1972int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
1973{
1974 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
1975}
c87deff7
HS		 1976/**
1977 * pci_release_selected_regions - Release selected PCI I/O and memory resources
1978 * @pdev: PCI device whose resources were previously reserved
1979 * @bars: Bitmask of BARs to be released
1980 *
1981 * Release selected PCI I/O and memory resources previously reserved.
1982 * Call this function only after all use of the PCI regions has ceased.
1983 */
1984void pci_release_selected_regions(struct pci_dev *pdev, int bars)
1985{
1986 int i;
1987
1988 for (i = 0; i < 6; i++)
1989 if (bars & (1 << i))
1990 pci_release_region(pdev, i);
1991}
1992
e8de1481
AV		 1993int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
1994 const char *res_name, int excl)
c87deff7
HS		 1995{
1996 int i;
1997
1998 for (i = 0; i < 6; i++)
1999 if (bars & (1 << i))
e8de1481 2000 if (__pci_request_region(pdev, i, res_name, excl))
c87deff7
HS		 2001 goto err_out;
2002 return 0;
2003
2004err_out:
2005 while(--i >= 0)
2006 if (bars & (1 << i))
2007 pci_release_region(pdev, i);
2008
2009 return -EBUSY;
2010}
1da177e4 2011
e8de1481
AV		 2012
2013/**
2014 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2015 * @pdev: PCI device whose resources are to be reserved
2016 * @bars: Bitmask of BARs to be requested
2017 * @res_name: Name to be associated with resource
2018 */
2019int pci_request_selected_regions(struct pci_dev *pdev, int bars,
2020 const char *res_name)
2021{
2022 return __pci_request_selected_regions(pdev, bars, res_name, 0);
2023}
2024
2025int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
2026 int bars, const char *res_name)
2027{
2028 return __pci_request_selected_regions(pdev, bars, res_name,
2029 IORESOURCE_EXCLUSIVE);
2030}
2031
1da177e4
LT		 2032/**
2033 * pci_release_regions - Release reserved PCI I/O and memory resources
2034 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2035 *
2036 * Releases all PCI I/O and memory resources previously reserved by a
2037 * successful call to pci_request_regions. Call this function only
2038 * after all use of the PCI regions has ceased.
2039 */
2040
2041void pci_release_regions(struct pci_dev *pdev)
2042{
c87deff7 2043 pci_release_selected_regions(pdev, (1 << 6) - 1);
1da177e4
LT		 2044}
2045
2046/**
2047 * pci_request_regions - Reserved PCI I/O and memory resources
2048 * @pdev: PCI device whose resources are to be reserved
2049 * @res_name: Name to be associated with resource.
2050 *
2051 * Mark all PCI regions associated with PCI device @pdev as
2052 * being reserved by owner @res_name. Do not access any
2053 * address inside the PCI regions unless this call returns
2054 * successfully.
2055 *
2056 * Returns 0 on success, or %EBUSY on error. A warning
2057 * message is also printed on failure.
2058 */
3c990e92 2059int pci_request_regions(struct pci_dev *pdev, const char *res_name)
1da177e4 2060{
c87deff7 2061 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
1da177e4
LT		 2062}
2063
e8de1481
AV		 2064/**
2065 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
2066 * @pdev: PCI device whose resources are to be reserved
2067 * @res_name: Name to be associated with resource.
2068 *
2069 * Mark all PCI regions associated with PCI device @pdev as
2070 * being reserved by owner @res_name. Do not access any
2071 * address inside the PCI regions unless this call returns
2072 * successfully.
2073 *
2074 * pci_request_regions_exclusive() will mark the region so that
2075 * /dev/mem and the sysfs MMIO access will not be allowed.
2076 *
2077 * Returns 0 on success, or %EBUSY on error. A warning
2078 * message is also printed on failure.
2079 */
2080int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
2081{
2082 return pci_request_selected_regions_exclusive(pdev,
2083 ((1 << 6) - 1), res_name);
2084}
2085
6a479079
BH		 2086static void __pci_set_master(struct pci_dev *dev, bool enable)
2087{
2088 u16 old_cmd, cmd;
2089
2090 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
2091 if (enable)
2092 cmd = old_cmd | PCI_COMMAND_MASTER;
2093 else
2094 cmd = old_cmd & ~PCI_COMMAND_MASTER;
2095 if (cmd != old_cmd) {
2096 dev_dbg(&dev->dev, "%s bus mastering\n",
2097 enable ? "enabling" : "disabling");
2098 pci_write_config_word(dev, PCI_COMMAND, cmd);
2099 }
2100 dev->is_busmaster = enable;
2101}
e8de1481 2102
1da177e4
LT		 2103/**
2104 * pci_set_master - enables bus-mastering for device dev
2105 * @dev: the PCI device to enable
2106 *
2107 * Enables bus-mastering on the device and calls pcibios_set_master()
2108 * to do the needed arch specific settings.
2109 */
6a479079 2110void pci_set_master(struct pci_dev *dev)
1da177e4 2111{
6a479079 2112 __pci_set_master(dev, true);
1da177e4
LT		 2113 pcibios_set_master(dev);
2114}
2115
6a479079
BH		 2116/**
2117 * pci_clear_master - disables bus-mastering for device dev
2118 * @dev: the PCI device to disable
2119 */
2120void pci_clear_master(struct pci_dev *dev)
2121{
2122 __pci_set_master(dev, false);
2123}
2124
1da177e4 2125/**
edb2d97e
MW		 2126 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
2127 * @dev: the PCI device for which MWI is to be enabled
1da177e4 2128 *
edb2d97e
MW		 2129 * Helper function for pci_set_mwi.
2130 * Originally copied from drivers/net/acenic.c.
1da177e4
LT		 2131 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
2132 *
2133 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2134 */
15ea76d4 2135int pci_set_cacheline_size(struct pci_dev *dev)
1da177e4
LT		 2136{
2137 u8 cacheline_size;
2138
2139 if (!pci_cache_line_size)
15ea76d4 2140 return -EINVAL;
1da177e4
LT		 2141
2142 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
2143 equal to or multiple of the right value. */
2144 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2145 if (cacheline_size >= pci_cache_line_size &&
2146 (cacheline_size % pci_cache_line_size) == 0)
2147 return 0;
2148
2149 /* Write the correct value. */
2150 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
2151 /* Read it back. */
2152 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2153 if (cacheline_size == pci_cache_line_size)
2154 return 0;
2155
80ccba11
BH		 2156 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
2157 "supported\n", pci_cache_line_size << 2);
1da177e4
LT		 2158
2159 return -EINVAL;
2160}
15ea76d4
TH		 2161EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
2162
2163#ifdef PCI_DISABLE_MWI
2164int pci_set_mwi(struct pci_dev *dev)
2165{
2166 return 0;
2167}
2168
2169int pci_try_set_mwi(struct pci_dev *dev)
2170{
2171 return 0;
2172}
2173
2174void pci_clear_mwi(struct pci_dev *dev)
2175{
2176}
2177
2178#else
1da177e4
LT		 2179
2180/**
2181 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2182 * @dev: the PCI device for which MWI is enabled
2183 *
694625c0 2184 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1da177e4
LT		 2185 *
2186 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2187 */
2188int
2189pci_set_mwi(struct pci_dev *dev)
2190{
2191 int rc;
2192 u16 cmd;
2193
edb2d97e 2194 rc = pci_set_cacheline_size(dev);
1da177e4
LT		 2195 if (rc)
2196 return rc;
2197
2198 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2199 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
80ccba11 2200 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
1da177e4
LT		 2201 cmd |= PCI_COMMAND_INVALIDATE;
2202 pci_write_config_word(dev, PCI_COMMAND, cmd);
2203 }
2204
2205 return 0;
2206}
2207
694625c0
RD		 2208/**
2209 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2210 * @dev: the PCI device for which MWI is enabled
2211 *
2212 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2213 * Callers are not required to check the return value.
2214 *
2215 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2216 */
2217int pci_try_set_mwi(struct pci_dev *dev)
2218{
2219 int rc = pci_set_mwi(dev);
2220 return rc;
2221}
2222
1da177e4
LT		 2223/**
2224 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2225 * @dev: the PCI device to disable
2226 *
2227 * Disables PCI Memory-Write-Invalidate transaction on the device
2228 */
2229void
2230pci_clear_mwi(struct pci_dev *dev)
2231{
2232 u16 cmd;
2233
2234 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2235 if (cmd & PCI_COMMAND_INVALIDATE) {
2236 cmd &= ~PCI_COMMAND_INVALIDATE;
2237 pci_write_config_word(dev, PCI_COMMAND, cmd);
2238 }
2239}
edb2d97e 2240#endif /* ! PCI_DISABLE_MWI */
1da177e4 2241
a04ce0ff
BR		 2242/**
2243 * pci_intx - enables/disables PCI INTx for device dev
8f7020d3
RD		 2244 * @pdev: the PCI device to operate on
2245 * @enable: boolean: whether to enable or disable PCI INTx
a04ce0ff
BR		 2246 *
2247 * Enables/disables PCI INTx for device dev
2248 */
2249void
2250pci_intx(struct pci_dev *pdev, int enable)
2251{
2252 u16 pci_command, new;
2253
2254 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
2255
2256 if (enable) {
2257 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
2258 } else {
2259 new = pci_command | PCI_COMMAND_INTX_DISABLE;
2260 }
2261
2262 if (new != pci_command) {
9ac7849e
TH		 2263 struct pci_devres *dr;
2264
2fd9d74b 2265 pci_write_config_word(pdev, PCI_COMMAND, new);
9ac7849e
TH		 2266
2267 dr = find_pci_dr(pdev);
2268 if (dr && !dr->restore_intx) {
2269 dr->restore_intx = 1;
2270 dr->orig_intx = !enable;
2271 }
a04ce0ff
BR		 2272 }
2273}
2274
f5f2b131
EB		 2275/**
2276 * pci_msi_off - disables any msi or msix capabilities
8d7d86e9 2277 * @dev: the PCI device to operate on
f5f2b131
EB		 2278 *
2279 * If you want to use msi see pci_enable_msi and friends.
2280 * This is a lower level primitive that allows us to disable
2281 * msi operation at the device level.
2282 */
2283void pci_msi_off(struct pci_dev *dev)
2284{
2285 int pos;
2286 u16 control;
2287
2288 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
2289 if (pos) {
2290 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
2291 control &= ~PCI_MSI_FLAGS_ENABLE;
2292 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
2293 }
2294 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
2295 if (pos) {
2296 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
2297 control &= ~PCI_MSIX_FLAGS_ENABLE;
2298 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
2299 }
2300}
2301
4d57cdfa
FT		 2302#ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE
2303int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
2304{
2305 return dma_set_max_seg_size(&dev->dev, size);
2306}
2307EXPORT_SYMBOL(pci_set_dma_max_seg_size);
2308#endif
2309
59fc67de
FT		 2310#ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY
2311int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
2312{
2313 return dma_set_seg_boundary(&dev->dev, mask);
2314}
2315EXPORT_SYMBOL(pci_set_dma_seg_boundary);
2316#endif
2317
8c1c699f 2318static int pcie_flr(struct pci_dev *dev, int probe)
8dd7f803 2319{
8c1c699f
YZ		 2320 int i;
2321 int pos;
8dd7f803 2322 u32 cap;
04b55c47 2323 u16 status, control;
8dd7f803 2324
06a1cbaf 2325 pos = pci_pcie_cap(dev);
8c1c699f 2326 if (!pos)
8dd7f803 2327 return -ENOTTY;
8c1c699f
YZ		 2328
2329 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap);
8dd7f803
SY		 2330 if (!(cap & PCI_EXP_DEVCAP_FLR))
2331 return -ENOTTY;
2332
d91cdc74
SY		 2333 if (probe)
2334 return 0;
2335
8dd7f803 2336 /* Wait for Transaction Pending bit clean */
8c1c699f
YZ		 2337 for (i = 0; i < 4; i++) {
2338 if (i)
2339 msleep((1 << (i - 1)) * 100);
5fe5db05 2340
8c1c699f
YZ		 2341 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
2342 if (!(status & PCI_EXP_DEVSTA_TRPND))
2343 goto clear;
2344 }
2345
2346 dev_err(&dev->dev, "transaction is not cleared; "
2347 "proceeding with reset anyway\n");
2348
2349clear:
04b55c47
SR		 2350 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &control);
2351 control |= PCI_EXP_DEVCTL_BCR_FLR;
2352 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, control);
2353
8c1c699f 2354 msleep(100);
8dd7f803 2355
8dd7f803
SY		 2356 return 0;
2357}
d91cdc74 2358
8c1c699f 2359static int pci_af_flr(struct pci_dev *dev, int probe)
1ca88797 2360{
8c1c699f
YZ		 2361 int i;
2362 int pos;
1ca88797 2363 u8 cap;
8c1c699f 2364 u8 status;
1ca88797 2365
8c1c699f
YZ		 2366 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
2367 if (!pos)
1ca88797 2368 return -ENOTTY;
8c1c699f
YZ		 2369
2370 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
1ca88797
SY		 2371 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
2372 return -ENOTTY;
2373
2374 if (probe)
2375 return 0;
2376
1ca88797 2377 /* Wait for Transaction Pending bit clean */
8c1c699f
YZ		 2378 for (i = 0; i < 4; i++) {
2379 if (i)
2380 msleep((1 << (i - 1)) * 100);
2381
2382 pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status);
2383 if (!(status & PCI_AF_STATUS_TP))
2384 goto clear;
2385 }
5fe5db05 2386
8c1c699f
YZ		 2387 dev_err(&dev->dev, "transaction is not cleared; "
2388 "proceeding with reset anyway\n");
5fe5db05 2389
8c1c699f
YZ		 2390clear:
2391 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
1ca88797 2392 msleep(100);
8c1c699f 2393
1ca88797
SY		 2394 return 0;
2395}
2396
f85876ba 2397static int pci_pm_reset(struct pci_dev *dev, int probe)
d91cdc74 2398{
f85876ba
YZ		 2399 u16 csr;
2400
2401 if (!dev->pm_cap)
2402 return -ENOTTY;
d91cdc74 2403
f85876ba
YZ		 2404 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
2405 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
2406 return -ENOTTY;
d91cdc74 2407
f85876ba
YZ		 2408 if (probe)
2409 return 0;
1ca88797 2410
f85876ba
YZ		 2411 if (dev->current_state != PCI_D0)
2412 return -EINVAL;
2413
2414 csr &= ~PCI_PM_CTRL_STATE_MASK;
2415 csr |= PCI_D3hot;
2416 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
1ae861e6 2417 pci_dev_d3_sleep(dev);
f85876ba
YZ		 2418
2419 csr &= ~PCI_PM_CTRL_STATE_MASK;
2420 csr |= PCI_D0;
2421 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
1ae861e6 2422 pci_dev_d3_sleep(dev);
f85876ba
YZ		 2423
2424 return 0;
2425}
2426
c12ff1df
YZ		 2427static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
2428{
2429 u16 ctrl;
2430 struct pci_dev *pdev;
2431
654b75e0 2432 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
c12ff1df
YZ		 2433 return -ENOTTY;
2434
2435 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
2436 if (pdev != dev)
2437 return -ENOTTY;
2438
2439 if (probe)
2440 return 0;
2441
2442 pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl);
2443 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
2444 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
2445 msleep(100);
2446
2447 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
2448 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
2449 msleep(100);
2450
2451 return 0;
2452}
2453
8c1c699f 2454static int pci_dev_reset(struct pci_dev *dev, int probe)
d91cdc74 2455{
8c1c699f
YZ		 2456 int rc;
2457
2458 might_sleep();
2459
2460 if (!probe) {
2461 pci_block_user_cfg_access(dev);
2462 /* block PM suspend, driver probe, etc. */
8e9394ce 2463 device_lock(&dev->dev);
8c1c699f 2464 }
d91cdc74 2465
b9c3b266
DC		 2466 rc = pci_dev_specific_reset(dev, probe);
2467 if (rc != -ENOTTY)
2468 goto done;
2469
8c1c699f
YZ		 2470 rc = pcie_flr(dev, probe);
2471 if (rc != -ENOTTY)
2472 goto done;
d91cdc74 2473
8c1c699f 2474 rc = pci_af_flr(dev, probe);
f85876ba
YZ		 2475 if (rc != -ENOTTY)
2476 goto done;
2477
2478 rc = pci_pm_reset(dev, probe);
c12ff1df
YZ		 2479 if (rc != -ENOTTY)
2480 goto done;
2481
2482 rc = pci_parent_bus_reset(dev, probe);
8c1c699f
YZ		 2483done:
2484 if (!probe) {
8e9394ce 2485 device_unlock(&dev->dev);
8c1c699f
YZ		 2486 pci_unblock_user_cfg_access(dev);
2487 }
1ca88797 2488
8c1c699f 2489 return rc;
d91cdc74
SY		 2490}
2491
2492/**
8c1c699f
YZ		 2493 * __pci_reset_function - reset a PCI device function
2494 * @dev: PCI device to reset
d91cdc74
SY		 2495 *
2496 * Some devices allow an individual function to be reset without affecting
2497 * other functions in the same device. The PCI device must be responsive
2498 * to PCI config space in order to use this function.
2499 *
2500 * The device function is presumed to be unused when this function is called.
2501 * Resetting the device will make the contents of PCI configuration space
2502 * random, so any caller of this must be prepared to reinitialise the
2503 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
2504 * etc.
2505 *
8c1c699f 2506 * Returns 0 if the device function was successfully reset or negative if the
d91cdc74
SY		 2507 * device doesn't support resetting a single function.
2508 */
8c1c699f 2509int __pci_reset_function(struct pci_dev *dev)
d91cdc74 2510{
8c1c699f 2511 return pci_dev_reset(dev, 0);
d91cdc74 2512}
8c1c699f 2513EXPORT_SYMBOL_GPL(__pci_reset_function);
8dd7f803 2514
711d5779
MT		 2515/**
2516 * pci_probe_reset_function - check whether the device can be safely reset
2517 * @dev: PCI device to reset
2518 *
2519 * Some devices allow an individual function to be reset without affecting
2520 * other functions in the same device. The PCI device must be responsive
2521 * to PCI config space in order to use this function.
2522 *
2523 * Returns 0 if the device function can be reset or negative if the
2524 * device doesn't support resetting a single function.
2525 */
2526int pci_probe_reset_function(struct pci_dev *dev)
2527{
2528 return pci_dev_reset(dev, 1);
2529}
2530
8dd7f803 2531/**
8c1c699f
YZ		 2532 * pci_reset_function - quiesce and reset a PCI device function
2533 * @dev: PCI device to reset
8dd7f803
SY		 2534 *
2535 * Some devices allow an individual function to be reset without affecting
2536 * other functions in the same device. The PCI device must be responsive
2537 * to PCI config space in order to use this function.
2538 *
2539 * This function does not just reset the PCI portion of a device, but
2540 * clears all the state associated with the device. This function differs
8c1c699f 2541 * from __pci_reset_function in that it saves and restores device state
8dd7f803
SY		 2542 * over the reset.
2543 *
8c1c699f 2544 * Returns 0 if the device function was successfully reset or negative if the
8dd7f803
SY		 2545 * device doesn't support resetting a single function.
2546 */
2547int pci_reset_function(struct pci_dev *dev)
2548{
8c1c699f 2549 int rc;
8dd7f803 2550
8c1c699f
YZ		 2551 rc = pci_dev_reset(dev, 1);
2552 if (rc)
2553 return rc;
8dd7f803 2554
8dd7f803
SY		 2555 pci_save_state(dev);
2556
8c1c699f
YZ		 2557 /*
2558 * both INTx and MSI are disabled after the Interrupt Disable bit
2559 * is set and the Bus Master bit is cleared.
2560 */
8dd7f803
SY		 2561 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
2562
8c1c699f 2563 rc = pci_dev_reset(dev, 0);
8dd7f803
SY		 2564
2565 pci_restore_state(dev);
8dd7f803 2566
8c1c699f 2567 return rc;
8dd7f803
SY		 2568}
2569EXPORT_SYMBOL_GPL(pci_reset_function);
2570
d556ad4b
PO		 2571/**
2572 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
2573 * @dev: PCI device to query
2574 *
2575 * Returns mmrbc: maximum designed memory read count in bytes
2576 * or appropriate error value.
2577 */
2578int pcix_get_max_mmrbc(struct pci_dev *dev)
2579{
7c9e2b1c 2580 int cap;
d556ad4b
PO		 2581 u32 stat;
2582
2583 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2584 if (!cap)
2585 return -EINVAL;
2586
7c9e2b1c 2587 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
d556ad4b
PO		 2588 return -EINVAL;
2589
25daeb55 2590 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
d556ad4b
PO		 2591}
2592EXPORT_SYMBOL(pcix_get_max_mmrbc);
2593
2594/**
2595 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
2596 * @dev: PCI device to query
2597 *
2598 * Returns mmrbc: maximum memory read count in bytes
2599 * or appropriate error value.
2600 */
2601int pcix_get_mmrbc(struct pci_dev *dev)
2602{
7c9e2b1c 2603 int cap;
bdc2bda7 2604 u16 cmd;
d556ad4b
PO		 2605
2606 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2607 if (!cap)
2608 return -EINVAL;
2609
7c9e2b1c
DN		 2610 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
2611 return -EINVAL;
d556ad4b 2612
7c9e2b1c 2613 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
d556ad4b
PO		 2614}
2615EXPORT_SYMBOL(pcix_get_mmrbc);
2616
2617/**
2618 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
2619 * @dev: PCI device to query
2620 * @mmrbc: maximum memory read count in bytes
2621 * valid values are 512, 1024, 2048, 4096
2622 *
2623 * If possible sets maximum memory read byte count, some bridges have erratas
2624 * that prevent this.
2625 */
2626int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
2627{
7c9e2b1c 2628 int cap;
bdc2bda7
DN		 2629 u32 stat, v, o;
2630 u16 cmd;
d556ad4b 2631
229f5afd 2632 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
7c9e2b1c 2633 return -EINVAL;
d556ad4b
PO		 2634
2635 v = ffs(mmrbc) - 10;
2636
2637 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2638 if (!cap)
7c9e2b1c 2639 return -EINVAL;
d556ad4b 2640
7c9e2b1c
DN		 2641 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
2642 return -EINVAL;
d556ad4b
PO		 2643
2644 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
2645 return -E2BIG;
2646
7c9e2b1c
DN		 2647 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
2648 return -EINVAL;
d556ad4b
PO		 2649
2650 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
2651 if (o != v) {
2652 if (v > o && dev->bus &&
2653 (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
2654 return -EIO;
2655
2656 cmd &= ~PCI_X_CMD_MAX_READ;
2657 cmd |= v << 2;
7c9e2b1c
DN		 2658 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
2659 return -EIO;
d556ad4b 2660 }
7c9e2b1c 2661 return 0;
d556ad4b
PO		 2662}
2663EXPORT_SYMBOL(pcix_set_mmrbc);
2664
2665/**
2666 * pcie_get_readrq - get PCI Express read request size
2667 * @dev: PCI device to query
2668 *
2669 * Returns maximum memory read request in bytes
2670 * or appropriate error value.
2671 */
2672int pcie_get_readrq(struct pci_dev *dev)
2673{
2674 int ret, cap;
2675 u16 ctl;
2676
06a1cbaf 2677 cap = pci_pcie_cap(dev);
d556ad4b
PO		 2678 if (!cap)
2679 return -EINVAL;
2680
2681 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
2682 if (!ret)
2683 ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
2684
2685 return ret;
2686}
2687EXPORT_SYMBOL(pcie_get_readrq);
2688
2689/**
2690 * pcie_set_readrq - set PCI Express maximum memory read request
2691 * @dev: PCI device to query
42e61f4a 2692 * @rq: maximum memory read count in bytes
d556ad4b
PO		 2693 * valid values are 128, 256, 512, 1024, 2048, 4096
2694 *
2695 * If possible sets maximum read byte count
2696 */
2697int pcie_set_readrq(struct pci_dev *dev, int rq)
2698{
2699 int cap, err = -EINVAL;
2700 u16 ctl, v;
2701
229f5afd 2702 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
d556ad4b
PO		 2703 goto out;
2704
2705 v = (ffs(rq) - 8) << 12;
2706
06a1cbaf 2707 cap = pci_pcie_cap(dev);
d556ad4b
PO		 2708 if (!cap)
2709 goto out;
2710
2711 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
2712 if (err)
2713 goto out;
2714
2715 if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
2716 ctl &= ~PCI_EXP_DEVCTL_READRQ;
2717 ctl |= v;
2718 err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl);
2719 }
2720
2721out:
2722 return err;
2723}
2724EXPORT_SYMBOL(pcie_set_readrq);
2725
c87deff7
HS		 2726/**
2727 * pci_select_bars - Make BAR mask from the type of resource
f95d882d 2728 * @dev: the PCI device for which BAR mask is made
c87deff7
HS		 2729 * @flags: resource type mask to be selected
2730 *
2731 * This helper routine makes bar mask from the type of resource.
2732 */
2733int pci_select_bars(struct pci_dev *dev, unsigned long flags)
2734{
2735 int i, bars = 0;
2736 for (i = 0; i < PCI_NUM_RESOURCES; i++)
2737 if (pci_resource_flags(dev, i) & flags)
2738 bars |= (1 << i);
2739 return bars;
2740}
2741
613e7ed6
YZ		 2742/**
2743 * pci_resource_bar - get position of the BAR associated with a resource
2744 * @dev: the PCI device
2745 * @resno: the resource number
2746 * @type: the BAR type to be filled in
2747 *
2748 * Returns BAR position in config space, or 0 if the BAR is invalid.
2749 */
2750int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
2751{
d1b054da
YZ		 2752 int reg;
2753
613e7ed6
YZ		 2754 if (resno < PCI_ROM_RESOURCE) {
2755 *type = pci_bar_unknown;
2756 return PCI_BASE_ADDRESS_0 + 4 * resno;
2757 } else if (resno == PCI_ROM_RESOURCE) {
2758 *type = pci_bar_mem32;
2759 return dev->rom_base_reg;
d1b054da
YZ		 2760 } else if (resno < PCI_BRIDGE_RESOURCES) {
2761 /* device specific resource */
2762 reg = pci_iov_resource_bar(dev, resno, type);
2763 if (reg)
2764 return reg;
613e7ed6
YZ		 2765 }
2766
865df576 2767 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
613e7ed6
YZ		 2768 return 0;
2769}
2770
95a8b6ef
MT		 2771/* Some architectures require additional programming to enable VGA */
2772static arch_set_vga_state_t arch_set_vga_state;
2773
2774void __init pci_register_set_vga_state(arch_set_vga_state_t func)
2775{
2776 arch_set_vga_state = func; /* NULL disables */
2777}
2778
2779static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
2780 unsigned int command_bits, bool change_bridge)
2781{
2782 if (arch_set_vga_state)
2783 return arch_set_vga_state(dev, decode, command_bits,
2784 change_bridge);
2785 return 0;
2786}
2787
deb2d2ec
BH		 2788/**
2789 * pci_set_vga_state - set VGA decode state on device and parents if requested
19eea630
RD		 2790 * @dev: the PCI device
2791 * @decode: true = enable decoding, false = disable decoding
2792 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
2793 * @change_bridge: traverse ancestors and change bridges
deb2d2ec
BH		 2794 */
2795int pci_set_vga_state(struct pci_dev *dev, bool decode,
2796 unsigned int command_bits, bool change_bridge)
2797{
2798 struct pci_bus *bus;
2799 struct pci_dev *bridge;
2800 u16 cmd;
95a8b6ef 2801 int rc;
deb2d2ec
BH		 2802
2803 WARN_ON(command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY));
2804
95a8b6ef
MT		 2805 /* ARCH specific VGA enables */
2806 rc = pci_set_vga_state_arch(dev, decode, command_bits, change_bridge);
2807 if (rc)
2808 return rc;
2809
deb2d2ec
BH		 2810 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2811 if (decode == true)
2812 cmd |= command_bits;
2813 else
2814 cmd &= ~command_bits;
2815 pci_write_config_word(dev, PCI_COMMAND, cmd);
2816
2817 if (change_bridge == false)
2818 return 0;
2819
2820 bus = dev->bus;
2821 while (bus) {
2822 bridge = bus->self;
2823 if (bridge) {
2824 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
2825 &cmd);
2826 if (decode == true)
2827 cmd |= PCI_BRIDGE_CTL_VGA;
2828 else
2829 cmd &= ~PCI_BRIDGE_CTL_VGA;
2830 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
2831 cmd);
2832 }
2833 bus = bus->parent;
2834 }
2835 return 0;
2836}
2837
32a9a682
YS		 2838#define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
2839static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
e9d1e492 2840static DEFINE_SPINLOCK(resource_alignment_lock);
32a9a682
YS		 2841
2842/**
2843 * pci_specified_resource_alignment - get resource alignment specified by user.
2844 * @dev: the PCI device to get
2845 *
2846 * RETURNS: Resource alignment if it is specified.
2847 * Zero if it is not specified.
2848 */
2849resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
2850{
2851 int seg, bus, slot, func, align_order, count;
2852 resource_size_t align = 0;
2853 char *p;
2854
2855 spin_lock(&resource_alignment_lock);
2856 p = resource_alignment_param;
2857 while (*p) {
2858 count = 0;
2859 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
2860 p[count] == '@') {
2861 p += count + 1;
2862 } else {
2863 align_order = -1;
2864 }
2865 if (sscanf(p, "%x:%x:%x.%x%n",
2866 &seg, &bus, &slot, &func, &count) != 4) {
2867 seg = 0;
2868 if (sscanf(p, "%x:%x.%x%n",
2869 &bus, &slot, &func, &count) != 3) {
2870 /* Invalid format */
2871 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
2872 p);
2873 break;
2874 }
2875 }
2876 p += count;
2877 if (seg == pci_domain_nr(dev->bus) &&
2878 bus == dev->bus->number &&
2879 slot == PCI_SLOT(dev->devfn) &&
2880 func == PCI_FUNC(dev->devfn)) {
2881 if (align_order == -1) {
2882 align = PAGE_SIZE;
2883 } else {
2884 align = 1 << align_order;
2885 }
2886 /* Found */
2887 break;
2888 }
2889 if (*p != ';' && *p != ',') {
2890 /* End of param or invalid format */
2891 break;
2892 }
2893 p++;
2894 }
2895 spin_unlock(&resource_alignment_lock);
2896 return align;
2897}
2898
2899/**
2900 * pci_is_reassigndev - check if specified PCI is target device to reassign
2901 * @dev: the PCI device to check
2902 *
2903 * RETURNS: non-zero for PCI device is a target device to reassign,
2904 * or zero is not.
2905 */
2906int pci_is_reassigndev(struct pci_dev *dev)
2907{
2908 return (pci_specified_resource_alignment(dev) != 0);
2909}
2910
2911ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
2912{
2913 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
2914 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
2915 spin_lock(&resource_alignment_lock);
2916 strncpy(resource_alignment_param, buf, count);
2917 resource_alignment_param[count] = '\0';
2918 spin_unlock(&resource_alignment_lock);
2919 return count;
2920}
2921
2922ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
2923{
2924 size_t count;
2925 spin_lock(&resource_alignment_lock);
2926 count = snprintf(buf, size, "%s", resource_alignment_param);
2927 spin_unlock(&resource_alignment_lock);
2928 return count;
2929}
2930
2931static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
2932{
2933 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
2934}
2935
2936static ssize_t pci_resource_alignment_store(struct bus_type *bus,
2937 const char *buf, size_t count)
2938{
2939 return pci_set_resource_alignment_param(buf, count);
2940}
2941
2942BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
2943 pci_resource_alignment_store);
2944
2945static int __init pci_resource_alignment_sysfs_init(void)
2946{
2947 return bus_create_file(&pci_bus_type,
2948 &bus_attr_resource_alignment);
2949}
2950
2951late_initcall(pci_resource_alignment_sysfs_init);
2952
32a2eea7
JG		 2953static void __devinit pci_no_domains(void)
2954{
2955#ifdef CONFIG_PCI_DOMAINS
2956 pci_domains_supported = 0;
2957#endif
2958}
2959
0ef5f8f6
AP		 2960/**
2961 * pci_ext_cfg_enabled - can we access extended PCI config space?
2962 * @dev: The PCI device of the root bridge.
2963 *
2964 * Returns 1 if we can access PCI extended config space (offsets
2965 * greater than 0xff). This is the default implementation. Architecture
2966 * implementations can override this.
2967 */
2968int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev)
2969{
2970 return 1;
2971}
2972
2d1c8618
BH		 2973void __weak pci_fixup_cardbus(struct pci_bus *bus)
2974{
2975}
2976EXPORT_SYMBOL(pci_fixup_cardbus);
2977
ad04d31e 2978static int __init pci_setup(char *str)
1da177e4
LT		 2979{
2980 while (str) {
2981 char *k = strchr(str, ',');
2982 if (k)
2983 *k++ = 0;
2984 if (*str && (str = pcibios_setup(str)) && *str) {
309e57df
MW		 2985 if (!strcmp(str, "nomsi")) {
2986 pci_no_msi();
7f785763
RD		 2987 } else if (!strcmp(str, "noaer")) {
2988 pci_no_aer();
32a2eea7
JG		 2989 } else if (!strcmp(str, "nodomains")) {
2990 pci_no_domains();
4516a618
AN		 2991 } else if (!strncmp(str, "cbiosize=", 9)) {
2992 pci_cardbus_io_size = memparse(str + 9, &str);
2993 } else if (!strncmp(str, "cbmemsize=", 10)) {
2994 pci_cardbus_mem_size = memparse(str + 10, &str);
32a9a682
YS		 2995 } else if (!strncmp(str, "resource_alignment=", 19)) {
2996 pci_set_resource_alignment_param(str + 19,
2997 strlen(str + 19));
43c16408
AP		 2998 } else if (!strncmp(str, "ecrc=", 5)) {
2999 pcie_ecrc_get_policy(str + 5);
28760489
EB		 3000 } else if (!strncmp(str, "hpiosize=", 9)) {
3001 pci_hotplug_io_size = memparse(str + 9, &str);
3002 } else if (!strncmp(str, "hpmemsize=", 10)) {
3003 pci_hotplug_mem_size = memparse(str + 10, &str);
309e57df
MW		 3004 } else {
3005 printk(KERN_ERR "PCI: Unknown option `%s'\n",
3006 str);
3007 }
1da177e4
LT		 3008 }
3009 str = k;
3010 }
0637a70a 3011 return 0;
1da177e4 3012}
0637a70a 3013early_param("pci", pci_setup);
1da177e4 3014
0b62e13b 3015EXPORT_SYMBOL(pci_reenable_device);
b718989d
BH		 3016EXPORT_SYMBOL(pci_enable_device_io);
3017EXPORT_SYMBOL(pci_enable_device_mem);
1da177e4 3018EXPORT_SYMBOL(pci_enable_device);
9ac7849e
TH		 3019EXPORT_SYMBOL(pcim_enable_device);
3020EXPORT_SYMBOL(pcim_pin_device);
1da177e4 3021EXPORT_SYMBOL(pci_disable_device);
1da177e4
LT		 3022EXPORT_SYMBOL(pci_find_capability);
3023EXPORT_SYMBOL(pci_bus_find_capability);
3024EXPORT_SYMBOL(pci_release_regions);
3025EXPORT_SYMBOL(pci_request_regions);
e8de1481 3026EXPORT_SYMBOL(pci_request_regions_exclusive);
1da177e4
LT		 3027EXPORT_SYMBOL(pci_release_region);
3028EXPORT_SYMBOL(pci_request_region);
e8de1481 3029EXPORT_SYMBOL(pci_request_region_exclusive);
c87deff7
HS		 3030EXPORT_SYMBOL(pci_release_selected_regions);
3031EXPORT_SYMBOL(pci_request_selected_regions);
e8de1481 3032EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
1da177e4 3033EXPORT_SYMBOL(pci_set_master);
6a479079 3034EXPORT_SYMBOL(pci_clear_master);
1da177e4 3035EXPORT_SYMBOL(pci_set_mwi);
694625c0 3036EXPORT_SYMBOL(pci_try_set_mwi);
1da177e4 3037EXPORT_SYMBOL(pci_clear_mwi);
a04ce0ff 3038EXPORT_SYMBOL_GPL(pci_intx);
1da177e4
LT		 3039EXPORT_SYMBOL(pci_assign_resource);
3040EXPORT_SYMBOL(pci_find_parent_resource);
c87deff7 3041EXPORT_SYMBOL(pci_select_bars);
1da177e4
LT		 3042
3043EXPORT_SYMBOL(pci_set_power_state);
3044EXPORT_SYMBOL(pci_save_state);
3045EXPORT_SYMBOL(pci_restore_state);
e5899e1b 3046EXPORT_SYMBOL(pci_pme_capable);
5a6c9b60 3047EXPORT_SYMBOL(pci_pme_active);
0235c4fc 3048EXPORT_SYMBOL(pci_wake_from_d3);
e5899e1b 3049EXPORT_SYMBOL(pci_target_state);
404cc2d8
RW		 3050EXPORT_SYMBOL(pci_prepare_to_sleep);
3051EXPORT_SYMBOL(pci_back_from_sleep);
f7bdd12d 3052EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
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