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1da177e4 LT |
1 | /* |
2 | * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $ | |
3 | * | |
4 | * PCI Bus Services, see include/linux/pci.h for further explanation. | |
5 | * | |
6 | * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, | |
7 | * David Mosberger-Tang | |
8 | * | |
9 | * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> | |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/delay.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/pci.h> | |
075c1771 | 16 | #include <linux/pm.h> |
1da177e4 LT |
17 | #include <linux/module.h> |
18 | #include <linux/spinlock.h> | |
4e57b681 | 19 | #include <linux/string.h> |
229f5afd | 20 | #include <linux/log2.h> |
1da177e4 | 21 | #include <asm/dma.h> /* isa_dma_bridge_buggy */ |
bc56b9e0 | 22 | #include "pci.h" |
1da177e4 | 23 | |
ffadcc2f | 24 | unsigned int pci_pm_d3_delay = 10; |
1da177e4 | 25 | |
32a2eea7 JG |
26 | #ifdef CONFIG_PCI_DOMAINS |
27 | int pci_domains_supported = 1; | |
28 | #endif | |
29 | ||
4516a618 AN |
30 | #define DEFAULT_CARDBUS_IO_SIZE (256) |
31 | #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024) | |
32 | /* pci=cbmemsize=nnM,cbiosize=nn can override this */ | |
33 | unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE; | |
34 | unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE; | |
35 | ||
1da177e4 LT |
36 | /** |
37 | * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children | |
38 | * @bus: pointer to PCI bus structure to search | |
39 | * | |
40 | * Given a PCI bus, returns the highest PCI bus number present in the set | |
41 | * including the given PCI bus and its list of child PCI buses. | |
42 | */ | |
96bde06a | 43 | unsigned char pci_bus_max_busnr(struct pci_bus* bus) |
1da177e4 LT |
44 | { |
45 | struct list_head *tmp; | |
46 | unsigned char max, n; | |
47 | ||
b82db5ce | 48 | max = bus->subordinate; |
1da177e4 LT |
49 | list_for_each(tmp, &bus->children) { |
50 | n = pci_bus_max_busnr(pci_bus_b(tmp)); | |
51 | if(n > max) | |
52 | max = n; | |
53 | } | |
54 | return max; | |
55 | } | |
b82db5ce | 56 | EXPORT_SYMBOL_GPL(pci_bus_max_busnr); |
1da177e4 | 57 | |
b82db5ce | 58 | #if 0 |
1da177e4 LT |
59 | /** |
60 | * pci_max_busnr - returns maximum PCI bus number | |
61 | * | |
62 | * Returns the highest PCI bus number present in the system global list of | |
63 | * PCI buses. | |
64 | */ | |
65 | unsigned char __devinit | |
66 | pci_max_busnr(void) | |
67 | { | |
68 | struct pci_bus *bus = NULL; | |
69 | unsigned char max, n; | |
70 | ||
71 | max = 0; | |
72 | while ((bus = pci_find_next_bus(bus)) != NULL) { | |
73 | n = pci_bus_max_busnr(bus); | |
74 | if(n > max) | |
75 | max = n; | |
76 | } | |
77 | return max; | |
78 | } | |
79 | ||
54c762fe AB |
80 | #endif /* 0 */ |
81 | ||
687d5fe3 ME |
82 | #define PCI_FIND_CAP_TTL 48 |
83 | ||
84 | static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, | |
85 | u8 pos, int cap, int *ttl) | |
24a4e377 RD |
86 | { |
87 | u8 id; | |
24a4e377 | 88 | |
687d5fe3 | 89 | while ((*ttl)--) { |
24a4e377 RD |
90 | pci_bus_read_config_byte(bus, devfn, pos, &pos); |
91 | if (pos < 0x40) | |
92 | break; | |
93 | pos &= ~3; | |
94 | pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, | |
95 | &id); | |
96 | if (id == 0xff) | |
97 | break; | |
98 | if (id == cap) | |
99 | return pos; | |
100 | pos += PCI_CAP_LIST_NEXT; | |
101 | } | |
102 | return 0; | |
103 | } | |
104 | ||
687d5fe3 ME |
105 | static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, |
106 | u8 pos, int cap) | |
107 | { | |
108 | int ttl = PCI_FIND_CAP_TTL; | |
109 | ||
110 | return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); | |
111 | } | |
112 | ||
24a4e377 RD |
113 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) |
114 | { | |
115 | return __pci_find_next_cap(dev->bus, dev->devfn, | |
116 | pos + PCI_CAP_LIST_NEXT, cap); | |
117 | } | |
118 | EXPORT_SYMBOL_GPL(pci_find_next_capability); | |
119 | ||
d3bac118 ME |
120 | static int __pci_bus_find_cap_start(struct pci_bus *bus, |
121 | unsigned int devfn, u8 hdr_type) | |
1da177e4 LT |
122 | { |
123 | u16 status; | |
1da177e4 LT |
124 | |
125 | pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); | |
126 | if (!(status & PCI_STATUS_CAP_LIST)) | |
127 | return 0; | |
128 | ||
129 | switch (hdr_type) { | |
130 | case PCI_HEADER_TYPE_NORMAL: | |
131 | case PCI_HEADER_TYPE_BRIDGE: | |
d3bac118 | 132 | return PCI_CAPABILITY_LIST; |
1da177e4 | 133 | case PCI_HEADER_TYPE_CARDBUS: |
d3bac118 | 134 | return PCI_CB_CAPABILITY_LIST; |
1da177e4 LT |
135 | default: |
136 | return 0; | |
137 | } | |
d3bac118 ME |
138 | |
139 | return 0; | |
1da177e4 LT |
140 | } |
141 | ||
142 | /** | |
143 | * pci_find_capability - query for devices' capabilities | |
144 | * @dev: PCI device to query | |
145 | * @cap: capability code | |
146 | * | |
147 | * Tell if a device supports a given PCI capability. | |
148 | * Returns the address of the requested capability structure within the | |
149 | * device's PCI configuration space or 0 in case the device does not | |
150 | * support it. Possible values for @cap: | |
151 | * | |
152 | * %PCI_CAP_ID_PM Power Management | |
153 | * %PCI_CAP_ID_AGP Accelerated Graphics Port | |
154 | * %PCI_CAP_ID_VPD Vital Product Data | |
155 | * %PCI_CAP_ID_SLOTID Slot Identification | |
156 | * %PCI_CAP_ID_MSI Message Signalled Interrupts | |
157 | * %PCI_CAP_ID_CHSWP CompactPCI HotSwap | |
158 | * %PCI_CAP_ID_PCIX PCI-X | |
159 | * %PCI_CAP_ID_EXP PCI Express | |
160 | */ | |
161 | int pci_find_capability(struct pci_dev *dev, int cap) | |
162 | { | |
d3bac118 ME |
163 | int pos; |
164 | ||
165 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
166 | if (pos) | |
167 | pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); | |
168 | ||
169 | return pos; | |
1da177e4 LT |
170 | } |
171 | ||
172 | /** | |
173 | * pci_bus_find_capability - query for devices' capabilities | |
174 | * @bus: the PCI bus to query | |
175 | * @devfn: PCI device to query | |
176 | * @cap: capability code | |
177 | * | |
178 | * Like pci_find_capability() but works for pci devices that do not have a | |
179 | * pci_dev structure set up yet. | |
180 | * | |
181 | * Returns the address of the requested capability structure within the | |
182 | * device's PCI configuration space or 0 in case the device does not | |
183 | * support it. | |
184 | */ | |
185 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) | |
186 | { | |
d3bac118 | 187 | int pos; |
1da177e4 LT |
188 | u8 hdr_type; |
189 | ||
190 | pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); | |
191 | ||
d3bac118 ME |
192 | pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f); |
193 | if (pos) | |
194 | pos = __pci_find_next_cap(bus, devfn, pos, cap); | |
195 | ||
196 | return pos; | |
1da177e4 LT |
197 | } |
198 | ||
199 | /** | |
200 | * pci_find_ext_capability - Find an extended capability | |
201 | * @dev: PCI device to query | |
202 | * @cap: capability code | |
203 | * | |
204 | * Returns the address of the requested extended capability structure | |
205 | * within the device's PCI configuration space or 0 if the device does | |
206 | * not support it. Possible values for @cap: | |
207 | * | |
208 | * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting | |
209 | * %PCI_EXT_CAP_ID_VC Virtual Channel | |
210 | * %PCI_EXT_CAP_ID_DSN Device Serial Number | |
211 | * %PCI_EXT_CAP_ID_PWR Power Budgeting | |
212 | */ | |
213 | int pci_find_ext_capability(struct pci_dev *dev, int cap) | |
214 | { | |
215 | u32 header; | |
216 | int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */ | |
217 | int pos = 0x100; | |
218 | ||
219 | if (dev->cfg_size <= 256) | |
220 | return 0; | |
221 | ||
222 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
223 | return 0; | |
224 | ||
225 | /* | |
226 | * If we have no capabilities, this is indicated by cap ID, | |
227 | * cap version and next pointer all being 0. | |
228 | */ | |
229 | if (header == 0) | |
230 | return 0; | |
231 | ||
232 | while (ttl-- > 0) { | |
233 | if (PCI_EXT_CAP_ID(header) == cap) | |
234 | return pos; | |
235 | ||
236 | pos = PCI_EXT_CAP_NEXT(header); | |
237 | if (pos < 0x100) | |
238 | break; | |
239 | ||
240 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
241 | break; | |
242 | } | |
243 | ||
244 | return 0; | |
245 | } | |
3a720d72 | 246 | EXPORT_SYMBOL_GPL(pci_find_ext_capability); |
1da177e4 | 247 | |
687d5fe3 ME |
248 | static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) |
249 | { | |
250 | int rc, ttl = PCI_FIND_CAP_TTL; | |
251 | u8 cap, mask; | |
252 | ||
253 | if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST) | |
254 | mask = HT_3BIT_CAP_MASK; | |
255 | else | |
256 | mask = HT_5BIT_CAP_MASK; | |
257 | ||
258 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, | |
259 | PCI_CAP_ID_HT, &ttl); | |
260 | while (pos) { | |
261 | rc = pci_read_config_byte(dev, pos + 3, &cap); | |
262 | if (rc != PCIBIOS_SUCCESSFUL) | |
263 | return 0; | |
264 | ||
265 | if ((cap & mask) == ht_cap) | |
266 | return pos; | |
267 | ||
47a4d5be BG |
268 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, |
269 | pos + PCI_CAP_LIST_NEXT, | |
687d5fe3 ME |
270 | PCI_CAP_ID_HT, &ttl); |
271 | } | |
272 | ||
273 | return 0; | |
274 | } | |
275 | /** | |
276 | * pci_find_next_ht_capability - query a device's Hypertransport capabilities | |
277 | * @dev: PCI device to query | |
278 | * @pos: Position from which to continue searching | |
279 | * @ht_cap: Hypertransport capability code | |
280 | * | |
281 | * To be used in conjunction with pci_find_ht_capability() to search for | |
282 | * all capabilities matching @ht_cap. @pos should always be a value returned | |
283 | * from pci_find_ht_capability(). | |
284 | * | |
285 | * NB. To be 100% safe against broken PCI devices, the caller should take | |
286 | * steps to avoid an infinite loop. | |
287 | */ | |
288 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap) | |
289 | { | |
290 | return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap); | |
291 | } | |
292 | EXPORT_SYMBOL_GPL(pci_find_next_ht_capability); | |
293 | ||
294 | /** | |
295 | * pci_find_ht_capability - query a device's Hypertransport capabilities | |
296 | * @dev: PCI device to query | |
297 | * @ht_cap: Hypertransport capability code | |
298 | * | |
299 | * Tell if a device supports a given Hypertransport capability. | |
300 | * Returns an address within the device's PCI configuration space | |
301 | * or 0 in case the device does not support the request capability. | |
302 | * The address points to the PCI capability, of type PCI_CAP_ID_HT, | |
303 | * which has a Hypertransport capability matching @ht_cap. | |
304 | */ | |
305 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap) | |
306 | { | |
307 | int pos; | |
308 | ||
309 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
310 | if (pos) | |
311 | pos = __pci_find_next_ht_cap(dev, pos, ht_cap); | |
312 | ||
313 | return pos; | |
314 | } | |
315 | EXPORT_SYMBOL_GPL(pci_find_ht_capability); | |
316 | ||
4348a2dc SL |
317 | void pcie_wait_pending_transaction(struct pci_dev *dev) |
318 | { | |
319 | int pos; | |
320 | u16 reg16; | |
321 | ||
322 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
323 | if (!pos) | |
324 | return; | |
325 | while (1) { | |
326 | pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, ®16); | |
327 | if (!(reg16 & PCI_EXP_DEVSTA_TRPND)) | |
328 | break; | |
329 | cpu_relax(); | |
330 | } | |
331 | ||
332 | } | |
333 | EXPORT_SYMBOL_GPL(pcie_wait_pending_transaction); | |
334 | ||
1da177e4 LT |
335 | /** |
336 | * pci_find_parent_resource - return resource region of parent bus of given region | |
337 | * @dev: PCI device structure contains resources to be searched | |
338 | * @res: child resource record for which parent is sought | |
339 | * | |
340 | * For given resource region of given device, return the resource | |
341 | * region of parent bus the given region is contained in or where | |
342 | * it should be allocated from. | |
343 | */ | |
344 | struct resource * | |
345 | pci_find_parent_resource(const struct pci_dev *dev, struct resource *res) | |
346 | { | |
347 | const struct pci_bus *bus = dev->bus; | |
348 | int i; | |
349 | struct resource *best = NULL; | |
350 | ||
351 | for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) { | |
352 | struct resource *r = bus->resource[i]; | |
353 | if (!r) | |
354 | continue; | |
355 | if (res->start && !(res->start >= r->start && res->end <= r->end)) | |
356 | continue; /* Not contained */ | |
357 | if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM)) | |
358 | continue; /* Wrong type */ | |
359 | if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) | |
360 | return r; /* Exact match */ | |
361 | if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH)) | |
362 | best = r; /* Approximating prefetchable by non-prefetchable */ | |
363 | } | |
364 | return best; | |
365 | } | |
366 | ||
064b53db JL |
367 | /** |
368 | * pci_restore_bars - restore a devices BAR values (e.g. after wake-up) | |
369 | * @dev: PCI device to have its BARs restored | |
370 | * | |
371 | * Restore the BAR values for a given device, so as to make it | |
372 | * accessible by its driver. | |
373 | */ | |
ad668599 | 374 | static void |
064b53db JL |
375 | pci_restore_bars(struct pci_dev *dev) |
376 | { | |
377 | int i, numres; | |
378 | ||
379 | switch (dev->hdr_type) { | |
380 | case PCI_HEADER_TYPE_NORMAL: | |
381 | numres = 6; | |
382 | break; | |
383 | case PCI_HEADER_TYPE_BRIDGE: | |
384 | numres = 2; | |
385 | break; | |
386 | case PCI_HEADER_TYPE_CARDBUS: | |
387 | numres = 1; | |
388 | break; | |
389 | default: | |
390 | /* Should never get here, but just in case... */ | |
391 | return; | |
392 | } | |
393 | ||
394 | for (i = 0; i < numres; i ++) | |
395 | pci_update_resource(dev, &dev->resource[i], i); | |
396 | } | |
397 | ||
8f7020d3 RD |
398 | int (*platform_pci_set_power_state)(struct pci_dev *dev, pci_power_t t); |
399 | ||
1da177e4 LT |
400 | /** |
401 | * pci_set_power_state - Set the power state of a PCI device | |
402 | * @dev: PCI device to be suspended | |
403 | * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering | |
404 | * | |
405 | * Transition a device to a new power state, using the Power Management | |
406 | * Capabilities in the device's config space. | |
407 | * | |
408 | * RETURN VALUE: | |
409 | * -EINVAL if trying to enter a lower state than we're already in. | |
410 | * 0 if we're already in the requested state. | |
411 | * -EIO if device does not support PCI PM. | |
412 | * 0 if we can successfully change the power state. | |
413 | */ | |
1da177e4 LT |
414 | int |
415 | pci_set_power_state(struct pci_dev *dev, pci_power_t state) | |
416 | { | |
064b53db | 417 | int pm, need_restore = 0; |
1da177e4 LT |
418 | u16 pmcsr, pmc; |
419 | ||
420 | /* bound the state we're entering */ | |
421 | if (state > PCI_D3hot) | |
422 | state = PCI_D3hot; | |
423 | ||
e36c455c PM |
424 | /* |
425 | * If the device or the parent bridge can't support PCI PM, ignore | |
426 | * the request if we're doing anything besides putting it into D0 | |
427 | * (which would only happen on boot). | |
428 | */ | |
429 | if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) | |
430 | return 0; | |
431 | ||
cca03dec AL |
432 | /* find PCI PM capability in list */ |
433 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
434 | ||
435 | /* abort if the device doesn't support PM capabilities */ | |
436 | if (!pm) | |
437 | return -EIO; | |
438 | ||
1da177e4 LT |
439 | /* Validate current state: |
440 | * Can enter D0 from any state, but if we can only go deeper | |
441 | * to sleep if we're already in a low power state | |
442 | */ | |
02669492 AM |
443 | if (state != PCI_D0 && dev->current_state > state) { |
444 | printk(KERN_ERR "%s(): %s: state=%d, current state=%d\n", | |
445 | __FUNCTION__, pci_name(dev), state, dev->current_state); | |
1da177e4 | 446 | return -EINVAL; |
02669492 | 447 | } else if (dev->current_state == state) |
1da177e4 LT |
448 | return 0; /* we're already there */ |
449 | ||
ffadcc2f | 450 | |
1da177e4 | 451 | pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc); |
3fe9d19f | 452 | if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { |
1da177e4 LT |
453 | printk(KERN_DEBUG |
454 | "PCI: %s has unsupported PM cap regs version (%u)\n", | |
455 | pci_name(dev), pmc & PCI_PM_CAP_VER_MASK); | |
456 | return -EIO; | |
457 | } | |
458 | ||
459 | /* check if this device supports the desired state */ | |
3fe9d19f DR |
460 | if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1)) |
461 | return -EIO; | |
462 | else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2)) | |
463 | return -EIO; | |
1da177e4 | 464 | |
064b53db JL |
465 | pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr); |
466 | ||
32a36585 | 467 | /* If we're (effectively) in D3, force entire word to 0. |
1da177e4 LT |
468 | * This doesn't affect PME_Status, disables PME_En, and |
469 | * sets PowerState to 0. | |
470 | */ | |
32a36585 | 471 | switch (dev->current_state) { |
d3535fbb JL |
472 | case PCI_D0: |
473 | case PCI_D1: | |
474 | case PCI_D2: | |
475 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
476 | pmcsr |= state; | |
477 | break; | |
32a36585 JL |
478 | case PCI_UNKNOWN: /* Boot-up */ |
479 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot | |
480 | && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) | |
064b53db | 481 | need_restore = 1; |
32a36585 | 482 | /* Fall-through: force to D0 */ |
32a36585 | 483 | default: |
d3535fbb | 484 | pmcsr = 0; |
32a36585 | 485 | break; |
1da177e4 LT |
486 | } |
487 | ||
488 | /* enter specified state */ | |
489 | pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr); | |
490 | ||
491 | /* Mandatory power management transition delays */ | |
492 | /* see PCI PM 1.1 5.6.1 table 18 */ | |
493 | if (state == PCI_D3hot || dev->current_state == PCI_D3hot) | |
ffadcc2f | 494 | msleep(pci_pm_d3_delay); |
1da177e4 LT |
495 | else if (state == PCI_D2 || dev->current_state == PCI_D2) |
496 | udelay(200); | |
1da177e4 | 497 | |
b913100d DSL |
498 | /* |
499 | * Give firmware a chance to be called, such as ACPI _PRx, _PSx | |
d6e05edc | 500 | * Firmware method after native method ? |
b913100d DSL |
501 | */ |
502 | if (platform_pci_set_power_state) | |
503 | platform_pci_set_power_state(dev, state); | |
504 | ||
505 | dev->current_state = state; | |
064b53db JL |
506 | |
507 | /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT | |
508 | * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning | |
509 | * from D3hot to D0 _may_ perform an internal reset, thereby | |
510 | * going to "D0 Uninitialized" rather than "D0 Initialized". | |
511 | * For example, at least some versions of the 3c905B and the | |
512 | * 3c556B exhibit this behaviour. | |
513 | * | |
514 | * At least some laptop BIOSen (e.g. the Thinkpad T21) leave | |
515 | * devices in a D3hot state at boot. Consequently, we need to | |
516 | * restore at least the BARs so that the device will be | |
517 | * accessible to its driver. | |
518 | */ | |
519 | if (need_restore) | |
520 | pci_restore_bars(dev); | |
521 | ||
1da177e4 LT |
522 | return 0; |
523 | } | |
524 | ||
ab826ca4 | 525 | pci_power_t (*platform_pci_choose_state)(struct pci_dev *dev, pm_message_t state); |
0f64474b | 526 | |
1da177e4 LT |
527 | /** |
528 | * pci_choose_state - Choose the power state of a PCI device | |
529 | * @dev: PCI device to be suspended | |
530 | * @state: target sleep state for the whole system. This is the value | |
531 | * that is passed to suspend() function. | |
532 | * | |
533 | * Returns PCI power state suitable for given device and given system | |
534 | * message. | |
535 | */ | |
536 | ||
537 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) | |
538 | { | |
ab826ca4 | 539 | pci_power_t ret; |
0f64474b | 540 | |
1da177e4 LT |
541 | if (!pci_find_capability(dev, PCI_CAP_ID_PM)) |
542 | return PCI_D0; | |
543 | ||
0f64474b DSL |
544 | if (platform_pci_choose_state) { |
545 | ret = platform_pci_choose_state(dev, state); | |
ab826ca4 SL |
546 | if (ret != PCI_POWER_ERROR) |
547 | return ret; | |
0f64474b | 548 | } |
ca078bae PM |
549 | |
550 | switch (state.event) { | |
551 | case PM_EVENT_ON: | |
552 | return PCI_D0; | |
553 | case PM_EVENT_FREEZE: | |
b887d2e6 DB |
554 | case PM_EVENT_PRETHAW: |
555 | /* REVISIT both freeze and pre-thaw "should" use D0 */ | |
ca078bae PM |
556 | case PM_EVENT_SUSPEND: |
557 | return PCI_D3hot; | |
1da177e4 | 558 | default: |
b887d2e6 | 559 | printk("Unrecognized suspend event %d\n", state.event); |
1da177e4 LT |
560 | BUG(); |
561 | } | |
562 | return PCI_D0; | |
563 | } | |
564 | ||
565 | EXPORT_SYMBOL(pci_choose_state); | |
566 | ||
b56a5a23 MT |
567 | static int pci_save_pcie_state(struct pci_dev *dev) |
568 | { | |
569 | int pos, i = 0; | |
570 | struct pci_cap_saved_state *save_state; | |
571 | u16 *cap; | |
572 | ||
573 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
574 | if (pos <= 0) | |
575 | return 0; | |
576 | ||
9f35575d EB |
577 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); |
578 | if (!save_state) | |
579 | save_state = kzalloc(sizeof(*save_state) + sizeof(u16) * 4, GFP_KERNEL); | |
b56a5a23 MT |
580 | if (!save_state) { |
581 | dev_err(&dev->dev, "Out of memory in pci_save_pcie_state\n"); | |
582 | return -ENOMEM; | |
583 | } | |
584 | cap = (u16 *)&save_state->data[0]; | |
585 | ||
586 | pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]); | |
587 | pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]); | |
588 | pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]); | |
589 | pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]); | |
590 | pci_add_saved_cap(dev, save_state); | |
591 | return 0; | |
592 | } | |
593 | ||
594 | static void pci_restore_pcie_state(struct pci_dev *dev) | |
595 | { | |
596 | int i = 0, pos; | |
597 | struct pci_cap_saved_state *save_state; | |
598 | u16 *cap; | |
599 | ||
600 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); | |
601 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
602 | if (!save_state || pos <= 0) | |
603 | return; | |
604 | cap = (u16 *)&save_state->data[0]; | |
605 | ||
606 | pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]); | |
607 | pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]); | |
608 | pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]); | |
609 | pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]); | |
b56a5a23 MT |
610 | } |
611 | ||
cc692a5f SH |
612 | |
613 | static int pci_save_pcix_state(struct pci_dev *dev) | |
614 | { | |
615 | int pos, i = 0; | |
616 | struct pci_cap_saved_state *save_state; | |
617 | u16 *cap; | |
618 | ||
619 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
620 | if (pos <= 0) | |
621 | return 0; | |
622 | ||
9f35575d EB |
623 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); |
624 | if (!save_state) | |
625 | save_state = kzalloc(sizeof(*save_state) + sizeof(u16), GFP_KERNEL); | |
cc692a5f SH |
626 | if (!save_state) { |
627 | dev_err(&dev->dev, "Out of memory in pci_save_pcie_state\n"); | |
628 | return -ENOMEM; | |
629 | } | |
630 | cap = (u16 *)&save_state->data[0]; | |
631 | ||
632 | pci_read_config_word(dev, pos + PCI_X_CMD, &cap[i++]); | |
633 | pci_add_saved_cap(dev, save_state); | |
634 | return 0; | |
635 | } | |
636 | ||
637 | static void pci_restore_pcix_state(struct pci_dev *dev) | |
638 | { | |
639 | int i = 0, pos; | |
640 | struct pci_cap_saved_state *save_state; | |
641 | u16 *cap; | |
642 | ||
643 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); | |
644 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
645 | if (!save_state || pos <= 0) | |
646 | return; | |
647 | cap = (u16 *)&save_state->data[0]; | |
648 | ||
649 | pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]); | |
cc692a5f SH |
650 | } |
651 | ||
652 | ||
1da177e4 LT |
653 | /** |
654 | * pci_save_state - save the PCI configuration space of a device before suspending | |
655 | * @dev: - PCI device that we're dealing with | |
1da177e4 LT |
656 | */ |
657 | int | |
658 | pci_save_state(struct pci_dev *dev) | |
659 | { | |
660 | int i; | |
661 | /* XXX: 100% dword access ok here? */ | |
662 | for (i = 0; i < 16; i++) | |
663 | pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]); | |
b56a5a23 MT |
664 | if ((i = pci_save_pcie_state(dev)) != 0) |
665 | return i; | |
cc692a5f SH |
666 | if ((i = pci_save_pcix_state(dev)) != 0) |
667 | return i; | |
1da177e4 LT |
668 | return 0; |
669 | } | |
670 | ||
671 | /** | |
672 | * pci_restore_state - Restore the saved state of a PCI device | |
673 | * @dev: - PCI device that we're dealing with | |
1da177e4 LT |
674 | */ |
675 | int | |
676 | pci_restore_state(struct pci_dev *dev) | |
677 | { | |
678 | int i; | |
b4482a4b | 679 | u32 val; |
1da177e4 | 680 | |
b56a5a23 MT |
681 | /* PCI Express register must be restored first */ |
682 | pci_restore_pcie_state(dev); | |
683 | ||
8b8c8d28 YL |
684 | /* |
685 | * The Base Address register should be programmed before the command | |
686 | * register(s) | |
687 | */ | |
688 | for (i = 15; i >= 0; i--) { | |
04d9c1a1 DJ |
689 | pci_read_config_dword(dev, i * 4, &val); |
690 | if (val != dev->saved_config_space[i]) { | |
691 | printk(KERN_DEBUG "PM: Writing back config space on " | |
692 | "device %s at offset %x (was %x, writing %x)\n", | |
693 | pci_name(dev), i, | |
694 | val, (int)dev->saved_config_space[i]); | |
695 | pci_write_config_dword(dev,i * 4, | |
696 | dev->saved_config_space[i]); | |
697 | } | |
698 | } | |
cc692a5f | 699 | pci_restore_pcix_state(dev); |
41017f0c | 700 | pci_restore_msi_state(dev); |
8fed4b65 | 701 | |
1da177e4 LT |
702 | return 0; |
703 | } | |
704 | ||
38cc1302 HS |
705 | static int do_pci_enable_device(struct pci_dev *dev, int bars) |
706 | { | |
707 | int err; | |
708 | ||
709 | err = pci_set_power_state(dev, PCI_D0); | |
710 | if (err < 0 && err != -EIO) | |
711 | return err; | |
712 | err = pcibios_enable_device(dev, bars); | |
713 | if (err < 0) | |
714 | return err; | |
715 | pci_fixup_device(pci_fixup_enable, dev); | |
716 | ||
717 | return 0; | |
718 | } | |
719 | ||
720 | /** | |
0b62e13b | 721 | * pci_reenable_device - Resume abandoned device |
38cc1302 HS |
722 | * @dev: PCI device to be resumed |
723 | * | |
724 | * Note this function is a backend of pci_default_resume and is not supposed | |
725 | * to be called by normal code, write proper resume handler and use it instead. | |
726 | */ | |
0b62e13b | 727 | int pci_reenable_device(struct pci_dev *dev) |
38cc1302 HS |
728 | { |
729 | if (atomic_read(&dev->enable_cnt)) | |
730 | return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); | |
731 | return 0; | |
732 | } | |
733 | ||
1da177e4 LT |
734 | /** |
735 | * pci_enable_device_bars - Initialize some of a device for use | |
736 | * @dev: PCI device to be initialized | |
737 | * @bars: bitmask of BAR's that must be configured | |
738 | * | |
739 | * Initialize device before it's used by a driver. Ask low-level code | |
9fb625c3 | 740 | * to enable selected I/O and memory resources. Wake up the device if it |
1da177e4 LT |
741 | * was suspended. Beware, this function can fail. |
742 | */ | |
1da177e4 LT |
743 | int |
744 | pci_enable_device_bars(struct pci_dev *dev, int bars) | |
745 | { | |
746 | int err; | |
747 | ||
9fb625c3 HS |
748 | if (atomic_add_return(1, &dev->enable_cnt) > 1) |
749 | return 0; /* already enabled */ | |
750 | ||
38cc1302 | 751 | err = do_pci_enable_device(dev, bars); |
95a62965 | 752 | if (err < 0) |
38cc1302 | 753 | atomic_dec(&dev->enable_cnt); |
9fb625c3 | 754 | return err; |
1da177e4 LT |
755 | } |
756 | ||
bae94d02 IPG |
757 | /** |
758 | * pci_enable_device - Initialize device before it's used by a driver. | |
759 | * @dev: PCI device to be initialized | |
760 | * | |
761 | * Initialize device before it's used by a driver. Ask low-level code | |
762 | * to enable I/O and memory. Wake up the device if it was suspended. | |
763 | * Beware, this function can fail. | |
764 | * | |
765 | * Note we don't actually enable the device many times if we call | |
766 | * this function repeatedly (we just increment the count). | |
767 | */ | |
768 | int pci_enable_device(struct pci_dev *dev) | |
769 | { | |
9fb625c3 | 770 | return pci_enable_device_bars(dev, (1 << PCI_NUM_RESOURCES) - 1); |
bae94d02 IPG |
771 | } |
772 | ||
9ac7849e TH |
773 | /* |
774 | * Managed PCI resources. This manages device on/off, intx/msi/msix | |
775 | * on/off and BAR regions. pci_dev itself records msi/msix status, so | |
776 | * there's no need to track it separately. pci_devres is initialized | |
777 | * when a device is enabled using managed PCI device enable interface. | |
778 | */ | |
779 | struct pci_devres { | |
7f375f32 TH |
780 | unsigned int enabled:1; |
781 | unsigned int pinned:1; | |
9ac7849e TH |
782 | unsigned int orig_intx:1; |
783 | unsigned int restore_intx:1; | |
784 | u32 region_mask; | |
785 | }; | |
786 | ||
787 | static void pcim_release(struct device *gendev, void *res) | |
788 | { | |
789 | struct pci_dev *dev = container_of(gendev, struct pci_dev, dev); | |
790 | struct pci_devres *this = res; | |
791 | int i; | |
792 | ||
793 | if (dev->msi_enabled) | |
794 | pci_disable_msi(dev); | |
795 | if (dev->msix_enabled) | |
796 | pci_disable_msix(dev); | |
797 | ||
798 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) | |
799 | if (this->region_mask & (1 << i)) | |
800 | pci_release_region(dev, i); | |
801 | ||
802 | if (this->restore_intx) | |
803 | pci_intx(dev, this->orig_intx); | |
804 | ||
7f375f32 | 805 | if (this->enabled && !this->pinned) |
9ac7849e TH |
806 | pci_disable_device(dev); |
807 | } | |
808 | ||
809 | static struct pci_devres * get_pci_dr(struct pci_dev *pdev) | |
810 | { | |
811 | struct pci_devres *dr, *new_dr; | |
812 | ||
813 | dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
814 | if (dr) | |
815 | return dr; | |
816 | ||
817 | new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL); | |
818 | if (!new_dr) | |
819 | return NULL; | |
820 | return devres_get(&pdev->dev, new_dr, NULL, NULL); | |
821 | } | |
822 | ||
823 | static struct pci_devres * find_pci_dr(struct pci_dev *pdev) | |
824 | { | |
825 | if (pci_is_managed(pdev)) | |
826 | return devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
827 | return NULL; | |
828 | } | |
829 | ||
830 | /** | |
831 | * pcim_enable_device - Managed pci_enable_device() | |
832 | * @pdev: PCI device to be initialized | |
833 | * | |
834 | * Managed pci_enable_device(). | |
835 | */ | |
836 | int pcim_enable_device(struct pci_dev *pdev) | |
837 | { | |
838 | struct pci_devres *dr; | |
839 | int rc; | |
840 | ||
841 | dr = get_pci_dr(pdev); | |
842 | if (unlikely(!dr)) | |
843 | return -ENOMEM; | |
7f375f32 | 844 | WARN_ON(!!dr->enabled); |
9ac7849e TH |
845 | |
846 | rc = pci_enable_device(pdev); | |
847 | if (!rc) { | |
848 | pdev->is_managed = 1; | |
7f375f32 | 849 | dr->enabled = 1; |
9ac7849e TH |
850 | } |
851 | return rc; | |
852 | } | |
853 | ||
854 | /** | |
855 | * pcim_pin_device - Pin managed PCI device | |
856 | * @pdev: PCI device to pin | |
857 | * | |
858 | * Pin managed PCI device @pdev. Pinned device won't be disabled on | |
859 | * driver detach. @pdev must have been enabled with | |
860 | * pcim_enable_device(). | |
861 | */ | |
862 | void pcim_pin_device(struct pci_dev *pdev) | |
863 | { | |
864 | struct pci_devres *dr; | |
865 | ||
866 | dr = find_pci_dr(pdev); | |
7f375f32 | 867 | WARN_ON(!dr || !dr->enabled); |
9ac7849e | 868 | if (dr) |
7f375f32 | 869 | dr->pinned = 1; |
9ac7849e TH |
870 | } |
871 | ||
1da177e4 LT |
872 | /** |
873 | * pcibios_disable_device - disable arch specific PCI resources for device dev | |
874 | * @dev: the PCI device to disable | |
875 | * | |
876 | * Disables architecture specific PCI resources for the device. This | |
877 | * is the default implementation. Architecture implementations can | |
878 | * override this. | |
879 | */ | |
880 | void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {} | |
881 | ||
882 | /** | |
883 | * pci_disable_device - Disable PCI device after use | |
884 | * @dev: PCI device to be disabled | |
885 | * | |
886 | * Signal to the system that the PCI device is not in use by the system | |
887 | * anymore. This only involves disabling PCI bus-mastering, if active. | |
bae94d02 IPG |
888 | * |
889 | * Note we don't actually disable the device until all callers of | |
890 | * pci_device_enable() have called pci_device_disable(). | |
1da177e4 LT |
891 | */ |
892 | void | |
893 | pci_disable_device(struct pci_dev *dev) | |
894 | { | |
9ac7849e | 895 | struct pci_devres *dr; |
1da177e4 | 896 | u16 pci_command; |
99dc804d | 897 | |
9ac7849e TH |
898 | dr = find_pci_dr(dev); |
899 | if (dr) | |
7f375f32 | 900 | dr->enabled = 0; |
9ac7849e | 901 | |
bae94d02 IPG |
902 | if (atomic_sub_return(1, &dev->enable_cnt) != 0) |
903 | return; | |
904 | ||
4348a2dc SL |
905 | /* Wait for all transactions are finished before disabling the device */ |
906 | pcie_wait_pending_transaction(dev); | |
907 | ||
1da177e4 LT |
908 | pci_read_config_word(dev, PCI_COMMAND, &pci_command); |
909 | if (pci_command & PCI_COMMAND_MASTER) { | |
910 | pci_command &= ~PCI_COMMAND_MASTER; | |
911 | pci_write_config_word(dev, PCI_COMMAND, pci_command); | |
912 | } | |
ceb43744 | 913 | dev->is_busmaster = 0; |
1da177e4 LT |
914 | |
915 | pcibios_disable_device(dev); | |
916 | } | |
917 | ||
f7bdd12d BK |
918 | /** |
919 | * pcibios_set_pcie_reset_state - set reset state for device dev | |
920 | * @dev: the PCI-E device reset | |
921 | * @state: Reset state to enter into | |
922 | * | |
923 | * | |
924 | * Sets the PCI-E reset state for the device. This is the default | |
925 | * implementation. Architecture implementations can override this. | |
926 | */ | |
927 | int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev, | |
928 | enum pcie_reset_state state) | |
929 | { | |
930 | return -EINVAL; | |
931 | } | |
932 | ||
933 | /** | |
934 | * pci_set_pcie_reset_state - set reset state for device dev | |
935 | * @dev: the PCI-E device reset | |
936 | * @state: Reset state to enter into | |
937 | * | |
938 | * | |
939 | * Sets the PCI reset state for the device. | |
940 | */ | |
941 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) | |
942 | { | |
943 | return pcibios_set_pcie_reset_state(dev, state); | |
944 | } | |
945 | ||
1da177e4 | 946 | /** |
075c1771 DB |
947 | * pci_enable_wake - enable PCI device as wakeup event source |
948 | * @dev: PCI device affected | |
949 | * @state: PCI state from which device will issue wakeup events | |
950 | * @enable: True to enable event generation; false to disable | |
951 | * | |
952 | * This enables the device as a wakeup event source, or disables it. | |
953 | * When such events involves platform-specific hooks, those hooks are | |
954 | * called automatically by this routine. | |
955 | * | |
956 | * Devices with legacy power management (no standard PCI PM capabilities) | |
957 | * always require such platform hooks. Depending on the platform, devices | |
958 | * supporting the standard PCI PME# signal may require such platform hooks; | |
959 | * they always update bits in config space to allow PME# generation. | |
960 | * | |
961 | * -EIO is returned if the device can't ever be a wakeup event source. | |
962 | * -EINVAL is returned if the device can't generate wakeup events from | |
963 | * the specified PCI state. Returns zero if the operation is successful. | |
1da177e4 LT |
964 | */ |
965 | int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable) | |
966 | { | |
967 | int pm; | |
075c1771 | 968 | int status; |
1da177e4 LT |
969 | u16 value; |
970 | ||
075c1771 DB |
971 | /* Note that drivers should verify device_may_wakeup(&dev->dev) |
972 | * before calling this function. Platform code should report | |
973 | * errors when drivers try to enable wakeup on devices that | |
974 | * can't issue wakeups, or on which wakeups were disabled by | |
975 | * userspace updating the /sys/devices.../power/wakeup file. | |
976 | */ | |
977 | ||
978 | status = call_platform_enable_wakeup(&dev->dev, enable); | |
979 | ||
1da177e4 LT |
980 | /* find PCI PM capability in list */ |
981 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
982 | ||
075c1771 DB |
983 | /* If device doesn't support PM Capabilities, but caller wants to |
984 | * disable wake events, it's a NOP. Otherwise fail unless the | |
985 | * platform hooks handled this legacy device already. | |
986 | */ | |
987 | if (!pm) | |
988 | return enable ? status : 0; | |
1da177e4 LT |
989 | |
990 | /* Check device's ability to generate PME# */ | |
991 | pci_read_config_word(dev,pm+PCI_PM_PMC,&value); | |
992 | ||
993 | value &= PCI_PM_CAP_PME_MASK; | |
994 | value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */ | |
995 | ||
996 | /* Check if it can generate PME# from requested state. */ | |
075c1771 DB |
997 | if (!value || !(value & (1 << state))) { |
998 | /* if it can't, revert what the platform hook changed, | |
999 | * always reporting the base "EINVAL, can't PME#" error | |
1000 | */ | |
1001 | if (enable) | |
1002 | call_platform_enable_wakeup(&dev->dev, 0); | |
1da177e4 | 1003 | return enable ? -EINVAL : 0; |
075c1771 | 1004 | } |
1da177e4 LT |
1005 | |
1006 | pci_read_config_word(dev, pm + PCI_PM_CTRL, &value); | |
1007 | ||
1008 | /* Clear PME_Status by writing 1 to it and enable PME# */ | |
1009 | value |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; | |
1010 | ||
1011 | if (!enable) | |
1012 | value &= ~PCI_PM_CTRL_PME_ENABLE; | |
1013 | ||
1014 | pci_write_config_word(dev, pm + PCI_PM_CTRL, value); | |
075c1771 | 1015 | |
1da177e4 LT |
1016 | return 0; |
1017 | } | |
1018 | ||
1019 | int | |
1020 | pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) | |
1021 | { | |
1022 | u8 pin; | |
1023 | ||
514d207d | 1024 | pin = dev->pin; |
1da177e4 LT |
1025 | if (!pin) |
1026 | return -1; | |
1027 | pin--; | |
1028 | while (dev->bus->self) { | |
1029 | pin = (pin + PCI_SLOT(dev->devfn)) % 4; | |
1030 | dev = dev->bus->self; | |
1031 | } | |
1032 | *bridge = dev; | |
1033 | return pin; | |
1034 | } | |
1035 | ||
1036 | /** | |
1037 | * pci_release_region - Release a PCI bar | |
1038 | * @pdev: PCI device whose resources were previously reserved by pci_request_region | |
1039 | * @bar: BAR to release | |
1040 | * | |
1041 | * Releases the PCI I/O and memory resources previously reserved by a | |
1042 | * successful call to pci_request_region. Call this function only | |
1043 | * after all use of the PCI regions has ceased. | |
1044 | */ | |
1045 | void pci_release_region(struct pci_dev *pdev, int bar) | |
1046 | { | |
9ac7849e TH |
1047 | struct pci_devres *dr; |
1048 | ||
1da177e4 LT |
1049 | if (pci_resource_len(pdev, bar) == 0) |
1050 | return; | |
1051 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) | |
1052 | release_region(pci_resource_start(pdev, bar), | |
1053 | pci_resource_len(pdev, bar)); | |
1054 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) | |
1055 | release_mem_region(pci_resource_start(pdev, bar), | |
1056 | pci_resource_len(pdev, bar)); | |
9ac7849e TH |
1057 | |
1058 | dr = find_pci_dr(pdev); | |
1059 | if (dr) | |
1060 | dr->region_mask &= ~(1 << bar); | |
1da177e4 LT |
1061 | } |
1062 | ||
1063 | /** | |
1064 | * pci_request_region - Reserved PCI I/O and memory resource | |
1065 | * @pdev: PCI device whose resources are to be reserved | |
1066 | * @bar: BAR to be reserved | |
1067 | * @res_name: Name to be associated with resource. | |
1068 | * | |
1069 | * Mark the PCI region associated with PCI device @pdev BR @bar as | |
1070 | * being reserved by owner @res_name. Do not access any | |
1071 | * address inside the PCI regions unless this call returns | |
1072 | * successfully. | |
1073 | * | |
1074 | * Returns 0 on success, or %EBUSY on error. A warning | |
1075 | * message is also printed on failure. | |
1076 | */ | |
3c990e92 | 1077 | int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) |
1da177e4 | 1078 | { |
9ac7849e TH |
1079 | struct pci_devres *dr; |
1080 | ||
1da177e4 LT |
1081 | if (pci_resource_len(pdev, bar) == 0) |
1082 | return 0; | |
1083 | ||
1084 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { | |
1085 | if (!request_region(pci_resource_start(pdev, bar), | |
1086 | pci_resource_len(pdev, bar), res_name)) | |
1087 | goto err_out; | |
1088 | } | |
1089 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { | |
1090 | if (!request_mem_region(pci_resource_start(pdev, bar), | |
1091 | pci_resource_len(pdev, bar), res_name)) | |
1092 | goto err_out; | |
1093 | } | |
9ac7849e TH |
1094 | |
1095 | dr = find_pci_dr(pdev); | |
1096 | if (dr) | |
1097 | dr->region_mask |= 1 << bar; | |
1098 | ||
1da177e4 LT |
1099 | return 0; |
1100 | ||
1101 | err_out: | |
1396a8c3 GKH |
1102 | printk (KERN_WARNING "PCI: Unable to reserve %s region #%d:%llx@%llx " |
1103 | "for device %s\n", | |
1da177e4 LT |
1104 | pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem", |
1105 | bar + 1, /* PCI BAR # */ | |
1396a8c3 GKH |
1106 | (unsigned long long)pci_resource_len(pdev, bar), |
1107 | (unsigned long long)pci_resource_start(pdev, bar), | |
1da177e4 LT |
1108 | pci_name(pdev)); |
1109 | return -EBUSY; | |
1110 | } | |
1111 | ||
c87deff7 HS |
1112 | /** |
1113 | * pci_release_selected_regions - Release selected PCI I/O and memory resources | |
1114 | * @pdev: PCI device whose resources were previously reserved | |
1115 | * @bars: Bitmask of BARs to be released | |
1116 | * | |
1117 | * Release selected PCI I/O and memory resources previously reserved. | |
1118 | * Call this function only after all use of the PCI regions has ceased. | |
1119 | */ | |
1120 | void pci_release_selected_regions(struct pci_dev *pdev, int bars) | |
1121 | { | |
1122 | int i; | |
1123 | ||
1124 | for (i = 0; i < 6; i++) | |
1125 | if (bars & (1 << i)) | |
1126 | pci_release_region(pdev, i); | |
1127 | } | |
1128 | ||
1129 | /** | |
1130 | * pci_request_selected_regions - Reserve selected PCI I/O and memory resources | |
1131 | * @pdev: PCI device whose resources are to be reserved | |
1132 | * @bars: Bitmask of BARs to be requested | |
1133 | * @res_name: Name to be associated with resource | |
1134 | */ | |
1135 | int pci_request_selected_regions(struct pci_dev *pdev, int bars, | |
1136 | const char *res_name) | |
1137 | { | |
1138 | int i; | |
1139 | ||
1140 | for (i = 0; i < 6; i++) | |
1141 | if (bars & (1 << i)) | |
1142 | if(pci_request_region(pdev, i, res_name)) | |
1143 | goto err_out; | |
1144 | return 0; | |
1145 | ||
1146 | err_out: | |
1147 | while(--i >= 0) | |
1148 | if (bars & (1 << i)) | |
1149 | pci_release_region(pdev, i); | |
1150 | ||
1151 | return -EBUSY; | |
1152 | } | |
1da177e4 LT |
1153 | |
1154 | /** | |
1155 | * pci_release_regions - Release reserved PCI I/O and memory resources | |
1156 | * @pdev: PCI device whose resources were previously reserved by pci_request_regions | |
1157 | * | |
1158 | * Releases all PCI I/O and memory resources previously reserved by a | |
1159 | * successful call to pci_request_regions. Call this function only | |
1160 | * after all use of the PCI regions has ceased. | |
1161 | */ | |
1162 | ||
1163 | void pci_release_regions(struct pci_dev *pdev) | |
1164 | { | |
c87deff7 | 1165 | pci_release_selected_regions(pdev, (1 << 6) - 1); |
1da177e4 LT |
1166 | } |
1167 | ||
1168 | /** | |
1169 | * pci_request_regions - Reserved PCI I/O and memory resources | |
1170 | * @pdev: PCI device whose resources are to be reserved | |
1171 | * @res_name: Name to be associated with resource. | |
1172 | * | |
1173 | * Mark all PCI regions associated with PCI device @pdev as | |
1174 | * being reserved by owner @res_name. Do not access any | |
1175 | * address inside the PCI regions unless this call returns | |
1176 | * successfully. | |
1177 | * | |
1178 | * Returns 0 on success, or %EBUSY on error. A warning | |
1179 | * message is also printed on failure. | |
1180 | */ | |
3c990e92 | 1181 | int pci_request_regions(struct pci_dev *pdev, const char *res_name) |
1da177e4 | 1182 | { |
c87deff7 | 1183 | return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name); |
1da177e4 LT |
1184 | } |
1185 | ||
1186 | /** | |
1187 | * pci_set_master - enables bus-mastering for device dev | |
1188 | * @dev: the PCI device to enable | |
1189 | * | |
1190 | * Enables bus-mastering on the device and calls pcibios_set_master() | |
1191 | * to do the needed arch specific settings. | |
1192 | */ | |
1193 | void | |
1194 | pci_set_master(struct pci_dev *dev) | |
1195 | { | |
1196 | u16 cmd; | |
1197 | ||
1198 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1199 | if (! (cmd & PCI_COMMAND_MASTER)) { | |
1200 | pr_debug("PCI: Enabling bus mastering for device %s\n", pci_name(dev)); | |
1201 | cmd |= PCI_COMMAND_MASTER; | |
1202 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1203 | } | |
1204 | dev->is_busmaster = 1; | |
1205 | pcibios_set_master(dev); | |
1206 | } | |
1207 | ||
edb2d97e MW |
1208 | #ifdef PCI_DISABLE_MWI |
1209 | int pci_set_mwi(struct pci_dev *dev) | |
1210 | { | |
1211 | return 0; | |
1212 | } | |
1213 | ||
694625c0 RD |
1214 | int pci_try_set_mwi(struct pci_dev *dev) |
1215 | { | |
1216 | return 0; | |
1217 | } | |
1218 | ||
edb2d97e MW |
1219 | void pci_clear_mwi(struct pci_dev *dev) |
1220 | { | |
1221 | } | |
1222 | ||
1223 | #else | |
ebf5a248 MW |
1224 | |
1225 | #ifndef PCI_CACHE_LINE_BYTES | |
1226 | #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES | |
1227 | #endif | |
1228 | ||
1da177e4 | 1229 | /* This can be overridden by arch code. */ |
ebf5a248 MW |
1230 | /* Don't forget this is measured in 32-bit words, not bytes */ |
1231 | u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4; | |
1da177e4 LT |
1232 | |
1233 | /** | |
edb2d97e MW |
1234 | * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed |
1235 | * @dev: the PCI device for which MWI is to be enabled | |
1da177e4 | 1236 | * |
edb2d97e MW |
1237 | * Helper function for pci_set_mwi. |
1238 | * Originally copied from drivers/net/acenic.c. | |
1da177e4 LT |
1239 | * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. |
1240 | * | |
1241 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
1242 | */ | |
1243 | static int | |
edb2d97e | 1244 | pci_set_cacheline_size(struct pci_dev *dev) |
1da177e4 LT |
1245 | { |
1246 | u8 cacheline_size; | |
1247 | ||
1248 | if (!pci_cache_line_size) | |
1249 | return -EINVAL; /* The system doesn't support MWI. */ | |
1250 | ||
1251 | /* Validate current setting: the PCI_CACHE_LINE_SIZE must be | |
1252 | equal to or multiple of the right value. */ | |
1253 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
1254 | if (cacheline_size >= pci_cache_line_size && | |
1255 | (cacheline_size % pci_cache_line_size) == 0) | |
1256 | return 0; | |
1257 | ||
1258 | /* Write the correct value. */ | |
1259 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); | |
1260 | /* Read it back. */ | |
1261 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
1262 | if (cacheline_size == pci_cache_line_size) | |
1263 | return 0; | |
1264 | ||
1265 | printk(KERN_DEBUG "PCI: cache line size of %d is not supported " | |
1266 | "by device %s\n", pci_cache_line_size << 2, pci_name(dev)); | |
1267 | ||
1268 | return -EINVAL; | |
1269 | } | |
1da177e4 LT |
1270 | |
1271 | /** | |
1272 | * pci_set_mwi - enables memory-write-invalidate PCI transaction | |
1273 | * @dev: the PCI device for which MWI is enabled | |
1274 | * | |
694625c0 | 1275 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. |
1da177e4 LT |
1276 | * |
1277 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
1278 | */ | |
1279 | int | |
1280 | pci_set_mwi(struct pci_dev *dev) | |
1281 | { | |
1282 | int rc; | |
1283 | u16 cmd; | |
1284 | ||
edb2d97e | 1285 | rc = pci_set_cacheline_size(dev); |
1da177e4 LT |
1286 | if (rc) |
1287 | return rc; | |
1288 | ||
1289 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1290 | if (! (cmd & PCI_COMMAND_INVALIDATE)) { | |
694625c0 RD |
1291 | pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n", |
1292 | pci_name(dev)); | |
1da177e4 LT |
1293 | cmd |= PCI_COMMAND_INVALIDATE; |
1294 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1295 | } | |
1296 | ||
1297 | return 0; | |
1298 | } | |
1299 | ||
694625c0 RD |
1300 | /** |
1301 | * pci_try_set_mwi - enables memory-write-invalidate PCI transaction | |
1302 | * @dev: the PCI device for which MWI is enabled | |
1303 | * | |
1304 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. | |
1305 | * Callers are not required to check the return value. | |
1306 | * | |
1307 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
1308 | */ | |
1309 | int pci_try_set_mwi(struct pci_dev *dev) | |
1310 | { | |
1311 | int rc = pci_set_mwi(dev); | |
1312 | return rc; | |
1313 | } | |
1314 | ||
1da177e4 LT |
1315 | /** |
1316 | * pci_clear_mwi - disables Memory-Write-Invalidate for device dev | |
1317 | * @dev: the PCI device to disable | |
1318 | * | |
1319 | * Disables PCI Memory-Write-Invalidate transaction on the device | |
1320 | */ | |
1321 | void | |
1322 | pci_clear_mwi(struct pci_dev *dev) | |
1323 | { | |
1324 | u16 cmd; | |
1325 | ||
1326 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1327 | if (cmd & PCI_COMMAND_INVALIDATE) { | |
1328 | cmd &= ~PCI_COMMAND_INVALIDATE; | |
1329 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1330 | } | |
1331 | } | |
edb2d97e | 1332 | #endif /* ! PCI_DISABLE_MWI */ |
1da177e4 | 1333 | |
a04ce0ff BR |
1334 | /** |
1335 | * pci_intx - enables/disables PCI INTx for device dev | |
8f7020d3 RD |
1336 | * @pdev: the PCI device to operate on |
1337 | * @enable: boolean: whether to enable or disable PCI INTx | |
a04ce0ff BR |
1338 | * |
1339 | * Enables/disables PCI INTx for device dev | |
1340 | */ | |
1341 | void | |
1342 | pci_intx(struct pci_dev *pdev, int enable) | |
1343 | { | |
1344 | u16 pci_command, new; | |
1345 | ||
1346 | pci_read_config_word(pdev, PCI_COMMAND, &pci_command); | |
1347 | ||
1348 | if (enable) { | |
1349 | new = pci_command & ~PCI_COMMAND_INTX_DISABLE; | |
1350 | } else { | |
1351 | new = pci_command | PCI_COMMAND_INTX_DISABLE; | |
1352 | } | |
1353 | ||
1354 | if (new != pci_command) { | |
9ac7849e TH |
1355 | struct pci_devres *dr; |
1356 | ||
2fd9d74b | 1357 | pci_write_config_word(pdev, PCI_COMMAND, new); |
9ac7849e TH |
1358 | |
1359 | dr = find_pci_dr(pdev); | |
1360 | if (dr && !dr->restore_intx) { | |
1361 | dr->restore_intx = 1; | |
1362 | dr->orig_intx = !enable; | |
1363 | } | |
a04ce0ff BR |
1364 | } |
1365 | } | |
1366 | ||
f5f2b131 EB |
1367 | /** |
1368 | * pci_msi_off - disables any msi or msix capabilities | |
8d7d86e9 | 1369 | * @dev: the PCI device to operate on |
f5f2b131 EB |
1370 | * |
1371 | * If you want to use msi see pci_enable_msi and friends. | |
1372 | * This is a lower level primitive that allows us to disable | |
1373 | * msi operation at the device level. | |
1374 | */ | |
1375 | void pci_msi_off(struct pci_dev *dev) | |
1376 | { | |
1377 | int pos; | |
1378 | u16 control; | |
1379 | ||
1380 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
1381 | if (pos) { | |
1382 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
1383 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
1384 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
1385 | } | |
1386 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
1387 | if (pos) { | |
1388 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
1389 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
1390 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
1391 | } | |
1392 | } | |
1393 | ||
1da177e4 LT |
1394 | #ifndef HAVE_ARCH_PCI_SET_DMA_MASK |
1395 | /* | |
1396 | * These can be overridden by arch-specific implementations | |
1397 | */ | |
1398 | int | |
1399 | pci_set_dma_mask(struct pci_dev *dev, u64 mask) | |
1400 | { | |
1401 | if (!pci_dma_supported(dev, mask)) | |
1402 | return -EIO; | |
1403 | ||
1404 | dev->dma_mask = mask; | |
1405 | ||
1406 | return 0; | |
1407 | } | |
1408 | ||
1da177e4 LT |
1409 | int |
1410 | pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) | |
1411 | { | |
1412 | if (!pci_dma_supported(dev, mask)) | |
1413 | return -EIO; | |
1414 | ||
1415 | dev->dev.coherent_dma_mask = mask; | |
1416 | ||
1417 | return 0; | |
1418 | } | |
1419 | #endif | |
c87deff7 | 1420 | |
d556ad4b PO |
1421 | /** |
1422 | * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count | |
1423 | * @dev: PCI device to query | |
1424 | * | |
1425 | * Returns mmrbc: maximum designed memory read count in bytes | |
1426 | * or appropriate error value. | |
1427 | */ | |
1428 | int pcix_get_max_mmrbc(struct pci_dev *dev) | |
1429 | { | |
b7b095c1 | 1430 | int err, cap; |
d556ad4b PO |
1431 | u32 stat; |
1432 | ||
1433 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
1434 | if (!cap) | |
1435 | return -EINVAL; | |
1436 | ||
1437 | err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat); | |
1438 | if (err) | |
1439 | return -EINVAL; | |
1440 | ||
b7b095c1 | 1441 | return (stat & PCI_X_STATUS_MAX_READ) >> 12; |
d556ad4b PO |
1442 | } |
1443 | EXPORT_SYMBOL(pcix_get_max_mmrbc); | |
1444 | ||
1445 | /** | |
1446 | * pcix_get_mmrbc - get PCI-X maximum memory read byte count | |
1447 | * @dev: PCI device to query | |
1448 | * | |
1449 | * Returns mmrbc: maximum memory read count in bytes | |
1450 | * or appropriate error value. | |
1451 | */ | |
1452 | int pcix_get_mmrbc(struct pci_dev *dev) | |
1453 | { | |
1454 | int ret, cap; | |
1455 | u32 cmd; | |
1456 | ||
1457 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
1458 | if (!cap) | |
1459 | return -EINVAL; | |
1460 | ||
1461 | ret = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd); | |
1462 | if (!ret) | |
1463 | ret = 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2); | |
1464 | ||
1465 | return ret; | |
1466 | } | |
1467 | EXPORT_SYMBOL(pcix_get_mmrbc); | |
1468 | ||
1469 | /** | |
1470 | * pcix_set_mmrbc - set PCI-X maximum memory read byte count | |
1471 | * @dev: PCI device to query | |
1472 | * @mmrbc: maximum memory read count in bytes | |
1473 | * valid values are 512, 1024, 2048, 4096 | |
1474 | * | |
1475 | * If possible sets maximum memory read byte count, some bridges have erratas | |
1476 | * that prevent this. | |
1477 | */ | |
1478 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) | |
1479 | { | |
1480 | int cap, err = -EINVAL; | |
1481 | u32 stat, cmd, v, o; | |
1482 | ||
229f5afd | 1483 | if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc)) |
d556ad4b PO |
1484 | goto out; |
1485 | ||
1486 | v = ffs(mmrbc) - 10; | |
1487 | ||
1488 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
1489 | if (!cap) | |
1490 | goto out; | |
1491 | ||
1492 | err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat); | |
1493 | if (err) | |
1494 | goto out; | |
1495 | ||
1496 | if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21) | |
1497 | return -E2BIG; | |
1498 | ||
1499 | err = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd); | |
1500 | if (err) | |
1501 | goto out; | |
1502 | ||
1503 | o = (cmd & PCI_X_CMD_MAX_READ) >> 2; | |
1504 | if (o != v) { | |
1505 | if (v > o && dev->bus && | |
1506 | (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) | |
1507 | return -EIO; | |
1508 | ||
1509 | cmd &= ~PCI_X_CMD_MAX_READ; | |
1510 | cmd |= v << 2; | |
1511 | err = pci_write_config_dword(dev, cap + PCI_X_CMD, cmd); | |
1512 | } | |
1513 | out: | |
1514 | return err; | |
1515 | } | |
1516 | EXPORT_SYMBOL(pcix_set_mmrbc); | |
1517 | ||
1518 | /** | |
1519 | * pcie_get_readrq - get PCI Express read request size | |
1520 | * @dev: PCI device to query | |
1521 | * | |
1522 | * Returns maximum memory read request in bytes | |
1523 | * or appropriate error value. | |
1524 | */ | |
1525 | int pcie_get_readrq(struct pci_dev *dev) | |
1526 | { | |
1527 | int ret, cap; | |
1528 | u16 ctl; | |
1529 | ||
1530 | cap = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
1531 | if (!cap) | |
1532 | return -EINVAL; | |
1533 | ||
1534 | ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); | |
1535 | if (!ret) | |
1536 | ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12); | |
1537 | ||
1538 | return ret; | |
1539 | } | |
1540 | EXPORT_SYMBOL(pcie_get_readrq); | |
1541 | ||
1542 | /** | |
1543 | * pcie_set_readrq - set PCI Express maximum memory read request | |
1544 | * @dev: PCI device to query | |
42e61f4a | 1545 | * @rq: maximum memory read count in bytes |
d556ad4b PO |
1546 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
1547 | * | |
1548 | * If possible sets maximum read byte count | |
1549 | */ | |
1550 | int pcie_set_readrq(struct pci_dev *dev, int rq) | |
1551 | { | |
1552 | int cap, err = -EINVAL; | |
1553 | u16 ctl, v; | |
1554 | ||
229f5afd | 1555 | if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) |
d556ad4b PO |
1556 | goto out; |
1557 | ||
1558 | v = (ffs(rq) - 8) << 12; | |
1559 | ||
1560 | cap = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
1561 | if (!cap) | |
1562 | goto out; | |
1563 | ||
1564 | err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); | |
1565 | if (err) | |
1566 | goto out; | |
1567 | ||
1568 | if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) { | |
1569 | ctl &= ~PCI_EXP_DEVCTL_READRQ; | |
1570 | ctl |= v; | |
1571 | err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl); | |
1572 | } | |
1573 | ||
1574 | out: | |
1575 | return err; | |
1576 | } | |
1577 | EXPORT_SYMBOL(pcie_set_readrq); | |
1578 | ||
c87deff7 HS |
1579 | /** |
1580 | * pci_select_bars - Make BAR mask from the type of resource | |
f95d882d | 1581 | * @dev: the PCI device for which BAR mask is made |
c87deff7 HS |
1582 | * @flags: resource type mask to be selected |
1583 | * | |
1584 | * This helper routine makes bar mask from the type of resource. | |
1585 | */ | |
1586 | int pci_select_bars(struct pci_dev *dev, unsigned long flags) | |
1587 | { | |
1588 | int i, bars = 0; | |
1589 | for (i = 0; i < PCI_NUM_RESOURCES; i++) | |
1590 | if (pci_resource_flags(dev, i) & flags) | |
1591 | bars |= (1 << i); | |
1592 | return bars; | |
1593 | } | |
1594 | ||
32a2eea7 JG |
1595 | static void __devinit pci_no_domains(void) |
1596 | { | |
1597 | #ifdef CONFIG_PCI_DOMAINS | |
1598 | pci_domains_supported = 0; | |
1599 | #endif | |
1600 | } | |
1601 | ||
1da177e4 LT |
1602 | static int __devinit pci_init(void) |
1603 | { | |
1604 | struct pci_dev *dev = NULL; | |
1605 | ||
1606 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
1607 | pci_fixup_device(pci_fixup_final, dev); | |
1608 | } | |
1609 | return 0; | |
1610 | } | |
1611 | ||
1612 | static int __devinit pci_setup(char *str) | |
1613 | { | |
1614 | while (str) { | |
1615 | char *k = strchr(str, ','); | |
1616 | if (k) | |
1617 | *k++ = 0; | |
1618 | if (*str && (str = pcibios_setup(str)) && *str) { | |
309e57df MW |
1619 | if (!strcmp(str, "nomsi")) { |
1620 | pci_no_msi(); | |
7f785763 RD |
1621 | } else if (!strcmp(str, "noaer")) { |
1622 | pci_no_aer(); | |
32a2eea7 JG |
1623 | } else if (!strcmp(str, "nodomains")) { |
1624 | pci_no_domains(); | |
4516a618 AN |
1625 | } else if (!strncmp(str, "cbiosize=", 9)) { |
1626 | pci_cardbus_io_size = memparse(str + 9, &str); | |
1627 | } else if (!strncmp(str, "cbmemsize=", 10)) { | |
1628 | pci_cardbus_mem_size = memparse(str + 10, &str); | |
309e57df MW |
1629 | } else { |
1630 | printk(KERN_ERR "PCI: Unknown option `%s'\n", | |
1631 | str); | |
1632 | } | |
1da177e4 LT |
1633 | } |
1634 | str = k; | |
1635 | } | |
0637a70a | 1636 | return 0; |
1da177e4 | 1637 | } |
0637a70a | 1638 | early_param("pci", pci_setup); |
1da177e4 LT |
1639 | |
1640 | device_initcall(pci_init); | |
1da177e4 | 1641 | |
0b62e13b | 1642 | EXPORT_SYMBOL(pci_reenable_device); |
1da177e4 LT |
1643 | EXPORT_SYMBOL(pci_enable_device_bars); |
1644 | EXPORT_SYMBOL(pci_enable_device); | |
9ac7849e TH |
1645 | EXPORT_SYMBOL(pcim_enable_device); |
1646 | EXPORT_SYMBOL(pcim_pin_device); | |
1da177e4 | 1647 | EXPORT_SYMBOL(pci_disable_device); |
1da177e4 LT |
1648 | EXPORT_SYMBOL(pci_find_capability); |
1649 | EXPORT_SYMBOL(pci_bus_find_capability); | |
1650 | EXPORT_SYMBOL(pci_release_regions); | |
1651 | EXPORT_SYMBOL(pci_request_regions); | |
1652 | EXPORT_SYMBOL(pci_release_region); | |
1653 | EXPORT_SYMBOL(pci_request_region); | |
c87deff7 HS |
1654 | EXPORT_SYMBOL(pci_release_selected_regions); |
1655 | EXPORT_SYMBOL(pci_request_selected_regions); | |
1da177e4 LT |
1656 | EXPORT_SYMBOL(pci_set_master); |
1657 | EXPORT_SYMBOL(pci_set_mwi); | |
694625c0 | 1658 | EXPORT_SYMBOL(pci_try_set_mwi); |
1da177e4 | 1659 | EXPORT_SYMBOL(pci_clear_mwi); |
a04ce0ff | 1660 | EXPORT_SYMBOL_GPL(pci_intx); |
1da177e4 | 1661 | EXPORT_SYMBOL(pci_set_dma_mask); |
1da177e4 LT |
1662 | EXPORT_SYMBOL(pci_set_consistent_dma_mask); |
1663 | EXPORT_SYMBOL(pci_assign_resource); | |
1664 | EXPORT_SYMBOL(pci_find_parent_resource); | |
c87deff7 | 1665 | EXPORT_SYMBOL(pci_select_bars); |
1da177e4 LT |
1666 | |
1667 | EXPORT_SYMBOL(pci_set_power_state); | |
1668 | EXPORT_SYMBOL(pci_save_state); | |
1669 | EXPORT_SYMBOL(pci_restore_state); | |
1670 | EXPORT_SYMBOL(pci_enable_wake); | |
f7bdd12d | 1671 | EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state); |
1da177e4 | 1672 |