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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * PCI Bus Services, see include/linux/pci.h for further explanation. |
3 | * | |
4 | * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, | |
5 | * David Mosberger-Tang | |
6 | * | |
7 | * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> | |
8 | */ | |
9 | ||
10 | #include <linux/kernel.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/pci.h> | |
075c1771 | 14 | #include <linux/pm.h> |
5a0e3ad6 | 15 | #include <linux/slab.h> |
1da177e4 LT |
16 | #include <linux/module.h> |
17 | #include <linux/spinlock.h> | |
4e57b681 | 18 | #include <linux/string.h> |
229f5afd | 19 | #include <linux/log2.h> |
7d715a6c | 20 | #include <linux/pci-aspm.h> |
c300bd2f | 21 | #include <linux/pm_wakeup.h> |
8dd7f803 | 22 | #include <linux/interrupt.h> |
32a9a682 | 23 | #include <linux/device.h> |
b67ea761 | 24 | #include <linux/pm_runtime.h> |
608c3881 | 25 | #include <linux/pci_hotplug.h> |
284f5f9d | 26 | #include <asm-generic/pci-bridge.h> |
32a9a682 | 27 | #include <asm/setup.h> |
bc56b9e0 | 28 | #include "pci.h" |
1da177e4 | 29 | |
00240c38 AS |
30 | const char *pci_power_names[] = { |
31 | "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown", | |
32 | }; | |
33 | EXPORT_SYMBOL_GPL(pci_power_names); | |
34 | ||
93177a74 RW |
35 | int isa_dma_bridge_buggy; |
36 | EXPORT_SYMBOL(isa_dma_bridge_buggy); | |
37 | ||
38 | int pci_pci_problems; | |
39 | EXPORT_SYMBOL(pci_pci_problems); | |
40 | ||
1ae861e6 RW |
41 | unsigned int pci_pm_d3_delay; |
42 | ||
df17e62e MG |
43 | static void pci_pme_list_scan(struct work_struct *work); |
44 | ||
45 | static LIST_HEAD(pci_pme_list); | |
46 | static DEFINE_MUTEX(pci_pme_list_mutex); | |
47 | static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan); | |
48 | ||
49 | struct pci_pme_device { | |
50 | struct list_head list; | |
51 | struct pci_dev *dev; | |
52 | }; | |
53 | ||
54 | #define PME_TIMEOUT 1000 /* How long between PME checks */ | |
55 | ||
1ae861e6 RW |
56 | static void pci_dev_d3_sleep(struct pci_dev *dev) |
57 | { | |
58 | unsigned int delay = dev->d3_delay; | |
59 | ||
60 | if (delay < pci_pm_d3_delay) | |
61 | delay = pci_pm_d3_delay; | |
62 | ||
63 | msleep(delay); | |
64 | } | |
1da177e4 | 65 | |
32a2eea7 JG |
66 | #ifdef CONFIG_PCI_DOMAINS |
67 | int pci_domains_supported = 1; | |
68 | #endif | |
69 | ||
4516a618 AN |
70 | #define DEFAULT_CARDBUS_IO_SIZE (256) |
71 | #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024) | |
72 | /* pci=cbmemsize=nnM,cbiosize=nn can override this */ | |
73 | unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE; | |
74 | unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE; | |
75 | ||
28760489 EB |
76 | #define DEFAULT_HOTPLUG_IO_SIZE (256) |
77 | #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024) | |
78 | /* pci=hpmemsize=nnM,hpiosize=nn can override this */ | |
79 | unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE; | |
80 | unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE; | |
81 | ||
5f39e670 | 82 | enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF; |
b03e7495 | 83 | |
ac1aa47b JB |
84 | /* |
85 | * The default CLS is used if arch didn't set CLS explicitly and not | |
86 | * all pci devices agree on the same value. Arch can override either | |
87 | * the dfl or actual value as it sees fit. Don't forget this is | |
88 | * measured in 32-bit words, not bytes. | |
89 | */ | |
15856ad5 | 90 | u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2; |
ac1aa47b JB |
91 | u8 pci_cache_line_size; |
92 | ||
96c55900 MS |
93 | /* |
94 | * If we set up a device for bus mastering, we need to check the latency | |
95 | * timer as certain BIOSes forget to set it properly. | |
96 | */ | |
97 | unsigned int pcibios_max_latency = 255; | |
98 | ||
6748dcc2 RW |
99 | /* If set, the PCIe ARI capability will not be used. */ |
100 | static bool pcie_ari_disabled; | |
101 | ||
1da177e4 LT |
102 | /** |
103 | * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children | |
104 | * @bus: pointer to PCI bus structure to search | |
105 | * | |
106 | * Given a PCI bus, returns the highest PCI bus number present in the set | |
107 | * including the given PCI bus and its list of child PCI buses. | |
108 | */ | |
96bde06a | 109 | unsigned char pci_bus_max_busnr(struct pci_bus* bus) |
1da177e4 | 110 | { |
94e6a9b9 | 111 | struct pci_bus *tmp; |
1da177e4 LT |
112 | unsigned char max, n; |
113 | ||
b918c62e | 114 | max = bus->busn_res.end; |
94e6a9b9 YW |
115 | list_for_each_entry(tmp, &bus->children, node) { |
116 | n = pci_bus_max_busnr(tmp); | |
1da177e4 LT |
117 | if(n > max) |
118 | max = n; | |
119 | } | |
120 | return max; | |
121 | } | |
b82db5ce | 122 | EXPORT_SYMBOL_GPL(pci_bus_max_busnr); |
1da177e4 | 123 | |
1684f5dd AM |
124 | #ifdef CONFIG_HAS_IOMEM |
125 | void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar) | |
126 | { | |
127 | /* | |
128 | * Make sure the BAR is actually a memory resource, not an IO resource | |
129 | */ | |
130 | if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { | |
131 | WARN_ON(1); | |
132 | return NULL; | |
133 | } | |
134 | return ioremap_nocache(pci_resource_start(pdev, bar), | |
135 | pci_resource_len(pdev, bar)); | |
136 | } | |
137 | EXPORT_SYMBOL_GPL(pci_ioremap_bar); | |
138 | #endif | |
139 | ||
687d5fe3 ME |
140 | #define PCI_FIND_CAP_TTL 48 |
141 | ||
142 | static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, | |
143 | u8 pos, int cap, int *ttl) | |
24a4e377 RD |
144 | { |
145 | u8 id; | |
24a4e377 | 146 | |
687d5fe3 | 147 | while ((*ttl)--) { |
24a4e377 RD |
148 | pci_bus_read_config_byte(bus, devfn, pos, &pos); |
149 | if (pos < 0x40) | |
150 | break; | |
151 | pos &= ~3; | |
152 | pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, | |
153 | &id); | |
154 | if (id == 0xff) | |
155 | break; | |
156 | if (id == cap) | |
157 | return pos; | |
158 | pos += PCI_CAP_LIST_NEXT; | |
159 | } | |
160 | return 0; | |
161 | } | |
162 | ||
687d5fe3 ME |
163 | static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, |
164 | u8 pos, int cap) | |
165 | { | |
166 | int ttl = PCI_FIND_CAP_TTL; | |
167 | ||
168 | return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); | |
169 | } | |
170 | ||
24a4e377 RD |
171 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) |
172 | { | |
173 | return __pci_find_next_cap(dev->bus, dev->devfn, | |
174 | pos + PCI_CAP_LIST_NEXT, cap); | |
175 | } | |
176 | EXPORT_SYMBOL_GPL(pci_find_next_capability); | |
177 | ||
d3bac118 ME |
178 | static int __pci_bus_find_cap_start(struct pci_bus *bus, |
179 | unsigned int devfn, u8 hdr_type) | |
1da177e4 LT |
180 | { |
181 | u16 status; | |
1da177e4 LT |
182 | |
183 | pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); | |
184 | if (!(status & PCI_STATUS_CAP_LIST)) | |
185 | return 0; | |
186 | ||
187 | switch (hdr_type) { | |
188 | case PCI_HEADER_TYPE_NORMAL: | |
189 | case PCI_HEADER_TYPE_BRIDGE: | |
d3bac118 | 190 | return PCI_CAPABILITY_LIST; |
1da177e4 | 191 | case PCI_HEADER_TYPE_CARDBUS: |
d3bac118 | 192 | return PCI_CB_CAPABILITY_LIST; |
1da177e4 LT |
193 | default: |
194 | return 0; | |
195 | } | |
d3bac118 ME |
196 | |
197 | return 0; | |
1da177e4 LT |
198 | } |
199 | ||
200 | /** | |
f7625980 | 201 | * pci_find_capability - query for devices' capabilities |
1da177e4 LT |
202 | * @dev: PCI device to query |
203 | * @cap: capability code | |
204 | * | |
205 | * Tell if a device supports a given PCI capability. | |
206 | * Returns the address of the requested capability structure within the | |
207 | * device's PCI configuration space or 0 in case the device does not | |
208 | * support it. Possible values for @cap: | |
209 | * | |
f7625980 BH |
210 | * %PCI_CAP_ID_PM Power Management |
211 | * %PCI_CAP_ID_AGP Accelerated Graphics Port | |
212 | * %PCI_CAP_ID_VPD Vital Product Data | |
213 | * %PCI_CAP_ID_SLOTID Slot Identification | |
1da177e4 | 214 | * %PCI_CAP_ID_MSI Message Signalled Interrupts |
f7625980 | 215 | * %PCI_CAP_ID_CHSWP CompactPCI HotSwap |
1da177e4 LT |
216 | * %PCI_CAP_ID_PCIX PCI-X |
217 | * %PCI_CAP_ID_EXP PCI Express | |
218 | */ | |
219 | int pci_find_capability(struct pci_dev *dev, int cap) | |
220 | { | |
d3bac118 ME |
221 | int pos; |
222 | ||
223 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
224 | if (pos) | |
225 | pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); | |
226 | ||
227 | return pos; | |
1da177e4 | 228 | } |
b7fe9434 | 229 | EXPORT_SYMBOL(pci_find_capability); |
1da177e4 LT |
230 | |
231 | /** | |
f7625980 | 232 | * pci_bus_find_capability - query for devices' capabilities |
1da177e4 LT |
233 | * @bus: the PCI bus to query |
234 | * @devfn: PCI device to query | |
235 | * @cap: capability code | |
236 | * | |
237 | * Like pci_find_capability() but works for pci devices that do not have a | |
f7625980 | 238 | * pci_dev structure set up yet. |
1da177e4 LT |
239 | * |
240 | * Returns the address of the requested capability structure within the | |
241 | * device's PCI configuration space or 0 in case the device does not | |
242 | * support it. | |
243 | */ | |
244 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) | |
245 | { | |
d3bac118 | 246 | int pos; |
1da177e4 LT |
247 | u8 hdr_type; |
248 | ||
249 | pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); | |
250 | ||
d3bac118 ME |
251 | pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f); |
252 | if (pos) | |
253 | pos = __pci_find_next_cap(bus, devfn, pos, cap); | |
254 | ||
255 | return pos; | |
1da177e4 | 256 | } |
b7fe9434 | 257 | EXPORT_SYMBOL(pci_bus_find_capability); |
1da177e4 LT |
258 | |
259 | /** | |
44a9a36f | 260 | * pci_find_next_ext_capability - Find an extended capability |
1da177e4 | 261 | * @dev: PCI device to query |
44a9a36f | 262 | * @start: address at which to start looking (0 to start at beginning of list) |
1da177e4 LT |
263 | * @cap: capability code |
264 | * | |
44a9a36f | 265 | * Returns the address of the next matching extended capability structure |
1da177e4 | 266 | * within the device's PCI configuration space or 0 if the device does |
44a9a36f BH |
267 | * not support it. Some capabilities can occur several times, e.g., the |
268 | * vendor-specific capability, and this provides a way to find them all. | |
1da177e4 | 269 | */ |
44a9a36f | 270 | int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap) |
1da177e4 LT |
271 | { |
272 | u32 header; | |
557848c3 ZY |
273 | int ttl; |
274 | int pos = PCI_CFG_SPACE_SIZE; | |
1da177e4 | 275 | |
557848c3 ZY |
276 | /* minimum 8 bytes per capability */ |
277 | ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; | |
278 | ||
279 | if (dev->cfg_size <= PCI_CFG_SPACE_SIZE) | |
1da177e4 LT |
280 | return 0; |
281 | ||
44a9a36f BH |
282 | if (start) |
283 | pos = start; | |
284 | ||
1da177e4 LT |
285 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) |
286 | return 0; | |
287 | ||
288 | /* | |
289 | * If we have no capabilities, this is indicated by cap ID, | |
290 | * cap version and next pointer all being 0. | |
291 | */ | |
292 | if (header == 0) | |
293 | return 0; | |
294 | ||
295 | while (ttl-- > 0) { | |
44a9a36f | 296 | if (PCI_EXT_CAP_ID(header) == cap && pos != start) |
1da177e4 LT |
297 | return pos; |
298 | ||
299 | pos = PCI_EXT_CAP_NEXT(header); | |
557848c3 | 300 | if (pos < PCI_CFG_SPACE_SIZE) |
1da177e4 LT |
301 | break; |
302 | ||
303 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
304 | break; | |
305 | } | |
306 | ||
307 | return 0; | |
308 | } | |
44a9a36f BH |
309 | EXPORT_SYMBOL_GPL(pci_find_next_ext_capability); |
310 | ||
311 | /** | |
312 | * pci_find_ext_capability - Find an extended capability | |
313 | * @dev: PCI device to query | |
314 | * @cap: capability code | |
315 | * | |
316 | * Returns the address of the requested extended capability structure | |
317 | * within the device's PCI configuration space or 0 if the device does | |
318 | * not support it. Possible values for @cap: | |
319 | * | |
320 | * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting | |
321 | * %PCI_EXT_CAP_ID_VC Virtual Channel | |
322 | * %PCI_EXT_CAP_ID_DSN Device Serial Number | |
323 | * %PCI_EXT_CAP_ID_PWR Power Budgeting | |
324 | */ | |
325 | int pci_find_ext_capability(struct pci_dev *dev, int cap) | |
326 | { | |
327 | return pci_find_next_ext_capability(dev, 0, cap); | |
328 | } | |
3a720d72 | 329 | EXPORT_SYMBOL_GPL(pci_find_ext_capability); |
1da177e4 | 330 | |
687d5fe3 ME |
331 | static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) |
332 | { | |
333 | int rc, ttl = PCI_FIND_CAP_TTL; | |
334 | u8 cap, mask; | |
335 | ||
336 | if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST) | |
337 | mask = HT_3BIT_CAP_MASK; | |
338 | else | |
339 | mask = HT_5BIT_CAP_MASK; | |
340 | ||
341 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, | |
342 | PCI_CAP_ID_HT, &ttl); | |
343 | while (pos) { | |
344 | rc = pci_read_config_byte(dev, pos + 3, &cap); | |
345 | if (rc != PCIBIOS_SUCCESSFUL) | |
346 | return 0; | |
347 | ||
348 | if ((cap & mask) == ht_cap) | |
349 | return pos; | |
350 | ||
47a4d5be BG |
351 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, |
352 | pos + PCI_CAP_LIST_NEXT, | |
687d5fe3 ME |
353 | PCI_CAP_ID_HT, &ttl); |
354 | } | |
355 | ||
356 | return 0; | |
357 | } | |
358 | /** | |
359 | * pci_find_next_ht_capability - query a device's Hypertransport capabilities | |
360 | * @dev: PCI device to query | |
361 | * @pos: Position from which to continue searching | |
362 | * @ht_cap: Hypertransport capability code | |
363 | * | |
364 | * To be used in conjunction with pci_find_ht_capability() to search for | |
365 | * all capabilities matching @ht_cap. @pos should always be a value returned | |
366 | * from pci_find_ht_capability(). | |
367 | * | |
368 | * NB. To be 100% safe against broken PCI devices, the caller should take | |
369 | * steps to avoid an infinite loop. | |
370 | */ | |
371 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap) | |
372 | { | |
373 | return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap); | |
374 | } | |
375 | EXPORT_SYMBOL_GPL(pci_find_next_ht_capability); | |
376 | ||
377 | /** | |
378 | * pci_find_ht_capability - query a device's Hypertransport capabilities | |
379 | * @dev: PCI device to query | |
380 | * @ht_cap: Hypertransport capability code | |
381 | * | |
382 | * Tell if a device supports a given Hypertransport capability. | |
383 | * Returns an address within the device's PCI configuration space | |
384 | * or 0 in case the device does not support the request capability. | |
385 | * The address points to the PCI capability, of type PCI_CAP_ID_HT, | |
386 | * which has a Hypertransport capability matching @ht_cap. | |
387 | */ | |
388 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap) | |
389 | { | |
390 | int pos; | |
391 | ||
392 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
393 | if (pos) | |
394 | pos = __pci_find_next_ht_cap(dev, pos, ht_cap); | |
395 | ||
396 | return pos; | |
397 | } | |
398 | EXPORT_SYMBOL_GPL(pci_find_ht_capability); | |
399 | ||
1da177e4 LT |
400 | /** |
401 | * pci_find_parent_resource - return resource region of parent bus of given region | |
402 | * @dev: PCI device structure contains resources to be searched | |
403 | * @res: child resource record for which parent is sought | |
404 | * | |
405 | * For given resource region of given device, return the resource | |
f44116ae | 406 | * region of parent bus the given region is contained in. |
1da177e4 LT |
407 | */ |
408 | struct resource * | |
409 | pci_find_parent_resource(const struct pci_dev *dev, struct resource *res) | |
410 | { | |
411 | const struct pci_bus *bus = dev->bus; | |
f44116ae | 412 | struct resource *r; |
1da177e4 | 413 | int i; |
1da177e4 | 414 | |
89a74ecc | 415 | pci_bus_for_each_resource(bus, r, i) { |
1da177e4 LT |
416 | if (!r) |
417 | continue; | |
f44116ae BH |
418 | if (res->start && resource_contains(r, res)) { |
419 | ||
420 | /* | |
421 | * If the window is prefetchable but the BAR is | |
422 | * not, the allocator made a mistake. | |
423 | */ | |
424 | if (r->flags & IORESOURCE_PREFETCH && | |
425 | !(res->flags & IORESOURCE_PREFETCH)) | |
426 | return NULL; | |
427 | ||
428 | /* | |
429 | * If we're below a transparent bridge, there may | |
430 | * be both a positively-decoded aperture and a | |
431 | * subtractively-decoded region that contain the BAR. | |
432 | * We want the positively-decoded one, so this depends | |
433 | * on pci_bus_for_each_resource() giving us those | |
434 | * first. | |
435 | */ | |
436 | return r; | |
437 | } | |
1da177e4 | 438 | } |
f44116ae | 439 | return NULL; |
1da177e4 | 440 | } |
b7fe9434 | 441 | EXPORT_SYMBOL(pci_find_parent_resource); |
1da177e4 | 442 | |
157e876f AW |
443 | /** |
444 | * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos | |
445 | * @dev: the PCI device to operate on | |
446 | * @pos: config space offset of status word | |
447 | * @mask: mask of bit(s) to care about in status word | |
448 | * | |
449 | * Return 1 when mask bit(s) in status word clear, 0 otherwise. | |
450 | */ | |
451 | int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask) | |
452 | { | |
453 | int i; | |
454 | ||
455 | /* Wait for Transaction Pending bit clean */ | |
456 | for (i = 0; i < 4; i++) { | |
457 | u16 status; | |
458 | if (i) | |
459 | msleep((1 << (i - 1)) * 100); | |
460 | ||
461 | pci_read_config_word(dev, pos, &status); | |
462 | if (!(status & mask)) | |
463 | return 1; | |
464 | } | |
465 | ||
466 | return 0; | |
467 | } | |
468 | ||
064b53db JL |
469 | /** |
470 | * pci_restore_bars - restore a devices BAR values (e.g. after wake-up) | |
471 | * @dev: PCI device to have its BARs restored | |
472 | * | |
473 | * Restore the BAR values for a given device, so as to make it | |
474 | * accessible by its driver. | |
475 | */ | |
ad668599 | 476 | static void |
064b53db JL |
477 | pci_restore_bars(struct pci_dev *dev) |
478 | { | |
bc5f5a82 | 479 | int i; |
064b53db | 480 | |
bc5f5a82 | 481 | for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) |
14add80b | 482 | pci_update_resource(dev, i); |
064b53db JL |
483 | } |
484 | ||
961d9120 RW |
485 | static struct pci_platform_pm_ops *pci_platform_pm; |
486 | ||
487 | int pci_set_platform_pm(struct pci_platform_pm_ops *ops) | |
488 | { | |
eb9d0fe4 | 489 | if (!ops->is_manageable || !ops->set_state || !ops->choose_state |
d2e5f0c1 | 490 | || !ops->sleep_wake) |
961d9120 RW |
491 | return -EINVAL; |
492 | pci_platform_pm = ops; | |
493 | return 0; | |
494 | } | |
495 | ||
496 | static inline bool platform_pci_power_manageable(struct pci_dev *dev) | |
497 | { | |
498 | return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false; | |
499 | } | |
500 | ||
501 | static inline int platform_pci_set_power_state(struct pci_dev *dev, | |
502 | pci_power_t t) | |
503 | { | |
504 | return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS; | |
505 | } | |
506 | ||
507 | static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev) | |
508 | { | |
509 | return pci_platform_pm ? | |
510 | pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR; | |
511 | } | |
8f7020d3 | 512 | |
eb9d0fe4 RW |
513 | static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable) |
514 | { | |
515 | return pci_platform_pm ? | |
516 | pci_platform_pm->sleep_wake(dev, enable) : -ENODEV; | |
517 | } | |
518 | ||
b67ea761 RW |
519 | static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable) |
520 | { | |
521 | return pci_platform_pm ? | |
522 | pci_platform_pm->run_wake(dev, enable) : -ENODEV; | |
523 | } | |
524 | ||
1da177e4 | 525 | /** |
44e4e66e RW |
526 | * pci_raw_set_power_state - Use PCI PM registers to set the power state of |
527 | * given PCI device | |
528 | * @dev: PCI device to handle. | |
44e4e66e | 529 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. |
1da177e4 | 530 | * |
44e4e66e RW |
531 | * RETURN VALUE: |
532 | * -EINVAL if the requested state is invalid. | |
533 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
534 | * wrong version, or device doesn't support the requested state. | |
535 | * 0 if device already is in the requested state. | |
536 | * 0 if device's power state has been successfully changed. | |
1da177e4 | 537 | */ |
f00a20ef | 538 | static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state) |
1da177e4 | 539 | { |
337001b6 | 540 | u16 pmcsr; |
44e4e66e | 541 | bool need_restore = false; |
1da177e4 | 542 | |
4a865905 RW |
543 | /* Check if we're already there */ |
544 | if (dev->current_state == state) | |
545 | return 0; | |
546 | ||
337001b6 | 547 | if (!dev->pm_cap) |
cca03dec AL |
548 | return -EIO; |
549 | ||
44e4e66e RW |
550 | if (state < PCI_D0 || state > PCI_D3hot) |
551 | return -EINVAL; | |
552 | ||
1da177e4 | 553 | /* Validate current state: |
f7625980 | 554 | * Can enter D0 from any state, but if we can only go deeper |
1da177e4 LT |
555 | * to sleep if we're already in a low power state |
556 | */ | |
4a865905 | 557 | if (state != PCI_D0 && dev->current_state <= PCI_D3cold |
44e4e66e | 558 | && dev->current_state > state) { |
80ccba11 BH |
559 | dev_err(&dev->dev, "invalid power transition " |
560 | "(from state %d to %d)\n", dev->current_state, state); | |
1da177e4 | 561 | return -EINVAL; |
44e4e66e | 562 | } |
1da177e4 | 563 | |
1da177e4 | 564 | /* check if this device supports the desired state */ |
337001b6 RW |
565 | if ((state == PCI_D1 && !dev->d1_support) |
566 | || (state == PCI_D2 && !dev->d2_support)) | |
3fe9d19f | 567 | return -EIO; |
1da177e4 | 568 | |
337001b6 | 569 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
064b53db | 570 | |
32a36585 | 571 | /* If we're (effectively) in D3, force entire word to 0. |
1da177e4 LT |
572 | * This doesn't affect PME_Status, disables PME_En, and |
573 | * sets PowerState to 0. | |
574 | */ | |
32a36585 | 575 | switch (dev->current_state) { |
d3535fbb JL |
576 | case PCI_D0: |
577 | case PCI_D1: | |
578 | case PCI_D2: | |
579 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
580 | pmcsr |= state; | |
581 | break; | |
f62795f1 RW |
582 | case PCI_D3hot: |
583 | case PCI_D3cold: | |
32a36585 JL |
584 | case PCI_UNKNOWN: /* Boot-up */ |
585 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot | |
f00a20ef | 586 | && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) |
44e4e66e | 587 | need_restore = true; |
32a36585 | 588 | /* Fall-through: force to D0 */ |
32a36585 | 589 | default: |
d3535fbb | 590 | pmcsr = 0; |
32a36585 | 591 | break; |
1da177e4 LT |
592 | } |
593 | ||
594 | /* enter specified state */ | |
337001b6 | 595 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
1da177e4 LT |
596 | |
597 | /* Mandatory power management transition delays */ | |
598 | /* see PCI PM 1.1 5.6.1 table 18 */ | |
599 | if (state == PCI_D3hot || dev->current_state == PCI_D3hot) | |
1ae861e6 | 600 | pci_dev_d3_sleep(dev); |
1da177e4 | 601 | else if (state == PCI_D2 || dev->current_state == PCI_D2) |
aa8c6c93 | 602 | udelay(PCI_PM_D2_DELAY); |
1da177e4 | 603 | |
e13cdbd7 RW |
604 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
605 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); | |
606 | if (dev->current_state != state && printk_ratelimit()) | |
607 | dev_info(&dev->dev, "Refused to change power state, " | |
608 | "currently in D%d\n", dev->current_state); | |
064b53db | 609 | |
448bd857 HY |
610 | /* |
611 | * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT | |
064b53db JL |
612 | * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning |
613 | * from D3hot to D0 _may_ perform an internal reset, thereby | |
614 | * going to "D0 Uninitialized" rather than "D0 Initialized". | |
615 | * For example, at least some versions of the 3c905B and the | |
616 | * 3c556B exhibit this behaviour. | |
617 | * | |
618 | * At least some laptop BIOSen (e.g. the Thinkpad T21) leave | |
619 | * devices in a D3hot state at boot. Consequently, we need to | |
620 | * restore at least the BARs so that the device will be | |
621 | * accessible to its driver. | |
622 | */ | |
623 | if (need_restore) | |
624 | pci_restore_bars(dev); | |
625 | ||
f00a20ef | 626 | if (dev->bus->self) |
7d715a6c SL |
627 | pcie_aspm_pm_state_change(dev->bus->self); |
628 | ||
1da177e4 LT |
629 | return 0; |
630 | } | |
631 | ||
44e4e66e RW |
632 | /** |
633 | * pci_update_current_state - Read PCI power state of given device from its | |
634 | * PCI PM registers and cache it | |
635 | * @dev: PCI device to handle. | |
f06fc0b6 | 636 | * @state: State to cache in case the device doesn't have the PM capability |
44e4e66e | 637 | */ |
73410429 | 638 | void pci_update_current_state(struct pci_dev *dev, pci_power_t state) |
44e4e66e | 639 | { |
337001b6 | 640 | if (dev->pm_cap) { |
44e4e66e RW |
641 | u16 pmcsr; |
642 | ||
448bd857 HY |
643 | /* |
644 | * Configuration space is not accessible for device in | |
645 | * D3cold, so just keep or set D3cold for safety | |
646 | */ | |
647 | if (dev->current_state == PCI_D3cold) | |
648 | return; | |
649 | if (state == PCI_D3cold) { | |
650 | dev->current_state = PCI_D3cold; | |
651 | return; | |
652 | } | |
337001b6 | 653 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
44e4e66e | 654 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); |
f06fc0b6 RW |
655 | } else { |
656 | dev->current_state = state; | |
44e4e66e RW |
657 | } |
658 | } | |
659 | ||
db288c9c RW |
660 | /** |
661 | * pci_power_up - Put the given device into D0 forcibly | |
662 | * @dev: PCI device to power up | |
663 | */ | |
664 | void pci_power_up(struct pci_dev *dev) | |
665 | { | |
666 | if (platform_pci_power_manageable(dev)) | |
667 | platform_pci_set_power_state(dev, PCI_D0); | |
668 | ||
669 | pci_raw_set_power_state(dev, PCI_D0); | |
670 | pci_update_current_state(dev, PCI_D0); | |
671 | } | |
672 | ||
0e5dd46b RW |
673 | /** |
674 | * pci_platform_power_transition - Use platform to change device power state | |
675 | * @dev: PCI device to handle. | |
676 | * @state: State to put the device into. | |
677 | */ | |
678 | static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state) | |
679 | { | |
680 | int error; | |
681 | ||
682 | if (platform_pci_power_manageable(dev)) { | |
683 | error = platform_pci_set_power_state(dev, state); | |
684 | if (!error) | |
685 | pci_update_current_state(dev, state); | |
769ba721 | 686 | } else |
0e5dd46b | 687 | error = -ENODEV; |
769ba721 RW |
688 | |
689 | if (error && !dev->pm_cap) /* Fall back to PCI_D0 */ | |
690 | dev->current_state = PCI_D0; | |
0e5dd46b RW |
691 | |
692 | return error; | |
693 | } | |
694 | ||
0b950f0f SH |
695 | /** |
696 | * pci_wakeup - Wake up a PCI device | |
697 | * @pci_dev: Device to handle. | |
698 | * @ign: ignored parameter | |
699 | */ | |
700 | static int pci_wakeup(struct pci_dev *pci_dev, void *ign) | |
701 | { | |
702 | pci_wakeup_event(pci_dev); | |
703 | pm_request_resume(&pci_dev->dev); | |
704 | return 0; | |
705 | } | |
706 | ||
707 | /** | |
708 | * pci_wakeup_bus - Walk given bus and wake up devices on it | |
709 | * @bus: Top bus of the subtree to walk. | |
710 | */ | |
711 | static void pci_wakeup_bus(struct pci_bus *bus) | |
712 | { | |
713 | if (bus) | |
714 | pci_walk_bus(bus, pci_wakeup, NULL); | |
715 | } | |
716 | ||
0e5dd46b RW |
717 | /** |
718 | * __pci_start_power_transition - Start power transition of a PCI device | |
719 | * @dev: PCI device to handle. | |
720 | * @state: State to put the device into. | |
721 | */ | |
722 | static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state) | |
723 | { | |
448bd857 | 724 | if (state == PCI_D0) { |
0e5dd46b | 725 | pci_platform_power_transition(dev, PCI_D0); |
448bd857 HY |
726 | /* |
727 | * Mandatory power management transition delays, see | |
728 | * PCI Express Base Specification Revision 2.0 Section | |
729 | * 6.6.1: Conventional Reset. Do not delay for | |
730 | * devices powered on/off by corresponding bridge, | |
731 | * because have already delayed for the bridge. | |
732 | */ | |
733 | if (dev->runtime_d3cold) { | |
734 | msleep(dev->d3cold_delay); | |
735 | /* | |
736 | * When powering on a bridge from D3cold, the | |
737 | * whole hierarchy may be powered on into | |
738 | * D0uninitialized state, resume them to give | |
739 | * them a chance to suspend again | |
740 | */ | |
741 | pci_wakeup_bus(dev->subordinate); | |
742 | } | |
743 | } | |
744 | } | |
745 | ||
746 | /** | |
747 | * __pci_dev_set_current_state - Set current state of a PCI device | |
748 | * @dev: Device to handle | |
749 | * @data: pointer to state to be set | |
750 | */ | |
751 | static int __pci_dev_set_current_state(struct pci_dev *dev, void *data) | |
752 | { | |
753 | pci_power_t state = *(pci_power_t *)data; | |
754 | ||
755 | dev->current_state = state; | |
756 | return 0; | |
757 | } | |
758 | ||
759 | /** | |
760 | * __pci_bus_set_current_state - Walk given bus and set current state of devices | |
761 | * @bus: Top bus of the subtree to walk. | |
762 | * @state: state to be set | |
763 | */ | |
764 | static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state) | |
765 | { | |
766 | if (bus) | |
767 | pci_walk_bus(bus, __pci_dev_set_current_state, &state); | |
0e5dd46b RW |
768 | } |
769 | ||
770 | /** | |
771 | * __pci_complete_power_transition - Complete power transition of a PCI device | |
772 | * @dev: PCI device to handle. | |
773 | * @state: State to put the device into. | |
774 | * | |
775 | * This function should not be called directly by device drivers. | |
776 | */ | |
777 | int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state) | |
778 | { | |
448bd857 HY |
779 | int ret; |
780 | ||
db288c9c | 781 | if (state <= PCI_D0) |
448bd857 HY |
782 | return -EINVAL; |
783 | ret = pci_platform_power_transition(dev, state); | |
784 | /* Power off the bridge may power off the whole hierarchy */ | |
785 | if (!ret && state == PCI_D3cold) | |
786 | __pci_bus_set_current_state(dev->subordinate, PCI_D3cold); | |
787 | return ret; | |
0e5dd46b RW |
788 | } |
789 | EXPORT_SYMBOL_GPL(__pci_complete_power_transition); | |
790 | ||
44e4e66e RW |
791 | /** |
792 | * pci_set_power_state - Set the power state of a PCI device | |
793 | * @dev: PCI device to handle. | |
794 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. | |
795 | * | |
877d0310 | 796 | * Transition a device to a new power state, using the platform firmware and/or |
44e4e66e RW |
797 | * the device's PCI PM registers. |
798 | * | |
799 | * RETURN VALUE: | |
800 | * -EINVAL if the requested state is invalid. | |
801 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
802 | * wrong version, or device doesn't support the requested state. | |
803 | * 0 if device already is in the requested state. | |
804 | * 0 if device's power state has been successfully changed. | |
805 | */ | |
806 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state) | |
807 | { | |
337001b6 | 808 | int error; |
44e4e66e RW |
809 | |
810 | /* bound the state we're entering */ | |
448bd857 HY |
811 | if (state > PCI_D3cold) |
812 | state = PCI_D3cold; | |
44e4e66e RW |
813 | else if (state < PCI_D0) |
814 | state = PCI_D0; | |
815 | else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) | |
816 | /* | |
817 | * If the device or the parent bridge do not support PCI PM, | |
818 | * ignore the request if we're doing anything other than putting | |
819 | * it into D0 (which would only happen on boot). | |
820 | */ | |
821 | return 0; | |
822 | ||
db288c9c RW |
823 | /* Check if we're already there */ |
824 | if (dev->current_state == state) | |
825 | return 0; | |
826 | ||
0e5dd46b RW |
827 | __pci_start_power_transition(dev, state); |
828 | ||
979b1791 AC |
829 | /* This device is quirked not to be put into D3, so |
830 | don't put it in D3 */ | |
448bd857 | 831 | if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) |
979b1791 | 832 | return 0; |
44e4e66e | 833 | |
448bd857 HY |
834 | /* |
835 | * To put device in D3cold, we put device into D3hot in native | |
836 | * way, then put device into D3cold with platform ops | |
837 | */ | |
838 | error = pci_raw_set_power_state(dev, state > PCI_D3hot ? | |
839 | PCI_D3hot : state); | |
44e4e66e | 840 | |
0e5dd46b RW |
841 | if (!__pci_complete_power_transition(dev, state)) |
842 | error = 0; | |
1a680b7c NC |
843 | /* |
844 | * When aspm_policy is "powersave" this call ensures | |
845 | * that ASPM is configured. | |
846 | */ | |
847 | if (!error && dev->bus->self) | |
848 | pcie_aspm_powersave_config_link(dev->bus->self); | |
44e4e66e RW |
849 | |
850 | return error; | |
851 | } | |
b7fe9434 | 852 | EXPORT_SYMBOL(pci_set_power_state); |
44e4e66e | 853 | |
1da177e4 LT |
854 | /** |
855 | * pci_choose_state - Choose the power state of a PCI device | |
856 | * @dev: PCI device to be suspended | |
857 | * @state: target sleep state for the whole system. This is the value | |
858 | * that is passed to suspend() function. | |
859 | * | |
860 | * Returns PCI power state suitable for given device and given system | |
861 | * message. | |
862 | */ | |
863 | ||
864 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) | |
865 | { | |
ab826ca4 | 866 | pci_power_t ret; |
0f64474b | 867 | |
728cdb75 | 868 | if (!dev->pm_cap) |
1da177e4 LT |
869 | return PCI_D0; |
870 | ||
961d9120 RW |
871 | ret = platform_pci_choose_state(dev); |
872 | if (ret != PCI_POWER_ERROR) | |
873 | return ret; | |
ca078bae PM |
874 | |
875 | switch (state.event) { | |
876 | case PM_EVENT_ON: | |
877 | return PCI_D0; | |
878 | case PM_EVENT_FREEZE: | |
b887d2e6 DB |
879 | case PM_EVENT_PRETHAW: |
880 | /* REVISIT both freeze and pre-thaw "should" use D0 */ | |
ca078bae | 881 | case PM_EVENT_SUSPEND: |
3a2d5b70 | 882 | case PM_EVENT_HIBERNATE: |
ca078bae | 883 | return PCI_D3hot; |
1da177e4 | 884 | default: |
80ccba11 BH |
885 | dev_info(&dev->dev, "unrecognized suspend event %d\n", |
886 | state.event); | |
1da177e4 LT |
887 | BUG(); |
888 | } | |
889 | return PCI_D0; | |
890 | } | |
891 | ||
892 | EXPORT_SYMBOL(pci_choose_state); | |
893 | ||
89858517 YZ |
894 | #define PCI_EXP_SAVE_REGS 7 |
895 | ||
1b6b8ce2 | 896 | |
fd0f7f73 AW |
897 | static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev, |
898 | u16 cap, bool extended) | |
34a4876e YL |
899 | { |
900 | struct pci_cap_saved_state *tmp; | |
34a4876e | 901 | |
b67bfe0d | 902 | hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) { |
fd0f7f73 | 903 | if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap) |
34a4876e YL |
904 | return tmp; |
905 | } | |
906 | return NULL; | |
907 | } | |
908 | ||
fd0f7f73 AW |
909 | struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap) |
910 | { | |
911 | return _pci_find_saved_cap(dev, cap, false); | |
912 | } | |
913 | ||
914 | struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap) | |
915 | { | |
916 | return _pci_find_saved_cap(dev, cap, true); | |
917 | } | |
918 | ||
b56a5a23 MT |
919 | static int pci_save_pcie_state(struct pci_dev *dev) |
920 | { | |
59875ae4 | 921 | int i = 0; |
b56a5a23 MT |
922 | struct pci_cap_saved_state *save_state; |
923 | u16 *cap; | |
924 | ||
59875ae4 | 925 | if (!pci_is_pcie(dev)) |
b56a5a23 MT |
926 | return 0; |
927 | ||
9f35575d | 928 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); |
b56a5a23 | 929 | if (!save_state) { |
e496b617 | 930 | dev_err(&dev->dev, "buffer not found in %s\n", __func__); |
b56a5a23 MT |
931 | return -ENOMEM; |
932 | } | |
63f4898a | 933 | |
59875ae4 JL |
934 | cap = (u16 *)&save_state->cap.data[0]; |
935 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]); | |
936 | pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]); | |
937 | pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]); | |
938 | pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]); | |
939 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]); | |
940 | pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]); | |
941 | pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]); | |
9cb604ed | 942 | |
b56a5a23 MT |
943 | return 0; |
944 | } | |
945 | ||
946 | static void pci_restore_pcie_state(struct pci_dev *dev) | |
947 | { | |
59875ae4 | 948 | int i = 0; |
b56a5a23 MT |
949 | struct pci_cap_saved_state *save_state; |
950 | u16 *cap; | |
951 | ||
952 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); | |
59875ae4 | 953 | if (!save_state) |
9cb604ed MS |
954 | return; |
955 | ||
59875ae4 JL |
956 | cap = (u16 *)&save_state->cap.data[0]; |
957 | pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]); | |
958 | pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]); | |
959 | pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]); | |
960 | pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]); | |
961 | pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]); | |
962 | pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]); | |
963 | pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]); | |
b56a5a23 MT |
964 | } |
965 | ||
cc692a5f SH |
966 | |
967 | static int pci_save_pcix_state(struct pci_dev *dev) | |
968 | { | |
63f4898a | 969 | int pos; |
cc692a5f | 970 | struct pci_cap_saved_state *save_state; |
cc692a5f SH |
971 | |
972 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
973 | if (pos <= 0) | |
974 | return 0; | |
975 | ||
f34303de | 976 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); |
cc692a5f | 977 | if (!save_state) { |
e496b617 | 978 | dev_err(&dev->dev, "buffer not found in %s\n", __func__); |
cc692a5f SH |
979 | return -ENOMEM; |
980 | } | |
cc692a5f | 981 | |
24a4742f AW |
982 | pci_read_config_word(dev, pos + PCI_X_CMD, |
983 | (u16 *)save_state->cap.data); | |
63f4898a | 984 | |
cc692a5f SH |
985 | return 0; |
986 | } | |
987 | ||
988 | static void pci_restore_pcix_state(struct pci_dev *dev) | |
989 | { | |
990 | int i = 0, pos; | |
991 | struct pci_cap_saved_state *save_state; | |
992 | u16 *cap; | |
993 | ||
994 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); | |
995 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
996 | if (!save_state || pos <= 0) | |
997 | return; | |
24a4742f | 998 | cap = (u16 *)&save_state->cap.data[0]; |
cc692a5f SH |
999 | |
1000 | pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]); | |
cc692a5f SH |
1001 | } |
1002 | ||
1003 | ||
1da177e4 LT |
1004 | /** |
1005 | * pci_save_state - save the PCI configuration space of a device before suspending | |
1006 | * @dev: - PCI device that we're dealing with | |
1da177e4 LT |
1007 | */ |
1008 | int | |
1009 | pci_save_state(struct pci_dev *dev) | |
1010 | { | |
1011 | int i; | |
1012 | /* XXX: 100% dword access ok here? */ | |
1013 | for (i = 0; i < 16; i++) | |
9e0b5b2c | 1014 | pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]); |
aa8c6c93 | 1015 | dev->state_saved = true; |
b56a5a23 MT |
1016 | if ((i = pci_save_pcie_state(dev)) != 0) |
1017 | return i; | |
cc692a5f SH |
1018 | if ((i = pci_save_pcix_state(dev)) != 0) |
1019 | return i; | |
425c1b22 AW |
1020 | if ((i = pci_save_vc_state(dev)) != 0) |
1021 | return i; | |
1da177e4 LT |
1022 | return 0; |
1023 | } | |
b7fe9434 | 1024 | EXPORT_SYMBOL(pci_save_state); |
1da177e4 | 1025 | |
ebfc5b80 RW |
1026 | static void pci_restore_config_dword(struct pci_dev *pdev, int offset, |
1027 | u32 saved_val, int retry) | |
1028 | { | |
1029 | u32 val; | |
1030 | ||
1031 | pci_read_config_dword(pdev, offset, &val); | |
1032 | if (val == saved_val) | |
1033 | return; | |
1034 | ||
1035 | for (;;) { | |
1036 | dev_dbg(&pdev->dev, "restoring config space at offset " | |
1037 | "%#x (was %#x, writing %#x)\n", offset, val, saved_val); | |
1038 | pci_write_config_dword(pdev, offset, saved_val); | |
1039 | if (retry-- <= 0) | |
1040 | return; | |
1041 | ||
1042 | pci_read_config_dword(pdev, offset, &val); | |
1043 | if (val == saved_val) | |
1044 | return; | |
1045 | ||
1046 | mdelay(1); | |
1047 | } | |
1048 | } | |
1049 | ||
a6cb9ee7 RW |
1050 | static void pci_restore_config_space_range(struct pci_dev *pdev, |
1051 | int start, int end, int retry) | |
ebfc5b80 RW |
1052 | { |
1053 | int index; | |
1054 | ||
1055 | for (index = end; index >= start; index--) | |
1056 | pci_restore_config_dword(pdev, 4 * index, | |
1057 | pdev->saved_config_space[index], | |
1058 | retry); | |
1059 | } | |
1060 | ||
a6cb9ee7 RW |
1061 | static void pci_restore_config_space(struct pci_dev *pdev) |
1062 | { | |
1063 | if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) { | |
1064 | pci_restore_config_space_range(pdev, 10, 15, 0); | |
1065 | /* Restore BARs before the command register. */ | |
1066 | pci_restore_config_space_range(pdev, 4, 9, 10); | |
1067 | pci_restore_config_space_range(pdev, 0, 3, 0); | |
1068 | } else { | |
1069 | pci_restore_config_space_range(pdev, 0, 15, 0); | |
1070 | } | |
1071 | } | |
1072 | ||
f7625980 | 1073 | /** |
1da177e4 LT |
1074 | * pci_restore_state - Restore the saved state of a PCI device |
1075 | * @dev: - PCI device that we're dealing with | |
1da177e4 | 1076 | */ |
1d3c16a8 | 1077 | void pci_restore_state(struct pci_dev *dev) |
1da177e4 | 1078 | { |
c82f63e4 | 1079 | if (!dev->state_saved) |
1d3c16a8 | 1080 | return; |
4b77b0a2 | 1081 | |
b56a5a23 MT |
1082 | /* PCI Express register must be restored first */ |
1083 | pci_restore_pcie_state(dev); | |
1900ca13 | 1084 | pci_restore_ats_state(dev); |
425c1b22 | 1085 | pci_restore_vc_state(dev); |
b56a5a23 | 1086 | |
a6cb9ee7 | 1087 | pci_restore_config_space(dev); |
ebfc5b80 | 1088 | |
cc692a5f | 1089 | pci_restore_pcix_state(dev); |
41017f0c | 1090 | pci_restore_msi_state(dev); |
8c5cdb6a | 1091 | pci_restore_iov_state(dev); |
8fed4b65 | 1092 | |
4b77b0a2 | 1093 | dev->state_saved = false; |
1da177e4 | 1094 | } |
b7fe9434 | 1095 | EXPORT_SYMBOL(pci_restore_state); |
1da177e4 | 1096 | |
ffbdd3f7 AW |
1097 | struct pci_saved_state { |
1098 | u32 config_space[16]; | |
1099 | struct pci_cap_saved_data cap[0]; | |
1100 | }; | |
1101 | ||
1102 | /** | |
1103 | * pci_store_saved_state - Allocate and return an opaque struct containing | |
1104 | * the device saved state. | |
1105 | * @dev: PCI device that we're dealing with | |
1106 | * | |
f7625980 | 1107 | * Return NULL if no state or error. |
ffbdd3f7 AW |
1108 | */ |
1109 | struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev) | |
1110 | { | |
1111 | struct pci_saved_state *state; | |
1112 | struct pci_cap_saved_state *tmp; | |
1113 | struct pci_cap_saved_data *cap; | |
ffbdd3f7 AW |
1114 | size_t size; |
1115 | ||
1116 | if (!dev->state_saved) | |
1117 | return NULL; | |
1118 | ||
1119 | size = sizeof(*state) + sizeof(struct pci_cap_saved_data); | |
1120 | ||
b67bfe0d | 1121 | hlist_for_each_entry(tmp, &dev->saved_cap_space, next) |
ffbdd3f7 AW |
1122 | size += sizeof(struct pci_cap_saved_data) + tmp->cap.size; |
1123 | ||
1124 | state = kzalloc(size, GFP_KERNEL); | |
1125 | if (!state) | |
1126 | return NULL; | |
1127 | ||
1128 | memcpy(state->config_space, dev->saved_config_space, | |
1129 | sizeof(state->config_space)); | |
1130 | ||
1131 | cap = state->cap; | |
b67bfe0d | 1132 | hlist_for_each_entry(tmp, &dev->saved_cap_space, next) { |
ffbdd3f7 AW |
1133 | size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size; |
1134 | memcpy(cap, &tmp->cap, len); | |
1135 | cap = (struct pci_cap_saved_data *)((u8 *)cap + len); | |
1136 | } | |
1137 | /* Empty cap_save terminates list */ | |
1138 | ||
1139 | return state; | |
1140 | } | |
1141 | EXPORT_SYMBOL_GPL(pci_store_saved_state); | |
1142 | ||
1143 | /** | |
1144 | * pci_load_saved_state - Reload the provided save state into struct pci_dev. | |
1145 | * @dev: PCI device that we're dealing with | |
1146 | * @state: Saved state returned from pci_store_saved_state() | |
1147 | */ | |
0b950f0f SH |
1148 | static int pci_load_saved_state(struct pci_dev *dev, |
1149 | struct pci_saved_state *state) | |
ffbdd3f7 AW |
1150 | { |
1151 | struct pci_cap_saved_data *cap; | |
1152 | ||
1153 | dev->state_saved = false; | |
1154 | ||
1155 | if (!state) | |
1156 | return 0; | |
1157 | ||
1158 | memcpy(dev->saved_config_space, state->config_space, | |
1159 | sizeof(state->config_space)); | |
1160 | ||
1161 | cap = state->cap; | |
1162 | while (cap->size) { | |
1163 | struct pci_cap_saved_state *tmp; | |
1164 | ||
fd0f7f73 | 1165 | tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended); |
ffbdd3f7 AW |
1166 | if (!tmp || tmp->cap.size != cap->size) |
1167 | return -EINVAL; | |
1168 | ||
1169 | memcpy(tmp->cap.data, cap->data, tmp->cap.size); | |
1170 | cap = (struct pci_cap_saved_data *)((u8 *)cap + | |
1171 | sizeof(struct pci_cap_saved_data) + cap->size); | |
1172 | } | |
1173 | ||
1174 | dev->state_saved = true; | |
1175 | return 0; | |
1176 | } | |
ffbdd3f7 AW |
1177 | |
1178 | /** | |
1179 | * pci_load_and_free_saved_state - Reload the save state pointed to by state, | |
1180 | * and free the memory allocated for it. | |
1181 | * @dev: PCI device that we're dealing with | |
1182 | * @state: Pointer to saved state returned from pci_store_saved_state() | |
1183 | */ | |
1184 | int pci_load_and_free_saved_state(struct pci_dev *dev, | |
1185 | struct pci_saved_state **state) | |
1186 | { | |
1187 | int ret = pci_load_saved_state(dev, *state); | |
1188 | kfree(*state); | |
1189 | *state = NULL; | |
1190 | return ret; | |
1191 | } | |
1192 | EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state); | |
1193 | ||
8a9d5609 BH |
1194 | int __weak pcibios_enable_device(struct pci_dev *dev, int bars) |
1195 | { | |
1196 | return pci_enable_resources(dev, bars); | |
1197 | } | |
1198 | ||
38cc1302 HS |
1199 | static int do_pci_enable_device(struct pci_dev *dev, int bars) |
1200 | { | |
1201 | int err; | |
1e2571a7 BH |
1202 | u16 cmd; |
1203 | u8 pin; | |
38cc1302 HS |
1204 | |
1205 | err = pci_set_power_state(dev, PCI_D0); | |
1206 | if (err < 0 && err != -EIO) | |
1207 | return err; | |
1208 | err = pcibios_enable_device(dev, bars); | |
1209 | if (err < 0) | |
1210 | return err; | |
1211 | pci_fixup_device(pci_fixup_enable, dev); | |
1212 | ||
866d5417 BH |
1213 | if (dev->msi_enabled || dev->msix_enabled) |
1214 | return 0; | |
1215 | ||
1e2571a7 BH |
1216 | pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); |
1217 | if (pin) { | |
1218 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1219 | if (cmd & PCI_COMMAND_INTX_DISABLE) | |
1220 | pci_write_config_word(dev, PCI_COMMAND, | |
1221 | cmd & ~PCI_COMMAND_INTX_DISABLE); | |
1222 | } | |
1223 | ||
38cc1302 HS |
1224 | return 0; |
1225 | } | |
1226 | ||
1227 | /** | |
0b62e13b | 1228 | * pci_reenable_device - Resume abandoned device |
38cc1302 HS |
1229 | * @dev: PCI device to be resumed |
1230 | * | |
1231 | * Note this function is a backend of pci_default_resume and is not supposed | |
1232 | * to be called by normal code, write proper resume handler and use it instead. | |
1233 | */ | |
0b62e13b | 1234 | int pci_reenable_device(struct pci_dev *dev) |
38cc1302 | 1235 | { |
296ccb08 | 1236 | if (pci_is_enabled(dev)) |
38cc1302 HS |
1237 | return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); |
1238 | return 0; | |
1239 | } | |
b7fe9434 | 1240 | EXPORT_SYMBOL(pci_reenable_device); |
38cc1302 | 1241 | |
928bea96 YL |
1242 | static void pci_enable_bridge(struct pci_dev *dev) |
1243 | { | |
79272138 | 1244 | struct pci_dev *bridge; |
928bea96 YL |
1245 | int retval; |
1246 | ||
79272138 BH |
1247 | bridge = pci_upstream_bridge(dev); |
1248 | if (bridge) | |
1249 | pci_enable_bridge(bridge); | |
928bea96 | 1250 | |
cf3e1feb | 1251 | if (pci_is_enabled(dev)) { |
fbeeb822 | 1252 | if (!dev->is_busmaster) |
cf3e1feb | 1253 | pci_set_master(dev); |
928bea96 | 1254 | return; |
cf3e1feb YL |
1255 | } |
1256 | ||
928bea96 YL |
1257 | retval = pci_enable_device(dev); |
1258 | if (retval) | |
1259 | dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n", | |
1260 | retval); | |
1261 | pci_set_master(dev); | |
1262 | } | |
1263 | ||
b4b4fbba | 1264 | static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags) |
1da177e4 | 1265 | { |
79272138 | 1266 | struct pci_dev *bridge; |
1da177e4 | 1267 | int err; |
b718989d | 1268 | int i, bars = 0; |
1da177e4 | 1269 | |
97c145f7 JB |
1270 | /* |
1271 | * Power state could be unknown at this point, either due to a fresh | |
1272 | * boot or a device removal call. So get the current power state | |
1273 | * so that things like MSI message writing will behave as expected | |
1274 | * (e.g. if the device really is in D0 at enable time). | |
1275 | */ | |
1276 | if (dev->pm_cap) { | |
1277 | u16 pmcsr; | |
1278 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); | |
1279 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); | |
1280 | } | |
1281 | ||
cc7ba39b | 1282 | if (atomic_inc_return(&dev->enable_cnt) > 1) |
9fb625c3 HS |
1283 | return 0; /* already enabled */ |
1284 | ||
79272138 BH |
1285 | bridge = pci_upstream_bridge(dev); |
1286 | if (bridge) | |
1287 | pci_enable_bridge(bridge); | |
928bea96 | 1288 | |
497f16f2 YL |
1289 | /* only skip sriov related */ |
1290 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) | |
1291 | if (dev->resource[i].flags & flags) | |
1292 | bars |= (1 << i); | |
1293 | for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++) | |
b718989d BH |
1294 | if (dev->resource[i].flags & flags) |
1295 | bars |= (1 << i); | |
1296 | ||
38cc1302 | 1297 | err = do_pci_enable_device(dev, bars); |
95a62965 | 1298 | if (err < 0) |
38cc1302 | 1299 | atomic_dec(&dev->enable_cnt); |
9fb625c3 | 1300 | return err; |
1da177e4 LT |
1301 | } |
1302 | ||
b718989d BH |
1303 | /** |
1304 | * pci_enable_device_io - Initialize a device for use with IO space | |
1305 | * @dev: PCI device to be initialized | |
1306 | * | |
1307 | * Initialize device before it's used by a driver. Ask low-level code | |
1308 | * to enable I/O resources. Wake up the device if it was suspended. | |
1309 | * Beware, this function can fail. | |
1310 | */ | |
1311 | int pci_enable_device_io(struct pci_dev *dev) | |
1312 | { | |
b4b4fbba | 1313 | return pci_enable_device_flags(dev, IORESOURCE_IO); |
b718989d | 1314 | } |
b7fe9434 | 1315 | EXPORT_SYMBOL(pci_enable_device_io); |
b718989d BH |
1316 | |
1317 | /** | |
1318 | * pci_enable_device_mem - Initialize a device for use with Memory space | |
1319 | * @dev: PCI device to be initialized | |
1320 | * | |
1321 | * Initialize device before it's used by a driver. Ask low-level code | |
1322 | * to enable Memory resources. Wake up the device if it was suspended. | |
1323 | * Beware, this function can fail. | |
1324 | */ | |
1325 | int pci_enable_device_mem(struct pci_dev *dev) | |
1326 | { | |
b4b4fbba | 1327 | return pci_enable_device_flags(dev, IORESOURCE_MEM); |
b718989d | 1328 | } |
b7fe9434 | 1329 | EXPORT_SYMBOL(pci_enable_device_mem); |
b718989d | 1330 | |
bae94d02 IPG |
1331 | /** |
1332 | * pci_enable_device - Initialize device before it's used by a driver. | |
1333 | * @dev: PCI device to be initialized | |
1334 | * | |
1335 | * Initialize device before it's used by a driver. Ask low-level code | |
1336 | * to enable I/O and memory. Wake up the device if it was suspended. | |
1337 | * Beware, this function can fail. | |
1338 | * | |
1339 | * Note we don't actually enable the device many times if we call | |
1340 | * this function repeatedly (we just increment the count). | |
1341 | */ | |
1342 | int pci_enable_device(struct pci_dev *dev) | |
1343 | { | |
b4b4fbba | 1344 | return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO); |
bae94d02 | 1345 | } |
b7fe9434 | 1346 | EXPORT_SYMBOL(pci_enable_device); |
bae94d02 | 1347 | |
9ac7849e TH |
1348 | /* |
1349 | * Managed PCI resources. This manages device on/off, intx/msi/msix | |
1350 | * on/off and BAR regions. pci_dev itself records msi/msix status, so | |
1351 | * there's no need to track it separately. pci_devres is initialized | |
1352 | * when a device is enabled using managed PCI device enable interface. | |
1353 | */ | |
1354 | struct pci_devres { | |
7f375f32 TH |
1355 | unsigned int enabled:1; |
1356 | unsigned int pinned:1; | |
9ac7849e TH |
1357 | unsigned int orig_intx:1; |
1358 | unsigned int restore_intx:1; | |
1359 | u32 region_mask; | |
1360 | }; | |
1361 | ||
1362 | static void pcim_release(struct device *gendev, void *res) | |
1363 | { | |
1364 | struct pci_dev *dev = container_of(gendev, struct pci_dev, dev); | |
1365 | struct pci_devres *this = res; | |
1366 | int i; | |
1367 | ||
1368 | if (dev->msi_enabled) | |
1369 | pci_disable_msi(dev); | |
1370 | if (dev->msix_enabled) | |
1371 | pci_disable_msix(dev); | |
1372 | ||
1373 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) | |
1374 | if (this->region_mask & (1 << i)) | |
1375 | pci_release_region(dev, i); | |
1376 | ||
1377 | if (this->restore_intx) | |
1378 | pci_intx(dev, this->orig_intx); | |
1379 | ||
7f375f32 | 1380 | if (this->enabled && !this->pinned) |
9ac7849e TH |
1381 | pci_disable_device(dev); |
1382 | } | |
1383 | ||
1384 | static struct pci_devres * get_pci_dr(struct pci_dev *pdev) | |
1385 | { | |
1386 | struct pci_devres *dr, *new_dr; | |
1387 | ||
1388 | dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
1389 | if (dr) | |
1390 | return dr; | |
1391 | ||
1392 | new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL); | |
1393 | if (!new_dr) | |
1394 | return NULL; | |
1395 | return devres_get(&pdev->dev, new_dr, NULL, NULL); | |
1396 | } | |
1397 | ||
1398 | static struct pci_devres * find_pci_dr(struct pci_dev *pdev) | |
1399 | { | |
1400 | if (pci_is_managed(pdev)) | |
1401 | return devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
1402 | return NULL; | |
1403 | } | |
1404 | ||
1405 | /** | |
1406 | * pcim_enable_device - Managed pci_enable_device() | |
1407 | * @pdev: PCI device to be initialized | |
1408 | * | |
1409 | * Managed pci_enable_device(). | |
1410 | */ | |
1411 | int pcim_enable_device(struct pci_dev *pdev) | |
1412 | { | |
1413 | struct pci_devres *dr; | |
1414 | int rc; | |
1415 | ||
1416 | dr = get_pci_dr(pdev); | |
1417 | if (unlikely(!dr)) | |
1418 | return -ENOMEM; | |
b95d58ea TH |
1419 | if (dr->enabled) |
1420 | return 0; | |
9ac7849e TH |
1421 | |
1422 | rc = pci_enable_device(pdev); | |
1423 | if (!rc) { | |
1424 | pdev->is_managed = 1; | |
7f375f32 | 1425 | dr->enabled = 1; |
9ac7849e TH |
1426 | } |
1427 | return rc; | |
1428 | } | |
b7fe9434 | 1429 | EXPORT_SYMBOL(pcim_enable_device); |
9ac7849e TH |
1430 | |
1431 | /** | |
1432 | * pcim_pin_device - Pin managed PCI device | |
1433 | * @pdev: PCI device to pin | |
1434 | * | |
1435 | * Pin managed PCI device @pdev. Pinned device won't be disabled on | |
1436 | * driver detach. @pdev must have been enabled with | |
1437 | * pcim_enable_device(). | |
1438 | */ | |
1439 | void pcim_pin_device(struct pci_dev *pdev) | |
1440 | { | |
1441 | struct pci_devres *dr; | |
1442 | ||
1443 | dr = find_pci_dr(pdev); | |
7f375f32 | 1444 | WARN_ON(!dr || !dr->enabled); |
9ac7849e | 1445 | if (dr) |
7f375f32 | 1446 | dr->pinned = 1; |
9ac7849e | 1447 | } |
b7fe9434 | 1448 | EXPORT_SYMBOL(pcim_pin_device); |
9ac7849e | 1449 | |
eca0d467 MG |
1450 | /* |
1451 | * pcibios_add_device - provide arch specific hooks when adding device dev | |
1452 | * @dev: the PCI device being added | |
1453 | * | |
1454 | * Permits the platform to provide architecture specific functionality when | |
1455 | * devices are added. This is the default implementation. Architecture | |
1456 | * implementations can override this. | |
1457 | */ | |
1458 | int __weak pcibios_add_device (struct pci_dev *dev) | |
1459 | { | |
1460 | return 0; | |
1461 | } | |
1462 | ||
6ae32c53 SO |
1463 | /** |
1464 | * pcibios_release_device - provide arch specific hooks when releasing device dev | |
1465 | * @dev: the PCI device being released | |
1466 | * | |
1467 | * Permits the platform to provide architecture specific functionality when | |
1468 | * devices are released. This is the default implementation. Architecture | |
1469 | * implementations can override this. | |
1470 | */ | |
1471 | void __weak pcibios_release_device(struct pci_dev *dev) {} | |
1472 | ||
1da177e4 LT |
1473 | /** |
1474 | * pcibios_disable_device - disable arch specific PCI resources for device dev | |
1475 | * @dev: the PCI device to disable | |
1476 | * | |
1477 | * Disables architecture specific PCI resources for the device. This | |
1478 | * is the default implementation. Architecture implementations can | |
1479 | * override this. | |
1480 | */ | |
d6d88c83 | 1481 | void __weak pcibios_disable_device (struct pci_dev *dev) {} |
1da177e4 | 1482 | |
a43ae58c HG |
1483 | /** |
1484 | * pcibios_penalize_isa_irq - penalize an ISA IRQ | |
1485 | * @irq: ISA IRQ to penalize | |
1486 | * @active: IRQ active or not | |
1487 | * | |
1488 | * Permits the platform to provide architecture-specific functionality when | |
1489 | * penalizing ISA IRQs. This is the default implementation. Architecture | |
1490 | * implementations can override this. | |
1491 | */ | |
1492 | void __weak pcibios_penalize_isa_irq(int irq, int active) {} | |
1493 | ||
fa58d305 RW |
1494 | static void do_pci_disable_device(struct pci_dev *dev) |
1495 | { | |
1496 | u16 pci_command; | |
1497 | ||
1498 | pci_read_config_word(dev, PCI_COMMAND, &pci_command); | |
1499 | if (pci_command & PCI_COMMAND_MASTER) { | |
1500 | pci_command &= ~PCI_COMMAND_MASTER; | |
1501 | pci_write_config_word(dev, PCI_COMMAND, pci_command); | |
1502 | } | |
1503 | ||
1504 | pcibios_disable_device(dev); | |
1505 | } | |
1506 | ||
1507 | /** | |
1508 | * pci_disable_enabled_device - Disable device without updating enable_cnt | |
1509 | * @dev: PCI device to disable | |
1510 | * | |
1511 | * NOTE: This function is a backend of PCI power management routines and is | |
1512 | * not supposed to be called drivers. | |
1513 | */ | |
1514 | void pci_disable_enabled_device(struct pci_dev *dev) | |
1515 | { | |
296ccb08 | 1516 | if (pci_is_enabled(dev)) |
fa58d305 RW |
1517 | do_pci_disable_device(dev); |
1518 | } | |
1519 | ||
1da177e4 LT |
1520 | /** |
1521 | * pci_disable_device - Disable PCI device after use | |
1522 | * @dev: PCI device to be disabled | |
1523 | * | |
1524 | * Signal to the system that the PCI device is not in use by the system | |
1525 | * anymore. This only involves disabling PCI bus-mastering, if active. | |
bae94d02 IPG |
1526 | * |
1527 | * Note we don't actually disable the device until all callers of | |
ee6583f6 | 1528 | * pci_enable_device() have called pci_disable_device(). |
1da177e4 LT |
1529 | */ |
1530 | void | |
1531 | pci_disable_device(struct pci_dev *dev) | |
1532 | { | |
9ac7849e | 1533 | struct pci_devres *dr; |
99dc804d | 1534 | |
9ac7849e TH |
1535 | dr = find_pci_dr(dev); |
1536 | if (dr) | |
7f375f32 | 1537 | dr->enabled = 0; |
9ac7849e | 1538 | |
fd6dceab KK |
1539 | dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0, |
1540 | "disabling already-disabled device"); | |
1541 | ||
cc7ba39b | 1542 | if (atomic_dec_return(&dev->enable_cnt) != 0) |
bae94d02 IPG |
1543 | return; |
1544 | ||
fa58d305 | 1545 | do_pci_disable_device(dev); |
1da177e4 | 1546 | |
fa58d305 | 1547 | dev->is_busmaster = 0; |
1da177e4 | 1548 | } |
b7fe9434 | 1549 | EXPORT_SYMBOL(pci_disable_device); |
1da177e4 | 1550 | |
f7bdd12d BK |
1551 | /** |
1552 | * pcibios_set_pcie_reset_state - set reset state for device dev | |
45e829ea | 1553 | * @dev: the PCIe device reset |
f7bdd12d BK |
1554 | * @state: Reset state to enter into |
1555 | * | |
1556 | * | |
45e829ea | 1557 | * Sets the PCIe reset state for the device. This is the default |
f7bdd12d BK |
1558 | * implementation. Architecture implementations can override this. |
1559 | */ | |
d6d88c83 BH |
1560 | int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev, |
1561 | enum pcie_reset_state state) | |
f7bdd12d BK |
1562 | { |
1563 | return -EINVAL; | |
1564 | } | |
1565 | ||
1566 | /** | |
1567 | * pci_set_pcie_reset_state - set reset state for device dev | |
45e829ea | 1568 | * @dev: the PCIe device reset |
f7bdd12d BK |
1569 | * @state: Reset state to enter into |
1570 | * | |
1571 | * | |
1572 | * Sets the PCI reset state for the device. | |
1573 | */ | |
1574 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) | |
1575 | { | |
1576 | return pcibios_set_pcie_reset_state(dev, state); | |
1577 | } | |
b7fe9434 | 1578 | EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state); |
f7bdd12d | 1579 | |
58ff4633 RW |
1580 | /** |
1581 | * pci_check_pme_status - Check if given device has generated PME. | |
1582 | * @dev: Device to check. | |
1583 | * | |
1584 | * Check the PME status of the device and if set, clear it and clear PME enable | |
1585 | * (if set). Return 'true' if PME status and PME enable were both set or | |
1586 | * 'false' otherwise. | |
1587 | */ | |
1588 | bool pci_check_pme_status(struct pci_dev *dev) | |
1589 | { | |
1590 | int pmcsr_pos; | |
1591 | u16 pmcsr; | |
1592 | bool ret = false; | |
1593 | ||
1594 | if (!dev->pm_cap) | |
1595 | return false; | |
1596 | ||
1597 | pmcsr_pos = dev->pm_cap + PCI_PM_CTRL; | |
1598 | pci_read_config_word(dev, pmcsr_pos, &pmcsr); | |
1599 | if (!(pmcsr & PCI_PM_CTRL_PME_STATUS)) | |
1600 | return false; | |
1601 | ||
1602 | /* Clear PME status. */ | |
1603 | pmcsr |= PCI_PM_CTRL_PME_STATUS; | |
1604 | if (pmcsr & PCI_PM_CTRL_PME_ENABLE) { | |
1605 | /* Disable PME to avoid interrupt flood. */ | |
1606 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
1607 | ret = true; | |
1608 | } | |
1609 | ||
1610 | pci_write_config_word(dev, pmcsr_pos, pmcsr); | |
1611 | ||
1612 | return ret; | |
1613 | } | |
1614 | ||
b67ea761 RW |
1615 | /** |
1616 | * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set. | |
1617 | * @dev: Device to handle. | |
379021d5 | 1618 | * @pme_poll_reset: Whether or not to reset the device's pme_poll flag. |
b67ea761 RW |
1619 | * |
1620 | * Check if @dev has generated PME and queue a resume request for it in that | |
1621 | * case. | |
1622 | */ | |
379021d5 | 1623 | static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset) |
b67ea761 | 1624 | { |
379021d5 RW |
1625 | if (pme_poll_reset && dev->pme_poll) |
1626 | dev->pme_poll = false; | |
1627 | ||
c125e96f | 1628 | if (pci_check_pme_status(dev)) { |
c125e96f | 1629 | pci_wakeup_event(dev); |
0f953bf6 | 1630 | pm_request_resume(&dev->dev); |
c125e96f | 1631 | } |
b67ea761 RW |
1632 | return 0; |
1633 | } | |
1634 | ||
1635 | /** | |
1636 | * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary. | |
1637 | * @bus: Top bus of the subtree to walk. | |
1638 | */ | |
1639 | void pci_pme_wakeup_bus(struct pci_bus *bus) | |
1640 | { | |
1641 | if (bus) | |
379021d5 | 1642 | pci_walk_bus(bus, pci_pme_wakeup, (void *)true); |
b67ea761 RW |
1643 | } |
1644 | ||
448bd857 | 1645 | |
eb9d0fe4 RW |
1646 | /** |
1647 | * pci_pme_capable - check the capability of PCI device to generate PME# | |
1648 | * @dev: PCI device to handle. | |
eb9d0fe4 RW |
1649 | * @state: PCI state from which device will issue PME#. |
1650 | */ | |
e5899e1b | 1651 | bool pci_pme_capable(struct pci_dev *dev, pci_power_t state) |
eb9d0fe4 | 1652 | { |
337001b6 | 1653 | if (!dev->pm_cap) |
eb9d0fe4 RW |
1654 | return false; |
1655 | ||
337001b6 | 1656 | return !!(dev->pme_support & (1 << state)); |
eb9d0fe4 | 1657 | } |
b7fe9434 | 1658 | EXPORT_SYMBOL(pci_pme_capable); |
eb9d0fe4 | 1659 | |
df17e62e MG |
1660 | static void pci_pme_list_scan(struct work_struct *work) |
1661 | { | |
379021d5 | 1662 | struct pci_pme_device *pme_dev, *n; |
df17e62e MG |
1663 | |
1664 | mutex_lock(&pci_pme_list_mutex); | |
ce300008 BH |
1665 | list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) { |
1666 | if (pme_dev->dev->pme_poll) { | |
1667 | struct pci_dev *bridge; | |
1668 | ||
1669 | bridge = pme_dev->dev->bus->self; | |
1670 | /* | |
1671 | * If bridge is in low power state, the | |
1672 | * configuration space of subordinate devices | |
1673 | * may be not accessible | |
1674 | */ | |
1675 | if (bridge && bridge->current_state != PCI_D0) | |
1676 | continue; | |
1677 | pci_pme_wakeup(pme_dev->dev, NULL); | |
1678 | } else { | |
1679 | list_del(&pme_dev->list); | |
1680 | kfree(pme_dev); | |
379021d5 | 1681 | } |
df17e62e | 1682 | } |
ce300008 BH |
1683 | if (!list_empty(&pci_pme_list)) |
1684 | schedule_delayed_work(&pci_pme_work, | |
1685 | msecs_to_jiffies(PME_TIMEOUT)); | |
df17e62e MG |
1686 | mutex_unlock(&pci_pme_list_mutex); |
1687 | } | |
1688 | ||
eb9d0fe4 RW |
1689 | /** |
1690 | * pci_pme_active - enable or disable PCI device's PME# function | |
1691 | * @dev: PCI device to handle. | |
eb9d0fe4 RW |
1692 | * @enable: 'true' to enable PME# generation; 'false' to disable it. |
1693 | * | |
1694 | * The caller must verify that the device is capable of generating PME# before | |
1695 | * calling this function with @enable equal to 'true'. | |
1696 | */ | |
5a6c9b60 | 1697 | void pci_pme_active(struct pci_dev *dev, bool enable) |
eb9d0fe4 RW |
1698 | { |
1699 | u16 pmcsr; | |
1700 | ||
ffaddbe8 | 1701 | if (!dev->pme_support) |
eb9d0fe4 RW |
1702 | return; |
1703 | ||
337001b6 | 1704 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
eb9d0fe4 RW |
1705 | /* Clear PME_Status by writing 1 to it and enable PME# */ |
1706 | pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; | |
1707 | if (!enable) | |
1708 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
1709 | ||
337001b6 | 1710 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
eb9d0fe4 | 1711 | |
6e965e0d HY |
1712 | /* |
1713 | * PCI (as opposed to PCIe) PME requires that the device have | |
1714 | * its PME# line hooked up correctly. Not all hardware vendors | |
1715 | * do this, so the PME never gets delivered and the device | |
1716 | * remains asleep. The easiest way around this is to | |
1717 | * periodically walk the list of suspended devices and check | |
1718 | * whether any have their PME flag set. The assumption is that | |
1719 | * we'll wake up often enough anyway that this won't be a huge | |
1720 | * hit, and the power savings from the devices will still be a | |
1721 | * win. | |
1722 | * | |
1723 | * Although PCIe uses in-band PME message instead of PME# line | |
1724 | * to report PME, PME does not work for some PCIe devices in | |
1725 | * reality. For example, there are devices that set their PME | |
1726 | * status bits, but don't really bother to send a PME message; | |
1727 | * there are PCI Express Root Ports that don't bother to | |
1728 | * trigger interrupts when they receive PME messages from the | |
1729 | * devices below. So PME poll is used for PCIe devices too. | |
1730 | */ | |
df17e62e | 1731 | |
379021d5 | 1732 | if (dev->pme_poll) { |
df17e62e MG |
1733 | struct pci_pme_device *pme_dev; |
1734 | if (enable) { | |
1735 | pme_dev = kmalloc(sizeof(struct pci_pme_device), | |
1736 | GFP_KERNEL); | |
0394cb19 BH |
1737 | if (!pme_dev) { |
1738 | dev_warn(&dev->dev, "can't enable PME#\n"); | |
1739 | return; | |
1740 | } | |
df17e62e MG |
1741 | pme_dev->dev = dev; |
1742 | mutex_lock(&pci_pme_list_mutex); | |
1743 | list_add(&pme_dev->list, &pci_pme_list); | |
1744 | if (list_is_singular(&pci_pme_list)) | |
1745 | schedule_delayed_work(&pci_pme_work, | |
1746 | msecs_to_jiffies(PME_TIMEOUT)); | |
1747 | mutex_unlock(&pci_pme_list_mutex); | |
1748 | } else { | |
1749 | mutex_lock(&pci_pme_list_mutex); | |
1750 | list_for_each_entry(pme_dev, &pci_pme_list, list) { | |
1751 | if (pme_dev->dev == dev) { | |
1752 | list_del(&pme_dev->list); | |
1753 | kfree(pme_dev); | |
1754 | break; | |
1755 | } | |
1756 | } | |
1757 | mutex_unlock(&pci_pme_list_mutex); | |
1758 | } | |
1759 | } | |
1760 | ||
85b8582d | 1761 | dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled"); |
eb9d0fe4 | 1762 | } |
b7fe9434 | 1763 | EXPORT_SYMBOL(pci_pme_active); |
eb9d0fe4 | 1764 | |
1da177e4 | 1765 | /** |
6cbf8214 | 1766 | * __pci_enable_wake - enable PCI device as wakeup event source |
075c1771 DB |
1767 | * @dev: PCI device affected |
1768 | * @state: PCI state from which device will issue wakeup events | |
6cbf8214 | 1769 | * @runtime: True if the events are to be generated at run time |
075c1771 DB |
1770 | * @enable: True to enable event generation; false to disable |
1771 | * | |
1772 | * This enables the device as a wakeup event source, or disables it. | |
1773 | * When such events involves platform-specific hooks, those hooks are | |
1774 | * called automatically by this routine. | |
1775 | * | |
1776 | * Devices with legacy power management (no standard PCI PM capabilities) | |
eb9d0fe4 | 1777 | * always require such platform hooks. |
075c1771 | 1778 | * |
eb9d0fe4 RW |
1779 | * RETURN VALUE: |
1780 | * 0 is returned on success | |
1781 | * -EINVAL is returned if device is not supposed to wake up the system | |
1782 | * Error code depending on the platform is returned if both the platform and | |
1783 | * the native mechanism fail to enable the generation of wake-up events | |
1da177e4 | 1784 | */ |
6cbf8214 RW |
1785 | int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, |
1786 | bool runtime, bool enable) | |
1da177e4 | 1787 | { |
5bcc2fb4 | 1788 | int ret = 0; |
075c1771 | 1789 | |
6cbf8214 | 1790 | if (enable && !runtime && !device_may_wakeup(&dev->dev)) |
eb9d0fe4 | 1791 | return -EINVAL; |
1da177e4 | 1792 | |
e80bb09d RW |
1793 | /* Don't do the same thing twice in a row for one device. */ |
1794 | if (!!enable == !!dev->wakeup_prepared) | |
1795 | return 0; | |
1796 | ||
eb9d0fe4 RW |
1797 | /* |
1798 | * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don | |
1799 | * Anderson we should be doing PME# wake enable followed by ACPI wake | |
1800 | * enable. To disable wake-up we call the platform first, for symmetry. | |
075c1771 | 1801 | */ |
1da177e4 | 1802 | |
5bcc2fb4 RW |
1803 | if (enable) { |
1804 | int error; | |
1da177e4 | 1805 | |
5bcc2fb4 RW |
1806 | if (pci_pme_capable(dev, state)) |
1807 | pci_pme_active(dev, true); | |
1808 | else | |
1809 | ret = 1; | |
6cbf8214 RW |
1810 | error = runtime ? platform_pci_run_wake(dev, true) : |
1811 | platform_pci_sleep_wake(dev, true); | |
5bcc2fb4 RW |
1812 | if (ret) |
1813 | ret = error; | |
e80bb09d RW |
1814 | if (!ret) |
1815 | dev->wakeup_prepared = true; | |
5bcc2fb4 | 1816 | } else { |
6cbf8214 RW |
1817 | if (runtime) |
1818 | platform_pci_run_wake(dev, false); | |
1819 | else | |
1820 | platform_pci_sleep_wake(dev, false); | |
5bcc2fb4 | 1821 | pci_pme_active(dev, false); |
e80bb09d | 1822 | dev->wakeup_prepared = false; |
5bcc2fb4 | 1823 | } |
1da177e4 | 1824 | |
5bcc2fb4 | 1825 | return ret; |
eb9d0fe4 | 1826 | } |
6cbf8214 | 1827 | EXPORT_SYMBOL(__pci_enable_wake); |
1da177e4 | 1828 | |
0235c4fc RW |
1829 | /** |
1830 | * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold | |
1831 | * @dev: PCI device to prepare | |
1832 | * @enable: True to enable wake-up event generation; false to disable | |
1833 | * | |
1834 | * Many drivers want the device to wake up the system from D3_hot or D3_cold | |
1835 | * and this function allows them to set that up cleanly - pci_enable_wake() | |
1836 | * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI | |
1837 | * ordering constraints. | |
1838 | * | |
1839 | * This function only returns error code if the device is not capable of | |
1840 | * generating PME# from both D3_hot and D3_cold, and the platform is unable to | |
1841 | * enable wake-up power for it. | |
1842 | */ | |
1843 | int pci_wake_from_d3(struct pci_dev *dev, bool enable) | |
1844 | { | |
1845 | return pci_pme_capable(dev, PCI_D3cold) ? | |
1846 | pci_enable_wake(dev, PCI_D3cold, enable) : | |
1847 | pci_enable_wake(dev, PCI_D3hot, enable); | |
1848 | } | |
b7fe9434 | 1849 | EXPORT_SYMBOL(pci_wake_from_d3); |
0235c4fc | 1850 | |
404cc2d8 | 1851 | /** |
37139074 JB |
1852 | * pci_target_state - find an appropriate low power state for a given PCI dev |
1853 | * @dev: PCI device | |
1854 | * | |
1855 | * Use underlying platform code to find a supported low power state for @dev. | |
1856 | * If the platform can't manage @dev, return the deepest state from which it | |
1857 | * can generate wake events, based on any available PME info. | |
404cc2d8 | 1858 | */ |
0b950f0f | 1859 | static pci_power_t pci_target_state(struct pci_dev *dev) |
404cc2d8 RW |
1860 | { |
1861 | pci_power_t target_state = PCI_D3hot; | |
404cc2d8 RW |
1862 | |
1863 | if (platform_pci_power_manageable(dev)) { | |
1864 | /* | |
1865 | * Call the platform to choose the target state of the device | |
1866 | * and enable wake-up from this state if supported. | |
1867 | */ | |
1868 | pci_power_t state = platform_pci_choose_state(dev); | |
1869 | ||
1870 | switch (state) { | |
1871 | case PCI_POWER_ERROR: | |
1872 | case PCI_UNKNOWN: | |
1873 | break; | |
1874 | case PCI_D1: | |
1875 | case PCI_D2: | |
1876 | if (pci_no_d1d2(dev)) | |
1877 | break; | |
1878 | default: | |
1879 | target_state = state; | |
404cc2d8 | 1880 | } |
d2abdf62 RW |
1881 | } else if (!dev->pm_cap) { |
1882 | target_state = PCI_D0; | |
404cc2d8 RW |
1883 | } else if (device_may_wakeup(&dev->dev)) { |
1884 | /* | |
1885 | * Find the deepest state from which the device can generate | |
1886 | * wake-up events, make it the target state and enable device | |
1887 | * to generate PME#. | |
1888 | */ | |
337001b6 RW |
1889 | if (dev->pme_support) { |
1890 | while (target_state | |
1891 | && !(dev->pme_support & (1 << target_state))) | |
1892 | target_state--; | |
404cc2d8 RW |
1893 | } |
1894 | } | |
1895 | ||
e5899e1b RW |
1896 | return target_state; |
1897 | } | |
1898 | ||
1899 | /** | |
1900 | * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state | |
1901 | * @dev: Device to handle. | |
1902 | * | |
1903 | * Choose the power state appropriate for the device depending on whether | |
1904 | * it can wake up the system and/or is power manageable by the platform | |
1905 | * (PCI_D3hot is the default) and put the device into that state. | |
1906 | */ | |
1907 | int pci_prepare_to_sleep(struct pci_dev *dev) | |
1908 | { | |
1909 | pci_power_t target_state = pci_target_state(dev); | |
1910 | int error; | |
1911 | ||
1912 | if (target_state == PCI_POWER_ERROR) | |
1913 | return -EIO; | |
1914 | ||
448bd857 HY |
1915 | /* D3cold during system suspend/hibernate is not supported */ |
1916 | if (target_state > PCI_D3hot) | |
1917 | target_state = PCI_D3hot; | |
1918 | ||
8efb8c76 | 1919 | pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev)); |
c157dfa3 | 1920 | |
404cc2d8 RW |
1921 | error = pci_set_power_state(dev, target_state); |
1922 | ||
1923 | if (error) | |
1924 | pci_enable_wake(dev, target_state, false); | |
1925 | ||
1926 | return error; | |
1927 | } | |
b7fe9434 | 1928 | EXPORT_SYMBOL(pci_prepare_to_sleep); |
404cc2d8 RW |
1929 | |
1930 | /** | |
443bd1c4 | 1931 | * pci_back_from_sleep - turn PCI device on during system-wide transition into working state |
404cc2d8 RW |
1932 | * @dev: Device to handle. |
1933 | * | |
88393161 | 1934 | * Disable device's system wake-up capability and put it into D0. |
404cc2d8 RW |
1935 | */ |
1936 | int pci_back_from_sleep(struct pci_dev *dev) | |
1937 | { | |
1938 | pci_enable_wake(dev, PCI_D0, false); | |
1939 | return pci_set_power_state(dev, PCI_D0); | |
1940 | } | |
b7fe9434 | 1941 | EXPORT_SYMBOL(pci_back_from_sleep); |
404cc2d8 | 1942 | |
6cbf8214 RW |
1943 | /** |
1944 | * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend. | |
1945 | * @dev: PCI device being suspended. | |
1946 | * | |
1947 | * Prepare @dev to generate wake-up events at run time and put it into a low | |
1948 | * power state. | |
1949 | */ | |
1950 | int pci_finish_runtime_suspend(struct pci_dev *dev) | |
1951 | { | |
1952 | pci_power_t target_state = pci_target_state(dev); | |
1953 | int error; | |
1954 | ||
1955 | if (target_state == PCI_POWER_ERROR) | |
1956 | return -EIO; | |
1957 | ||
448bd857 HY |
1958 | dev->runtime_d3cold = target_state == PCI_D3cold; |
1959 | ||
6cbf8214 RW |
1960 | __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev)); |
1961 | ||
1962 | error = pci_set_power_state(dev, target_state); | |
1963 | ||
448bd857 | 1964 | if (error) { |
6cbf8214 | 1965 | __pci_enable_wake(dev, target_state, true, false); |
448bd857 HY |
1966 | dev->runtime_d3cold = false; |
1967 | } | |
6cbf8214 RW |
1968 | |
1969 | return error; | |
1970 | } | |
1971 | ||
b67ea761 RW |
1972 | /** |
1973 | * pci_dev_run_wake - Check if device can generate run-time wake-up events. | |
1974 | * @dev: Device to check. | |
1975 | * | |
f7625980 | 1976 | * Return true if the device itself is capable of generating wake-up events |
b67ea761 RW |
1977 | * (through the platform or using the native PCIe PME) or if the device supports |
1978 | * PME and one of its upstream bridges can generate wake-up events. | |
1979 | */ | |
1980 | bool pci_dev_run_wake(struct pci_dev *dev) | |
1981 | { | |
1982 | struct pci_bus *bus = dev->bus; | |
1983 | ||
1984 | if (device_run_wake(&dev->dev)) | |
1985 | return true; | |
1986 | ||
1987 | if (!dev->pme_support) | |
1988 | return false; | |
1989 | ||
1990 | while (bus->parent) { | |
1991 | struct pci_dev *bridge = bus->self; | |
1992 | ||
1993 | if (device_run_wake(&bridge->dev)) | |
1994 | return true; | |
1995 | ||
1996 | bus = bus->parent; | |
1997 | } | |
1998 | ||
1999 | /* We have reached the root bus. */ | |
2000 | if (bus->bridge) | |
2001 | return device_run_wake(bus->bridge); | |
2002 | ||
2003 | return false; | |
2004 | } | |
2005 | EXPORT_SYMBOL_GPL(pci_dev_run_wake); | |
2006 | ||
b3c32c4f HY |
2007 | void pci_config_pm_runtime_get(struct pci_dev *pdev) |
2008 | { | |
2009 | struct device *dev = &pdev->dev; | |
2010 | struct device *parent = dev->parent; | |
2011 | ||
2012 | if (parent) | |
2013 | pm_runtime_get_sync(parent); | |
2014 | pm_runtime_get_noresume(dev); | |
2015 | /* | |
2016 | * pdev->current_state is set to PCI_D3cold during suspending, | |
2017 | * so wait until suspending completes | |
2018 | */ | |
2019 | pm_runtime_barrier(dev); | |
2020 | /* | |
2021 | * Only need to resume devices in D3cold, because config | |
2022 | * registers are still accessible for devices suspended but | |
2023 | * not in D3cold. | |
2024 | */ | |
2025 | if (pdev->current_state == PCI_D3cold) | |
2026 | pm_runtime_resume(dev); | |
2027 | } | |
2028 | ||
2029 | void pci_config_pm_runtime_put(struct pci_dev *pdev) | |
2030 | { | |
2031 | struct device *dev = &pdev->dev; | |
2032 | struct device *parent = dev->parent; | |
2033 | ||
2034 | pm_runtime_put(dev); | |
2035 | if (parent) | |
2036 | pm_runtime_put_sync(parent); | |
2037 | } | |
2038 | ||
eb9d0fe4 RW |
2039 | /** |
2040 | * pci_pm_init - Initialize PM functions of given PCI device | |
2041 | * @dev: PCI device to handle. | |
2042 | */ | |
2043 | void pci_pm_init(struct pci_dev *dev) | |
2044 | { | |
2045 | int pm; | |
2046 | u16 pmc; | |
1da177e4 | 2047 | |
bb910a70 | 2048 | pm_runtime_forbid(&dev->dev); |
967577b0 HY |
2049 | pm_runtime_set_active(&dev->dev); |
2050 | pm_runtime_enable(&dev->dev); | |
a1e4d72c | 2051 | device_enable_async_suspend(&dev->dev); |
e80bb09d | 2052 | dev->wakeup_prepared = false; |
bb910a70 | 2053 | |
337001b6 | 2054 | dev->pm_cap = 0; |
ffaddbe8 | 2055 | dev->pme_support = 0; |
337001b6 | 2056 | |
eb9d0fe4 RW |
2057 | /* find PCI PM capability in list */ |
2058 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
2059 | if (!pm) | |
50246dd4 | 2060 | return; |
eb9d0fe4 RW |
2061 | /* Check device's ability to generate PME# */ |
2062 | pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc); | |
075c1771 | 2063 | |
eb9d0fe4 RW |
2064 | if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { |
2065 | dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n", | |
2066 | pmc & PCI_PM_CAP_VER_MASK); | |
50246dd4 | 2067 | return; |
eb9d0fe4 RW |
2068 | } |
2069 | ||
337001b6 | 2070 | dev->pm_cap = pm; |
1ae861e6 | 2071 | dev->d3_delay = PCI_PM_D3_WAIT; |
448bd857 | 2072 | dev->d3cold_delay = PCI_PM_D3COLD_WAIT; |
4f9c1397 | 2073 | dev->d3cold_allowed = true; |
337001b6 RW |
2074 | |
2075 | dev->d1_support = false; | |
2076 | dev->d2_support = false; | |
2077 | if (!pci_no_d1d2(dev)) { | |
c9ed77ee | 2078 | if (pmc & PCI_PM_CAP_D1) |
337001b6 | 2079 | dev->d1_support = true; |
c9ed77ee | 2080 | if (pmc & PCI_PM_CAP_D2) |
337001b6 | 2081 | dev->d2_support = true; |
c9ed77ee BH |
2082 | |
2083 | if (dev->d1_support || dev->d2_support) | |
2084 | dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n", | |
ec84f126 JB |
2085 | dev->d1_support ? " D1" : "", |
2086 | dev->d2_support ? " D2" : ""); | |
337001b6 RW |
2087 | } |
2088 | ||
2089 | pmc &= PCI_PM_CAP_PME_MASK; | |
2090 | if (pmc) { | |
10c3d71d BH |
2091 | dev_printk(KERN_DEBUG, &dev->dev, |
2092 | "PME# supported from%s%s%s%s%s\n", | |
c9ed77ee BH |
2093 | (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "", |
2094 | (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "", | |
2095 | (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "", | |
2096 | (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "", | |
2097 | (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : ""); | |
337001b6 | 2098 | dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT; |
379021d5 | 2099 | dev->pme_poll = true; |
eb9d0fe4 RW |
2100 | /* |
2101 | * Make device's PM flags reflect the wake-up capability, but | |
2102 | * let the user space enable it to wake up the system as needed. | |
2103 | */ | |
2104 | device_set_wakeup_capable(&dev->dev, true); | |
eb9d0fe4 | 2105 | /* Disable the PME# generation functionality */ |
337001b6 | 2106 | pci_pme_active(dev, false); |
eb9d0fe4 | 2107 | } |
1da177e4 LT |
2108 | } |
2109 | ||
34a4876e YL |
2110 | static void pci_add_saved_cap(struct pci_dev *pci_dev, |
2111 | struct pci_cap_saved_state *new_cap) | |
2112 | { | |
2113 | hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space); | |
2114 | } | |
2115 | ||
63f4898a | 2116 | /** |
fd0f7f73 AW |
2117 | * _pci_add_cap_save_buffer - allocate buffer for saving given |
2118 | * capability registers | |
63f4898a RW |
2119 | * @dev: the PCI device |
2120 | * @cap: the capability to allocate the buffer for | |
fd0f7f73 | 2121 | * @extended: Standard or Extended capability ID |
63f4898a RW |
2122 | * @size: requested size of the buffer |
2123 | */ | |
fd0f7f73 AW |
2124 | static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap, |
2125 | bool extended, unsigned int size) | |
63f4898a RW |
2126 | { |
2127 | int pos; | |
2128 | struct pci_cap_saved_state *save_state; | |
2129 | ||
fd0f7f73 AW |
2130 | if (extended) |
2131 | pos = pci_find_ext_capability(dev, cap); | |
2132 | else | |
2133 | pos = pci_find_capability(dev, cap); | |
2134 | ||
63f4898a RW |
2135 | if (pos <= 0) |
2136 | return 0; | |
2137 | ||
2138 | save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL); | |
2139 | if (!save_state) | |
2140 | return -ENOMEM; | |
2141 | ||
24a4742f | 2142 | save_state->cap.cap_nr = cap; |
fd0f7f73 | 2143 | save_state->cap.cap_extended = extended; |
24a4742f | 2144 | save_state->cap.size = size; |
63f4898a RW |
2145 | pci_add_saved_cap(dev, save_state); |
2146 | ||
2147 | return 0; | |
2148 | } | |
2149 | ||
fd0f7f73 AW |
2150 | int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size) |
2151 | { | |
2152 | return _pci_add_cap_save_buffer(dev, cap, false, size); | |
2153 | } | |
2154 | ||
2155 | int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size) | |
2156 | { | |
2157 | return _pci_add_cap_save_buffer(dev, cap, true, size); | |
2158 | } | |
2159 | ||
63f4898a RW |
2160 | /** |
2161 | * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities | |
2162 | * @dev: the PCI device | |
2163 | */ | |
2164 | void pci_allocate_cap_save_buffers(struct pci_dev *dev) | |
2165 | { | |
2166 | int error; | |
2167 | ||
89858517 YZ |
2168 | error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP, |
2169 | PCI_EXP_SAVE_REGS * sizeof(u16)); | |
63f4898a RW |
2170 | if (error) |
2171 | dev_err(&dev->dev, | |
2172 | "unable to preallocate PCI Express save buffer\n"); | |
2173 | ||
2174 | error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16)); | |
2175 | if (error) | |
2176 | dev_err(&dev->dev, | |
2177 | "unable to preallocate PCI-X save buffer\n"); | |
425c1b22 AW |
2178 | |
2179 | pci_allocate_vc_save_buffers(dev); | |
63f4898a RW |
2180 | } |
2181 | ||
f796841e YL |
2182 | void pci_free_cap_save_buffers(struct pci_dev *dev) |
2183 | { | |
2184 | struct pci_cap_saved_state *tmp; | |
b67bfe0d | 2185 | struct hlist_node *n; |
f796841e | 2186 | |
b67bfe0d | 2187 | hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next) |
f796841e YL |
2188 | kfree(tmp); |
2189 | } | |
2190 | ||
58c3a727 | 2191 | /** |
31ab2476 | 2192 | * pci_configure_ari - enable or disable ARI forwarding |
58c3a727 | 2193 | * @dev: the PCI device |
b0cc6020 YW |
2194 | * |
2195 | * If @dev and its upstream bridge both support ARI, enable ARI in the | |
2196 | * bridge. Otherwise, disable ARI in the bridge. | |
58c3a727 | 2197 | */ |
31ab2476 | 2198 | void pci_configure_ari(struct pci_dev *dev) |
58c3a727 | 2199 | { |
58c3a727 | 2200 | u32 cap; |
8113587c | 2201 | struct pci_dev *bridge; |
58c3a727 | 2202 | |
6748dcc2 | 2203 | if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn) |
58c3a727 YZ |
2204 | return; |
2205 | ||
8113587c | 2206 | bridge = dev->bus->self; |
cb97ae34 | 2207 | if (!bridge) |
8113587c ZY |
2208 | return; |
2209 | ||
59875ae4 | 2210 | pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap); |
58c3a727 YZ |
2211 | if (!(cap & PCI_EXP_DEVCAP2_ARI)) |
2212 | return; | |
2213 | ||
b0cc6020 YW |
2214 | if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) { |
2215 | pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2, | |
2216 | PCI_EXP_DEVCTL2_ARI); | |
2217 | bridge->ari_enabled = 1; | |
2218 | } else { | |
2219 | pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2, | |
2220 | PCI_EXP_DEVCTL2_ARI); | |
2221 | bridge->ari_enabled = 0; | |
2222 | } | |
58c3a727 YZ |
2223 | } |
2224 | ||
5d990b62 CW |
2225 | static int pci_acs_enable; |
2226 | ||
2227 | /** | |
2228 | * pci_request_acs - ask for ACS to be enabled if supported | |
2229 | */ | |
2230 | void pci_request_acs(void) | |
2231 | { | |
2232 | pci_acs_enable = 1; | |
2233 | } | |
2234 | ||
ae21ee65 | 2235 | /** |
2c744244 | 2236 | * pci_std_enable_acs - enable ACS on devices using standard ACS capabilites |
ae21ee65 AK |
2237 | * @dev: the PCI device |
2238 | */ | |
2c744244 | 2239 | static int pci_std_enable_acs(struct pci_dev *dev) |
ae21ee65 AK |
2240 | { |
2241 | int pos; | |
2242 | u16 cap; | |
2243 | u16 ctrl; | |
2244 | ||
ae21ee65 AK |
2245 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); |
2246 | if (!pos) | |
2c744244 | 2247 | return -ENODEV; |
ae21ee65 AK |
2248 | |
2249 | pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap); | |
2250 | pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl); | |
2251 | ||
2252 | /* Source Validation */ | |
2253 | ctrl |= (cap & PCI_ACS_SV); | |
2254 | ||
2255 | /* P2P Request Redirect */ | |
2256 | ctrl |= (cap & PCI_ACS_RR); | |
2257 | ||
2258 | /* P2P Completion Redirect */ | |
2259 | ctrl |= (cap & PCI_ACS_CR); | |
2260 | ||
2261 | /* Upstream Forwarding */ | |
2262 | ctrl |= (cap & PCI_ACS_UF); | |
2263 | ||
2264 | pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl); | |
2c744244 AW |
2265 | |
2266 | return 0; | |
2267 | } | |
2268 | ||
2269 | /** | |
2270 | * pci_enable_acs - enable ACS if hardware support it | |
2271 | * @dev: the PCI device | |
2272 | */ | |
2273 | void pci_enable_acs(struct pci_dev *dev) | |
2274 | { | |
2275 | if (!pci_acs_enable) | |
2276 | return; | |
2277 | ||
2278 | if (!pci_std_enable_acs(dev)) | |
2279 | return; | |
2280 | ||
2281 | pci_dev_specific_enable_acs(dev); | |
ae21ee65 AK |
2282 | } |
2283 | ||
0a67119f AW |
2284 | static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags) |
2285 | { | |
2286 | int pos; | |
83db7e0b | 2287 | u16 cap, ctrl; |
0a67119f AW |
2288 | |
2289 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS); | |
2290 | if (!pos) | |
2291 | return false; | |
2292 | ||
83db7e0b AW |
2293 | /* |
2294 | * Except for egress control, capabilities are either required | |
2295 | * or only required if controllable. Features missing from the | |
2296 | * capability field can therefore be assumed as hard-wired enabled. | |
2297 | */ | |
2298 | pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap); | |
2299 | acs_flags &= (cap | PCI_ACS_EC); | |
2300 | ||
0a67119f AW |
2301 | pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl); |
2302 | return (ctrl & acs_flags) == acs_flags; | |
2303 | } | |
2304 | ||
ad805758 AW |
2305 | /** |
2306 | * pci_acs_enabled - test ACS against required flags for a given device | |
2307 | * @pdev: device to test | |
2308 | * @acs_flags: required PCI ACS flags | |
2309 | * | |
2310 | * Return true if the device supports the provided flags. Automatically | |
2311 | * filters out flags that are not implemented on multifunction devices. | |
0a67119f AW |
2312 | * |
2313 | * Note that this interface checks the effective ACS capabilities of the | |
2314 | * device rather than the actual capabilities. For instance, most single | |
2315 | * function endpoints are not required to support ACS because they have no | |
2316 | * opportunity for peer-to-peer access. We therefore return 'true' | |
2317 | * regardless of whether the device exposes an ACS capability. This makes | |
2318 | * it much easier for callers of this function to ignore the actual type | |
2319 | * or topology of the device when testing ACS support. | |
ad805758 AW |
2320 | */ |
2321 | bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) | |
2322 | { | |
0a67119f | 2323 | int ret; |
ad805758 AW |
2324 | |
2325 | ret = pci_dev_specific_acs_enabled(pdev, acs_flags); | |
2326 | if (ret >= 0) | |
2327 | return ret > 0; | |
2328 | ||
0a67119f AW |
2329 | /* |
2330 | * Conventional PCI and PCI-X devices never support ACS, either | |
2331 | * effectively or actually. The shared bus topology implies that | |
2332 | * any device on the bus can receive or snoop DMA. | |
2333 | */ | |
ad805758 AW |
2334 | if (!pci_is_pcie(pdev)) |
2335 | return false; | |
2336 | ||
0a67119f AW |
2337 | switch (pci_pcie_type(pdev)) { |
2338 | /* | |
2339 | * PCI/X-to-PCIe bridges are not specifically mentioned by the spec, | |
f7625980 | 2340 | * but since their primary interface is PCI/X, we conservatively |
0a67119f AW |
2341 | * handle them as we would a non-PCIe device. |
2342 | */ | |
2343 | case PCI_EXP_TYPE_PCIE_BRIDGE: | |
2344 | /* | |
2345 | * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never | |
2346 | * applicable... must never implement an ACS Extended Capability...". | |
2347 | * This seems arbitrary, but we take a conservative interpretation | |
2348 | * of this statement. | |
2349 | */ | |
2350 | case PCI_EXP_TYPE_PCI_BRIDGE: | |
2351 | case PCI_EXP_TYPE_RC_EC: | |
2352 | return false; | |
2353 | /* | |
2354 | * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should | |
2355 | * implement ACS in order to indicate their peer-to-peer capabilities, | |
2356 | * regardless of whether they are single- or multi-function devices. | |
2357 | */ | |
2358 | case PCI_EXP_TYPE_DOWNSTREAM: | |
2359 | case PCI_EXP_TYPE_ROOT_PORT: | |
2360 | return pci_acs_flags_enabled(pdev, acs_flags); | |
2361 | /* | |
2362 | * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be | |
2363 | * implemented by the remaining PCIe types to indicate peer-to-peer | |
f7625980 | 2364 | * capabilities, but only when they are part of a multifunction |
0a67119f AW |
2365 | * device. The footnote for section 6.12 indicates the specific |
2366 | * PCIe types included here. | |
2367 | */ | |
2368 | case PCI_EXP_TYPE_ENDPOINT: | |
2369 | case PCI_EXP_TYPE_UPSTREAM: | |
2370 | case PCI_EXP_TYPE_LEG_END: | |
2371 | case PCI_EXP_TYPE_RC_END: | |
2372 | if (!pdev->multifunction) | |
2373 | break; | |
2374 | ||
0a67119f | 2375 | return pci_acs_flags_enabled(pdev, acs_flags); |
ad805758 AW |
2376 | } |
2377 | ||
0a67119f | 2378 | /* |
f7625980 | 2379 | * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable |
0a67119f AW |
2380 | * to single function devices with the exception of downstream ports. |
2381 | */ | |
ad805758 AW |
2382 | return true; |
2383 | } | |
2384 | ||
2385 | /** | |
2386 | * pci_acs_path_enable - test ACS flags from start to end in a hierarchy | |
2387 | * @start: starting downstream device | |
2388 | * @end: ending upstream device or NULL to search to the root bus | |
2389 | * @acs_flags: required flags | |
2390 | * | |
2391 | * Walk up a device tree from start to end testing PCI ACS support. If | |
2392 | * any step along the way does not support the required flags, return false. | |
2393 | */ | |
2394 | bool pci_acs_path_enabled(struct pci_dev *start, | |
2395 | struct pci_dev *end, u16 acs_flags) | |
2396 | { | |
2397 | struct pci_dev *pdev, *parent = start; | |
2398 | ||
2399 | do { | |
2400 | pdev = parent; | |
2401 | ||
2402 | if (!pci_acs_enabled(pdev, acs_flags)) | |
2403 | return false; | |
2404 | ||
2405 | if (pci_is_root_bus(pdev->bus)) | |
2406 | return (end == NULL); | |
2407 | ||
2408 | parent = pdev->bus->self; | |
2409 | } while (pdev != end); | |
2410 | ||
2411 | return true; | |
2412 | } | |
2413 | ||
57c2cf71 BH |
2414 | /** |
2415 | * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge | |
2416 | * @dev: the PCI device | |
bb5c2de2 | 2417 | * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD) |
57c2cf71 BH |
2418 | * |
2419 | * Perform INTx swizzling for a device behind one level of bridge. This is | |
2420 | * required by section 9.1 of the PCI-to-PCI bridge specification for devices | |
46b952a3 MW |
2421 | * behind bridges on add-in cards. For devices with ARI enabled, the slot |
2422 | * number is always 0 (see the Implementation Note in section 2.2.8.1 of | |
2423 | * the PCI Express Base Specification, Revision 2.1) | |
57c2cf71 | 2424 | */ |
3df425f3 | 2425 | u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin) |
57c2cf71 | 2426 | { |
46b952a3 MW |
2427 | int slot; |
2428 | ||
2429 | if (pci_ari_enabled(dev->bus)) | |
2430 | slot = 0; | |
2431 | else | |
2432 | slot = PCI_SLOT(dev->devfn); | |
2433 | ||
2434 | return (((pin - 1) + slot) % 4) + 1; | |
57c2cf71 BH |
2435 | } |
2436 | ||
1da177e4 LT |
2437 | int |
2438 | pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) | |
2439 | { | |
2440 | u8 pin; | |
2441 | ||
514d207d | 2442 | pin = dev->pin; |
1da177e4 LT |
2443 | if (!pin) |
2444 | return -1; | |
878f2e50 | 2445 | |
8784fd4d | 2446 | while (!pci_is_root_bus(dev->bus)) { |
57c2cf71 | 2447 | pin = pci_swizzle_interrupt_pin(dev, pin); |
1da177e4 LT |
2448 | dev = dev->bus->self; |
2449 | } | |
2450 | *bridge = dev; | |
2451 | return pin; | |
2452 | } | |
2453 | ||
68feac87 BH |
2454 | /** |
2455 | * pci_common_swizzle - swizzle INTx all the way to root bridge | |
2456 | * @dev: the PCI device | |
2457 | * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD) | |
2458 | * | |
2459 | * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI | |
2460 | * bridges all the way up to a PCI root bus. | |
2461 | */ | |
2462 | u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp) | |
2463 | { | |
2464 | u8 pin = *pinp; | |
2465 | ||
1eb39487 | 2466 | while (!pci_is_root_bus(dev->bus)) { |
68feac87 BH |
2467 | pin = pci_swizzle_interrupt_pin(dev, pin); |
2468 | dev = dev->bus->self; | |
2469 | } | |
2470 | *pinp = pin; | |
2471 | return PCI_SLOT(dev->devfn); | |
2472 | } | |
2473 | ||
1da177e4 LT |
2474 | /** |
2475 | * pci_release_region - Release a PCI bar | |
2476 | * @pdev: PCI device whose resources were previously reserved by pci_request_region | |
2477 | * @bar: BAR to release | |
2478 | * | |
2479 | * Releases the PCI I/O and memory resources previously reserved by a | |
2480 | * successful call to pci_request_region. Call this function only | |
2481 | * after all use of the PCI regions has ceased. | |
2482 | */ | |
2483 | void pci_release_region(struct pci_dev *pdev, int bar) | |
2484 | { | |
9ac7849e TH |
2485 | struct pci_devres *dr; |
2486 | ||
1da177e4 LT |
2487 | if (pci_resource_len(pdev, bar) == 0) |
2488 | return; | |
2489 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) | |
2490 | release_region(pci_resource_start(pdev, bar), | |
2491 | pci_resource_len(pdev, bar)); | |
2492 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) | |
2493 | release_mem_region(pci_resource_start(pdev, bar), | |
2494 | pci_resource_len(pdev, bar)); | |
9ac7849e TH |
2495 | |
2496 | dr = find_pci_dr(pdev); | |
2497 | if (dr) | |
2498 | dr->region_mask &= ~(1 << bar); | |
1da177e4 | 2499 | } |
b7fe9434 | 2500 | EXPORT_SYMBOL(pci_release_region); |
1da177e4 LT |
2501 | |
2502 | /** | |
f5ddcac4 | 2503 | * __pci_request_region - Reserved PCI I/O and memory resource |
1da177e4 LT |
2504 | * @pdev: PCI device whose resources are to be reserved |
2505 | * @bar: BAR to be reserved | |
2506 | * @res_name: Name to be associated with resource. | |
f5ddcac4 | 2507 | * @exclusive: whether the region access is exclusive or not |
1da177e4 LT |
2508 | * |
2509 | * Mark the PCI region associated with PCI device @pdev BR @bar as | |
2510 | * being reserved by owner @res_name. Do not access any | |
2511 | * address inside the PCI regions unless this call returns | |
2512 | * successfully. | |
2513 | * | |
f5ddcac4 RD |
2514 | * If @exclusive is set, then the region is marked so that userspace |
2515 | * is explicitly not allowed to map the resource via /dev/mem or | |
f7625980 | 2516 | * sysfs MMIO access. |
f5ddcac4 | 2517 | * |
1da177e4 LT |
2518 | * Returns 0 on success, or %EBUSY on error. A warning |
2519 | * message is also printed on failure. | |
2520 | */ | |
e8de1481 AV |
2521 | static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name, |
2522 | int exclusive) | |
1da177e4 | 2523 | { |
9ac7849e TH |
2524 | struct pci_devres *dr; |
2525 | ||
1da177e4 LT |
2526 | if (pci_resource_len(pdev, bar) == 0) |
2527 | return 0; | |
f7625980 | 2528 | |
1da177e4 LT |
2529 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { |
2530 | if (!request_region(pci_resource_start(pdev, bar), | |
2531 | pci_resource_len(pdev, bar), res_name)) | |
2532 | goto err_out; | |
2533 | } | |
2534 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { | |
e8de1481 AV |
2535 | if (!__request_mem_region(pci_resource_start(pdev, bar), |
2536 | pci_resource_len(pdev, bar), res_name, | |
2537 | exclusive)) | |
1da177e4 LT |
2538 | goto err_out; |
2539 | } | |
9ac7849e TH |
2540 | |
2541 | dr = find_pci_dr(pdev); | |
2542 | if (dr) | |
2543 | dr->region_mask |= 1 << bar; | |
2544 | ||
1da177e4 LT |
2545 | return 0; |
2546 | ||
2547 | err_out: | |
c7dabef8 | 2548 | dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar, |
096e6f67 | 2549 | &pdev->resource[bar]); |
1da177e4 LT |
2550 | return -EBUSY; |
2551 | } | |
2552 | ||
e8de1481 | 2553 | /** |
f5ddcac4 | 2554 | * pci_request_region - Reserve PCI I/O and memory resource |
e8de1481 AV |
2555 | * @pdev: PCI device whose resources are to be reserved |
2556 | * @bar: BAR to be reserved | |
f5ddcac4 | 2557 | * @res_name: Name to be associated with resource |
e8de1481 | 2558 | * |
f5ddcac4 | 2559 | * Mark the PCI region associated with PCI device @pdev BAR @bar as |
e8de1481 AV |
2560 | * being reserved by owner @res_name. Do not access any |
2561 | * address inside the PCI regions unless this call returns | |
2562 | * successfully. | |
2563 | * | |
2564 | * Returns 0 on success, or %EBUSY on error. A warning | |
2565 | * message is also printed on failure. | |
2566 | */ | |
2567 | int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) | |
2568 | { | |
2569 | return __pci_request_region(pdev, bar, res_name, 0); | |
2570 | } | |
b7fe9434 | 2571 | EXPORT_SYMBOL(pci_request_region); |
e8de1481 AV |
2572 | |
2573 | /** | |
2574 | * pci_request_region_exclusive - Reserved PCI I/O and memory resource | |
2575 | * @pdev: PCI device whose resources are to be reserved | |
2576 | * @bar: BAR to be reserved | |
2577 | * @res_name: Name to be associated with resource. | |
2578 | * | |
2579 | * Mark the PCI region associated with PCI device @pdev BR @bar as | |
2580 | * being reserved by owner @res_name. Do not access any | |
2581 | * address inside the PCI regions unless this call returns | |
2582 | * successfully. | |
2583 | * | |
2584 | * Returns 0 on success, or %EBUSY on error. A warning | |
2585 | * message is also printed on failure. | |
2586 | * | |
2587 | * The key difference that _exclusive makes it that userspace is | |
2588 | * explicitly not allowed to map the resource via /dev/mem or | |
f7625980 | 2589 | * sysfs. |
e8de1481 AV |
2590 | */ |
2591 | int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name) | |
2592 | { | |
2593 | return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE); | |
2594 | } | |
b7fe9434 RD |
2595 | EXPORT_SYMBOL(pci_request_region_exclusive); |
2596 | ||
c87deff7 HS |
2597 | /** |
2598 | * pci_release_selected_regions - Release selected PCI I/O and memory resources | |
2599 | * @pdev: PCI device whose resources were previously reserved | |
2600 | * @bars: Bitmask of BARs to be released | |
2601 | * | |
2602 | * Release selected PCI I/O and memory resources previously reserved. | |
2603 | * Call this function only after all use of the PCI regions has ceased. | |
2604 | */ | |
2605 | void pci_release_selected_regions(struct pci_dev *pdev, int bars) | |
2606 | { | |
2607 | int i; | |
2608 | ||
2609 | for (i = 0; i < 6; i++) | |
2610 | if (bars & (1 << i)) | |
2611 | pci_release_region(pdev, i); | |
2612 | } | |
b7fe9434 | 2613 | EXPORT_SYMBOL(pci_release_selected_regions); |
c87deff7 | 2614 | |
9738abed | 2615 | static int __pci_request_selected_regions(struct pci_dev *pdev, int bars, |
e8de1481 | 2616 | const char *res_name, int excl) |
c87deff7 HS |
2617 | { |
2618 | int i; | |
2619 | ||
2620 | for (i = 0; i < 6; i++) | |
2621 | if (bars & (1 << i)) | |
e8de1481 | 2622 | if (__pci_request_region(pdev, i, res_name, excl)) |
c87deff7 HS |
2623 | goto err_out; |
2624 | return 0; | |
2625 | ||
2626 | err_out: | |
2627 | while(--i >= 0) | |
2628 | if (bars & (1 << i)) | |
2629 | pci_release_region(pdev, i); | |
2630 | ||
2631 | return -EBUSY; | |
2632 | } | |
1da177e4 | 2633 | |
e8de1481 AV |
2634 | |
2635 | /** | |
2636 | * pci_request_selected_regions - Reserve selected PCI I/O and memory resources | |
2637 | * @pdev: PCI device whose resources are to be reserved | |
2638 | * @bars: Bitmask of BARs to be requested | |
2639 | * @res_name: Name to be associated with resource | |
2640 | */ | |
2641 | int pci_request_selected_regions(struct pci_dev *pdev, int bars, | |
2642 | const char *res_name) | |
2643 | { | |
2644 | return __pci_request_selected_regions(pdev, bars, res_name, 0); | |
2645 | } | |
b7fe9434 | 2646 | EXPORT_SYMBOL(pci_request_selected_regions); |
e8de1481 AV |
2647 | |
2648 | int pci_request_selected_regions_exclusive(struct pci_dev *pdev, | |
2649 | int bars, const char *res_name) | |
2650 | { | |
2651 | return __pci_request_selected_regions(pdev, bars, res_name, | |
2652 | IORESOURCE_EXCLUSIVE); | |
2653 | } | |
b7fe9434 | 2654 | EXPORT_SYMBOL(pci_request_selected_regions_exclusive); |
e8de1481 | 2655 | |
1da177e4 LT |
2656 | /** |
2657 | * pci_release_regions - Release reserved PCI I/O and memory resources | |
2658 | * @pdev: PCI device whose resources were previously reserved by pci_request_regions | |
2659 | * | |
2660 | * Releases all PCI I/O and memory resources previously reserved by a | |
2661 | * successful call to pci_request_regions. Call this function only | |
2662 | * after all use of the PCI regions has ceased. | |
2663 | */ | |
2664 | ||
2665 | void pci_release_regions(struct pci_dev *pdev) | |
2666 | { | |
c87deff7 | 2667 | pci_release_selected_regions(pdev, (1 << 6) - 1); |
1da177e4 | 2668 | } |
b7fe9434 | 2669 | EXPORT_SYMBOL(pci_release_regions); |
1da177e4 LT |
2670 | |
2671 | /** | |
2672 | * pci_request_regions - Reserved PCI I/O and memory resources | |
2673 | * @pdev: PCI device whose resources are to be reserved | |
2674 | * @res_name: Name to be associated with resource. | |
2675 | * | |
2676 | * Mark all PCI regions associated with PCI device @pdev as | |
2677 | * being reserved by owner @res_name. Do not access any | |
2678 | * address inside the PCI regions unless this call returns | |
2679 | * successfully. | |
2680 | * | |
2681 | * Returns 0 on success, or %EBUSY on error. A warning | |
2682 | * message is also printed on failure. | |
2683 | */ | |
3c990e92 | 2684 | int pci_request_regions(struct pci_dev *pdev, const char *res_name) |
1da177e4 | 2685 | { |
c87deff7 | 2686 | return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name); |
1da177e4 | 2687 | } |
b7fe9434 | 2688 | EXPORT_SYMBOL(pci_request_regions); |
1da177e4 | 2689 | |
e8de1481 AV |
2690 | /** |
2691 | * pci_request_regions_exclusive - Reserved PCI I/O and memory resources | |
2692 | * @pdev: PCI device whose resources are to be reserved | |
2693 | * @res_name: Name to be associated with resource. | |
2694 | * | |
2695 | * Mark all PCI regions associated with PCI device @pdev as | |
2696 | * being reserved by owner @res_name. Do not access any | |
2697 | * address inside the PCI regions unless this call returns | |
2698 | * successfully. | |
2699 | * | |
2700 | * pci_request_regions_exclusive() will mark the region so that | |
f7625980 | 2701 | * /dev/mem and the sysfs MMIO access will not be allowed. |
e8de1481 AV |
2702 | * |
2703 | * Returns 0 on success, or %EBUSY on error. A warning | |
2704 | * message is also printed on failure. | |
2705 | */ | |
2706 | int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name) | |
2707 | { | |
2708 | return pci_request_selected_regions_exclusive(pdev, | |
2709 | ((1 << 6) - 1), res_name); | |
2710 | } | |
b7fe9434 | 2711 | EXPORT_SYMBOL(pci_request_regions_exclusive); |
e8de1481 | 2712 | |
6a479079 BH |
2713 | static void __pci_set_master(struct pci_dev *dev, bool enable) |
2714 | { | |
2715 | u16 old_cmd, cmd; | |
2716 | ||
2717 | pci_read_config_word(dev, PCI_COMMAND, &old_cmd); | |
2718 | if (enable) | |
2719 | cmd = old_cmd | PCI_COMMAND_MASTER; | |
2720 | else | |
2721 | cmd = old_cmd & ~PCI_COMMAND_MASTER; | |
2722 | if (cmd != old_cmd) { | |
2723 | dev_dbg(&dev->dev, "%s bus mastering\n", | |
2724 | enable ? "enabling" : "disabling"); | |
2725 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
2726 | } | |
2727 | dev->is_busmaster = enable; | |
2728 | } | |
e8de1481 | 2729 | |
2b6f2c35 MS |
2730 | /** |
2731 | * pcibios_setup - process "pci=" kernel boot arguments | |
2732 | * @str: string used to pass in "pci=" kernel boot arguments | |
2733 | * | |
2734 | * Process kernel boot arguments. This is the default implementation. | |
2735 | * Architecture specific implementations can override this as necessary. | |
2736 | */ | |
2737 | char * __weak __init pcibios_setup(char *str) | |
2738 | { | |
2739 | return str; | |
2740 | } | |
2741 | ||
96c55900 MS |
2742 | /** |
2743 | * pcibios_set_master - enable PCI bus-mastering for device dev | |
2744 | * @dev: the PCI device to enable | |
2745 | * | |
2746 | * Enables PCI bus-mastering for the device. This is the default | |
2747 | * implementation. Architecture specific implementations can override | |
2748 | * this if necessary. | |
2749 | */ | |
2750 | void __weak pcibios_set_master(struct pci_dev *dev) | |
2751 | { | |
2752 | u8 lat; | |
2753 | ||
f676678f MS |
2754 | /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */ |
2755 | if (pci_is_pcie(dev)) | |
2756 | return; | |
2757 | ||
96c55900 MS |
2758 | pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); |
2759 | if (lat < 16) | |
2760 | lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; | |
2761 | else if (lat > pcibios_max_latency) | |
2762 | lat = pcibios_max_latency; | |
2763 | else | |
2764 | return; | |
a006482b | 2765 | |
96c55900 MS |
2766 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); |
2767 | } | |
2768 | ||
1da177e4 LT |
2769 | /** |
2770 | * pci_set_master - enables bus-mastering for device dev | |
2771 | * @dev: the PCI device to enable | |
2772 | * | |
2773 | * Enables bus-mastering on the device and calls pcibios_set_master() | |
2774 | * to do the needed arch specific settings. | |
2775 | */ | |
6a479079 | 2776 | void pci_set_master(struct pci_dev *dev) |
1da177e4 | 2777 | { |
6a479079 | 2778 | __pci_set_master(dev, true); |
1da177e4 LT |
2779 | pcibios_set_master(dev); |
2780 | } | |
b7fe9434 | 2781 | EXPORT_SYMBOL(pci_set_master); |
1da177e4 | 2782 | |
6a479079 BH |
2783 | /** |
2784 | * pci_clear_master - disables bus-mastering for device dev | |
2785 | * @dev: the PCI device to disable | |
2786 | */ | |
2787 | void pci_clear_master(struct pci_dev *dev) | |
2788 | { | |
2789 | __pci_set_master(dev, false); | |
2790 | } | |
b7fe9434 | 2791 | EXPORT_SYMBOL(pci_clear_master); |
6a479079 | 2792 | |
1da177e4 | 2793 | /** |
edb2d97e MW |
2794 | * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed |
2795 | * @dev: the PCI device for which MWI is to be enabled | |
1da177e4 | 2796 | * |
edb2d97e MW |
2797 | * Helper function for pci_set_mwi. |
2798 | * Originally copied from drivers/net/acenic.c. | |
1da177e4 LT |
2799 | * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. |
2800 | * | |
2801 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
2802 | */ | |
15ea76d4 | 2803 | int pci_set_cacheline_size(struct pci_dev *dev) |
1da177e4 LT |
2804 | { |
2805 | u8 cacheline_size; | |
2806 | ||
2807 | if (!pci_cache_line_size) | |
15ea76d4 | 2808 | return -EINVAL; |
1da177e4 LT |
2809 | |
2810 | /* Validate current setting: the PCI_CACHE_LINE_SIZE must be | |
2811 | equal to or multiple of the right value. */ | |
2812 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
2813 | if (cacheline_size >= pci_cache_line_size && | |
2814 | (cacheline_size % pci_cache_line_size) == 0) | |
2815 | return 0; | |
2816 | ||
2817 | /* Write the correct value. */ | |
2818 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); | |
2819 | /* Read it back. */ | |
2820 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
2821 | if (cacheline_size == pci_cache_line_size) | |
2822 | return 0; | |
2823 | ||
80ccba11 BH |
2824 | dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not " |
2825 | "supported\n", pci_cache_line_size << 2); | |
1da177e4 LT |
2826 | |
2827 | return -EINVAL; | |
2828 | } | |
15ea76d4 TH |
2829 | EXPORT_SYMBOL_GPL(pci_set_cacheline_size); |
2830 | ||
1da177e4 LT |
2831 | /** |
2832 | * pci_set_mwi - enables memory-write-invalidate PCI transaction | |
2833 | * @dev: the PCI device for which MWI is enabled | |
2834 | * | |
694625c0 | 2835 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. |
1da177e4 LT |
2836 | * |
2837 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
2838 | */ | |
2839 | int | |
2840 | pci_set_mwi(struct pci_dev *dev) | |
2841 | { | |
b7fe9434 RD |
2842 | #ifdef PCI_DISABLE_MWI |
2843 | return 0; | |
2844 | #else | |
1da177e4 LT |
2845 | int rc; |
2846 | u16 cmd; | |
2847 | ||
edb2d97e | 2848 | rc = pci_set_cacheline_size(dev); |
1da177e4 LT |
2849 | if (rc) |
2850 | return rc; | |
2851 | ||
2852 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
2853 | if (! (cmd & PCI_COMMAND_INVALIDATE)) { | |
80ccba11 | 2854 | dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n"); |
1da177e4 LT |
2855 | cmd |= PCI_COMMAND_INVALIDATE; |
2856 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
2857 | } | |
1da177e4 | 2858 | return 0; |
b7fe9434 | 2859 | #endif |
1da177e4 | 2860 | } |
b7fe9434 | 2861 | EXPORT_SYMBOL(pci_set_mwi); |
1da177e4 | 2862 | |
694625c0 RD |
2863 | /** |
2864 | * pci_try_set_mwi - enables memory-write-invalidate PCI transaction | |
2865 | * @dev: the PCI device for which MWI is enabled | |
2866 | * | |
2867 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. | |
2868 | * Callers are not required to check the return value. | |
2869 | * | |
2870 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
2871 | */ | |
2872 | int pci_try_set_mwi(struct pci_dev *dev) | |
2873 | { | |
b7fe9434 RD |
2874 | #ifdef PCI_DISABLE_MWI |
2875 | return 0; | |
2876 | #else | |
2877 | return pci_set_mwi(dev); | |
2878 | #endif | |
694625c0 | 2879 | } |
b7fe9434 | 2880 | EXPORT_SYMBOL(pci_try_set_mwi); |
694625c0 | 2881 | |
1da177e4 LT |
2882 | /** |
2883 | * pci_clear_mwi - disables Memory-Write-Invalidate for device dev | |
2884 | * @dev: the PCI device to disable | |
2885 | * | |
2886 | * Disables PCI Memory-Write-Invalidate transaction on the device | |
2887 | */ | |
2888 | void | |
2889 | pci_clear_mwi(struct pci_dev *dev) | |
2890 | { | |
b7fe9434 | 2891 | #ifndef PCI_DISABLE_MWI |
1da177e4 LT |
2892 | u16 cmd; |
2893 | ||
2894 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
2895 | if (cmd & PCI_COMMAND_INVALIDATE) { | |
2896 | cmd &= ~PCI_COMMAND_INVALIDATE; | |
2897 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
2898 | } | |
b7fe9434 | 2899 | #endif |
1da177e4 | 2900 | } |
b7fe9434 | 2901 | EXPORT_SYMBOL(pci_clear_mwi); |
1da177e4 | 2902 | |
a04ce0ff BR |
2903 | /** |
2904 | * pci_intx - enables/disables PCI INTx for device dev | |
8f7020d3 RD |
2905 | * @pdev: the PCI device to operate on |
2906 | * @enable: boolean: whether to enable or disable PCI INTx | |
a04ce0ff BR |
2907 | * |
2908 | * Enables/disables PCI INTx for device dev | |
2909 | */ | |
2910 | void | |
2911 | pci_intx(struct pci_dev *pdev, int enable) | |
2912 | { | |
2913 | u16 pci_command, new; | |
2914 | ||
2915 | pci_read_config_word(pdev, PCI_COMMAND, &pci_command); | |
2916 | ||
2917 | if (enable) { | |
2918 | new = pci_command & ~PCI_COMMAND_INTX_DISABLE; | |
2919 | } else { | |
2920 | new = pci_command | PCI_COMMAND_INTX_DISABLE; | |
2921 | } | |
2922 | ||
2923 | if (new != pci_command) { | |
9ac7849e TH |
2924 | struct pci_devres *dr; |
2925 | ||
2fd9d74b | 2926 | pci_write_config_word(pdev, PCI_COMMAND, new); |
9ac7849e TH |
2927 | |
2928 | dr = find_pci_dr(pdev); | |
2929 | if (dr && !dr->restore_intx) { | |
2930 | dr->restore_intx = 1; | |
2931 | dr->orig_intx = !enable; | |
2932 | } | |
a04ce0ff BR |
2933 | } |
2934 | } | |
b7fe9434 | 2935 | EXPORT_SYMBOL_GPL(pci_intx); |
a04ce0ff | 2936 | |
a2e27787 JK |
2937 | /** |
2938 | * pci_intx_mask_supported - probe for INTx masking support | |
6e9292c5 | 2939 | * @dev: the PCI device to operate on |
a2e27787 JK |
2940 | * |
2941 | * Check if the device dev support INTx masking via the config space | |
2942 | * command word. | |
2943 | */ | |
2944 | bool pci_intx_mask_supported(struct pci_dev *dev) | |
2945 | { | |
2946 | bool mask_supported = false; | |
2947 | u16 orig, new; | |
2948 | ||
fbebb9fd BH |
2949 | if (dev->broken_intx_masking) |
2950 | return false; | |
2951 | ||
a2e27787 JK |
2952 | pci_cfg_access_lock(dev); |
2953 | ||
2954 | pci_read_config_word(dev, PCI_COMMAND, &orig); | |
2955 | pci_write_config_word(dev, PCI_COMMAND, | |
2956 | orig ^ PCI_COMMAND_INTX_DISABLE); | |
2957 | pci_read_config_word(dev, PCI_COMMAND, &new); | |
2958 | ||
2959 | /* | |
2960 | * There's no way to protect against hardware bugs or detect them | |
2961 | * reliably, but as long as we know what the value should be, let's | |
2962 | * go ahead and check it. | |
2963 | */ | |
2964 | if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) { | |
2965 | dev_err(&dev->dev, "Command register changed from " | |
2966 | "0x%x to 0x%x: driver or hardware bug?\n", orig, new); | |
2967 | } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) { | |
2968 | mask_supported = true; | |
2969 | pci_write_config_word(dev, PCI_COMMAND, orig); | |
2970 | } | |
2971 | ||
2972 | pci_cfg_access_unlock(dev); | |
2973 | return mask_supported; | |
2974 | } | |
2975 | EXPORT_SYMBOL_GPL(pci_intx_mask_supported); | |
2976 | ||
2977 | static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask) | |
2978 | { | |
2979 | struct pci_bus *bus = dev->bus; | |
2980 | bool mask_updated = true; | |
2981 | u32 cmd_status_dword; | |
2982 | u16 origcmd, newcmd; | |
2983 | unsigned long flags; | |
2984 | bool irq_pending; | |
2985 | ||
2986 | /* | |
2987 | * We do a single dword read to retrieve both command and status. | |
2988 | * Document assumptions that make this possible. | |
2989 | */ | |
2990 | BUILD_BUG_ON(PCI_COMMAND % 4); | |
2991 | BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS); | |
2992 | ||
2993 | raw_spin_lock_irqsave(&pci_lock, flags); | |
2994 | ||
2995 | bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword); | |
2996 | ||
2997 | irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT; | |
2998 | ||
2999 | /* | |
3000 | * Check interrupt status register to see whether our device | |
3001 | * triggered the interrupt (when masking) or the next IRQ is | |
3002 | * already pending (when unmasking). | |
3003 | */ | |
3004 | if (mask != irq_pending) { | |
3005 | mask_updated = false; | |
3006 | goto done; | |
3007 | } | |
3008 | ||
3009 | origcmd = cmd_status_dword; | |
3010 | newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE; | |
3011 | if (mask) | |
3012 | newcmd |= PCI_COMMAND_INTX_DISABLE; | |
3013 | if (newcmd != origcmd) | |
3014 | bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd); | |
3015 | ||
3016 | done: | |
3017 | raw_spin_unlock_irqrestore(&pci_lock, flags); | |
3018 | ||
3019 | return mask_updated; | |
3020 | } | |
3021 | ||
3022 | /** | |
3023 | * pci_check_and_mask_intx - mask INTx on pending interrupt | |
6e9292c5 | 3024 | * @dev: the PCI device to operate on |
a2e27787 JK |
3025 | * |
3026 | * Check if the device dev has its INTx line asserted, mask it and | |
3027 | * return true in that case. False is returned if not interrupt was | |
3028 | * pending. | |
3029 | */ | |
3030 | bool pci_check_and_mask_intx(struct pci_dev *dev) | |
3031 | { | |
3032 | return pci_check_and_set_intx_mask(dev, true); | |
3033 | } | |
3034 | EXPORT_SYMBOL_GPL(pci_check_and_mask_intx); | |
3035 | ||
3036 | /** | |
ebd50b93 | 3037 | * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending |
6e9292c5 | 3038 | * @dev: the PCI device to operate on |
a2e27787 JK |
3039 | * |
3040 | * Check if the device dev has its INTx line asserted, unmask it if not | |
3041 | * and return true. False is returned and the mask remains active if | |
3042 | * there was still an interrupt pending. | |
3043 | */ | |
3044 | bool pci_check_and_unmask_intx(struct pci_dev *dev) | |
3045 | { | |
3046 | return pci_check_and_set_intx_mask(dev, false); | |
3047 | } | |
3048 | EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx); | |
3049 | ||
f5f2b131 | 3050 | /** |
da27f4b3 | 3051 | * pci_msi_off - disables any MSI or MSI-X capabilities |
8d7d86e9 | 3052 | * @dev: the PCI device to operate on |
f5f2b131 | 3053 | * |
da27f4b3 BH |
3054 | * If you want to use MSI, see pci_enable_msi() and friends. |
3055 | * This is a lower-level primitive that allows us to disable | |
3056 | * MSI operation at the device level. | |
f5f2b131 EB |
3057 | */ |
3058 | void pci_msi_off(struct pci_dev *dev) | |
3059 | { | |
3060 | int pos; | |
3061 | u16 control; | |
3062 | ||
da27f4b3 BH |
3063 | /* |
3064 | * This looks like it could go in msi.c, but we need it even when | |
3065 | * CONFIG_PCI_MSI=n. For the same reason, we can't use | |
3066 | * dev->msi_cap or dev->msix_cap here. | |
3067 | */ | |
f5f2b131 EB |
3068 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); |
3069 | if (pos) { | |
3070 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
3071 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
3072 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
3073 | } | |
3074 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
3075 | if (pos) { | |
3076 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
3077 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
3078 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
3079 | } | |
3080 | } | |
b03214d5 | 3081 | EXPORT_SYMBOL_GPL(pci_msi_off); |
f5f2b131 | 3082 | |
4d57cdfa FT |
3083 | int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size) |
3084 | { | |
3085 | return dma_set_max_seg_size(&dev->dev, size); | |
3086 | } | |
3087 | EXPORT_SYMBOL(pci_set_dma_max_seg_size); | |
4d57cdfa | 3088 | |
59fc67de FT |
3089 | int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask) |
3090 | { | |
3091 | return dma_set_seg_boundary(&dev->dev, mask); | |
3092 | } | |
3093 | EXPORT_SYMBOL(pci_set_dma_seg_boundary); | |
59fc67de | 3094 | |
3775a209 CL |
3095 | /** |
3096 | * pci_wait_for_pending_transaction - waits for pending transaction | |
3097 | * @dev: the PCI device to operate on | |
3098 | * | |
3099 | * Return 0 if transaction is pending 1 otherwise. | |
3100 | */ | |
3101 | int pci_wait_for_pending_transaction(struct pci_dev *dev) | |
8dd7f803 | 3102 | { |
157e876f AW |
3103 | if (!pci_is_pcie(dev)) |
3104 | return 1; | |
8c1c699f | 3105 | |
157e876f | 3106 | return pci_wait_for_pending(dev, PCI_EXP_DEVSTA, PCI_EXP_DEVSTA_TRPND); |
3775a209 CL |
3107 | } |
3108 | EXPORT_SYMBOL(pci_wait_for_pending_transaction); | |
3109 | ||
3110 | static int pcie_flr(struct pci_dev *dev, int probe) | |
3111 | { | |
3112 | u32 cap; | |
3113 | ||
3114 | pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); | |
3115 | if (!(cap & PCI_EXP_DEVCAP_FLR)) | |
3116 | return -ENOTTY; | |
3117 | ||
3118 | if (probe) | |
3119 | return 0; | |
3120 | ||
3121 | if (!pci_wait_for_pending_transaction(dev)) | |
3122 | dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n"); | |
8c1c699f | 3123 | |
59875ae4 | 3124 | pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); |
04b55c47 | 3125 | |
8c1c699f | 3126 | msleep(100); |
8dd7f803 | 3127 | |
8dd7f803 SY |
3128 | return 0; |
3129 | } | |
d91cdc74 | 3130 | |
8c1c699f | 3131 | static int pci_af_flr(struct pci_dev *dev, int probe) |
1ca88797 | 3132 | { |
8c1c699f | 3133 | int pos; |
1ca88797 SY |
3134 | u8 cap; |
3135 | ||
8c1c699f YZ |
3136 | pos = pci_find_capability(dev, PCI_CAP_ID_AF); |
3137 | if (!pos) | |
1ca88797 | 3138 | return -ENOTTY; |
8c1c699f YZ |
3139 | |
3140 | pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap); | |
1ca88797 SY |
3141 | if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) |
3142 | return -ENOTTY; | |
3143 | ||
3144 | if (probe) | |
3145 | return 0; | |
3146 | ||
1ca88797 | 3147 | /* Wait for Transaction Pending bit clean */ |
157e876f AW |
3148 | if (pci_wait_for_pending(dev, PCI_AF_STATUS, PCI_AF_STATUS_TP)) |
3149 | goto clear; | |
5fe5db05 | 3150 | |
8c1c699f YZ |
3151 | dev_err(&dev->dev, "transaction is not cleared; " |
3152 | "proceeding with reset anyway\n"); | |
5fe5db05 | 3153 | |
8c1c699f YZ |
3154 | clear: |
3155 | pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR); | |
1ca88797 | 3156 | msleep(100); |
8c1c699f | 3157 | |
1ca88797 SY |
3158 | return 0; |
3159 | } | |
3160 | ||
83d74e03 RW |
3161 | /** |
3162 | * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0. | |
3163 | * @dev: Device to reset. | |
3164 | * @probe: If set, only check if the device can be reset this way. | |
3165 | * | |
3166 | * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is | |
3167 | * unset, it will be reinitialized internally when going from PCI_D3hot to | |
3168 | * PCI_D0. If that's the case and the device is not in a low-power state | |
3169 | * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset. | |
3170 | * | |
3171 | * NOTE: This causes the caller to sleep for twice the device power transition | |
3172 | * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms | |
f7625980 | 3173 | * by default (i.e. unless the @dev's d3_delay field has a different value). |
83d74e03 RW |
3174 | * Moreover, only devices in D0 can be reset by this function. |
3175 | */ | |
f85876ba | 3176 | static int pci_pm_reset(struct pci_dev *dev, int probe) |
d91cdc74 | 3177 | { |
f85876ba YZ |
3178 | u16 csr; |
3179 | ||
3180 | if (!dev->pm_cap) | |
3181 | return -ENOTTY; | |
d91cdc74 | 3182 | |
f85876ba YZ |
3183 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr); |
3184 | if (csr & PCI_PM_CTRL_NO_SOFT_RESET) | |
3185 | return -ENOTTY; | |
d91cdc74 | 3186 | |
f85876ba YZ |
3187 | if (probe) |
3188 | return 0; | |
1ca88797 | 3189 | |
f85876ba YZ |
3190 | if (dev->current_state != PCI_D0) |
3191 | return -EINVAL; | |
3192 | ||
3193 | csr &= ~PCI_PM_CTRL_STATE_MASK; | |
3194 | csr |= PCI_D3hot; | |
3195 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); | |
1ae861e6 | 3196 | pci_dev_d3_sleep(dev); |
f85876ba YZ |
3197 | |
3198 | csr &= ~PCI_PM_CTRL_STATE_MASK; | |
3199 | csr |= PCI_D0; | |
3200 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); | |
1ae861e6 | 3201 | pci_dev_d3_sleep(dev); |
f85876ba YZ |
3202 | |
3203 | return 0; | |
3204 | } | |
3205 | ||
64e8674f AW |
3206 | /** |
3207 | * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge. | |
3208 | * @dev: Bridge device | |
3209 | * | |
3210 | * Use the bridge control register to assert reset on the secondary bus. | |
3211 | * Devices on the secondary bus are left in power-on state. | |
3212 | */ | |
3213 | void pci_reset_bridge_secondary_bus(struct pci_dev *dev) | |
c12ff1df YZ |
3214 | { |
3215 | u16 ctrl; | |
64e8674f AW |
3216 | |
3217 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl); | |
3218 | ctrl |= PCI_BRIDGE_CTL_BUS_RESET; | |
3219 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); | |
de0c548c AW |
3220 | /* |
3221 | * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double | |
f7625980 | 3222 | * this to 2ms to ensure that we meet the minimum requirement. |
de0c548c AW |
3223 | */ |
3224 | msleep(2); | |
64e8674f AW |
3225 | |
3226 | ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; | |
3227 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl); | |
de0c548c AW |
3228 | |
3229 | /* | |
3230 | * Trhfa for conventional PCI is 2^25 clock cycles. | |
3231 | * Assuming a minimum 33MHz clock this results in a 1s | |
3232 | * delay before we can consider subordinate devices to | |
3233 | * be re-initialized. PCIe has some ways to shorten this, | |
3234 | * but we don't make use of them yet. | |
3235 | */ | |
3236 | ssleep(1); | |
64e8674f AW |
3237 | } |
3238 | EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus); | |
3239 | ||
3240 | static int pci_parent_bus_reset(struct pci_dev *dev, int probe) | |
3241 | { | |
c12ff1df YZ |
3242 | struct pci_dev *pdev; |
3243 | ||
654b75e0 | 3244 | if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self) |
c12ff1df YZ |
3245 | return -ENOTTY; |
3246 | ||
3247 | list_for_each_entry(pdev, &dev->bus->devices, bus_list) | |
3248 | if (pdev != dev) | |
3249 | return -ENOTTY; | |
3250 | ||
3251 | if (probe) | |
3252 | return 0; | |
3253 | ||
64e8674f | 3254 | pci_reset_bridge_secondary_bus(dev->bus->self); |
c12ff1df YZ |
3255 | |
3256 | return 0; | |
3257 | } | |
3258 | ||
608c3881 AW |
3259 | static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe) |
3260 | { | |
3261 | int rc = -ENOTTY; | |
3262 | ||
3263 | if (!hotplug || !try_module_get(hotplug->ops->owner)) | |
3264 | return rc; | |
3265 | ||
3266 | if (hotplug->ops->reset_slot) | |
3267 | rc = hotplug->ops->reset_slot(hotplug, probe); | |
3268 | ||
3269 | module_put(hotplug->ops->owner); | |
3270 | ||
3271 | return rc; | |
3272 | } | |
3273 | ||
3274 | static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe) | |
3275 | { | |
3276 | struct pci_dev *pdev; | |
3277 | ||
3278 | if (dev->subordinate || !dev->slot) | |
3279 | return -ENOTTY; | |
3280 | ||
3281 | list_for_each_entry(pdev, &dev->bus->devices, bus_list) | |
3282 | if (pdev != dev && pdev->slot == dev->slot) | |
3283 | return -ENOTTY; | |
3284 | ||
3285 | return pci_reset_hotplug_slot(dev->slot->hotplug, probe); | |
3286 | } | |
3287 | ||
977f857c | 3288 | static int __pci_dev_reset(struct pci_dev *dev, int probe) |
d91cdc74 | 3289 | { |
8c1c699f YZ |
3290 | int rc; |
3291 | ||
3292 | might_sleep(); | |
3293 | ||
b9c3b266 DC |
3294 | rc = pci_dev_specific_reset(dev, probe); |
3295 | if (rc != -ENOTTY) | |
3296 | goto done; | |
3297 | ||
8c1c699f YZ |
3298 | rc = pcie_flr(dev, probe); |
3299 | if (rc != -ENOTTY) | |
3300 | goto done; | |
d91cdc74 | 3301 | |
8c1c699f | 3302 | rc = pci_af_flr(dev, probe); |
f85876ba YZ |
3303 | if (rc != -ENOTTY) |
3304 | goto done; | |
3305 | ||
3306 | rc = pci_pm_reset(dev, probe); | |
c12ff1df YZ |
3307 | if (rc != -ENOTTY) |
3308 | goto done; | |
3309 | ||
608c3881 AW |
3310 | rc = pci_dev_reset_slot_function(dev, probe); |
3311 | if (rc != -ENOTTY) | |
3312 | goto done; | |
3313 | ||
c12ff1df | 3314 | rc = pci_parent_bus_reset(dev, probe); |
8c1c699f | 3315 | done: |
977f857c KRW |
3316 | return rc; |
3317 | } | |
3318 | ||
77cb985a AW |
3319 | static void pci_dev_lock(struct pci_dev *dev) |
3320 | { | |
3321 | pci_cfg_access_lock(dev); | |
3322 | /* block PM suspend, driver probe, etc. */ | |
3323 | device_lock(&dev->dev); | |
3324 | } | |
3325 | ||
61cf16d8 AW |
3326 | /* Return 1 on successful lock, 0 on contention */ |
3327 | static int pci_dev_trylock(struct pci_dev *dev) | |
3328 | { | |
3329 | if (pci_cfg_access_trylock(dev)) { | |
3330 | if (device_trylock(&dev->dev)) | |
3331 | return 1; | |
3332 | pci_cfg_access_unlock(dev); | |
3333 | } | |
3334 | ||
3335 | return 0; | |
3336 | } | |
3337 | ||
77cb985a AW |
3338 | static void pci_dev_unlock(struct pci_dev *dev) |
3339 | { | |
3340 | device_unlock(&dev->dev); | |
3341 | pci_cfg_access_unlock(dev); | |
3342 | } | |
3343 | ||
3ebe7f9f KB |
3344 | /** |
3345 | * pci_reset_notify - notify device driver of reset | |
3346 | * @dev: device to be notified of reset | |
3347 | * @prepare: 'true' if device is about to be reset; 'false' if reset attempt | |
3348 | * completed | |
3349 | * | |
3350 | * Must be called prior to device access being disabled and after device | |
3351 | * access is restored. | |
3352 | */ | |
3353 | static void pci_reset_notify(struct pci_dev *dev, bool prepare) | |
3354 | { | |
3355 | const struct pci_error_handlers *err_handler = | |
3356 | dev->driver ? dev->driver->err_handler : NULL; | |
3357 | if (err_handler && err_handler->reset_notify) | |
3358 | err_handler->reset_notify(dev, prepare); | |
3359 | } | |
3360 | ||
77cb985a AW |
3361 | static void pci_dev_save_and_disable(struct pci_dev *dev) |
3362 | { | |
3ebe7f9f KB |
3363 | pci_reset_notify(dev, true); |
3364 | ||
a6cbaade AW |
3365 | /* |
3366 | * Wake-up device prior to save. PM registers default to D0 after | |
3367 | * reset and a simple register restore doesn't reliably return | |
3368 | * to a non-D0 state anyway. | |
3369 | */ | |
3370 | pci_set_power_state(dev, PCI_D0); | |
3371 | ||
77cb985a AW |
3372 | pci_save_state(dev); |
3373 | /* | |
3374 | * Disable the device by clearing the Command register, except for | |
3375 | * INTx-disable which is set. This not only disables MMIO and I/O port | |
3376 | * BARs, but also prevents the device from being Bus Master, preventing | |
3377 | * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3 | |
3378 | * compliant devices, INTx-disable prevents legacy interrupts. | |
3379 | */ | |
3380 | pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE); | |
3381 | } | |
3382 | ||
3383 | static void pci_dev_restore(struct pci_dev *dev) | |
3384 | { | |
3385 | pci_restore_state(dev); | |
3ebe7f9f | 3386 | pci_reset_notify(dev, false); |
77cb985a AW |
3387 | } |
3388 | ||
977f857c KRW |
3389 | static int pci_dev_reset(struct pci_dev *dev, int probe) |
3390 | { | |
3391 | int rc; | |
3392 | ||
77cb985a AW |
3393 | if (!probe) |
3394 | pci_dev_lock(dev); | |
977f857c KRW |
3395 | |
3396 | rc = __pci_dev_reset(dev, probe); | |
3397 | ||
77cb985a AW |
3398 | if (!probe) |
3399 | pci_dev_unlock(dev); | |
3400 | ||
8c1c699f | 3401 | return rc; |
d91cdc74 | 3402 | } |
3ebe7f9f | 3403 | |
d91cdc74 | 3404 | /** |
8c1c699f YZ |
3405 | * __pci_reset_function - reset a PCI device function |
3406 | * @dev: PCI device to reset | |
d91cdc74 SY |
3407 | * |
3408 | * Some devices allow an individual function to be reset without affecting | |
3409 | * other functions in the same device. The PCI device must be responsive | |
3410 | * to PCI config space in order to use this function. | |
3411 | * | |
3412 | * The device function is presumed to be unused when this function is called. | |
3413 | * Resetting the device will make the contents of PCI configuration space | |
3414 | * random, so any caller of this must be prepared to reinitialise the | |
3415 | * device including MSI, bus mastering, BARs, decoding IO and memory spaces, | |
3416 | * etc. | |
3417 | * | |
8c1c699f | 3418 | * Returns 0 if the device function was successfully reset or negative if the |
d91cdc74 SY |
3419 | * device doesn't support resetting a single function. |
3420 | */ | |
8c1c699f | 3421 | int __pci_reset_function(struct pci_dev *dev) |
d91cdc74 | 3422 | { |
8c1c699f | 3423 | return pci_dev_reset(dev, 0); |
d91cdc74 | 3424 | } |
8c1c699f | 3425 | EXPORT_SYMBOL_GPL(__pci_reset_function); |
8dd7f803 | 3426 | |
6fbf9e7a KRW |
3427 | /** |
3428 | * __pci_reset_function_locked - reset a PCI device function while holding | |
3429 | * the @dev mutex lock. | |
3430 | * @dev: PCI device to reset | |
3431 | * | |
3432 | * Some devices allow an individual function to be reset without affecting | |
3433 | * other functions in the same device. The PCI device must be responsive | |
3434 | * to PCI config space in order to use this function. | |
3435 | * | |
3436 | * The device function is presumed to be unused and the caller is holding | |
3437 | * the device mutex lock when this function is called. | |
3438 | * Resetting the device will make the contents of PCI configuration space | |
3439 | * random, so any caller of this must be prepared to reinitialise the | |
3440 | * device including MSI, bus mastering, BARs, decoding IO and memory spaces, | |
3441 | * etc. | |
3442 | * | |
3443 | * Returns 0 if the device function was successfully reset or negative if the | |
3444 | * device doesn't support resetting a single function. | |
3445 | */ | |
3446 | int __pci_reset_function_locked(struct pci_dev *dev) | |
3447 | { | |
977f857c | 3448 | return __pci_dev_reset(dev, 0); |
6fbf9e7a KRW |
3449 | } |
3450 | EXPORT_SYMBOL_GPL(__pci_reset_function_locked); | |
3451 | ||
711d5779 MT |
3452 | /** |
3453 | * pci_probe_reset_function - check whether the device can be safely reset | |
3454 | * @dev: PCI device to reset | |
3455 | * | |
3456 | * Some devices allow an individual function to be reset without affecting | |
3457 | * other functions in the same device. The PCI device must be responsive | |
3458 | * to PCI config space in order to use this function. | |
3459 | * | |
3460 | * Returns 0 if the device function can be reset or negative if the | |
3461 | * device doesn't support resetting a single function. | |
3462 | */ | |
3463 | int pci_probe_reset_function(struct pci_dev *dev) | |
3464 | { | |
3465 | return pci_dev_reset(dev, 1); | |
3466 | } | |
3467 | ||
8dd7f803 | 3468 | /** |
8c1c699f YZ |
3469 | * pci_reset_function - quiesce and reset a PCI device function |
3470 | * @dev: PCI device to reset | |
8dd7f803 SY |
3471 | * |
3472 | * Some devices allow an individual function to be reset without affecting | |
3473 | * other functions in the same device. The PCI device must be responsive | |
3474 | * to PCI config space in order to use this function. | |
3475 | * | |
3476 | * This function does not just reset the PCI portion of a device, but | |
3477 | * clears all the state associated with the device. This function differs | |
8c1c699f | 3478 | * from __pci_reset_function in that it saves and restores device state |
8dd7f803 SY |
3479 | * over the reset. |
3480 | * | |
8c1c699f | 3481 | * Returns 0 if the device function was successfully reset or negative if the |
8dd7f803 SY |
3482 | * device doesn't support resetting a single function. |
3483 | */ | |
3484 | int pci_reset_function(struct pci_dev *dev) | |
3485 | { | |
8c1c699f | 3486 | int rc; |
8dd7f803 | 3487 | |
8c1c699f YZ |
3488 | rc = pci_dev_reset(dev, 1); |
3489 | if (rc) | |
3490 | return rc; | |
8dd7f803 | 3491 | |
77cb985a | 3492 | pci_dev_save_and_disable(dev); |
8dd7f803 | 3493 | |
8c1c699f | 3494 | rc = pci_dev_reset(dev, 0); |
8dd7f803 | 3495 | |
77cb985a | 3496 | pci_dev_restore(dev); |
8dd7f803 | 3497 | |
8c1c699f | 3498 | return rc; |
8dd7f803 SY |
3499 | } |
3500 | EXPORT_SYMBOL_GPL(pci_reset_function); | |
3501 | ||
61cf16d8 AW |
3502 | /** |
3503 | * pci_try_reset_function - quiesce and reset a PCI device function | |
3504 | * @dev: PCI device to reset | |
3505 | * | |
3506 | * Same as above, except return -EAGAIN if unable to lock device. | |
3507 | */ | |
3508 | int pci_try_reset_function(struct pci_dev *dev) | |
3509 | { | |
3510 | int rc; | |
3511 | ||
3512 | rc = pci_dev_reset(dev, 1); | |
3513 | if (rc) | |
3514 | return rc; | |
3515 | ||
3516 | pci_dev_save_and_disable(dev); | |
3517 | ||
3518 | if (pci_dev_trylock(dev)) { | |
3519 | rc = __pci_dev_reset(dev, 0); | |
3520 | pci_dev_unlock(dev); | |
3521 | } else | |
3522 | rc = -EAGAIN; | |
3523 | ||
3524 | pci_dev_restore(dev); | |
3525 | ||
3526 | return rc; | |
3527 | } | |
3528 | EXPORT_SYMBOL_GPL(pci_try_reset_function); | |
3529 | ||
090a3c53 AW |
3530 | /* Lock devices from the top of the tree down */ |
3531 | static void pci_bus_lock(struct pci_bus *bus) | |
3532 | { | |
3533 | struct pci_dev *dev; | |
3534 | ||
3535 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
3536 | pci_dev_lock(dev); | |
3537 | if (dev->subordinate) | |
3538 | pci_bus_lock(dev->subordinate); | |
3539 | } | |
3540 | } | |
3541 | ||
3542 | /* Unlock devices from the bottom of the tree up */ | |
3543 | static void pci_bus_unlock(struct pci_bus *bus) | |
3544 | { | |
3545 | struct pci_dev *dev; | |
3546 | ||
3547 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
3548 | if (dev->subordinate) | |
3549 | pci_bus_unlock(dev->subordinate); | |
3550 | pci_dev_unlock(dev); | |
3551 | } | |
3552 | } | |
3553 | ||
61cf16d8 AW |
3554 | /* Return 1 on successful lock, 0 on contention */ |
3555 | static int pci_bus_trylock(struct pci_bus *bus) | |
3556 | { | |
3557 | struct pci_dev *dev; | |
3558 | ||
3559 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
3560 | if (!pci_dev_trylock(dev)) | |
3561 | goto unlock; | |
3562 | if (dev->subordinate) { | |
3563 | if (!pci_bus_trylock(dev->subordinate)) { | |
3564 | pci_dev_unlock(dev); | |
3565 | goto unlock; | |
3566 | } | |
3567 | } | |
3568 | } | |
3569 | return 1; | |
3570 | ||
3571 | unlock: | |
3572 | list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) { | |
3573 | if (dev->subordinate) | |
3574 | pci_bus_unlock(dev->subordinate); | |
3575 | pci_dev_unlock(dev); | |
3576 | } | |
3577 | return 0; | |
3578 | } | |
3579 | ||
090a3c53 AW |
3580 | /* Lock devices from the top of the tree down */ |
3581 | static void pci_slot_lock(struct pci_slot *slot) | |
3582 | { | |
3583 | struct pci_dev *dev; | |
3584 | ||
3585 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
3586 | if (!dev->slot || dev->slot != slot) | |
3587 | continue; | |
3588 | pci_dev_lock(dev); | |
3589 | if (dev->subordinate) | |
3590 | pci_bus_lock(dev->subordinate); | |
3591 | } | |
3592 | } | |
3593 | ||
3594 | /* Unlock devices from the bottom of the tree up */ | |
3595 | static void pci_slot_unlock(struct pci_slot *slot) | |
3596 | { | |
3597 | struct pci_dev *dev; | |
3598 | ||
3599 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
3600 | if (!dev->slot || dev->slot != slot) | |
3601 | continue; | |
3602 | if (dev->subordinate) | |
3603 | pci_bus_unlock(dev->subordinate); | |
3604 | pci_dev_unlock(dev); | |
3605 | } | |
3606 | } | |
3607 | ||
61cf16d8 AW |
3608 | /* Return 1 on successful lock, 0 on contention */ |
3609 | static int pci_slot_trylock(struct pci_slot *slot) | |
3610 | { | |
3611 | struct pci_dev *dev; | |
3612 | ||
3613 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
3614 | if (!dev->slot || dev->slot != slot) | |
3615 | continue; | |
3616 | if (!pci_dev_trylock(dev)) | |
3617 | goto unlock; | |
3618 | if (dev->subordinate) { | |
3619 | if (!pci_bus_trylock(dev->subordinate)) { | |
3620 | pci_dev_unlock(dev); | |
3621 | goto unlock; | |
3622 | } | |
3623 | } | |
3624 | } | |
3625 | return 1; | |
3626 | ||
3627 | unlock: | |
3628 | list_for_each_entry_continue_reverse(dev, | |
3629 | &slot->bus->devices, bus_list) { | |
3630 | if (!dev->slot || dev->slot != slot) | |
3631 | continue; | |
3632 | if (dev->subordinate) | |
3633 | pci_bus_unlock(dev->subordinate); | |
3634 | pci_dev_unlock(dev); | |
3635 | } | |
3636 | return 0; | |
3637 | } | |
3638 | ||
090a3c53 AW |
3639 | /* Save and disable devices from the top of the tree down */ |
3640 | static void pci_bus_save_and_disable(struct pci_bus *bus) | |
3641 | { | |
3642 | struct pci_dev *dev; | |
3643 | ||
3644 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
3645 | pci_dev_save_and_disable(dev); | |
3646 | if (dev->subordinate) | |
3647 | pci_bus_save_and_disable(dev->subordinate); | |
3648 | } | |
3649 | } | |
3650 | ||
3651 | /* | |
3652 | * Restore devices from top of the tree down - parent bridges need to be | |
3653 | * restored before we can get to subordinate devices. | |
3654 | */ | |
3655 | static void pci_bus_restore(struct pci_bus *bus) | |
3656 | { | |
3657 | struct pci_dev *dev; | |
3658 | ||
3659 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
3660 | pci_dev_restore(dev); | |
3661 | if (dev->subordinate) | |
3662 | pci_bus_restore(dev->subordinate); | |
3663 | } | |
3664 | } | |
3665 | ||
3666 | /* Save and disable devices from the top of the tree down */ | |
3667 | static void pci_slot_save_and_disable(struct pci_slot *slot) | |
3668 | { | |
3669 | struct pci_dev *dev; | |
3670 | ||
3671 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
3672 | if (!dev->slot || dev->slot != slot) | |
3673 | continue; | |
3674 | pci_dev_save_and_disable(dev); | |
3675 | if (dev->subordinate) | |
3676 | pci_bus_save_and_disable(dev->subordinate); | |
3677 | } | |
3678 | } | |
3679 | ||
3680 | /* | |
3681 | * Restore devices from top of the tree down - parent bridges need to be | |
3682 | * restored before we can get to subordinate devices. | |
3683 | */ | |
3684 | static void pci_slot_restore(struct pci_slot *slot) | |
3685 | { | |
3686 | struct pci_dev *dev; | |
3687 | ||
3688 | list_for_each_entry(dev, &slot->bus->devices, bus_list) { | |
3689 | if (!dev->slot || dev->slot != slot) | |
3690 | continue; | |
3691 | pci_dev_restore(dev); | |
3692 | if (dev->subordinate) | |
3693 | pci_bus_restore(dev->subordinate); | |
3694 | } | |
3695 | } | |
3696 | ||
3697 | static int pci_slot_reset(struct pci_slot *slot, int probe) | |
3698 | { | |
3699 | int rc; | |
3700 | ||
3701 | if (!slot) | |
3702 | return -ENOTTY; | |
3703 | ||
3704 | if (!probe) | |
3705 | pci_slot_lock(slot); | |
3706 | ||
3707 | might_sleep(); | |
3708 | ||
3709 | rc = pci_reset_hotplug_slot(slot->hotplug, probe); | |
3710 | ||
3711 | if (!probe) | |
3712 | pci_slot_unlock(slot); | |
3713 | ||
3714 | return rc; | |
3715 | } | |
3716 | ||
9a3d2b9b AW |
3717 | /** |
3718 | * pci_probe_reset_slot - probe whether a PCI slot can be reset | |
3719 | * @slot: PCI slot to probe | |
3720 | * | |
3721 | * Return 0 if slot can be reset, negative if a slot reset is not supported. | |
3722 | */ | |
3723 | int pci_probe_reset_slot(struct pci_slot *slot) | |
3724 | { | |
3725 | return pci_slot_reset(slot, 1); | |
3726 | } | |
3727 | EXPORT_SYMBOL_GPL(pci_probe_reset_slot); | |
3728 | ||
090a3c53 AW |
3729 | /** |
3730 | * pci_reset_slot - reset a PCI slot | |
3731 | * @slot: PCI slot to reset | |
3732 | * | |
3733 | * A PCI bus may host multiple slots, each slot may support a reset mechanism | |
3734 | * independent of other slots. For instance, some slots may support slot power | |
3735 | * control. In the case of a 1:1 bus to slot architecture, this function may | |
3736 | * wrap the bus reset to avoid spurious slot related events such as hotplug. | |
3737 | * Generally a slot reset should be attempted before a bus reset. All of the | |
3738 | * function of the slot and any subordinate buses behind the slot are reset | |
3739 | * through this function. PCI config space of all devices in the slot and | |
3740 | * behind the slot is saved before and restored after reset. | |
3741 | * | |
3742 | * Return 0 on success, non-zero on error. | |
3743 | */ | |
3744 | int pci_reset_slot(struct pci_slot *slot) | |
3745 | { | |
3746 | int rc; | |
3747 | ||
3748 | rc = pci_slot_reset(slot, 1); | |
3749 | if (rc) | |
3750 | return rc; | |
3751 | ||
3752 | pci_slot_save_and_disable(slot); | |
3753 | ||
3754 | rc = pci_slot_reset(slot, 0); | |
3755 | ||
3756 | pci_slot_restore(slot); | |
3757 | ||
3758 | return rc; | |
3759 | } | |
3760 | EXPORT_SYMBOL_GPL(pci_reset_slot); | |
3761 | ||
61cf16d8 AW |
3762 | /** |
3763 | * pci_try_reset_slot - Try to reset a PCI slot | |
3764 | * @slot: PCI slot to reset | |
3765 | * | |
3766 | * Same as above except return -EAGAIN if the slot cannot be locked | |
3767 | */ | |
3768 | int pci_try_reset_slot(struct pci_slot *slot) | |
3769 | { | |
3770 | int rc; | |
3771 | ||
3772 | rc = pci_slot_reset(slot, 1); | |
3773 | if (rc) | |
3774 | return rc; | |
3775 | ||
3776 | pci_slot_save_and_disable(slot); | |
3777 | ||
3778 | if (pci_slot_trylock(slot)) { | |
3779 | might_sleep(); | |
3780 | rc = pci_reset_hotplug_slot(slot->hotplug, 0); | |
3781 | pci_slot_unlock(slot); | |
3782 | } else | |
3783 | rc = -EAGAIN; | |
3784 | ||
3785 | pci_slot_restore(slot); | |
3786 | ||
3787 | return rc; | |
3788 | } | |
3789 | EXPORT_SYMBOL_GPL(pci_try_reset_slot); | |
3790 | ||
090a3c53 AW |
3791 | static int pci_bus_reset(struct pci_bus *bus, int probe) |
3792 | { | |
3793 | if (!bus->self) | |
3794 | return -ENOTTY; | |
3795 | ||
3796 | if (probe) | |
3797 | return 0; | |
3798 | ||
3799 | pci_bus_lock(bus); | |
3800 | ||
3801 | might_sleep(); | |
3802 | ||
3803 | pci_reset_bridge_secondary_bus(bus->self); | |
3804 | ||
3805 | pci_bus_unlock(bus); | |
3806 | ||
3807 | return 0; | |
3808 | } | |
3809 | ||
9a3d2b9b AW |
3810 | /** |
3811 | * pci_probe_reset_bus - probe whether a PCI bus can be reset | |
3812 | * @bus: PCI bus to probe | |
3813 | * | |
3814 | * Return 0 if bus can be reset, negative if a bus reset is not supported. | |
3815 | */ | |
3816 | int pci_probe_reset_bus(struct pci_bus *bus) | |
3817 | { | |
3818 | return pci_bus_reset(bus, 1); | |
3819 | } | |
3820 | EXPORT_SYMBOL_GPL(pci_probe_reset_bus); | |
3821 | ||
090a3c53 AW |
3822 | /** |
3823 | * pci_reset_bus - reset a PCI bus | |
3824 | * @bus: top level PCI bus to reset | |
3825 | * | |
3826 | * Do a bus reset on the given bus and any subordinate buses, saving | |
3827 | * and restoring state of all devices. | |
3828 | * | |
3829 | * Return 0 on success, non-zero on error. | |
3830 | */ | |
3831 | int pci_reset_bus(struct pci_bus *bus) | |
3832 | { | |
3833 | int rc; | |
3834 | ||
3835 | rc = pci_bus_reset(bus, 1); | |
3836 | if (rc) | |
3837 | return rc; | |
3838 | ||
3839 | pci_bus_save_and_disable(bus); | |
3840 | ||
3841 | rc = pci_bus_reset(bus, 0); | |
3842 | ||
3843 | pci_bus_restore(bus); | |
3844 | ||
3845 | return rc; | |
3846 | } | |
3847 | EXPORT_SYMBOL_GPL(pci_reset_bus); | |
3848 | ||
61cf16d8 AW |
3849 | /** |
3850 | * pci_try_reset_bus - Try to reset a PCI bus | |
3851 | * @bus: top level PCI bus to reset | |
3852 | * | |
3853 | * Same as above except return -EAGAIN if the bus cannot be locked | |
3854 | */ | |
3855 | int pci_try_reset_bus(struct pci_bus *bus) | |
3856 | { | |
3857 | int rc; | |
3858 | ||
3859 | rc = pci_bus_reset(bus, 1); | |
3860 | if (rc) | |
3861 | return rc; | |
3862 | ||
3863 | pci_bus_save_and_disable(bus); | |
3864 | ||
3865 | if (pci_bus_trylock(bus)) { | |
3866 | might_sleep(); | |
3867 | pci_reset_bridge_secondary_bus(bus->self); | |
3868 | pci_bus_unlock(bus); | |
3869 | } else | |
3870 | rc = -EAGAIN; | |
3871 | ||
3872 | pci_bus_restore(bus); | |
3873 | ||
3874 | return rc; | |
3875 | } | |
3876 | EXPORT_SYMBOL_GPL(pci_try_reset_bus); | |
3877 | ||
d556ad4b PO |
3878 | /** |
3879 | * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count | |
3880 | * @dev: PCI device to query | |
3881 | * | |
3882 | * Returns mmrbc: maximum designed memory read count in bytes | |
3883 | * or appropriate error value. | |
3884 | */ | |
3885 | int pcix_get_max_mmrbc(struct pci_dev *dev) | |
3886 | { | |
7c9e2b1c | 3887 | int cap; |
d556ad4b PO |
3888 | u32 stat; |
3889 | ||
3890 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
3891 | if (!cap) | |
3892 | return -EINVAL; | |
3893 | ||
7c9e2b1c | 3894 | if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) |
d556ad4b PO |
3895 | return -EINVAL; |
3896 | ||
25daeb55 | 3897 | return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21); |
d556ad4b PO |
3898 | } |
3899 | EXPORT_SYMBOL(pcix_get_max_mmrbc); | |
3900 | ||
3901 | /** | |
3902 | * pcix_get_mmrbc - get PCI-X maximum memory read byte count | |
3903 | * @dev: PCI device to query | |
3904 | * | |
3905 | * Returns mmrbc: maximum memory read count in bytes | |
3906 | * or appropriate error value. | |
3907 | */ | |
3908 | int pcix_get_mmrbc(struct pci_dev *dev) | |
3909 | { | |
7c9e2b1c | 3910 | int cap; |
bdc2bda7 | 3911 | u16 cmd; |
d556ad4b PO |
3912 | |
3913 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
3914 | if (!cap) | |
3915 | return -EINVAL; | |
3916 | ||
7c9e2b1c DN |
3917 | if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) |
3918 | return -EINVAL; | |
d556ad4b | 3919 | |
7c9e2b1c | 3920 | return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2); |
d556ad4b PO |
3921 | } |
3922 | EXPORT_SYMBOL(pcix_get_mmrbc); | |
3923 | ||
3924 | /** | |
3925 | * pcix_set_mmrbc - set PCI-X maximum memory read byte count | |
3926 | * @dev: PCI device to query | |
3927 | * @mmrbc: maximum memory read count in bytes | |
3928 | * valid values are 512, 1024, 2048, 4096 | |
3929 | * | |
3930 | * If possible sets maximum memory read byte count, some bridges have erratas | |
3931 | * that prevent this. | |
3932 | */ | |
3933 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) | |
3934 | { | |
7c9e2b1c | 3935 | int cap; |
bdc2bda7 DN |
3936 | u32 stat, v, o; |
3937 | u16 cmd; | |
d556ad4b | 3938 | |
229f5afd | 3939 | if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc)) |
7c9e2b1c | 3940 | return -EINVAL; |
d556ad4b PO |
3941 | |
3942 | v = ffs(mmrbc) - 10; | |
3943 | ||
3944 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
3945 | if (!cap) | |
7c9e2b1c | 3946 | return -EINVAL; |
d556ad4b | 3947 | |
7c9e2b1c DN |
3948 | if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat)) |
3949 | return -EINVAL; | |
d556ad4b PO |
3950 | |
3951 | if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21) | |
3952 | return -E2BIG; | |
3953 | ||
7c9e2b1c DN |
3954 | if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd)) |
3955 | return -EINVAL; | |
d556ad4b PO |
3956 | |
3957 | o = (cmd & PCI_X_CMD_MAX_READ) >> 2; | |
3958 | if (o != v) { | |
809a3bf9 | 3959 | if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) |
d556ad4b PO |
3960 | return -EIO; |
3961 | ||
3962 | cmd &= ~PCI_X_CMD_MAX_READ; | |
3963 | cmd |= v << 2; | |
7c9e2b1c DN |
3964 | if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd)) |
3965 | return -EIO; | |
d556ad4b | 3966 | } |
7c9e2b1c | 3967 | return 0; |
d556ad4b PO |
3968 | } |
3969 | EXPORT_SYMBOL(pcix_set_mmrbc); | |
3970 | ||
3971 | /** | |
3972 | * pcie_get_readrq - get PCI Express read request size | |
3973 | * @dev: PCI device to query | |
3974 | * | |
3975 | * Returns maximum memory read request in bytes | |
3976 | * or appropriate error value. | |
3977 | */ | |
3978 | int pcie_get_readrq(struct pci_dev *dev) | |
3979 | { | |
d556ad4b PO |
3980 | u16 ctl; |
3981 | ||
59875ae4 | 3982 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); |
d556ad4b | 3983 | |
59875ae4 | 3984 | return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12); |
d556ad4b PO |
3985 | } |
3986 | EXPORT_SYMBOL(pcie_get_readrq); | |
3987 | ||
3988 | /** | |
3989 | * pcie_set_readrq - set PCI Express maximum memory read request | |
3990 | * @dev: PCI device to query | |
42e61f4a | 3991 | * @rq: maximum memory read count in bytes |
d556ad4b PO |
3992 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
3993 | * | |
c9b378c7 | 3994 | * If possible sets maximum memory read request in bytes |
d556ad4b PO |
3995 | */ |
3996 | int pcie_set_readrq(struct pci_dev *dev, int rq) | |
3997 | { | |
59875ae4 | 3998 | u16 v; |
d556ad4b | 3999 | |
229f5afd | 4000 | if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) |
59875ae4 | 4001 | return -EINVAL; |
d556ad4b | 4002 | |
a1c473aa BH |
4003 | /* |
4004 | * If using the "performance" PCIe config, we clamp the | |
4005 | * read rq size to the max packet size to prevent the | |
4006 | * host bridge generating requests larger than we can | |
4007 | * cope with | |
4008 | */ | |
4009 | if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { | |
4010 | int mps = pcie_get_mps(dev); | |
4011 | ||
a1c473aa BH |
4012 | if (mps < rq) |
4013 | rq = mps; | |
4014 | } | |
4015 | ||
4016 | v = (ffs(rq) - 8) << 12; | |
d556ad4b | 4017 | |
59875ae4 JL |
4018 | return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, |
4019 | PCI_EXP_DEVCTL_READRQ, v); | |
d556ad4b PO |
4020 | } |
4021 | EXPORT_SYMBOL(pcie_set_readrq); | |
4022 | ||
b03e7495 JM |
4023 | /** |
4024 | * pcie_get_mps - get PCI Express maximum payload size | |
4025 | * @dev: PCI device to query | |
4026 | * | |
4027 | * Returns maximum payload size in bytes | |
b03e7495 JM |
4028 | */ |
4029 | int pcie_get_mps(struct pci_dev *dev) | |
4030 | { | |
b03e7495 JM |
4031 | u16 ctl; |
4032 | ||
59875ae4 | 4033 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); |
b03e7495 | 4034 | |
59875ae4 | 4035 | return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5); |
b03e7495 | 4036 | } |
f1c66c46 | 4037 | EXPORT_SYMBOL(pcie_get_mps); |
b03e7495 JM |
4038 | |
4039 | /** | |
4040 | * pcie_set_mps - set PCI Express maximum payload size | |
4041 | * @dev: PCI device to query | |
47c08f31 | 4042 | * @mps: maximum payload size in bytes |
b03e7495 JM |
4043 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
4044 | * | |
4045 | * If possible sets maximum payload size | |
4046 | */ | |
4047 | int pcie_set_mps(struct pci_dev *dev, int mps) | |
4048 | { | |
59875ae4 | 4049 | u16 v; |
b03e7495 JM |
4050 | |
4051 | if (mps < 128 || mps > 4096 || !is_power_of_2(mps)) | |
59875ae4 | 4052 | return -EINVAL; |
b03e7495 JM |
4053 | |
4054 | v = ffs(mps) - 8; | |
f7625980 | 4055 | if (v > dev->pcie_mpss) |
59875ae4 | 4056 | return -EINVAL; |
b03e7495 JM |
4057 | v <<= 5; |
4058 | ||
59875ae4 JL |
4059 | return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, |
4060 | PCI_EXP_DEVCTL_PAYLOAD, v); | |
b03e7495 | 4061 | } |
f1c66c46 | 4062 | EXPORT_SYMBOL(pcie_set_mps); |
b03e7495 | 4063 | |
81377c8d JK |
4064 | /** |
4065 | * pcie_get_minimum_link - determine minimum link settings of a PCI device | |
4066 | * @dev: PCI device to query | |
4067 | * @speed: storage for minimum speed | |
4068 | * @width: storage for minimum width | |
4069 | * | |
4070 | * This function will walk up the PCI device chain and determine the minimum | |
4071 | * link width and speed of the device. | |
4072 | */ | |
4073 | int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, | |
4074 | enum pcie_link_width *width) | |
4075 | { | |
4076 | int ret; | |
4077 | ||
4078 | *speed = PCI_SPEED_UNKNOWN; | |
4079 | *width = PCIE_LNK_WIDTH_UNKNOWN; | |
4080 | ||
4081 | while (dev) { | |
4082 | u16 lnksta; | |
4083 | enum pci_bus_speed next_speed; | |
4084 | enum pcie_link_width next_width; | |
4085 | ||
4086 | ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); | |
4087 | if (ret) | |
4088 | return ret; | |
4089 | ||
4090 | next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS]; | |
4091 | next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >> | |
4092 | PCI_EXP_LNKSTA_NLW_SHIFT; | |
4093 | ||
4094 | if (next_speed < *speed) | |
4095 | *speed = next_speed; | |
4096 | ||
4097 | if (next_width < *width) | |
4098 | *width = next_width; | |
4099 | ||
4100 | dev = dev->bus->self; | |
4101 | } | |
4102 | ||
4103 | return 0; | |
4104 | } | |
4105 | EXPORT_SYMBOL(pcie_get_minimum_link); | |
4106 | ||
c87deff7 HS |
4107 | /** |
4108 | * pci_select_bars - Make BAR mask from the type of resource | |
f95d882d | 4109 | * @dev: the PCI device for which BAR mask is made |
c87deff7 HS |
4110 | * @flags: resource type mask to be selected |
4111 | * | |
4112 | * This helper routine makes bar mask from the type of resource. | |
4113 | */ | |
4114 | int pci_select_bars(struct pci_dev *dev, unsigned long flags) | |
4115 | { | |
4116 | int i, bars = 0; | |
4117 | for (i = 0; i < PCI_NUM_RESOURCES; i++) | |
4118 | if (pci_resource_flags(dev, i) & flags) | |
4119 | bars |= (1 << i); | |
4120 | return bars; | |
4121 | } | |
b7fe9434 | 4122 | EXPORT_SYMBOL(pci_select_bars); |
c87deff7 | 4123 | |
613e7ed6 YZ |
4124 | /** |
4125 | * pci_resource_bar - get position of the BAR associated with a resource | |
4126 | * @dev: the PCI device | |
4127 | * @resno: the resource number | |
4128 | * @type: the BAR type to be filled in | |
4129 | * | |
4130 | * Returns BAR position in config space, or 0 if the BAR is invalid. | |
4131 | */ | |
4132 | int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type) | |
4133 | { | |
d1b054da YZ |
4134 | int reg; |
4135 | ||
613e7ed6 YZ |
4136 | if (resno < PCI_ROM_RESOURCE) { |
4137 | *type = pci_bar_unknown; | |
4138 | return PCI_BASE_ADDRESS_0 + 4 * resno; | |
4139 | } else if (resno == PCI_ROM_RESOURCE) { | |
4140 | *type = pci_bar_mem32; | |
4141 | return dev->rom_base_reg; | |
d1b054da YZ |
4142 | } else if (resno < PCI_BRIDGE_RESOURCES) { |
4143 | /* device specific resource */ | |
4144 | reg = pci_iov_resource_bar(dev, resno, type); | |
4145 | if (reg) | |
4146 | return reg; | |
613e7ed6 YZ |
4147 | } |
4148 | ||
865df576 | 4149 | dev_err(&dev->dev, "BAR %d: invalid resource\n", resno); |
613e7ed6 YZ |
4150 | return 0; |
4151 | } | |
4152 | ||
95a8b6ef MT |
4153 | /* Some architectures require additional programming to enable VGA */ |
4154 | static arch_set_vga_state_t arch_set_vga_state; | |
4155 | ||
4156 | void __init pci_register_set_vga_state(arch_set_vga_state_t func) | |
4157 | { | |
4158 | arch_set_vga_state = func; /* NULL disables */ | |
4159 | } | |
4160 | ||
4161 | static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode, | |
7ad35cf2 | 4162 | unsigned int command_bits, u32 flags) |
95a8b6ef MT |
4163 | { |
4164 | if (arch_set_vga_state) | |
4165 | return arch_set_vga_state(dev, decode, command_bits, | |
7ad35cf2 | 4166 | flags); |
95a8b6ef MT |
4167 | return 0; |
4168 | } | |
4169 | ||
deb2d2ec BH |
4170 | /** |
4171 | * pci_set_vga_state - set VGA decode state on device and parents if requested | |
19eea630 RD |
4172 | * @dev: the PCI device |
4173 | * @decode: true = enable decoding, false = disable decoding | |
4174 | * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY | |
3f37d622 | 4175 | * @flags: traverse ancestors and change bridges |
3448a19d | 4176 | * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE |
deb2d2ec BH |
4177 | */ |
4178 | int pci_set_vga_state(struct pci_dev *dev, bool decode, | |
3448a19d | 4179 | unsigned int command_bits, u32 flags) |
deb2d2ec BH |
4180 | { |
4181 | struct pci_bus *bus; | |
4182 | struct pci_dev *bridge; | |
4183 | u16 cmd; | |
95a8b6ef | 4184 | int rc; |
deb2d2ec | 4185 | |
67ebd814 | 4186 | WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY))); |
deb2d2ec | 4187 | |
95a8b6ef | 4188 | /* ARCH specific VGA enables */ |
3448a19d | 4189 | rc = pci_set_vga_state_arch(dev, decode, command_bits, flags); |
95a8b6ef MT |
4190 | if (rc) |
4191 | return rc; | |
4192 | ||
3448a19d DA |
4193 | if (flags & PCI_VGA_STATE_CHANGE_DECODES) { |
4194 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
4195 | if (decode == true) | |
4196 | cmd |= command_bits; | |
4197 | else | |
4198 | cmd &= ~command_bits; | |
4199 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
4200 | } | |
deb2d2ec | 4201 | |
3448a19d | 4202 | if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE)) |
deb2d2ec BH |
4203 | return 0; |
4204 | ||
4205 | bus = dev->bus; | |
4206 | while (bus) { | |
4207 | bridge = bus->self; | |
4208 | if (bridge) { | |
4209 | pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, | |
4210 | &cmd); | |
4211 | if (decode == true) | |
4212 | cmd |= PCI_BRIDGE_CTL_VGA; | |
4213 | else | |
4214 | cmd &= ~PCI_BRIDGE_CTL_VGA; | |
4215 | pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, | |
4216 | cmd); | |
4217 | } | |
4218 | bus = bus->parent; | |
4219 | } | |
4220 | return 0; | |
4221 | } | |
4222 | ||
8496e85c RW |
4223 | bool pci_device_is_present(struct pci_dev *pdev) |
4224 | { | |
4225 | u32 v; | |
4226 | ||
4227 | return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0); | |
4228 | } | |
4229 | EXPORT_SYMBOL_GPL(pci_device_is_present); | |
4230 | ||
32a9a682 YS |
4231 | #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE |
4232 | static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0}; | |
e9d1e492 | 4233 | static DEFINE_SPINLOCK(resource_alignment_lock); |
32a9a682 YS |
4234 | |
4235 | /** | |
4236 | * pci_specified_resource_alignment - get resource alignment specified by user. | |
4237 | * @dev: the PCI device to get | |
4238 | * | |
4239 | * RETURNS: Resource alignment if it is specified. | |
4240 | * Zero if it is not specified. | |
4241 | */ | |
9738abed | 4242 | static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev) |
32a9a682 YS |
4243 | { |
4244 | int seg, bus, slot, func, align_order, count; | |
4245 | resource_size_t align = 0; | |
4246 | char *p; | |
4247 | ||
4248 | spin_lock(&resource_alignment_lock); | |
4249 | p = resource_alignment_param; | |
4250 | while (*p) { | |
4251 | count = 0; | |
4252 | if (sscanf(p, "%d%n", &align_order, &count) == 1 && | |
4253 | p[count] == '@') { | |
4254 | p += count + 1; | |
4255 | } else { | |
4256 | align_order = -1; | |
4257 | } | |
4258 | if (sscanf(p, "%x:%x:%x.%x%n", | |
4259 | &seg, &bus, &slot, &func, &count) != 4) { | |
4260 | seg = 0; | |
4261 | if (sscanf(p, "%x:%x.%x%n", | |
4262 | &bus, &slot, &func, &count) != 3) { | |
4263 | /* Invalid format */ | |
4264 | printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n", | |
4265 | p); | |
4266 | break; | |
4267 | } | |
4268 | } | |
4269 | p += count; | |
4270 | if (seg == pci_domain_nr(dev->bus) && | |
4271 | bus == dev->bus->number && | |
4272 | slot == PCI_SLOT(dev->devfn) && | |
4273 | func == PCI_FUNC(dev->devfn)) { | |
4274 | if (align_order == -1) { | |
4275 | align = PAGE_SIZE; | |
4276 | } else { | |
4277 | align = 1 << align_order; | |
4278 | } | |
4279 | /* Found */ | |
4280 | break; | |
4281 | } | |
4282 | if (*p != ';' && *p != ',') { | |
4283 | /* End of param or invalid format */ | |
4284 | break; | |
4285 | } | |
4286 | p++; | |
4287 | } | |
4288 | spin_unlock(&resource_alignment_lock); | |
4289 | return align; | |
4290 | } | |
4291 | ||
2069ecfb YL |
4292 | /* |
4293 | * This function disables memory decoding and releases memory resources | |
4294 | * of the device specified by kernel's boot parameter 'pci=resource_alignment='. | |
4295 | * It also rounds up size to specified alignment. | |
4296 | * Later on, the kernel will assign page-aligned memory resource back | |
4297 | * to the device. | |
4298 | */ | |
4299 | void pci_reassigndev_resource_alignment(struct pci_dev *dev) | |
4300 | { | |
4301 | int i; | |
4302 | struct resource *r; | |
4303 | resource_size_t align, size; | |
4304 | u16 command; | |
4305 | ||
10c463a7 YL |
4306 | /* check if specified PCI is target device to reassign */ |
4307 | align = pci_specified_resource_alignment(dev); | |
4308 | if (!align) | |
2069ecfb YL |
4309 | return; |
4310 | ||
4311 | if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL && | |
4312 | (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { | |
4313 | dev_warn(&dev->dev, | |
4314 | "Can't reassign resources to host bridge.\n"); | |
4315 | return; | |
4316 | } | |
4317 | ||
4318 | dev_info(&dev->dev, | |
4319 | "Disabling memory decoding and releasing memory resources.\n"); | |
4320 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
4321 | command &= ~PCI_COMMAND_MEMORY; | |
4322 | pci_write_config_word(dev, PCI_COMMAND, command); | |
4323 | ||
2069ecfb YL |
4324 | for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) { |
4325 | r = &dev->resource[i]; | |
4326 | if (!(r->flags & IORESOURCE_MEM)) | |
4327 | continue; | |
4328 | size = resource_size(r); | |
4329 | if (size < align) { | |
4330 | size = align; | |
4331 | dev_info(&dev->dev, | |
4332 | "Rounding up size of resource #%d to %#llx.\n", | |
4333 | i, (unsigned long long)size); | |
4334 | } | |
bd064f0a | 4335 | r->flags |= IORESOURCE_UNSET; |
2069ecfb YL |
4336 | r->end = size - 1; |
4337 | r->start = 0; | |
4338 | } | |
4339 | /* Need to disable bridge's resource window, | |
4340 | * to enable the kernel to reassign new resource | |
4341 | * window later on. | |
4342 | */ | |
4343 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE && | |
4344 | (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { | |
4345 | for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) { | |
4346 | r = &dev->resource[i]; | |
4347 | if (!(r->flags & IORESOURCE_MEM)) | |
4348 | continue; | |
bd064f0a | 4349 | r->flags |= IORESOURCE_UNSET; |
2069ecfb YL |
4350 | r->end = resource_size(r) - 1; |
4351 | r->start = 0; | |
4352 | } | |
4353 | pci_disable_bridge_window(dev); | |
4354 | } | |
4355 | } | |
4356 | ||
9738abed | 4357 | static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count) |
32a9a682 YS |
4358 | { |
4359 | if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1) | |
4360 | count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1; | |
4361 | spin_lock(&resource_alignment_lock); | |
4362 | strncpy(resource_alignment_param, buf, count); | |
4363 | resource_alignment_param[count] = '\0'; | |
4364 | spin_unlock(&resource_alignment_lock); | |
4365 | return count; | |
4366 | } | |
4367 | ||
9738abed | 4368 | static ssize_t pci_get_resource_alignment_param(char *buf, size_t size) |
32a9a682 YS |
4369 | { |
4370 | size_t count; | |
4371 | spin_lock(&resource_alignment_lock); | |
4372 | count = snprintf(buf, size, "%s", resource_alignment_param); | |
4373 | spin_unlock(&resource_alignment_lock); | |
4374 | return count; | |
4375 | } | |
4376 | ||
4377 | static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf) | |
4378 | { | |
4379 | return pci_get_resource_alignment_param(buf, PAGE_SIZE); | |
4380 | } | |
4381 | ||
4382 | static ssize_t pci_resource_alignment_store(struct bus_type *bus, | |
4383 | const char *buf, size_t count) | |
4384 | { | |
4385 | return pci_set_resource_alignment_param(buf, count); | |
4386 | } | |
4387 | ||
4388 | BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show, | |
4389 | pci_resource_alignment_store); | |
4390 | ||
4391 | static int __init pci_resource_alignment_sysfs_init(void) | |
4392 | { | |
4393 | return bus_create_file(&pci_bus_type, | |
4394 | &bus_attr_resource_alignment); | |
4395 | } | |
4396 | ||
4397 | late_initcall(pci_resource_alignment_sysfs_init); | |
4398 | ||
15856ad5 | 4399 | static void pci_no_domains(void) |
32a2eea7 JG |
4400 | { |
4401 | #ifdef CONFIG_PCI_DOMAINS | |
4402 | pci_domains_supported = 0; | |
4403 | #endif | |
4404 | } | |
4405 | ||
0ef5f8f6 | 4406 | /** |
642c92da | 4407 | * pci_ext_cfg_avail - can we access extended PCI config space? |
0ef5f8f6 AP |
4408 | * |
4409 | * Returns 1 if we can access PCI extended config space (offsets | |
4410 | * greater than 0xff). This is the default implementation. Architecture | |
4411 | * implementations can override this. | |
4412 | */ | |
642c92da | 4413 | int __weak pci_ext_cfg_avail(void) |
0ef5f8f6 AP |
4414 | { |
4415 | return 1; | |
4416 | } | |
4417 | ||
2d1c8618 BH |
4418 | void __weak pci_fixup_cardbus(struct pci_bus *bus) |
4419 | { | |
4420 | } | |
4421 | EXPORT_SYMBOL(pci_fixup_cardbus); | |
4422 | ||
ad04d31e | 4423 | static int __init pci_setup(char *str) |
1da177e4 LT |
4424 | { |
4425 | while (str) { | |
4426 | char *k = strchr(str, ','); | |
4427 | if (k) | |
4428 | *k++ = 0; | |
4429 | if (*str && (str = pcibios_setup(str)) && *str) { | |
309e57df MW |
4430 | if (!strcmp(str, "nomsi")) { |
4431 | pci_no_msi(); | |
7f785763 RD |
4432 | } else if (!strcmp(str, "noaer")) { |
4433 | pci_no_aer(); | |
b55438fd YL |
4434 | } else if (!strncmp(str, "realloc=", 8)) { |
4435 | pci_realloc_get_opt(str + 8); | |
f483d392 | 4436 | } else if (!strncmp(str, "realloc", 7)) { |
b55438fd | 4437 | pci_realloc_get_opt("on"); |
32a2eea7 JG |
4438 | } else if (!strcmp(str, "nodomains")) { |
4439 | pci_no_domains(); | |
6748dcc2 RW |
4440 | } else if (!strncmp(str, "noari", 5)) { |
4441 | pcie_ari_disabled = true; | |
4516a618 AN |
4442 | } else if (!strncmp(str, "cbiosize=", 9)) { |
4443 | pci_cardbus_io_size = memparse(str + 9, &str); | |
4444 | } else if (!strncmp(str, "cbmemsize=", 10)) { | |
4445 | pci_cardbus_mem_size = memparse(str + 10, &str); | |
32a9a682 YS |
4446 | } else if (!strncmp(str, "resource_alignment=", 19)) { |
4447 | pci_set_resource_alignment_param(str + 19, | |
4448 | strlen(str + 19)); | |
43c16408 AP |
4449 | } else if (!strncmp(str, "ecrc=", 5)) { |
4450 | pcie_ecrc_get_policy(str + 5); | |
28760489 EB |
4451 | } else if (!strncmp(str, "hpiosize=", 9)) { |
4452 | pci_hotplug_io_size = memparse(str + 9, &str); | |
4453 | } else if (!strncmp(str, "hpmemsize=", 10)) { | |
4454 | pci_hotplug_mem_size = memparse(str + 10, &str); | |
5f39e670 JM |
4455 | } else if (!strncmp(str, "pcie_bus_tune_off", 17)) { |
4456 | pcie_bus_config = PCIE_BUS_TUNE_OFF; | |
b03e7495 JM |
4457 | } else if (!strncmp(str, "pcie_bus_safe", 13)) { |
4458 | pcie_bus_config = PCIE_BUS_SAFE; | |
4459 | } else if (!strncmp(str, "pcie_bus_perf", 13)) { | |
4460 | pcie_bus_config = PCIE_BUS_PERFORMANCE; | |
5f39e670 JM |
4461 | } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) { |
4462 | pcie_bus_config = PCIE_BUS_PEER2PEER; | |
284f5f9d BH |
4463 | } else if (!strncmp(str, "pcie_scan_all", 13)) { |
4464 | pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS); | |
309e57df MW |
4465 | } else { |
4466 | printk(KERN_ERR "PCI: Unknown option `%s'\n", | |
4467 | str); | |
4468 | } | |
1da177e4 LT |
4469 | } |
4470 | str = k; | |
4471 | } | |
0637a70a | 4472 | return 0; |
1da177e4 | 4473 | } |
0637a70a | 4474 | early_param("pci", pci_setup); |