]>
Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * PCI Bus Services, see include/linux/pci.h for further explanation. |
3 | * | |
4 | * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, | |
5 | * David Mosberger-Tang | |
6 | * | |
7 | * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> | |
8 | */ | |
9 | ||
10 | #include <linux/kernel.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/pci.h> | |
075c1771 | 14 | #include <linux/pm.h> |
1da177e4 LT |
15 | #include <linux/module.h> |
16 | #include <linux/spinlock.h> | |
4e57b681 | 17 | #include <linux/string.h> |
229f5afd | 18 | #include <linux/log2.h> |
7d715a6c | 19 | #include <linux/pci-aspm.h> |
c300bd2f | 20 | #include <linux/pm_wakeup.h> |
1da177e4 | 21 | #include <asm/dma.h> /* isa_dma_bridge_buggy */ |
bc56b9e0 | 22 | #include "pci.h" |
1da177e4 | 23 | |
ffadcc2f | 24 | unsigned int pci_pm_d3_delay = 10; |
1da177e4 | 25 | |
32a2eea7 JG |
26 | #ifdef CONFIG_PCI_DOMAINS |
27 | int pci_domains_supported = 1; | |
28 | #endif | |
29 | ||
4516a618 AN |
30 | #define DEFAULT_CARDBUS_IO_SIZE (256) |
31 | #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024) | |
32 | /* pci=cbmemsize=nnM,cbiosize=nn can override this */ | |
33 | unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE; | |
34 | unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE; | |
35 | ||
1da177e4 LT |
36 | /** |
37 | * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children | |
38 | * @bus: pointer to PCI bus structure to search | |
39 | * | |
40 | * Given a PCI bus, returns the highest PCI bus number present in the set | |
41 | * including the given PCI bus and its list of child PCI buses. | |
42 | */ | |
96bde06a | 43 | unsigned char pci_bus_max_busnr(struct pci_bus* bus) |
1da177e4 LT |
44 | { |
45 | struct list_head *tmp; | |
46 | unsigned char max, n; | |
47 | ||
b82db5ce | 48 | max = bus->subordinate; |
1da177e4 LT |
49 | list_for_each(tmp, &bus->children) { |
50 | n = pci_bus_max_busnr(pci_bus_b(tmp)); | |
51 | if(n > max) | |
52 | max = n; | |
53 | } | |
54 | return max; | |
55 | } | |
b82db5ce | 56 | EXPORT_SYMBOL_GPL(pci_bus_max_busnr); |
1da177e4 | 57 | |
b82db5ce | 58 | #if 0 |
1da177e4 LT |
59 | /** |
60 | * pci_max_busnr - returns maximum PCI bus number | |
61 | * | |
62 | * Returns the highest PCI bus number present in the system global list of | |
63 | * PCI buses. | |
64 | */ | |
65 | unsigned char __devinit | |
66 | pci_max_busnr(void) | |
67 | { | |
68 | struct pci_bus *bus = NULL; | |
69 | unsigned char max, n; | |
70 | ||
71 | max = 0; | |
72 | while ((bus = pci_find_next_bus(bus)) != NULL) { | |
73 | n = pci_bus_max_busnr(bus); | |
74 | if(n > max) | |
75 | max = n; | |
76 | } | |
77 | return max; | |
78 | } | |
79 | ||
54c762fe AB |
80 | #endif /* 0 */ |
81 | ||
687d5fe3 ME |
82 | #define PCI_FIND_CAP_TTL 48 |
83 | ||
84 | static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, | |
85 | u8 pos, int cap, int *ttl) | |
24a4e377 RD |
86 | { |
87 | u8 id; | |
24a4e377 | 88 | |
687d5fe3 | 89 | while ((*ttl)--) { |
24a4e377 RD |
90 | pci_bus_read_config_byte(bus, devfn, pos, &pos); |
91 | if (pos < 0x40) | |
92 | break; | |
93 | pos &= ~3; | |
94 | pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, | |
95 | &id); | |
96 | if (id == 0xff) | |
97 | break; | |
98 | if (id == cap) | |
99 | return pos; | |
100 | pos += PCI_CAP_LIST_NEXT; | |
101 | } | |
102 | return 0; | |
103 | } | |
104 | ||
687d5fe3 ME |
105 | static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, |
106 | u8 pos, int cap) | |
107 | { | |
108 | int ttl = PCI_FIND_CAP_TTL; | |
109 | ||
110 | return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); | |
111 | } | |
112 | ||
24a4e377 RD |
113 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) |
114 | { | |
115 | return __pci_find_next_cap(dev->bus, dev->devfn, | |
116 | pos + PCI_CAP_LIST_NEXT, cap); | |
117 | } | |
118 | EXPORT_SYMBOL_GPL(pci_find_next_capability); | |
119 | ||
d3bac118 ME |
120 | static int __pci_bus_find_cap_start(struct pci_bus *bus, |
121 | unsigned int devfn, u8 hdr_type) | |
1da177e4 LT |
122 | { |
123 | u16 status; | |
1da177e4 LT |
124 | |
125 | pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); | |
126 | if (!(status & PCI_STATUS_CAP_LIST)) | |
127 | return 0; | |
128 | ||
129 | switch (hdr_type) { | |
130 | case PCI_HEADER_TYPE_NORMAL: | |
131 | case PCI_HEADER_TYPE_BRIDGE: | |
d3bac118 | 132 | return PCI_CAPABILITY_LIST; |
1da177e4 | 133 | case PCI_HEADER_TYPE_CARDBUS: |
d3bac118 | 134 | return PCI_CB_CAPABILITY_LIST; |
1da177e4 LT |
135 | default: |
136 | return 0; | |
137 | } | |
d3bac118 ME |
138 | |
139 | return 0; | |
1da177e4 LT |
140 | } |
141 | ||
142 | /** | |
143 | * pci_find_capability - query for devices' capabilities | |
144 | * @dev: PCI device to query | |
145 | * @cap: capability code | |
146 | * | |
147 | * Tell if a device supports a given PCI capability. | |
148 | * Returns the address of the requested capability structure within the | |
149 | * device's PCI configuration space or 0 in case the device does not | |
150 | * support it. Possible values for @cap: | |
151 | * | |
152 | * %PCI_CAP_ID_PM Power Management | |
153 | * %PCI_CAP_ID_AGP Accelerated Graphics Port | |
154 | * %PCI_CAP_ID_VPD Vital Product Data | |
155 | * %PCI_CAP_ID_SLOTID Slot Identification | |
156 | * %PCI_CAP_ID_MSI Message Signalled Interrupts | |
157 | * %PCI_CAP_ID_CHSWP CompactPCI HotSwap | |
158 | * %PCI_CAP_ID_PCIX PCI-X | |
159 | * %PCI_CAP_ID_EXP PCI Express | |
160 | */ | |
161 | int pci_find_capability(struct pci_dev *dev, int cap) | |
162 | { | |
d3bac118 ME |
163 | int pos; |
164 | ||
165 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
166 | if (pos) | |
167 | pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); | |
168 | ||
169 | return pos; | |
1da177e4 LT |
170 | } |
171 | ||
172 | /** | |
173 | * pci_bus_find_capability - query for devices' capabilities | |
174 | * @bus: the PCI bus to query | |
175 | * @devfn: PCI device to query | |
176 | * @cap: capability code | |
177 | * | |
178 | * Like pci_find_capability() but works for pci devices that do not have a | |
179 | * pci_dev structure set up yet. | |
180 | * | |
181 | * Returns the address of the requested capability structure within the | |
182 | * device's PCI configuration space or 0 in case the device does not | |
183 | * support it. | |
184 | */ | |
185 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) | |
186 | { | |
d3bac118 | 187 | int pos; |
1da177e4 LT |
188 | u8 hdr_type; |
189 | ||
190 | pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); | |
191 | ||
d3bac118 ME |
192 | pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f); |
193 | if (pos) | |
194 | pos = __pci_find_next_cap(bus, devfn, pos, cap); | |
195 | ||
196 | return pos; | |
1da177e4 LT |
197 | } |
198 | ||
199 | /** | |
200 | * pci_find_ext_capability - Find an extended capability | |
201 | * @dev: PCI device to query | |
202 | * @cap: capability code | |
203 | * | |
204 | * Returns the address of the requested extended capability structure | |
205 | * within the device's PCI configuration space or 0 if the device does | |
206 | * not support it. Possible values for @cap: | |
207 | * | |
208 | * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting | |
209 | * %PCI_EXT_CAP_ID_VC Virtual Channel | |
210 | * %PCI_EXT_CAP_ID_DSN Device Serial Number | |
211 | * %PCI_EXT_CAP_ID_PWR Power Budgeting | |
212 | */ | |
213 | int pci_find_ext_capability(struct pci_dev *dev, int cap) | |
214 | { | |
215 | u32 header; | |
216 | int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */ | |
217 | int pos = 0x100; | |
218 | ||
219 | if (dev->cfg_size <= 256) | |
220 | return 0; | |
221 | ||
222 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
223 | return 0; | |
224 | ||
225 | /* | |
226 | * If we have no capabilities, this is indicated by cap ID, | |
227 | * cap version and next pointer all being 0. | |
228 | */ | |
229 | if (header == 0) | |
230 | return 0; | |
231 | ||
232 | while (ttl-- > 0) { | |
233 | if (PCI_EXT_CAP_ID(header) == cap) | |
234 | return pos; | |
235 | ||
236 | pos = PCI_EXT_CAP_NEXT(header); | |
237 | if (pos < 0x100) | |
238 | break; | |
239 | ||
240 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
241 | break; | |
242 | } | |
243 | ||
244 | return 0; | |
245 | } | |
3a720d72 | 246 | EXPORT_SYMBOL_GPL(pci_find_ext_capability); |
1da177e4 | 247 | |
687d5fe3 ME |
248 | static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) |
249 | { | |
250 | int rc, ttl = PCI_FIND_CAP_TTL; | |
251 | u8 cap, mask; | |
252 | ||
253 | if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST) | |
254 | mask = HT_3BIT_CAP_MASK; | |
255 | else | |
256 | mask = HT_5BIT_CAP_MASK; | |
257 | ||
258 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, | |
259 | PCI_CAP_ID_HT, &ttl); | |
260 | while (pos) { | |
261 | rc = pci_read_config_byte(dev, pos + 3, &cap); | |
262 | if (rc != PCIBIOS_SUCCESSFUL) | |
263 | return 0; | |
264 | ||
265 | if ((cap & mask) == ht_cap) | |
266 | return pos; | |
267 | ||
47a4d5be BG |
268 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, |
269 | pos + PCI_CAP_LIST_NEXT, | |
687d5fe3 ME |
270 | PCI_CAP_ID_HT, &ttl); |
271 | } | |
272 | ||
273 | return 0; | |
274 | } | |
275 | /** | |
276 | * pci_find_next_ht_capability - query a device's Hypertransport capabilities | |
277 | * @dev: PCI device to query | |
278 | * @pos: Position from which to continue searching | |
279 | * @ht_cap: Hypertransport capability code | |
280 | * | |
281 | * To be used in conjunction with pci_find_ht_capability() to search for | |
282 | * all capabilities matching @ht_cap. @pos should always be a value returned | |
283 | * from pci_find_ht_capability(). | |
284 | * | |
285 | * NB. To be 100% safe against broken PCI devices, the caller should take | |
286 | * steps to avoid an infinite loop. | |
287 | */ | |
288 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap) | |
289 | { | |
290 | return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap); | |
291 | } | |
292 | EXPORT_SYMBOL_GPL(pci_find_next_ht_capability); | |
293 | ||
294 | /** | |
295 | * pci_find_ht_capability - query a device's Hypertransport capabilities | |
296 | * @dev: PCI device to query | |
297 | * @ht_cap: Hypertransport capability code | |
298 | * | |
299 | * Tell if a device supports a given Hypertransport capability. | |
300 | * Returns an address within the device's PCI configuration space | |
301 | * or 0 in case the device does not support the request capability. | |
302 | * The address points to the PCI capability, of type PCI_CAP_ID_HT, | |
303 | * which has a Hypertransport capability matching @ht_cap. | |
304 | */ | |
305 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap) | |
306 | { | |
307 | int pos; | |
308 | ||
309 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
310 | if (pos) | |
311 | pos = __pci_find_next_ht_cap(dev, pos, ht_cap); | |
312 | ||
313 | return pos; | |
314 | } | |
315 | EXPORT_SYMBOL_GPL(pci_find_ht_capability); | |
316 | ||
1da177e4 LT |
317 | /** |
318 | * pci_find_parent_resource - return resource region of parent bus of given region | |
319 | * @dev: PCI device structure contains resources to be searched | |
320 | * @res: child resource record for which parent is sought | |
321 | * | |
322 | * For given resource region of given device, return the resource | |
323 | * region of parent bus the given region is contained in or where | |
324 | * it should be allocated from. | |
325 | */ | |
326 | struct resource * | |
327 | pci_find_parent_resource(const struct pci_dev *dev, struct resource *res) | |
328 | { | |
329 | const struct pci_bus *bus = dev->bus; | |
330 | int i; | |
331 | struct resource *best = NULL; | |
332 | ||
333 | for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) { | |
334 | struct resource *r = bus->resource[i]; | |
335 | if (!r) | |
336 | continue; | |
337 | if (res->start && !(res->start >= r->start && res->end <= r->end)) | |
338 | continue; /* Not contained */ | |
339 | if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM)) | |
340 | continue; /* Wrong type */ | |
341 | if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) | |
342 | return r; /* Exact match */ | |
343 | if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH)) | |
344 | best = r; /* Approximating prefetchable by non-prefetchable */ | |
345 | } | |
346 | return best; | |
347 | } | |
348 | ||
064b53db JL |
349 | /** |
350 | * pci_restore_bars - restore a devices BAR values (e.g. after wake-up) | |
351 | * @dev: PCI device to have its BARs restored | |
352 | * | |
353 | * Restore the BAR values for a given device, so as to make it | |
354 | * accessible by its driver. | |
355 | */ | |
ad668599 | 356 | static void |
064b53db JL |
357 | pci_restore_bars(struct pci_dev *dev) |
358 | { | |
359 | int i, numres; | |
360 | ||
361 | switch (dev->hdr_type) { | |
362 | case PCI_HEADER_TYPE_NORMAL: | |
363 | numres = 6; | |
364 | break; | |
365 | case PCI_HEADER_TYPE_BRIDGE: | |
366 | numres = 2; | |
367 | break; | |
368 | case PCI_HEADER_TYPE_CARDBUS: | |
369 | numres = 1; | |
370 | break; | |
371 | default: | |
372 | /* Should never get here, but just in case... */ | |
373 | return; | |
374 | } | |
375 | ||
376 | for (i = 0; i < numres; i ++) | |
377 | pci_update_resource(dev, &dev->resource[i], i); | |
378 | } | |
379 | ||
961d9120 RW |
380 | static struct pci_platform_pm_ops *pci_platform_pm; |
381 | ||
382 | int pci_set_platform_pm(struct pci_platform_pm_ops *ops) | |
383 | { | |
eb9d0fe4 RW |
384 | if (!ops->is_manageable || !ops->set_state || !ops->choose_state |
385 | || !ops->sleep_wake || !ops->can_wakeup) | |
961d9120 RW |
386 | return -EINVAL; |
387 | pci_platform_pm = ops; | |
388 | return 0; | |
389 | } | |
390 | ||
391 | static inline bool platform_pci_power_manageable(struct pci_dev *dev) | |
392 | { | |
393 | return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false; | |
394 | } | |
395 | ||
396 | static inline int platform_pci_set_power_state(struct pci_dev *dev, | |
397 | pci_power_t t) | |
398 | { | |
399 | return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS; | |
400 | } | |
401 | ||
402 | static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev) | |
403 | { | |
404 | return pci_platform_pm ? | |
405 | pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR; | |
406 | } | |
8f7020d3 | 407 | |
eb9d0fe4 RW |
408 | static inline bool platform_pci_can_wakeup(struct pci_dev *dev) |
409 | { | |
410 | return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false; | |
411 | } | |
412 | ||
413 | static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable) | |
414 | { | |
415 | return pci_platform_pm ? | |
416 | pci_platform_pm->sleep_wake(dev, enable) : -ENODEV; | |
417 | } | |
418 | ||
1da177e4 | 419 | /** |
44e4e66e RW |
420 | * pci_raw_set_power_state - Use PCI PM registers to set the power state of |
421 | * given PCI device | |
422 | * @dev: PCI device to handle. | |
44e4e66e | 423 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. |
1da177e4 | 424 | * |
44e4e66e RW |
425 | * RETURN VALUE: |
426 | * -EINVAL if the requested state is invalid. | |
427 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
428 | * wrong version, or device doesn't support the requested state. | |
429 | * 0 if device already is in the requested state. | |
430 | * 0 if device's power state has been successfully changed. | |
1da177e4 | 431 | */ |
44e4e66e | 432 | static int |
337001b6 | 433 | pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state) |
1da177e4 | 434 | { |
337001b6 | 435 | u16 pmcsr; |
44e4e66e | 436 | bool need_restore = false; |
1da177e4 | 437 | |
337001b6 | 438 | if (!dev->pm_cap) |
cca03dec AL |
439 | return -EIO; |
440 | ||
44e4e66e RW |
441 | if (state < PCI_D0 || state > PCI_D3hot) |
442 | return -EINVAL; | |
443 | ||
1da177e4 LT |
444 | /* Validate current state: |
445 | * Can enter D0 from any state, but if we can only go deeper | |
446 | * to sleep if we're already in a low power state | |
447 | */ | |
44e4e66e RW |
448 | if (dev->current_state == state) { |
449 | /* we're already there */ | |
450 | return 0; | |
451 | } else if (state != PCI_D0 && dev->current_state <= PCI_D3cold | |
452 | && dev->current_state > state) { | |
80ccba11 BH |
453 | dev_err(&dev->dev, "invalid power transition " |
454 | "(from state %d to %d)\n", dev->current_state, state); | |
1da177e4 | 455 | return -EINVAL; |
44e4e66e | 456 | } |
1da177e4 | 457 | |
1da177e4 | 458 | /* check if this device supports the desired state */ |
337001b6 RW |
459 | if ((state == PCI_D1 && !dev->d1_support) |
460 | || (state == PCI_D2 && !dev->d2_support)) | |
3fe9d19f | 461 | return -EIO; |
1da177e4 | 462 | |
337001b6 | 463 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
064b53db | 464 | |
32a36585 | 465 | /* If we're (effectively) in D3, force entire word to 0. |
1da177e4 LT |
466 | * This doesn't affect PME_Status, disables PME_En, and |
467 | * sets PowerState to 0. | |
468 | */ | |
32a36585 | 469 | switch (dev->current_state) { |
d3535fbb JL |
470 | case PCI_D0: |
471 | case PCI_D1: | |
472 | case PCI_D2: | |
473 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
474 | pmcsr |= state; | |
475 | break; | |
32a36585 JL |
476 | case PCI_UNKNOWN: /* Boot-up */ |
477 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot | |
478 | && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) | |
44e4e66e | 479 | need_restore = true; |
32a36585 | 480 | /* Fall-through: force to D0 */ |
32a36585 | 481 | default: |
d3535fbb | 482 | pmcsr = 0; |
32a36585 | 483 | break; |
1da177e4 LT |
484 | } |
485 | ||
486 | /* enter specified state */ | |
337001b6 | 487 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
1da177e4 LT |
488 | |
489 | /* Mandatory power management transition delays */ | |
490 | /* see PCI PM 1.1 5.6.1 table 18 */ | |
491 | if (state == PCI_D3hot || dev->current_state == PCI_D3hot) | |
ffadcc2f | 492 | msleep(pci_pm_d3_delay); |
1da177e4 LT |
493 | else if (state == PCI_D2 || dev->current_state == PCI_D2) |
494 | udelay(200); | |
1da177e4 | 495 | |
b913100d | 496 | dev->current_state = state; |
064b53db JL |
497 | |
498 | /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT | |
499 | * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning | |
500 | * from D3hot to D0 _may_ perform an internal reset, thereby | |
501 | * going to "D0 Uninitialized" rather than "D0 Initialized". | |
502 | * For example, at least some versions of the 3c905B and the | |
503 | * 3c556B exhibit this behaviour. | |
504 | * | |
505 | * At least some laptop BIOSen (e.g. the Thinkpad T21) leave | |
506 | * devices in a D3hot state at boot. Consequently, we need to | |
507 | * restore at least the BARs so that the device will be | |
508 | * accessible to its driver. | |
509 | */ | |
510 | if (need_restore) | |
511 | pci_restore_bars(dev); | |
512 | ||
7d715a6c SL |
513 | if (dev->bus->self) |
514 | pcie_aspm_pm_state_change(dev->bus->self); | |
515 | ||
1da177e4 LT |
516 | return 0; |
517 | } | |
518 | ||
44e4e66e RW |
519 | /** |
520 | * pci_update_current_state - Read PCI power state of given device from its | |
521 | * PCI PM registers and cache it | |
522 | * @dev: PCI device to handle. | |
44e4e66e | 523 | */ |
337001b6 | 524 | static void pci_update_current_state(struct pci_dev *dev) |
44e4e66e | 525 | { |
337001b6 | 526 | if (dev->pm_cap) { |
44e4e66e RW |
527 | u16 pmcsr; |
528 | ||
337001b6 | 529 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
44e4e66e RW |
530 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); |
531 | } | |
532 | } | |
533 | ||
534 | /** | |
535 | * pci_set_power_state - Set the power state of a PCI device | |
536 | * @dev: PCI device to handle. | |
537 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. | |
538 | * | |
539 | * Transition a device to a new power state, using the platform formware and/or | |
540 | * the device's PCI PM registers. | |
541 | * | |
542 | * RETURN VALUE: | |
543 | * -EINVAL if the requested state is invalid. | |
544 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
545 | * wrong version, or device doesn't support the requested state. | |
546 | * 0 if device already is in the requested state. | |
547 | * 0 if device's power state has been successfully changed. | |
548 | */ | |
549 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state) | |
550 | { | |
337001b6 | 551 | int error; |
44e4e66e RW |
552 | |
553 | /* bound the state we're entering */ | |
554 | if (state > PCI_D3hot) | |
555 | state = PCI_D3hot; | |
556 | else if (state < PCI_D0) | |
557 | state = PCI_D0; | |
558 | else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) | |
559 | /* | |
560 | * If the device or the parent bridge do not support PCI PM, | |
561 | * ignore the request if we're doing anything other than putting | |
562 | * it into D0 (which would only happen on boot). | |
563 | */ | |
564 | return 0; | |
565 | ||
44e4e66e RW |
566 | if (state == PCI_D0 && platform_pci_power_manageable(dev)) { |
567 | /* | |
568 | * Allow the platform to change the state, for example via ACPI | |
569 | * _PR0, _PS0 and some such, but do not trust it. | |
570 | */ | |
571 | int ret = platform_pci_set_power_state(dev, PCI_D0); | |
572 | if (!ret) | |
337001b6 | 573 | pci_update_current_state(dev); |
44e4e66e | 574 | } |
979b1791 AC |
575 | /* This device is quirked not to be put into D3, so |
576 | don't put it in D3 */ | |
577 | if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) | |
578 | return 0; | |
44e4e66e | 579 | |
337001b6 | 580 | error = pci_raw_set_power_state(dev, state); |
44e4e66e RW |
581 | |
582 | if (state > PCI_D0 && platform_pci_power_manageable(dev)) { | |
583 | /* Allow the platform to finalize the transition */ | |
584 | int ret = platform_pci_set_power_state(dev, state); | |
585 | if (!ret) { | |
337001b6 | 586 | pci_update_current_state(dev); |
44e4e66e RW |
587 | error = 0; |
588 | } | |
589 | } | |
590 | ||
591 | return error; | |
592 | } | |
593 | ||
1da177e4 LT |
594 | /** |
595 | * pci_choose_state - Choose the power state of a PCI device | |
596 | * @dev: PCI device to be suspended | |
597 | * @state: target sleep state for the whole system. This is the value | |
598 | * that is passed to suspend() function. | |
599 | * | |
600 | * Returns PCI power state suitable for given device and given system | |
601 | * message. | |
602 | */ | |
603 | ||
604 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) | |
605 | { | |
ab826ca4 | 606 | pci_power_t ret; |
0f64474b | 607 | |
1da177e4 LT |
608 | if (!pci_find_capability(dev, PCI_CAP_ID_PM)) |
609 | return PCI_D0; | |
610 | ||
961d9120 RW |
611 | ret = platform_pci_choose_state(dev); |
612 | if (ret != PCI_POWER_ERROR) | |
613 | return ret; | |
ca078bae PM |
614 | |
615 | switch (state.event) { | |
616 | case PM_EVENT_ON: | |
617 | return PCI_D0; | |
618 | case PM_EVENT_FREEZE: | |
b887d2e6 DB |
619 | case PM_EVENT_PRETHAW: |
620 | /* REVISIT both freeze and pre-thaw "should" use D0 */ | |
ca078bae | 621 | case PM_EVENT_SUSPEND: |
3a2d5b70 | 622 | case PM_EVENT_HIBERNATE: |
ca078bae | 623 | return PCI_D3hot; |
1da177e4 | 624 | default: |
80ccba11 BH |
625 | dev_info(&dev->dev, "unrecognized suspend event %d\n", |
626 | state.event); | |
1da177e4 LT |
627 | BUG(); |
628 | } | |
629 | return PCI_D0; | |
630 | } | |
631 | ||
632 | EXPORT_SYMBOL(pci_choose_state); | |
633 | ||
b56a5a23 MT |
634 | static int pci_save_pcie_state(struct pci_dev *dev) |
635 | { | |
636 | int pos, i = 0; | |
637 | struct pci_cap_saved_state *save_state; | |
638 | u16 *cap; | |
017fc480 | 639 | int found = 0; |
b56a5a23 MT |
640 | |
641 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
642 | if (pos <= 0) | |
643 | return 0; | |
644 | ||
9f35575d EB |
645 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); |
646 | if (!save_state) | |
647 | save_state = kzalloc(sizeof(*save_state) + sizeof(u16) * 4, GFP_KERNEL); | |
017fc480 SL |
648 | else |
649 | found = 1; | |
b56a5a23 | 650 | if (!save_state) { |
80ccba11 | 651 | dev_err(&dev->dev, "out of memory in pci_save_pcie_state\n"); |
b56a5a23 MT |
652 | return -ENOMEM; |
653 | } | |
654 | cap = (u16 *)&save_state->data[0]; | |
655 | ||
656 | pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]); | |
657 | pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]); | |
658 | pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]); | |
659 | pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]); | |
ec0a3a27 | 660 | save_state->cap_nr = PCI_CAP_ID_EXP; |
017fc480 SL |
661 | if (!found) |
662 | pci_add_saved_cap(dev, save_state); | |
b56a5a23 MT |
663 | return 0; |
664 | } | |
665 | ||
666 | static void pci_restore_pcie_state(struct pci_dev *dev) | |
667 | { | |
668 | int i = 0, pos; | |
669 | struct pci_cap_saved_state *save_state; | |
670 | u16 *cap; | |
671 | ||
672 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); | |
673 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
674 | if (!save_state || pos <= 0) | |
675 | return; | |
676 | cap = (u16 *)&save_state->data[0]; | |
677 | ||
678 | pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]); | |
679 | pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]); | |
680 | pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]); | |
681 | pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]); | |
b56a5a23 MT |
682 | } |
683 | ||
cc692a5f SH |
684 | |
685 | static int pci_save_pcix_state(struct pci_dev *dev) | |
686 | { | |
687 | int pos, i = 0; | |
688 | struct pci_cap_saved_state *save_state; | |
689 | u16 *cap; | |
017fc480 | 690 | int found = 0; |
cc692a5f SH |
691 | |
692 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
693 | if (pos <= 0) | |
694 | return 0; | |
695 | ||
f34303de | 696 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); |
9f35575d EB |
697 | if (!save_state) |
698 | save_state = kzalloc(sizeof(*save_state) + sizeof(u16), GFP_KERNEL); | |
017fc480 SL |
699 | else |
700 | found = 1; | |
cc692a5f | 701 | if (!save_state) { |
80ccba11 | 702 | dev_err(&dev->dev, "out of memory in pci_save_pcie_state\n"); |
cc692a5f SH |
703 | return -ENOMEM; |
704 | } | |
705 | cap = (u16 *)&save_state->data[0]; | |
706 | ||
707 | pci_read_config_word(dev, pos + PCI_X_CMD, &cap[i++]); | |
ec0a3a27 | 708 | save_state->cap_nr = PCI_CAP_ID_PCIX; |
017fc480 SL |
709 | if (!found) |
710 | pci_add_saved_cap(dev, save_state); | |
cc692a5f SH |
711 | return 0; |
712 | } | |
713 | ||
714 | static void pci_restore_pcix_state(struct pci_dev *dev) | |
715 | { | |
716 | int i = 0, pos; | |
717 | struct pci_cap_saved_state *save_state; | |
718 | u16 *cap; | |
719 | ||
720 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); | |
721 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
722 | if (!save_state || pos <= 0) | |
723 | return; | |
724 | cap = (u16 *)&save_state->data[0]; | |
725 | ||
726 | pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]); | |
cc692a5f SH |
727 | } |
728 | ||
729 | ||
1da177e4 LT |
730 | /** |
731 | * pci_save_state - save the PCI configuration space of a device before suspending | |
732 | * @dev: - PCI device that we're dealing with | |
1da177e4 LT |
733 | */ |
734 | int | |
735 | pci_save_state(struct pci_dev *dev) | |
736 | { | |
737 | int i; | |
738 | /* XXX: 100% dword access ok here? */ | |
739 | for (i = 0; i < 16; i++) | |
740 | pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]); | |
b56a5a23 MT |
741 | if ((i = pci_save_pcie_state(dev)) != 0) |
742 | return i; | |
cc692a5f SH |
743 | if ((i = pci_save_pcix_state(dev)) != 0) |
744 | return i; | |
1da177e4 LT |
745 | return 0; |
746 | } | |
747 | ||
748 | /** | |
749 | * pci_restore_state - Restore the saved state of a PCI device | |
750 | * @dev: - PCI device that we're dealing with | |
1da177e4 LT |
751 | */ |
752 | int | |
753 | pci_restore_state(struct pci_dev *dev) | |
754 | { | |
755 | int i; | |
b4482a4b | 756 | u32 val; |
1da177e4 | 757 | |
b56a5a23 MT |
758 | /* PCI Express register must be restored first */ |
759 | pci_restore_pcie_state(dev); | |
760 | ||
8b8c8d28 YL |
761 | /* |
762 | * The Base Address register should be programmed before the command | |
763 | * register(s) | |
764 | */ | |
765 | for (i = 15; i >= 0; i--) { | |
04d9c1a1 DJ |
766 | pci_read_config_dword(dev, i * 4, &val); |
767 | if (val != dev->saved_config_space[i]) { | |
80ccba11 BH |
768 | dev_printk(KERN_DEBUG, &dev->dev, "restoring config " |
769 | "space at offset %#x (was %#x, writing %#x)\n", | |
770 | i, val, (int)dev->saved_config_space[i]); | |
04d9c1a1 DJ |
771 | pci_write_config_dword(dev,i * 4, |
772 | dev->saved_config_space[i]); | |
773 | } | |
774 | } | |
cc692a5f | 775 | pci_restore_pcix_state(dev); |
41017f0c | 776 | pci_restore_msi_state(dev); |
8fed4b65 | 777 | |
1da177e4 LT |
778 | return 0; |
779 | } | |
780 | ||
38cc1302 HS |
781 | static int do_pci_enable_device(struct pci_dev *dev, int bars) |
782 | { | |
783 | int err; | |
784 | ||
785 | err = pci_set_power_state(dev, PCI_D0); | |
786 | if (err < 0 && err != -EIO) | |
787 | return err; | |
788 | err = pcibios_enable_device(dev, bars); | |
789 | if (err < 0) | |
790 | return err; | |
791 | pci_fixup_device(pci_fixup_enable, dev); | |
792 | ||
793 | return 0; | |
794 | } | |
795 | ||
796 | /** | |
0b62e13b | 797 | * pci_reenable_device - Resume abandoned device |
38cc1302 HS |
798 | * @dev: PCI device to be resumed |
799 | * | |
800 | * Note this function is a backend of pci_default_resume and is not supposed | |
801 | * to be called by normal code, write proper resume handler and use it instead. | |
802 | */ | |
0b62e13b | 803 | int pci_reenable_device(struct pci_dev *dev) |
38cc1302 HS |
804 | { |
805 | if (atomic_read(&dev->enable_cnt)) | |
806 | return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); | |
807 | return 0; | |
808 | } | |
809 | ||
b718989d BH |
810 | static int __pci_enable_device_flags(struct pci_dev *dev, |
811 | resource_size_t flags) | |
1da177e4 LT |
812 | { |
813 | int err; | |
b718989d | 814 | int i, bars = 0; |
1da177e4 | 815 | |
9fb625c3 HS |
816 | if (atomic_add_return(1, &dev->enable_cnt) > 1) |
817 | return 0; /* already enabled */ | |
818 | ||
b718989d BH |
819 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) |
820 | if (dev->resource[i].flags & flags) | |
821 | bars |= (1 << i); | |
822 | ||
38cc1302 | 823 | err = do_pci_enable_device(dev, bars); |
95a62965 | 824 | if (err < 0) |
38cc1302 | 825 | atomic_dec(&dev->enable_cnt); |
9fb625c3 | 826 | return err; |
1da177e4 LT |
827 | } |
828 | ||
b718989d BH |
829 | /** |
830 | * pci_enable_device_io - Initialize a device for use with IO space | |
831 | * @dev: PCI device to be initialized | |
832 | * | |
833 | * Initialize device before it's used by a driver. Ask low-level code | |
834 | * to enable I/O resources. Wake up the device if it was suspended. | |
835 | * Beware, this function can fail. | |
836 | */ | |
837 | int pci_enable_device_io(struct pci_dev *dev) | |
838 | { | |
839 | return __pci_enable_device_flags(dev, IORESOURCE_IO); | |
840 | } | |
841 | ||
842 | /** | |
843 | * pci_enable_device_mem - Initialize a device for use with Memory space | |
844 | * @dev: PCI device to be initialized | |
845 | * | |
846 | * Initialize device before it's used by a driver. Ask low-level code | |
847 | * to enable Memory resources. Wake up the device if it was suspended. | |
848 | * Beware, this function can fail. | |
849 | */ | |
850 | int pci_enable_device_mem(struct pci_dev *dev) | |
851 | { | |
852 | return __pci_enable_device_flags(dev, IORESOURCE_MEM); | |
853 | } | |
854 | ||
bae94d02 IPG |
855 | /** |
856 | * pci_enable_device - Initialize device before it's used by a driver. | |
857 | * @dev: PCI device to be initialized | |
858 | * | |
859 | * Initialize device before it's used by a driver. Ask low-level code | |
860 | * to enable I/O and memory. Wake up the device if it was suspended. | |
861 | * Beware, this function can fail. | |
862 | * | |
863 | * Note we don't actually enable the device many times if we call | |
864 | * this function repeatedly (we just increment the count). | |
865 | */ | |
866 | int pci_enable_device(struct pci_dev *dev) | |
867 | { | |
b718989d | 868 | return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO); |
bae94d02 IPG |
869 | } |
870 | ||
9ac7849e TH |
871 | /* |
872 | * Managed PCI resources. This manages device on/off, intx/msi/msix | |
873 | * on/off and BAR regions. pci_dev itself records msi/msix status, so | |
874 | * there's no need to track it separately. pci_devres is initialized | |
875 | * when a device is enabled using managed PCI device enable interface. | |
876 | */ | |
877 | struct pci_devres { | |
7f375f32 TH |
878 | unsigned int enabled:1; |
879 | unsigned int pinned:1; | |
9ac7849e TH |
880 | unsigned int orig_intx:1; |
881 | unsigned int restore_intx:1; | |
882 | u32 region_mask; | |
883 | }; | |
884 | ||
885 | static void pcim_release(struct device *gendev, void *res) | |
886 | { | |
887 | struct pci_dev *dev = container_of(gendev, struct pci_dev, dev); | |
888 | struct pci_devres *this = res; | |
889 | int i; | |
890 | ||
891 | if (dev->msi_enabled) | |
892 | pci_disable_msi(dev); | |
893 | if (dev->msix_enabled) | |
894 | pci_disable_msix(dev); | |
895 | ||
896 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) | |
897 | if (this->region_mask & (1 << i)) | |
898 | pci_release_region(dev, i); | |
899 | ||
900 | if (this->restore_intx) | |
901 | pci_intx(dev, this->orig_intx); | |
902 | ||
7f375f32 | 903 | if (this->enabled && !this->pinned) |
9ac7849e TH |
904 | pci_disable_device(dev); |
905 | } | |
906 | ||
907 | static struct pci_devres * get_pci_dr(struct pci_dev *pdev) | |
908 | { | |
909 | struct pci_devres *dr, *new_dr; | |
910 | ||
911 | dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
912 | if (dr) | |
913 | return dr; | |
914 | ||
915 | new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL); | |
916 | if (!new_dr) | |
917 | return NULL; | |
918 | return devres_get(&pdev->dev, new_dr, NULL, NULL); | |
919 | } | |
920 | ||
921 | static struct pci_devres * find_pci_dr(struct pci_dev *pdev) | |
922 | { | |
923 | if (pci_is_managed(pdev)) | |
924 | return devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
925 | return NULL; | |
926 | } | |
927 | ||
928 | /** | |
929 | * pcim_enable_device - Managed pci_enable_device() | |
930 | * @pdev: PCI device to be initialized | |
931 | * | |
932 | * Managed pci_enable_device(). | |
933 | */ | |
934 | int pcim_enable_device(struct pci_dev *pdev) | |
935 | { | |
936 | struct pci_devres *dr; | |
937 | int rc; | |
938 | ||
939 | dr = get_pci_dr(pdev); | |
940 | if (unlikely(!dr)) | |
941 | return -ENOMEM; | |
b95d58ea TH |
942 | if (dr->enabled) |
943 | return 0; | |
9ac7849e TH |
944 | |
945 | rc = pci_enable_device(pdev); | |
946 | if (!rc) { | |
947 | pdev->is_managed = 1; | |
7f375f32 | 948 | dr->enabled = 1; |
9ac7849e TH |
949 | } |
950 | return rc; | |
951 | } | |
952 | ||
953 | /** | |
954 | * pcim_pin_device - Pin managed PCI device | |
955 | * @pdev: PCI device to pin | |
956 | * | |
957 | * Pin managed PCI device @pdev. Pinned device won't be disabled on | |
958 | * driver detach. @pdev must have been enabled with | |
959 | * pcim_enable_device(). | |
960 | */ | |
961 | void pcim_pin_device(struct pci_dev *pdev) | |
962 | { | |
963 | struct pci_devres *dr; | |
964 | ||
965 | dr = find_pci_dr(pdev); | |
7f375f32 | 966 | WARN_ON(!dr || !dr->enabled); |
9ac7849e | 967 | if (dr) |
7f375f32 | 968 | dr->pinned = 1; |
9ac7849e TH |
969 | } |
970 | ||
1da177e4 LT |
971 | /** |
972 | * pcibios_disable_device - disable arch specific PCI resources for device dev | |
973 | * @dev: the PCI device to disable | |
974 | * | |
975 | * Disables architecture specific PCI resources for the device. This | |
976 | * is the default implementation. Architecture implementations can | |
977 | * override this. | |
978 | */ | |
979 | void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {} | |
980 | ||
981 | /** | |
982 | * pci_disable_device - Disable PCI device after use | |
983 | * @dev: PCI device to be disabled | |
984 | * | |
985 | * Signal to the system that the PCI device is not in use by the system | |
986 | * anymore. This only involves disabling PCI bus-mastering, if active. | |
bae94d02 IPG |
987 | * |
988 | * Note we don't actually disable the device until all callers of | |
989 | * pci_device_enable() have called pci_device_disable(). | |
1da177e4 LT |
990 | */ |
991 | void | |
992 | pci_disable_device(struct pci_dev *dev) | |
993 | { | |
9ac7849e | 994 | struct pci_devres *dr; |
1da177e4 | 995 | u16 pci_command; |
99dc804d | 996 | |
9ac7849e TH |
997 | dr = find_pci_dr(dev); |
998 | if (dr) | |
7f375f32 | 999 | dr->enabled = 0; |
9ac7849e | 1000 | |
bae94d02 IPG |
1001 | if (atomic_sub_return(1, &dev->enable_cnt) != 0) |
1002 | return; | |
1003 | ||
1da177e4 LT |
1004 | pci_read_config_word(dev, PCI_COMMAND, &pci_command); |
1005 | if (pci_command & PCI_COMMAND_MASTER) { | |
1006 | pci_command &= ~PCI_COMMAND_MASTER; | |
1007 | pci_write_config_word(dev, PCI_COMMAND, pci_command); | |
1008 | } | |
ceb43744 | 1009 | dev->is_busmaster = 0; |
1da177e4 LT |
1010 | |
1011 | pcibios_disable_device(dev); | |
1012 | } | |
1013 | ||
f7bdd12d BK |
1014 | /** |
1015 | * pcibios_set_pcie_reset_state - set reset state for device dev | |
1016 | * @dev: the PCI-E device reset | |
1017 | * @state: Reset state to enter into | |
1018 | * | |
1019 | * | |
1020 | * Sets the PCI-E reset state for the device. This is the default | |
1021 | * implementation. Architecture implementations can override this. | |
1022 | */ | |
1023 | int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev, | |
1024 | enum pcie_reset_state state) | |
1025 | { | |
1026 | return -EINVAL; | |
1027 | } | |
1028 | ||
1029 | /** | |
1030 | * pci_set_pcie_reset_state - set reset state for device dev | |
1031 | * @dev: the PCI-E device reset | |
1032 | * @state: Reset state to enter into | |
1033 | * | |
1034 | * | |
1035 | * Sets the PCI reset state for the device. | |
1036 | */ | |
1037 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) | |
1038 | { | |
1039 | return pcibios_set_pcie_reset_state(dev, state); | |
1040 | } | |
1041 | ||
eb9d0fe4 RW |
1042 | /** |
1043 | * pci_pme_capable - check the capability of PCI device to generate PME# | |
1044 | * @dev: PCI device to handle. | |
eb9d0fe4 RW |
1045 | * @state: PCI state from which device will issue PME#. |
1046 | */ | |
e5899e1b | 1047 | bool pci_pme_capable(struct pci_dev *dev, pci_power_t state) |
eb9d0fe4 | 1048 | { |
337001b6 | 1049 | if (!dev->pm_cap) |
eb9d0fe4 RW |
1050 | return false; |
1051 | ||
337001b6 | 1052 | return !!(dev->pme_support & (1 << state)); |
eb9d0fe4 RW |
1053 | } |
1054 | ||
1055 | /** | |
1056 | * pci_pme_active - enable or disable PCI device's PME# function | |
1057 | * @dev: PCI device to handle. | |
eb9d0fe4 RW |
1058 | * @enable: 'true' to enable PME# generation; 'false' to disable it. |
1059 | * | |
1060 | * The caller must verify that the device is capable of generating PME# before | |
1061 | * calling this function with @enable equal to 'true'. | |
1062 | */ | |
5a6c9b60 | 1063 | void pci_pme_active(struct pci_dev *dev, bool enable) |
eb9d0fe4 RW |
1064 | { |
1065 | u16 pmcsr; | |
1066 | ||
337001b6 | 1067 | if (!dev->pm_cap) |
eb9d0fe4 RW |
1068 | return; |
1069 | ||
337001b6 | 1070 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
eb9d0fe4 RW |
1071 | /* Clear PME_Status by writing 1 to it and enable PME# */ |
1072 | pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; | |
1073 | if (!enable) | |
1074 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
1075 | ||
337001b6 | 1076 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
eb9d0fe4 RW |
1077 | |
1078 | dev_printk(KERN_INFO, &dev->dev, "PME# %s\n", | |
1079 | enable ? "enabled" : "disabled"); | |
1080 | } | |
1081 | ||
1da177e4 | 1082 | /** |
075c1771 DB |
1083 | * pci_enable_wake - enable PCI device as wakeup event source |
1084 | * @dev: PCI device affected | |
1085 | * @state: PCI state from which device will issue wakeup events | |
1086 | * @enable: True to enable event generation; false to disable | |
1087 | * | |
1088 | * This enables the device as a wakeup event source, or disables it. | |
1089 | * When such events involves platform-specific hooks, those hooks are | |
1090 | * called automatically by this routine. | |
1091 | * | |
1092 | * Devices with legacy power management (no standard PCI PM capabilities) | |
eb9d0fe4 | 1093 | * always require such platform hooks. |
075c1771 | 1094 | * |
eb9d0fe4 RW |
1095 | * RETURN VALUE: |
1096 | * 0 is returned on success | |
1097 | * -EINVAL is returned if device is not supposed to wake up the system | |
1098 | * Error code depending on the platform is returned if both the platform and | |
1099 | * the native mechanism fail to enable the generation of wake-up events | |
1da177e4 LT |
1100 | */ |
1101 | int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable) | |
1102 | { | |
eb9d0fe4 RW |
1103 | int error = 0; |
1104 | bool pme_done = false; | |
075c1771 | 1105 | |
eb9d0fe4 RW |
1106 | if (!device_may_wakeup(&dev->dev)) |
1107 | return -EINVAL; | |
1da177e4 | 1108 | |
eb9d0fe4 RW |
1109 | /* |
1110 | * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don | |
1111 | * Anderson we should be doing PME# wake enable followed by ACPI wake | |
1112 | * enable. To disable wake-up we call the platform first, for symmetry. | |
075c1771 | 1113 | */ |
1da177e4 | 1114 | |
eb9d0fe4 RW |
1115 | if (!enable && platform_pci_can_wakeup(dev)) |
1116 | error = platform_pci_sleep_wake(dev, false); | |
1da177e4 | 1117 | |
337001b6 RW |
1118 | if (!enable || pci_pme_capable(dev, state)) { |
1119 | pci_pme_active(dev, enable); | |
eb9d0fe4 | 1120 | pme_done = true; |
075c1771 | 1121 | } |
1da177e4 | 1122 | |
eb9d0fe4 RW |
1123 | if (enable && platform_pci_can_wakeup(dev)) |
1124 | error = platform_pci_sleep_wake(dev, true); | |
1da177e4 | 1125 | |
eb9d0fe4 RW |
1126 | return pme_done ? 0 : error; |
1127 | } | |
1da177e4 | 1128 | |
0235c4fc RW |
1129 | /** |
1130 | * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold | |
1131 | * @dev: PCI device to prepare | |
1132 | * @enable: True to enable wake-up event generation; false to disable | |
1133 | * | |
1134 | * Many drivers want the device to wake up the system from D3_hot or D3_cold | |
1135 | * and this function allows them to set that up cleanly - pci_enable_wake() | |
1136 | * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI | |
1137 | * ordering constraints. | |
1138 | * | |
1139 | * This function only returns error code if the device is not capable of | |
1140 | * generating PME# from both D3_hot and D3_cold, and the platform is unable to | |
1141 | * enable wake-up power for it. | |
1142 | */ | |
1143 | int pci_wake_from_d3(struct pci_dev *dev, bool enable) | |
1144 | { | |
1145 | return pci_pme_capable(dev, PCI_D3cold) ? | |
1146 | pci_enable_wake(dev, PCI_D3cold, enable) : | |
1147 | pci_enable_wake(dev, PCI_D3hot, enable); | |
1148 | } | |
1149 | ||
404cc2d8 | 1150 | /** |
37139074 JB |
1151 | * pci_target_state - find an appropriate low power state for a given PCI dev |
1152 | * @dev: PCI device | |
1153 | * | |
1154 | * Use underlying platform code to find a supported low power state for @dev. | |
1155 | * If the platform can't manage @dev, return the deepest state from which it | |
1156 | * can generate wake events, based on any available PME info. | |
404cc2d8 | 1157 | */ |
e5899e1b | 1158 | pci_power_t pci_target_state(struct pci_dev *dev) |
404cc2d8 RW |
1159 | { |
1160 | pci_power_t target_state = PCI_D3hot; | |
404cc2d8 RW |
1161 | |
1162 | if (platform_pci_power_manageable(dev)) { | |
1163 | /* | |
1164 | * Call the platform to choose the target state of the device | |
1165 | * and enable wake-up from this state if supported. | |
1166 | */ | |
1167 | pci_power_t state = platform_pci_choose_state(dev); | |
1168 | ||
1169 | switch (state) { | |
1170 | case PCI_POWER_ERROR: | |
1171 | case PCI_UNKNOWN: | |
1172 | break; | |
1173 | case PCI_D1: | |
1174 | case PCI_D2: | |
1175 | if (pci_no_d1d2(dev)) | |
1176 | break; | |
1177 | default: | |
1178 | target_state = state; | |
404cc2d8 RW |
1179 | } |
1180 | } else if (device_may_wakeup(&dev->dev)) { | |
1181 | /* | |
1182 | * Find the deepest state from which the device can generate | |
1183 | * wake-up events, make it the target state and enable device | |
1184 | * to generate PME#. | |
1185 | */ | |
337001b6 | 1186 | if (!dev->pm_cap) |
e5899e1b | 1187 | return PCI_POWER_ERROR; |
404cc2d8 | 1188 | |
337001b6 RW |
1189 | if (dev->pme_support) { |
1190 | while (target_state | |
1191 | && !(dev->pme_support & (1 << target_state))) | |
1192 | target_state--; | |
404cc2d8 RW |
1193 | } |
1194 | } | |
1195 | ||
e5899e1b RW |
1196 | return target_state; |
1197 | } | |
1198 | ||
1199 | /** | |
1200 | * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state | |
1201 | * @dev: Device to handle. | |
1202 | * | |
1203 | * Choose the power state appropriate for the device depending on whether | |
1204 | * it can wake up the system and/or is power manageable by the platform | |
1205 | * (PCI_D3hot is the default) and put the device into that state. | |
1206 | */ | |
1207 | int pci_prepare_to_sleep(struct pci_dev *dev) | |
1208 | { | |
1209 | pci_power_t target_state = pci_target_state(dev); | |
1210 | int error; | |
1211 | ||
1212 | if (target_state == PCI_POWER_ERROR) | |
1213 | return -EIO; | |
1214 | ||
c157dfa3 RW |
1215 | pci_enable_wake(dev, target_state, true); |
1216 | ||
404cc2d8 RW |
1217 | error = pci_set_power_state(dev, target_state); |
1218 | ||
1219 | if (error) | |
1220 | pci_enable_wake(dev, target_state, false); | |
1221 | ||
1222 | return error; | |
1223 | } | |
1224 | ||
1225 | /** | |
443bd1c4 | 1226 | * pci_back_from_sleep - turn PCI device on during system-wide transition into working state |
404cc2d8 RW |
1227 | * @dev: Device to handle. |
1228 | * | |
1229 | * Disable device's sytem wake-up capability and put it into D0. | |
1230 | */ | |
1231 | int pci_back_from_sleep(struct pci_dev *dev) | |
1232 | { | |
1233 | pci_enable_wake(dev, PCI_D0, false); | |
1234 | return pci_set_power_state(dev, PCI_D0); | |
1235 | } | |
1236 | ||
eb9d0fe4 RW |
1237 | /** |
1238 | * pci_pm_init - Initialize PM functions of given PCI device | |
1239 | * @dev: PCI device to handle. | |
1240 | */ | |
1241 | void pci_pm_init(struct pci_dev *dev) | |
1242 | { | |
1243 | int pm; | |
1244 | u16 pmc; | |
1da177e4 | 1245 | |
337001b6 RW |
1246 | dev->pm_cap = 0; |
1247 | ||
eb9d0fe4 RW |
1248 | /* find PCI PM capability in list */ |
1249 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
1250 | if (!pm) | |
1251 | return; | |
1252 | /* Check device's ability to generate PME# */ | |
1253 | pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc); | |
075c1771 | 1254 | |
eb9d0fe4 RW |
1255 | if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { |
1256 | dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n", | |
1257 | pmc & PCI_PM_CAP_VER_MASK); | |
1258 | return; | |
1259 | } | |
1260 | ||
337001b6 RW |
1261 | dev->pm_cap = pm; |
1262 | ||
1263 | dev->d1_support = false; | |
1264 | dev->d2_support = false; | |
1265 | if (!pci_no_d1d2(dev)) { | |
c9ed77ee | 1266 | if (pmc & PCI_PM_CAP_D1) |
337001b6 | 1267 | dev->d1_support = true; |
c9ed77ee | 1268 | if (pmc & PCI_PM_CAP_D2) |
337001b6 | 1269 | dev->d2_support = true; |
c9ed77ee BH |
1270 | |
1271 | if (dev->d1_support || dev->d2_support) | |
1272 | dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n", | |
1273 | dev->d1_support ? " D1": "", | |
1274 | dev->d2_support ? " D2": ""); | |
337001b6 RW |
1275 | } |
1276 | ||
1277 | pmc &= PCI_PM_CAP_PME_MASK; | |
1278 | if (pmc) { | |
c9ed77ee BH |
1279 | dev_info(&dev->dev, "PME# supported from%s%s%s%s%s\n", |
1280 | (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "", | |
1281 | (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "", | |
1282 | (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "", | |
1283 | (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "", | |
1284 | (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : ""); | |
337001b6 | 1285 | dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT; |
eb9d0fe4 RW |
1286 | /* |
1287 | * Make device's PM flags reflect the wake-up capability, but | |
1288 | * let the user space enable it to wake up the system as needed. | |
1289 | */ | |
1290 | device_set_wakeup_capable(&dev->dev, true); | |
1291 | device_set_wakeup_enable(&dev->dev, false); | |
1292 | /* Disable the PME# generation functionality */ | |
337001b6 RW |
1293 | pci_pme_active(dev, false); |
1294 | } else { | |
1295 | dev->pme_support = 0; | |
eb9d0fe4 | 1296 | } |
1da177e4 LT |
1297 | } |
1298 | ||
1299 | int | |
1300 | pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) | |
1301 | { | |
1302 | u8 pin; | |
1303 | ||
514d207d | 1304 | pin = dev->pin; |
1da177e4 LT |
1305 | if (!pin) |
1306 | return -1; | |
1307 | pin--; | |
1308 | while (dev->bus->self) { | |
1309 | pin = (pin + PCI_SLOT(dev->devfn)) % 4; | |
1310 | dev = dev->bus->self; | |
1311 | } | |
1312 | *bridge = dev; | |
1313 | return pin; | |
1314 | } | |
1315 | ||
1316 | /** | |
1317 | * pci_release_region - Release a PCI bar | |
1318 | * @pdev: PCI device whose resources were previously reserved by pci_request_region | |
1319 | * @bar: BAR to release | |
1320 | * | |
1321 | * Releases the PCI I/O and memory resources previously reserved by a | |
1322 | * successful call to pci_request_region. Call this function only | |
1323 | * after all use of the PCI regions has ceased. | |
1324 | */ | |
1325 | void pci_release_region(struct pci_dev *pdev, int bar) | |
1326 | { | |
9ac7849e TH |
1327 | struct pci_devres *dr; |
1328 | ||
1da177e4 LT |
1329 | if (pci_resource_len(pdev, bar) == 0) |
1330 | return; | |
1331 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) | |
1332 | release_region(pci_resource_start(pdev, bar), | |
1333 | pci_resource_len(pdev, bar)); | |
1334 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) | |
1335 | release_mem_region(pci_resource_start(pdev, bar), | |
1336 | pci_resource_len(pdev, bar)); | |
9ac7849e TH |
1337 | |
1338 | dr = find_pci_dr(pdev); | |
1339 | if (dr) | |
1340 | dr->region_mask &= ~(1 << bar); | |
1da177e4 LT |
1341 | } |
1342 | ||
1343 | /** | |
1344 | * pci_request_region - Reserved PCI I/O and memory resource | |
1345 | * @pdev: PCI device whose resources are to be reserved | |
1346 | * @bar: BAR to be reserved | |
1347 | * @res_name: Name to be associated with resource. | |
1348 | * | |
1349 | * Mark the PCI region associated with PCI device @pdev BR @bar as | |
1350 | * being reserved by owner @res_name. Do not access any | |
1351 | * address inside the PCI regions unless this call returns | |
1352 | * successfully. | |
1353 | * | |
1354 | * Returns 0 on success, or %EBUSY on error. A warning | |
1355 | * message is also printed on failure. | |
1356 | */ | |
3c990e92 | 1357 | int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) |
1da177e4 | 1358 | { |
9ac7849e TH |
1359 | struct pci_devres *dr; |
1360 | ||
1da177e4 LT |
1361 | if (pci_resource_len(pdev, bar) == 0) |
1362 | return 0; | |
1363 | ||
1364 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { | |
1365 | if (!request_region(pci_resource_start(pdev, bar), | |
1366 | pci_resource_len(pdev, bar), res_name)) | |
1367 | goto err_out; | |
1368 | } | |
1369 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { | |
1370 | if (!request_mem_region(pci_resource_start(pdev, bar), | |
1371 | pci_resource_len(pdev, bar), res_name)) | |
1372 | goto err_out; | |
1373 | } | |
9ac7849e TH |
1374 | |
1375 | dr = find_pci_dr(pdev); | |
1376 | if (dr) | |
1377 | dr->region_mask |= 1 << bar; | |
1378 | ||
1da177e4 LT |
1379 | return 0; |
1380 | ||
1381 | err_out: | |
096e6f67 | 1382 | dev_warn(&pdev->dev, "BAR %d: can't reserve %s region %pR\n", |
e4ec7a00 JB |
1383 | bar, |
1384 | pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem", | |
096e6f67 | 1385 | &pdev->resource[bar]); |
1da177e4 LT |
1386 | return -EBUSY; |
1387 | } | |
1388 | ||
c87deff7 HS |
1389 | /** |
1390 | * pci_release_selected_regions - Release selected PCI I/O and memory resources | |
1391 | * @pdev: PCI device whose resources were previously reserved | |
1392 | * @bars: Bitmask of BARs to be released | |
1393 | * | |
1394 | * Release selected PCI I/O and memory resources previously reserved. | |
1395 | * Call this function only after all use of the PCI regions has ceased. | |
1396 | */ | |
1397 | void pci_release_selected_regions(struct pci_dev *pdev, int bars) | |
1398 | { | |
1399 | int i; | |
1400 | ||
1401 | for (i = 0; i < 6; i++) | |
1402 | if (bars & (1 << i)) | |
1403 | pci_release_region(pdev, i); | |
1404 | } | |
1405 | ||
1406 | /** | |
1407 | * pci_request_selected_regions - Reserve selected PCI I/O and memory resources | |
1408 | * @pdev: PCI device whose resources are to be reserved | |
1409 | * @bars: Bitmask of BARs to be requested | |
1410 | * @res_name: Name to be associated with resource | |
1411 | */ | |
1412 | int pci_request_selected_regions(struct pci_dev *pdev, int bars, | |
1413 | const char *res_name) | |
1414 | { | |
1415 | int i; | |
1416 | ||
1417 | for (i = 0; i < 6; i++) | |
1418 | if (bars & (1 << i)) | |
1419 | if(pci_request_region(pdev, i, res_name)) | |
1420 | goto err_out; | |
1421 | return 0; | |
1422 | ||
1423 | err_out: | |
1424 | while(--i >= 0) | |
1425 | if (bars & (1 << i)) | |
1426 | pci_release_region(pdev, i); | |
1427 | ||
1428 | return -EBUSY; | |
1429 | } | |
1da177e4 LT |
1430 | |
1431 | /** | |
1432 | * pci_release_regions - Release reserved PCI I/O and memory resources | |
1433 | * @pdev: PCI device whose resources were previously reserved by pci_request_regions | |
1434 | * | |
1435 | * Releases all PCI I/O and memory resources previously reserved by a | |
1436 | * successful call to pci_request_regions. Call this function only | |
1437 | * after all use of the PCI regions has ceased. | |
1438 | */ | |
1439 | ||
1440 | void pci_release_regions(struct pci_dev *pdev) | |
1441 | { | |
c87deff7 | 1442 | pci_release_selected_regions(pdev, (1 << 6) - 1); |
1da177e4 LT |
1443 | } |
1444 | ||
1445 | /** | |
1446 | * pci_request_regions - Reserved PCI I/O and memory resources | |
1447 | * @pdev: PCI device whose resources are to be reserved | |
1448 | * @res_name: Name to be associated with resource. | |
1449 | * | |
1450 | * Mark all PCI regions associated with PCI device @pdev as | |
1451 | * being reserved by owner @res_name. Do not access any | |
1452 | * address inside the PCI regions unless this call returns | |
1453 | * successfully. | |
1454 | * | |
1455 | * Returns 0 on success, or %EBUSY on error. A warning | |
1456 | * message is also printed on failure. | |
1457 | */ | |
3c990e92 | 1458 | int pci_request_regions(struct pci_dev *pdev, const char *res_name) |
1da177e4 | 1459 | { |
c87deff7 | 1460 | return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name); |
1da177e4 LT |
1461 | } |
1462 | ||
1463 | /** | |
1464 | * pci_set_master - enables bus-mastering for device dev | |
1465 | * @dev: the PCI device to enable | |
1466 | * | |
1467 | * Enables bus-mastering on the device and calls pcibios_set_master() | |
1468 | * to do the needed arch specific settings. | |
1469 | */ | |
1470 | void | |
1471 | pci_set_master(struct pci_dev *dev) | |
1472 | { | |
1473 | u16 cmd; | |
1474 | ||
1475 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1476 | if (! (cmd & PCI_COMMAND_MASTER)) { | |
80ccba11 | 1477 | dev_dbg(&dev->dev, "enabling bus mastering\n"); |
1da177e4 LT |
1478 | cmd |= PCI_COMMAND_MASTER; |
1479 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1480 | } | |
1481 | dev->is_busmaster = 1; | |
1482 | pcibios_set_master(dev); | |
1483 | } | |
1484 | ||
edb2d97e MW |
1485 | #ifdef PCI_DISABLE_MWI |
1486 | int pci_set_mwi(struct pci_dev *dev) | |
1487 | { | |
1488 | return 0; | |
1489 | } | |
1490 | ||
694625c0 RD |
1491 | int pci_try_set_mwi(struct pci_dev *dev) |
1492 | { | |
1493 | return 0; | |
1494 | } | |
1495 | ||
edb2d97e MW |
1496 | void pci_clear_mwi(struct pci_dev *dev) |
1497 | { | |
1498 | } | |
1499 | ||
1500 | #else | |
ebf5a248 MW |
1501 | |
1502 | #ifndef PCI_CACHE_LINE_BYTES | |
1503 | #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES | |
1504 | #endif | |
1505 | ||
1da177e4 | 1506 | /* This can be overridden by arch code. */ |
ebf5a248 MW |
1507 | /* Don't forget this is measured in 32-bit words, not bytes */ |
1508 | u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4; | |
1da177e4 LT |
1509 | |
1510 | /** | |
edb2d97e MW |
1511 | * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed |
1512 | * @dev: the PCI device for which MWI is to be enabled | |
1da177e4 | 1513 | * |
edb2d97e MW |
1514 | * Helper function for pci_set_mwi. |
1515 | * Originally copied from drivers/net/acenic.c. | |
1da177e4 LT |
1516 | * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. |
1517 | * | |
1518 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
1519 | */ | |
1520 | static int | |
edb2d97e | 1521 | pci_set_cacheline_size(struct pci_dev *dev) |
1da177e4 LT |
1522 | { |
1523 | u8 cacheline_size; | |
1524 | ||
1525 | if (!pci_cache_line_size) | |
1526 | return -EINVAL; /* The system doesn't support MWI. */ | |
1527 | ||
1528 | /* Validate current setting: the PCI_CACHE_LINE_SIZE must be | |
1529 | equal to or multiple of the right value. */ | |
1530 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
1531 | if (cacheline_size >= pci_cache_line_size && | |
1532 | (cacheline_size % pci_cache_line_size) == 0) | |
1533 | return 0; | |
1534 | ||
1535 | /* Write the correct value. */ | |
1536 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); | |
1537 | /* Read it back. */ | |
1538 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
1539 | if (cacheline_size == pci_cache_line_size) | |
1540 | return 0; | |
1541 | ||
80ccba11 BH |
1542 | dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not " |
1543 | "supported\n", pci_cache_line_size << 2); | |
1da177e4 LT |
1544 | |
1545 | return -EINVAL; | |
1546 | } | |
1da177e4 LT |
1547 | |
1548 | /** | |
1549 | * pci_set_mwi - enables memory-write-invalidate PCI transaction | |
1550 | * @dev: the PCI device for which MWI is enabled | |
1551 | * | |
694625c0 | 1552 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. |
1da177e4 LT |
1553 | * |
1554 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
1555 | */ | |
1556 | int | |
1557 | pci_set_mwi(struct pci_dev *dev) | |
1558 | { | |
1559 | int rc; | |
1560 | u16 cmd; | |
1561 | ||
edb2d97e | 1562 | rc = pci_set_cacheline_size(dev); |
1da177e4 LT |
1563 | if (rc) |
1564 | return rc; | |
1565 | ||
1566 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1567 | if (! (cmd & PCI_COMMAND_INVALIDATE)) { | |
80ccba11 | 1568 | dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n"); |
1da177e4 LT |
1569 | cmd |= PCI_COMMAND_INVALIDATE; |
1570 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1571 | } | |
1572 | ||
1573 | return 0; | |
1574 | } | |
1575 | ||
694625c0 RD |
1576 | /** |
1577 | * pci_try_set_mwi - enables memory-write-invalidate PCI transaction | |
1578 | * @dev: the PCI device for which MWI is enabled | |
1579 | * | |
1580 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. | |
1581 | * Callers are not required to check the return value. | |
1582 | * | |
1583 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
1584 | */ | |
1585 | int pci_try_set_mwi(struct pci_dev *dev) | |
1586 | { | |
1587 | int rc = pci_set_mwi(dev); | |
1588 | return rc; | |
1589 | } | |
1590 | ||
1da177e4 LT |
1591 | /** |
1592 | * pci_clear_mwi - disables Memory-Write-Invalidate for device dev | |
1593 | * @dev: the PCI device to disable | |
1594 | * | |
1595 | * Disables PCI Memory-Write-Invalidate transaction on the device | |
1596 | */ | |
1597 | void | |
1598 | pci_clear_mwi(struct pci_dev *dev) | |
1599 | { | |
1600 | u16 cmd; | |
1601 | ||
1602 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1603 | if (cmd & PCI_COMMAND_INVALIDATE) { | |
1604 | cmd &= ~PCI_COMMAND_INVALIDATE; | |
1605 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1606 | } | |
1607 | } | |
edb2d97e | 1608 | #endif /* ! PCI_DISABLE_MWI */ |
1da177e4 | 1609 | |
a04ce0ff BR |
1610 | /** |
1611 | * pci_intx - enables/disables PCI INTx for device dev | |
8f7020d3 RD |
1612 | * @pdev: the PCI device to operate on |
1613 | * @enable: boolean: whether to enable or disable PCI INTx | |
a04ce0ff BR |
1614 | * |
1615 | * Enables/disables PCI INTx for device dev | |
1616 | */ | |
1617 | void | |
1618 | pci_intx(struct pci_dev *pdev, int enable) | |
1619 | { | |
1620 | u16 pci_command, new; | |
1621 | ||
1622 | pci_read_config_word(pdev, PCI_COMMAND, &pci_command); | |
1623 | ||
1624 | if (enable) { | |
1625 | new = pci_command & ~PCI_COMMAND_INTX_DISABLE; | |
1626 | } else { | |
1627 | new = pci_command | PCI_COMMAND_INTX_DISABLE; | |
1628 | } | |
1629 | ||
1630 | if (new != pci_command) { | |
9ac7849e TH |
1631 | struct pci_devres *dr; |
1632 | ||
2fd9d74b | 1633 | pci_write_config_word(pdev, PCI_COMMAND, new); |
9ac7849e TH |
1634 | |
1635 | dr = find_pci_dr(pdev); | |
1636 | if (dr && !dr->restore_intx) { | |
1637 | dr->restore_intx = 1; | |
1638 | dr->orig_intx = !enable; | |
1639 | } | |
a04ce0ff BR |
1640 | } |
1641 | } | |
1642 | ||
f5f2b131 EB |
1643 | /** |
1644 | * pci_msi_off - disables any msi or msix capabilities | |
8d7d86e9 | 1645 | * @dev: the PCI device to operate on |
f5f2b131 EB |
1646 | * |
1647 | * If you want to use msi see pci_enable_msi and friends. | |
1648 | * This is a lower level primitive that allows us to disable | |
1649 | * msi operation at the device level. | |
1650 | */ | |
1651 | void pci_msi_off(struct pci_dev *dev) | |
1652 | { | |
1653 | int pos; | |
1654 | u16 control; | |
1655 | ||
1656 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
1657 | if (pos) { | |
1658 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
1659 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
1660 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
1661 | } | |
1662 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
1663 | if (pos) { | |
1664 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
1665 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
1666 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
1667 | } | |
1668 | } | |
1669 | ||
1da177e4 LT |
1670 | #ifndef HAVE_ARCH_PCI_SET_DMA_MASK |
1671 | /* | |
1672 | * These can be overridden by arch-specific implementations | |
1673 | */ | |
1674 | int | |
1675 | pci_set_dma_mask(struct pci_dev *dev, u64 mask) | |
1676 | { | |
1677 | if (!pci_dma_supported(dev, mask)) | |
1678 | return -EIO; | |
1679 | ||
1680 | dev->dma_mask = mask; | |
1681 | ||
1682 | return 0; | |
1683 | } | |
1684 | ||
1da177e4 LT |
1685 | int |
1686 | pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) | |
1687 | { | |
1688 | if (!pci_dma_supported(dev, mask)) | |
1689 | return -EIO; | |
1690 | ||
1691 | dev->dev.coherent_dma_mask = mask; | |
1692 | ||
1693 | return 0; | |
1694 | } | |
1695 | #endif | |
c87deff7 | 1696 | |
4d57cdfa FT |
1697 | #ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE |
1698 | int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size) | |
1699 | { | |
1700 | return dma_set_max_seg_size(&dev->dev, size); | |
1701 | } | |
1702 | EXPORT_SYMBOL(pci_set_dma_max_seg_size); | |
1703 | #endif | |
1704 | ||
59fc67de FT |
1705 | #ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY |
1706 | int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask) | |
1707 | { | |
1708 | return dma_set_seg_boundary(&dev->dev, mask); | |
1709 | } | |
1710 | EXPORT_SYMBOL(pci_set_dma_seg_boundary); | |
1711 | #endif | |
1712 | ||
d556ad4b PO |
1713 | /** |
1714 | * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count | |
1715 | * @dev: PCI device to query | |
1716 | * | |
1717 | * Returns mmrbc: maximum designed memory read count in bytes | |
1718 | * or appropriate error value. | |
1719 | */ | |
1720 | int pcix_get_max_mmrbc(struct pci_dev *dev) | |
1721 | { | |
b7b095c1 | 1722 | int err, cap; |
d556ad4b PO |
1723 | u32 stat; |
1724 | ||
1725 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
1726 | if (!cap) | |
1727 | return -EINVAL; | |
1728 | ||
1729 | err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat); | |
1730 | if (err) | |
1731 | return -EINVAL; | |
1732 | ||
b7b095c1 | 1733 | return (stat & PCI_X_STATUS_MAX_READ) >> 12; |
d556ad4b PO |
1734 | } |
1735 | EXPORT_SYMBOL(pcix_get_max_mmrbc); | |
1736 | ||
1737 | /** | |
1738 | * pcix_get_mmrbc - get PCI-X maximum memory read byte count | |
1739 | * @dev: PCI device to query | |
1740 | * | |
1741 | * Returns mmrbc: maximum memory read count in bytes | |
1742 | * or appropriate error value. | |
1743 | */ | |
1744 | int pcix_get_mmrbc(struct pci_dev *dev) | |
1745 | { | |
1746 | int ret, cap; | |
1747 | u32 cmd; | |
1748 | ||
1749 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
1750 | if (!cap) | |
1751 | return -EINVAL; | |
1752 | ||
1753 | ret = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd); | |
1754 | if (!ret) | |
1755 | ret = 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2); | |
1756 | ||
1757 | return ret; | |
1758 | } | |
1759 | EXPORT_SYMBOL(pcix_get_mmrbc); | |
1760 | ||
1761 | /** | |
1762 | * pcix_set_mmrbc - set PCI-X maximum memory read byte count | |
1763 | * @dev: PCI device to query | |
1764 | * @mmrbc: maximum memory read count in bytes | |
1765 | * valid values are 512, 1024, 2048, 4096 | |
1766 | * | |
1767 | * If possible sets maximum memory read byte count, some bridges have erratas | |
1768 | * that prevent this. | |
1769 | */ | |
1770 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) | |
1771 | { | |
1772 | int cap, err = -EINVAL; | |
1773 | u32 stat, cmd, v, o; | |
1774 | ||
229f5afd | 1775 | if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc)) |
d556ad4b PO |
1776 | goto out; |
1777 | ||
1778 | v = ffs(mmrbc) - 10; | |
1779 | ||
1780 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
1781 | if (!cap) | |
1782 | goto out; | |
1783 | ||
1784 | err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat); | |
1785 | if (err) | |
1786 | goto out; | |
1787 | ||
1788 | if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21) | |
1789 | return -E2BIG; | |
1790 | ||
1791 | err = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd); | |
1792 | if (err) | |
1793 | goto out; | |
1794 | ||
1795 | o = (cmd & PCI_X_CMD_MAX_READ) >> 2; | |
1796 | if (o != v) { | |
1797 | if (v > o && dev->bus && | |
1798 | (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) | |
1799 | return -EIO; | |
1800 | ||
1801 | cmd &= ~PCI_X_CMD_MAX_READ; | |
1802 | cmd |= v << 2; | |
1803 | err = pci_write_config_dword(dev, cap + PCI_X_CMD, cmd); | |
1804 | } | |
1805 | out: | |
1806 | return err; | |
1807 | } | |
1808 | EXPORT_SYMBOL(pcix_set_mmrbc); | |
1809 | ||
1810 | /** | |
1811 | * pcie_get_readrq - get PCI Express read request size | |
1812 | * @dev: PCI device to query | |
1813 | * | |
1814 | * Returns maximum memory read request in bytes | |
1815 | * or appropriate error value. | |
1816 | */ | |
1817 | int pcie_get_readrq(struct pci_dev *dev) | |
1818 | { | |
1819 | int ret, cap; | |
1820 | u16 ctl; | |
1821 | ||
1822 | cap = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
1823 | if (!cap) | |
1824 | return -EINVAL; | |
1825 | ||
1826 | ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); | |
1827 | if (!ret) | |
1828 | ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12); | |
1829 | ||
1830 | return ret; | |
1831 | } | |
1832 | EXPORT_SYMBOL(pcie_get_readrq); | |
1833 | ||
1834 | /** | |
1835 | * pcie_set_readrq - set PCI Express maximum memory read request | |
1836 | * @dev: PCI device to query | |
42e61f4a | 1837 | * @rq: maximum memory read count in bytes |
d556ad4b PO |
1838 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
1839 | * | |
1840 | * If possible sets maximum read byte count | |
1841 | */ | |
1842 | int pcie_set_readrq(struct pci_dev *dev, int rq) | |
1843 | { | |
1844 | int cap, err = -EINVAL; | |
1845 | u16 ctl, v; | |
1846 | ||
229f5afd | 1847 | if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) |
d556ad4b PO |
1848 | goto out; |
1849 | ||
1850 | v = (ffs(rq) - 8) << 12; | |
1851 | ||
1852 | cap = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
1853 | if (!cap) | |
1854 | goto out; | |
1855 | ||
1856 | err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); | |
1857 | if (err) | |
1858 | goto out; | |
1859 | ||
1860 | if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) { | |
1861 | ctl &= ~PCI_EXP_DEVCTL_READRQ; | |
1862 | ctl |= v; | |
1863 | err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl); | |
1864 | } | |
1865 | ||
1866 | out: | |
1867 | return err; | |
1868 | } | |
1869 | EXPORT_SYMBOL(pcie_set_readrq); | |
1870 | ||
c87deff7 HS |
1871 | /** |
1872 | * pci_select_bars - Make BAR mask from the type of resource | |
f95d882d | 1873 | * @dev: the PCI device for which BAR mask is made |
c87deff7 HS |
1874 | * @flags: resource type mask to be selected |
1875 | * | |
1876 | * This helper routine makes bar mask from the type of resource. | |
1877 | */ | |
1878 | int pci_select_bars(struct pci_dev *dev, unsigned long flags) | |
1879 | { | |
1880 | int i, bars = 0; | |
1881 | for (i = 0; i < PCI_NUM_RESOURCES; i++) | |
1882 | if (pci_resource_flags(dev, i) & flags) | |
1883 | bars |= (1 << i); | |
1884 | return bars; | |
1885 | } | |
1886 | ||
32a2eea7 JG |
1887 | static void __devinit pci_no_domains(void) |
1888 | { | |
1889 | #ifdef CONFIG_PCI_DOMAINS | |
1890 | pci_domains_supported = 0; | |
1891 | #endif | |
1892 | } | |
1893 | ||
1da177e4 LT |
1894 | static int __devinit pci_init(void) |
1895 | { | |
1896 | struct pci_dev *dev = NULL; | |
1897 | ||
1898 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
1899 | pci_fixup_device(pci_fixup_final, dev); | |
1900 | } | |
1901 | return 0; | |
1902 | } | |
1903 | ||
1904 | static int __devinit pci_setup(char *str) | |
1905 | { | |
1906 | while (str) { | |
1907 | char *k = strchr(str, ','); | |
1908 | if (k) | |
1909 | *k++ = 0; | |
1910 | if (*str && (str = pcibios_setup(str)) && *str) { | |
309e57df MW |
1911 | if (!strcmp(str, "nomsi")) { |
1912 | pci_no_msi(); | |
7f785763 RD |
1913 | } else if (!strcmp(str, "noaer")) { |
1914 | pci_no_aer(); | |
32a2eea7 JG |
1915 | } else if (!strcmp(str, "nodomains")) { |
1916 | pci_no_domains(); | |
4516a618 AN |
1917 | } else if (!strncmp(str, "cbiosize=", 9)) { |
1918 | pci_cardbus_io_size = memparse(str + 9, &str); | |
1919 | } else if (!strncmp(str, "cbmemsize=", 10)) { | |
1920 | pci_cardbus_mem_size = memparse(str + 10, &str); | |
309e57df MW |
1921 | } else { |
1922 | printk(KERN_ERR "PCI: Unknown option `%s'\n", | |
1923 | str); | |
1924 | } | |
1da177e4 LT |
1925 | } |
1926 | str = k; | |
1927 | } | |
0637a70a | 1928 | return 0; |
1da177e4 | 1929 | } |
0637a70a | 1930 | early_param("pci", pci_setup); |
1da177e4 LT |
1931 | |
1932 | device_initcall(pci_init); | |
1da177e4 | 1933 | |
0b62e13b | 1934 | EXPORT_SYMBOL(pci_reenable_device); |
b718989d BH |
1935 | EXPORT_SYMBOL(pci_enable_device_io); |
1936 | EXPORT_SYMBOL(pci_enable_device_mem); | |
1da177e4 | 1937 | EXPORT_SYMBOL(pci_enable_device); |
9ac7849e TH |
1938 | EXPORT_SYMBOL(pcim_enable_device); |
1939 | EXPORT_SYMBOL(pcim_pin_device); | |
1da177e4 | 1940 | EXPORT_SYMBOL(pci_disable_device); |
1da177e4 LT |
1941 | EXPORT_SYMBOL(pci_find_capability); |
1942 | EXPORT_SYMBOL(pci_bus_find_capability); | |
1943 | EXPORT_SYMBOL(pci_release_regions); | |
1944 | EXPORT_SYMBOL(pci_request_regions); | |
1945 | EXPORT_SYMBOL(pci_release_region); | |
1946 | EXPORT_SYMBOL(pci_request_region); | |
c87deff7 HS |
1947 | EXPORT_SYMBOL(pci_release_selected_regions); |
1948 | EXPORT_SYMBOL(pci_request_selected_regions); | |
1da177e4 LT |
1949 | EXPORT_SYMBOL(pci_set_master); |
1950 | EXPORT_SYMBOL(pci_set_mwi); | |
694625c0 | 1951 | EXPORT_SYMBOL(pci_try_set_mwi); |
1da177e4 | 1952 | EXPORT_SYMBOL(pci_clear_mwi); |
a04ce0ff | 1953 | EXPORT_SYMBOL_GPL(pci_intx); |
1da177e4 | 1954 | EXPORT_SYMBOL(pci_set_dma_mask); |
1da177e4 LT |
1955 | EXPORT_SYMBOL(pci_set_consistent_dma_mask); |
1956 | EXPORT_SYMBOL(pci_assign_resource); | |
1957 | EXPORT_SYMBOL(pci_find_parent_resource); | |
c87deff7 | 1958 | EXPORT_SYMBOL(pci_select_bars); |
1da177e4 LT |
1959 | |
1960 | EXPORT_SYMBOL(pci_set_power_state); | |
1961 | EXPORT_SYMBOL(pci_save_state); | |
1962 | EXPORT_SYMBOL(pci_restore_state); | |
e5899e1b | 1963 | EXPORT_SYMBOL(pci_pme_capable); |
5a6c9b60 | 1964 | EXPORT_SYMBOL(pci_pme_active); |
1da177e4 | 1965 | EXPORT_SYMBOL(pci_enable_wake); |
0235c4fc | 1966 | EXPORT_SYMBOL(pci_wake_from_d3); |
e5899e1b | 1967 | EXPORT_SYMBOL(pci_target_state); |
404cc2d8 RW |
1968 | EXPORT_SYMBOL(pci_prepare_to_sleep); |
1969 | EXPORT_SYMBOL(pci_back_from_sleep); | |
f7bdd12d | 1970 | EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state); |
1da177e4 | 1971 |