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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * PCI Bus Services, see include/linux/pci.h for further explanation. |
3 | * | |
4 | * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, | |
5 | * David Mosberger-Tang | |
6 | * | |
7 | * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> | |
8 | */ | |
9 | ||
10 | #include <linux/kernel.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/pci.h> | |
075c1771 | 14 | #include <linux/pm.h> |
1da177e4 LT |
15 | #include <linux/module.h> |
16 | #include <linux/spinlock.h> | |
4e57b681 | 17 | #include <linux/string.h> |
229f5afd | 18 | #include <linux/log2.h> |
7d715a6c | 19 | #include <linux/pci-aspm.h> |
c300bd2f | 20 | #include <linux/pm_wakeup.h> |
8dd7f803 | 21 | #include <linux/interrupt.h> |
1da177e4 | 22 | #include <asm/dma.h> /* isa_dma_bridge_buggy */ |
bc56b9e0 | 23 | #include "pci.h" |
1da177e4 | 24 | |
ffadcc2f | 25 | unsigned int pci_pm_d3_delay = 10; |
1da177e4 | 26 | |
32a2eea7 JG |
27 | #ifdef CONFIG_PCI_DOMAINS |
28 | int pci_domains_supported = 1; | |
29 | #endif | |
30 | ||
4516a618 AN |
31 | #define DEFAULT_CARDBUS_IO_SIZE (256) |
32 | #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024) | |
33 | /* pci=cbmemsize=nnM,cbiosize=nn can override this */ | |
34 | unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE; | |
35 | unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE; | |
36 | ||
1da177e4 LT |
37 | /** |
38 | * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children | |
39 | * @bus: pointer to PCI bus structure to search | |
40 | * | |
41 | * Given a PCI bus, returns the highest PCI bus number present in the set | |
42 | * including the given PCI bus and its list of child PCI buses. | |
43 | */ | |
96bde06a | 44 | unsigned char pci_bus_max_busnr(struct pci_bus* bus) |
1da177e4 LT |
45 | { |
46 | struct list_head *tmp; | |
47 | unsigned char max, n; | |
48 | ||
b82db5ce | 49 | max = bus->subordinate; |
1da177e4 LT |
50 | list_for_each(tmp, &bus->children) { |
51 | n = pci_bus_max_busnr(pci_bus_b(tmp)); | |
52 | if(n > max) | |
53 | max = n; | |
54 | } | |
55 | return max; | |
56 | } | |
b82db5ce | 57 | EXPORT_SYMBOL_GPL(pci_bus_max_busnr); |
1da177e4 | 58 | |
1684f5dd AM |
59 | #ifdef CONFIG_HAS_IOMEM |
60 | void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar) | |
61 | { | |
62 | /* | |
63 | * Make sure the BAR is actually a memory resource, not an IO resource | |
64 | */ | |
65 | if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { | |
66 | WARN_ON(1); | |
67 | return NULL; | |
68 | } | |
69 | return ioremap_nocache(pci_resource_start(pdev, bar), | |
70 | pci_resource_len(pdev, bar)); | |
71 | } | |
72 | EXPORT_SYMBOL_GPL(pci_ioremap_bar); | |
73 | #endif | |
74 | ||
b82db5ce | 75 | #if 0 |
1da177e4 LT |
76 | /** |
77 | * pci_max_busnr - returns maximum PCI bus number | |
78 | * | |
79 | * Returns the highest PCI bus number present in the system global list of | |
80 | * PCI buses. | |
81 | */ | |
82 | unsigned char __devinit | |
83 | pci_max_busnr(void) | |
84 | { | |
85 | struct pci_bus *bus = NULL; | |
86 | unsigned char max, n; | |
87 | ||
88 | max = 0; | |
89 | while ((bus = pci_find_next_bus(bus)) != NULL) { | |
90 | n = pci_bus_max_busnr(bus); | |
91 | if(n > max) | |
92 | max = n; | |
93 | } | |
94 | return max; | |
95 | } | |
96 | ||
54c762fe AB |
97 | #endif /* 0 */ |
98 | ||
687d5fe3 ME |
99 | #define PCI_FIND_CAP_TTL 48 |
100 | ||
101 | static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, | |
102 | u8 pos, int cap, int *ttl) | |
24a4e377 RD |
103 | { |
104 | u8 id; | |
24a4e377 | 105 | |
687d5fe3 | 106 | while ((*ttl)--) { |
24a4e377 RD |
107 | pci_bus_read_config_byte(bus, devfn, pos, &pos); |
108 | if (pos < 0x40) | |
109 | break; | |
110 | pos &= ~3; | |
111 | pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, | |
112 | &id); | |
113 | if (id == 0xff) | |
114 | break; | |
115 | if (id == cap) | |
116 | return pos; | |
117 | pos += PCI_CAP_LIST_NEXT; | |
118 | } | |
119 | return 0; | |
120 | } | |
121 | ||
687d5fe3 ME |
122 | static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, |
123 | u8 pos, int cap) | |
124 | { | |
125 | int ttl = PCI_FIND_CAP_TTL; | |
126 | ||
127 | return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); | |
128 | } | |
129 | ||
24a4e377 RD |
130 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) |
131 | { | |
132 | return __pci_find_next_cap(dev->bus, dev->devfn, | |
133 | pos + PCI_CAP_LIST_NEXT, cap); | |
134 | } | |
135 | EXPORT_SYMBOL_GPL(pci_find_next_capability); | |
136 | ||
d3bac118 ME |
137 | static int __pci_bus_find_cap_start(struct pci_bus *bus, |
138 | unsigned int devfn, u8 hdr_type) | |
1da177e4 LT |
139 | { |
140 | u16 status; | |
1da177e4 LT |
141 | |
142 | pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); | |
143 | if (!(status & PCI_STATUS_CAP_LIST)) | |
144 | return 0; | |
145 | ||
146 | switch (hdr_type) { | |
147 | case PCI_HEADER_TYPE_NORMAL: | |
148 | case PCI_HEADER_TYPE_BRIDGE: | |
d3bac118 | 149 | return PCI_CAPABILITY_LIST; |
1da177e4 | 150 | case PCI_HEADER_TYPE_CARDBUS: |
d3bac118 | 151 | return PCI_CB_CAPABILITY_LIST; |
1da177e4 LT |
152 | default: |
153 | return 0; | |
154 | } | |
d3bac118 ME |
155 | |
156 | return 0; | |
1da177e4 LT |
157 | } |
158 | ||
159 | /** | |
160 | * pci_find_capability - query for devices' capabilities | |
161 | * @dev: PCI device to query | |
162 | * @cap: capability code | |
163 | * | |
164 | * Tell if a device supports a given PCI capability. | |
165 | * Returns the address of the requested capability structure within the | |
166 | * device's PCI configuration space or 0 in case the device does not | |
167 | * support it. Possible values for @cap: | |
168 | * | |
169 | * %PCI_CAP_ID_PM Power Management | |
170 | * %PCI_CAP_ID_AGP Accelerated Graphics Port | |
171 | * %PCI_CAP_ID_VPD Vital Product Data | |
172 | * %PCI_CAP_ID_SLOTID Slot Identification | |
173 | * %PCI_CAP_ID_MSI Message Signalled Interrupts | |
174 | * %PCI_CAP_ID_CHSWP CompactPCI HotSwap | |
175 | * %PCI_CAP_ID_PCIX PCI-X | |
176 | * %PCI_CAP_ID_EXP PCI Express | |
177 | */ | |
178 | int pci_find_capability(struct pci_dev *dev, int cap) | |
179 | { | |
d3bac118 ME |
180 | int pos; |
181 | ||
182 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
183 | if (pos) | |
184 | pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); | |
185 | ||
186 | return pos; | |
1da177e4 LT |
187 | } |
188 | ||
189 | /** | |
190 | * pci_bus_find_capability - query for devices' capabilities | |
191 | * @bus: the PCI bus to query | |
192 | * @devfn: PCI device to query | |
193 | * @cap: capability code | |
194 | * | |
195 | * Like pci_find_capability() but works for pci devices that do not have a | |
196 | * pci_dev structure set up yet. | |
197 | * | |
198 | * Returns the address of the requested capability structure within the | |
199 | * device's PCI configuration space or 0 in case the device does not | |
200 | * support it. | |
201 | */ | |
202 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) | |
203 | { | |
d3bac118 | 204 | int pos; |
1da177e4 LT |
205 | u8 hdr_type; |
206 | ||
207 | pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); | |
208 | ||
d3bac118 ME |
209 | pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f); |
210 | if (pos) | |
211 | pos = __pci_find_next_cap(bus, devfn, pos, cap); | |
212 | ||
213 | return pos; | |
1da177e4 LT |
214 | } |
215 | ||
216 | /** | |
217 | * pci_find_ext_capability - Find an extended capability | |
218 | * @dev: PCI device to query | |
219 | * @cap: capability code | |
220 | * | |
221 | * Returns the address of the requested extended capability structure | |
222 | * within the device's PCI configuration space or 0 if the device does | |
223 | * not support it. Possible values for @cap: | |
224 | * | |
225 | * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting | |
226 | * %PCI_EXT_CAP_ID_VC Virtual Channel | |
227 | * %PCI_EXT_CAP_ID_DSN Device Serial Number | |
228 | * %PCI_EXT_CAP_ID_PWR Power Budgeting | |
229 | */ | |
230 | int pci_find_ext_capability(struct pci_dev *dev, int cap) | |
231 | { | |
232 | u32 header; | |
557848c3 ZY |
233 | int ttl; |
234 | int pos = PCI_CFG_SPACE_SIZE; | |
1da177e4 | 235 | |
557848c3 ZY |
236 | /* minimum 8 bytes per capability */ |
237 | ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; | |
238 | ||
239 | if (dev->cfg_size <= PCI_CFG_SPACE_SIZE) | |
1da177e4 LT |
240 | return 0; |
241 | ||
242 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
243 | return 0; | |
244 | ||
245 | /* | |
246 | * If we have no capabilities, this is indicated by cap ID, | |
247 | * cap version and next pointer all being 0. | |
248 | */ | |
249 | if (header == 0) | |
250 | return 0; | |
251 | ||
252 | while (ttl-- > 0) { | |
253 | if (PCI_EXT_CAP_ID(header) == cap) | |
254 | return pos; | |
255 | ||
256 | pos = PCI_EXT_CAP_NEXT(header); | |
557848c3 | 257 | if (pos < PCI_CFG_SPACE_SIZE) |
1da177e4 LT |
258 | break; |
259 | ||
260 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
261 | break; | |
262 | } | |
263 | ||
264 | return 0; | |
265 | } | |
3a720d72 | 266 | EXPORT_SYMBOL_GPL(pci_find_ext_capability); |
1da177e4 | 267 | |
687d5fe3 ME |
268 | static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) |
269 | { | |
270 | int rc, ttl = PCI_FIND_CAP_TTL; | |
271 | u8 cap, mask; | |
272 | ||
273 | if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST) | |
274 | mask = HT_3BIT_CAP_MASK; | |
275 | else | |
276 | mask = HT_5BIT_CAP_MASK; | |
277 | ||
278 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, | |
279 | PCI_CAP_ID_HT, &ttl); | |
280 | while (pos) { | |
281 | rc = pci_read_config_byte(dev, pos + 3, &cap); | |
282 | if (rc != PCIBIOS_SUCCESSFUL) | |
283 | return 0; | |
284 | ||
285 | if ((cap & mask) == ht_cap) | |
286 | return pos; | |
287 | ||
47a4d5be BG |
288 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, |
289 | pos + PCI_CAP_LIST_NEXT, | |
687d5fe3 ME |
290 | PCI_CAP_ID_HT, &ttl); |
291 | } | |
292 | ||
293 | return 0; | |
294 | } | |
295 | /** | |
296 | * pci_find_next_ht_capability - query a device's Hypertransport capabilities | |
297 | * @dev: PCI device to query | |
298 | * @pos: Position from which to continue searching | |
299 | * @ht_cap: Hypertransport capability code | |
300 | * | |
301 | * To be used in conjunction with pci_find_ht_capability() to search for | |
302 | * all capabilities matching @ht_cap. @pos should always be a value returned | |
303 | * from pci_find_ht_capability(). | |
304 | * | |
305 | * NB. To be 100% safe against broken PCI devices, the caller should take | |
306 | * steps to avoid an infinite loop. | |
307 | */ | |
308 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap) | |
309 | { | |
310 | return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap); | |
311 | } | |
312 | EXPORT_SYMBOL_GPL(pci_find_next_ht_capability); | |
313 | ||
314 | /** | |
315 | * pci_find_ht_capability - query a device's Hypertransport capabilities | |
316 | * @dev: PCI device to query | |
317 | * @ht_cap: Hypertransport capability code | |
318 | * | |
319 | * Tell if a device supports a given Hypertransport capability. | |
320 | * Returns an address within the device's PCI configuration space | |
321 | * or 0 in case the device does not support the request capability. | |
322 | * The address points to the PCI capability, of type PCI_CAP_ID_HT, | |
323 | * which has a Hypertransport capability matching @ht_cap. | |
324 | */ | |
325 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap) | |
326 | { | |
327 | int pos; | |
328 | ||
329 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
330 | if (pos) | |
331 | pos = __pci_find_next_ht_cap(dev, pos, ht_cap); | |
332 | ||
333 | return pos; | |
334 | } | |
335 | EXPORT_SYMBOL_GPL(pci_find_ht_capability); | |
336 | ||
1da177e4 LT |
337 | /** |
338 | * pci_find_parent_resource - return resource region of parent bus of given region | |
339 | * @dev: PCI device structure contains resources to be searched | |
340 | * @res: child resource record for which parent is sought | |
341 | * | |
342 | * For given resource region of given device, return the resource | |
343 | * region of parent bus the given region is contained in or where | |
344 | * it should be allocated from. | |
345 | */ | |
346 | struct resource * | |
347 | pci_find_parent_resource(const struct pci_dev *dev, struct resource *res) | |
348 | { | |
349 | const struct pci_bus *bus = dev->bus; | |
350 | int i; | |
351 | struct resource *best = NULL; | |
352 | ||
353 | for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) { | |
354 | struct resource *r = bus->resource[i]; | |
355 | if (!r) | |
356 | continue; | |
357 | if (res->start && !(res->start >= r->start && res->end <= r->end)) | |
358 | continue; /* Not contained */ | |
359 | if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM)) | |
360 | continue; /* Wrong type */ | |
361 | if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) | |
362 | return r; /* Exact match */ | |
363 | if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH)) | |
364 | best = r; /* Approximating prefetchable by non-prefetchable */ | |
365 | } | |
366 | return best; | |
367 | } | |
368 | ||
064b53db JL |
369 | /** |
370 | * pci_restore_bars - restore a devices BAR values (e.g. after wake-up) | |
371 | * @dev: PCI device to have its BARs restored | |
372 | * | |
373 | * Restore the BAR values for a given device, so as to make it | |
374 | * accessible by its driver. | |
375 | */ | |
ad668599 | 376 | static void |
064b53db JL |
377 | pci_restore_bars(struct pci_dev *dev) |
378 | { | |
bc5f5a82 | 379 | int i; |
064b53db | 380 | |
bc5f5a82 | 381 | for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) |
14add80b | 382 | pci_update_resource(dev, i); |
064b53db JL |
383 | } |
384 | ||
961d9120 RW |
385 | static struct pci_platform_pm_ops *pci_platform_pm; |
386 | ||
387 | int pci_set_platform_pm(struct pci_platform_pm_ops *ops) | |
388 | { | |
eb9d0fe4 RW |
389 | if (!ops->is_manageable || !ops->set_state || !ops->choose_state |
390 | || !ops->sleep_wake || !ops->can_wakeup) | |
961d9120 RW |
391 | return -EINVAL; |
392 | pci_platform_pm = ops; | |
393 | return 0; | |
394 | } | |
395 | ||
396 | static inline bool platform_pci_power_manageable(struct pci_dev *dev) | |
397 | { | |
398 | return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false; | |
399 | } | |
400 | ||
401 | static inline int platform_pci_set_power_state(struct pci_dev *dev, | |
402 | pci_power_t t) | |
403 | { | |
404 | return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS; | |
405 | } | |
406 | ||
407 | static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev) | |
408 | { | |
409 | return pci_platform_pm ? | |
410 | pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR; | |
411 | } | |
8f7020d3 | 412 | |
eb9d0fe4 RW |
413 | static inline bool platform_pci_can_wakeup(struct pci_dev *dev) |
414 | { | |
415 | return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false; | |
416 | } | |
417 | ||
418 | static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable) | |
419 | { | |
420 | return pci_platform_pm ? | |
421 | pci_platform_pm->sleep_wake(dev, enable) : -ENODEV; | |
422 | } | |
423 | ||
1da177e4 | 424 | /** |
44e4e66e RW |
425 | * pci_raw_set_power_state - Use PCI PM registers to set the power state of |
426 | * given PCI device | |
427 | * @dev: PCI device to handle. | |
44e4e66e | 428 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. |
1da177e4 | 429 | * |
44e4e66e RW |
430 | * RETURN VALUE: |
431 | * -EINVAL if the requested state is invalid. | |
432 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
433 | * wrong version, or device doesn't support the requested state. | |
434 | * 0 if device already is in the requested state. | |
435 | * 0 if device's power state has been successfully changed. | |
1da177e4 | 436 | */ |
44e4e66e | 437 | static int |
337001b6 | 438 | pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state) |
1da177e4 | 439 | { |
337001b6 | 440 | u16 pmcsr; |
44e4e66e | 441 | bool need_restore = false; |
1da177e4 | 442 | |
337001b6 | 443 | if (!dev->pm_cap) |
cca03dec AL |
444 | return -EIO; |
445 | ||
44e4e66e RW |
446 | if (state < PCI_D0 || state > PCI_D3hot) |
447 | return -EINVAL; | |
448 | ||
1da177e4 LT |
449 | /* Validate current state: |
450 | * Can enter D0 from any state, but if we can only go deeper | |
451 | * to sleep if we're already in a low power state | |
452 | */ | |
44e4e66e RW |
453 | if (dev->current_state == state) { |
454 | /* we're already there */ | |
455 | return 0; | |
456 | } else if (state != PCI_D0 && dev->current_state <= PCI_D3cold | |
457 | && dev->current_state > state) { | |
80ccba11 BH |
458 | dev_err(&dev->dev, "invalid power transition " |
459 | "(from state %d to %d)\n", dev->current_state, state); | |
1da177e4 | 460 | return -EINVAL; |
44e4e66e | 461 | } |
1da177e4 | 462 | |
1da177e4 | 463 | /* check if this device supports the desired state */ |
337001b6 RW |
464 | if ((state == PCI_D1 && !dev->d1_support) |
465 | || (state == PCI_D2 && !dev->d2_support)) | |
3fe9d19f | 466 | return -EIO; |
1da177e4 | 467 | |
337001b6 | 468 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
064b53db | 469 | |
32a36585 | 470 | /* If we're (effectively) in D3, force entire word to 0. |
1da177e4 LT |
471 | * This doesn't affect PME_Status, disables PME_En, and |
472 | * sets PowerState to 0. | |
473 | */ | |
32a36585 | 474 | switch (dev->current_state) { |
d3535fbb JL |
475 | case PCI_D0: |
476 | case PCI_D1: | |
477 | case PCI_D2: | |
478 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
479 | pmcsr |= state; | |
480 | break; | |
32a36585 JL |
481 | case PCI_UNKNOWN: /* Boot-up */ |
482 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot | |
483 | && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) | |
44e4e66e | 484 | need_restore = true; |
32a36585 | 485 | /* Fall-through: force to D0 */ |
32a36585 | 486 | default: |
d3535fbb | 487 | pmcsr = 0; |
32a36585 | 488 | break; |
1da177e4 LT |
489 | } |
490 | ||
491 | /* enter specified state */ | |
337001b6 | 492 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
1da177e4 LT |
493 | |
494 | /* Mandatory power management transition delays */ | |
495 | /* see PCI PM 1.1 5.6.1 table 18 */ | |
496 | if (state == PCI_D3hot || dev->current_state == PCI_D3hot) | |
ffadcc2f | 497 | msleep(pci_pm_d3_delay); |
1da177e4 LT |
498 | else if (state == PCI_D2 || dev->current_state == PCI_D2) |
499 | udelay(200); | |
1da177e4 | 500 | |
b913100d | 501 | dev->current_state = state; |
064b53db JL |
502 | |
503 | /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT | |
504 | * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning | |
505 | * from D3hot to D0 _may_ perform an internal reset, thereby | |
506 | * going to "D0 Uninitialized" rather than "D0 Initialized". | |
507 | * For example, at least some versions of the 3c905B and the | |
508 | * 3c556B exhibit this behaviour. | |
509 | * | |
510 | * At least some laptop BIOSen (e.g. the Thinkpad T21) leave | |
511 | * devices in a D3hot state at boot. Consequently, we need to | |
512 | * restore at least the BARs so that the device will be | |
513 | * accessible to its driver. | |
514 | */ | |
515 | if (need_restore) | |
516 | pci_restore_bars(dev); | |
517 | ||
7d715a6c SL |
518 | if (dev->bus->self) |
519 | pcie_aspm_pm_state_change(dev->bus->self); | |
520 | ||
1da177e4 LT |
521 | return 0; |
522 | } | |
523 | ||
44e4e66e RW |
524 | /** |
525 | * pci_update_current_state - Read PCI power state of given device from its | |
526 | * PCI PM registers and cache it | |
527 | * @dev: PCI device to handle. | |
f06fc0b6 | 528 | * @state: State to cache in case the device doesn't have the PM capability |
44e4e66e | 529 | */ |
f06fc0b6 | 530 | static void pci_update_current_state(struct pci_dev *dev, pci_power_t state) |
44e4e66e | 531 | { |
337001b6 | 532 | if (dev->pm_cap) { |
44e4e66e RW |
533 | u16 pmcsr; |
534 | ||
337001b6 | 535 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
44e4e66e | 536 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); |
f06fc0b6 RW |
537 | } else { |
538 | dev->current_state = state; | |
44e4e66e RW |
539 | } |
540 | } | |
541 | ||
542 | /** | |
543 | * pci_set_power_state - Set the power state of a PCI device | |
544 | * @dev: PCI device to handle. | |
545 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. | |
546 | * | |
547 | * Transition a device to a new power state, using the platform formware and/or | |
548 | * the device's PCI PM registers. | |
549 | * | |
550 | * RETURN VALUE: | |
551 | * -EINVAL if the requested state is invalid. | |
552 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
553 | * wrong version, or device doesn't support the requested state. | |
554 | * 0 if device already is in the requested state. | |
555 | * 0 if device's power state has been successfully changed. | |
556 | */ | |
557 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state) | |
558 | { | |
337001b6 | 559 | int error; |
44e4e66e RW |
560 | |
561 | /* bound the state we're entering */ | |
562 | if (state > PCI_D3hot) | |
563 | state = PCI_D3hot; | |
564 | else if (state < PCI_D0) | |
565 | state = PCI_D0; | |
566 | else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) | |
567 | /* | |
568 | * If the device or the parent bridge do not support PCI PM, | |
569 | * ignore the request if we're doing anything other than putting | |
570 | * it into D0 (which would only happen on boot). | |
571 | */ | |
572 | return 0; | |
573 | ||
44e4e66e RW |
574 | if (state == PCI_D0 && platform_pci_power_manageable(dev)) { |
575 | /* | |
576 | * Allow the platform to change the state, for example via ACPI | |
577 | * _PR0, _PS0 and some such, but do not trust it. | |
578 | */ | |
579 | int ret = platform_pci_set_power_state(dev, PCI_D0); | |
580 | if (!ret) | |
f06fc0b6 | 581 | pci_update_current_state(dev, PCI_D0); |
44e4e66e | 582 | } |
979b1791 AC |
583 | /* This device is quirked not to be put into D3, so |
584 | don't put it in D3 */ | |
585 | if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) | |
586 | return 0; | |
44e4e66e | 587 | |
337001b6 | 588 | error = pci_raw_set_power_state(dev, state); |
44e4e66e RW |
589 | |
590 | if (state > PCI_D0 && platform_pci_power_manageable(dev)) { | |
591 | /* Allow the platform to finalize the transition */ | |
592 | int ret = platform_pci_set_power_state(dev, state); | |
593 | if (!ret) { | |
f06fc0b6 | 594 | pci_update_current_state(dev, state); |
44e4e66e RW |
595 | error = 0; |
596 | } | |
597 | } | |
598 | ||
599 | return error; | |
600 | } | |
601 | ||
1da177e4 LT |
602 | /** |
603 | * pci_choose_state - Choose the power state of a PCI device | |
604 | * @dev: PCI device to be suspended | |
605 | * @state: target sleep state for the whole system. This is the value | |
606 | * that is passed to suspend() function. | |
607 | * | |
608 | * Returns PCI power state suitable for given device and given system | |
609 | * message. | |
610 | */ | |
611 | ||
612 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) | |
613 | { | |
ab826ca4 | 614 | pci_power_t ret; |
0f64474b | 615 | |
1da177e4 LT |
616 | if (!pci_find_capability(dev, PCI_CAP_ID_PM)) |
617 | return PCI_D0; | |
618 | ||
961d9120 RW |
619 | ret = platform_pci_choose_state(dev); |
620 | if (ret != PCI_POWER_ERROR) | |
621 | return ret; | |
ca078bae PM |
622 | |
623 | switch (state.event) { | |
624 | case PM_EVENT_ON: | |
625 | return PCI_D0; | |
626 | case PM_EVENT_FREEZE: | |
b887d2e6 DB |
627 | case PM_EVENT_PRETHAW: |
628 | /* REVISIT both freeze and pre-thaw "should" use D0 */ | |
ca078bae | 629 | case PM_EVENT_SUSPEND: |
3a2d5b70 | 630 | case PM_EVENT_HIBERNATE: |
ca078bae | 631 | return PCI_D3hot; |
1da177e4 | 632 | default: |
80ccba11 BH |
633 | dev_info(&dev->dev, "unrecognized suspend event %d\n", |
634 | state.event); | |
1da177e4 LT |
635 | BUG(); |
636 | } | |
637 | return PCI_D0; | |
638 | } | |
639 | ||
640 | EXPORT_SYMBOL(pci_choose_state); | |
641 | ||
b56a5a23 MT |
642 | static int pci_save_pcie_state(struct pci_dev *dev) |
643 | { | |
644 | int pos, i = 0; | |
645 | struct pci_cap_saved_state *save_state; | |
646 | u16 *cap; | |
647 | ||
648 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
649 | if (pos <= 0) | |
650 | return 0; | |
651 | ||
9f35575d | 652 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); |
b56a5a23 | 653 | if (!save_state) { |
63f4898a | 654 | dev_err(&dev->dev, "buffer not found in %s\n", __FUNCTION__); |
b56a5a23 MT |
655 | return -ENOMEM; |
656 | } | |
657 | cap = (u16 *)&save_state->data[0]; | |
658 | ||
659 | pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]); | |
660 | pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]); | |
661 | pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]); | |
662 | pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]); | |
63f4898a | 663 | |
b56a5a23 MT |
664 | return 0; |
665 | } | |
666 | ||
667 | static void pci_restore_pcie_state(struct pci_dev *dev) | |
668 | { | |
669 | int i = 0, pos; | |
670 | struct pci_cap_saved_state *save_state; | |
671 | u16 *cap; | |
672 | ||
673 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); | |
674 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
675 | if (!save_state || pos <= 0) | |
676 | return; | |
677 | cap = (u16 *)&save_state->data[0]; | |
678 | ||
679 | pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]); | |
680 | pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]); | |
681 | pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]); | |
682 | pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]); | |
b56a5a23 MT |
683 | } |
684 | ||
cc692a5f SH |
685 | |
686 | static int pci_save_pcix_state(struct pci_dev *dev) | |
687 | { | |
63f4898a | 688 | int pos; |
cc692a5f | 689 | struct pci_cap_saved_state *save_state; |
cc692a5f SH |
690 | |
691 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
692 | if (pos <= 0) | |
693 | return 0; | |
694 | ||
f34303de | 695 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); |
cc692a5f | 696 | if (!save_state) { |
63f4898a | 697 | dev_err(&dev->dev, "buffer not found in %s\n", __FUNCTION__); |
cc692a5f SH |
698 | return -ENOMEM; |
699 | } | |
cc692a5f | 700 | |
63f4898a RW |
701 | pci_read_config_word(dev, pos + PCI_X_CMD, (u16 *)save_state->data); |
702 | ||
cc692a5f SH |
703 | return 0; |
704 | } | |
705 | ||
706 | static void pci_restore_pcix_state(struct pci_dev *dev) | |
707 | { | |
708 | int i = 0, pos; | |
709 | struct pci_cap_saved_state *save_state; | |
710 | u16 *cap; | |
711 | ||
712 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); | |
713 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
714 | if (!save_state || pos <= 0) | |
715 | return; | |
716 | cap = (u16 *)&save_state->data[0]; | |
717 | ||
718 | pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]); | |
cc692a5f SH |
719 | } |
720 | ||
721 | ||
1da177e4 LT |
722 | /** |
723 | * pci_save_state - save the PCI configuration space of a device before suspending | |
724 | * @dev: - PCI device that we're dealing with | |
1da177e4 LT |
725 | */ |
726 | int | |
727 | pci_save_state(struct pci_dev *dev) | |
728 | { | |
729 | int i; | |
730 | /* XXX: 100% dword access ok here? */ | |
731 | for (i = 0; i < 16; i++) | |
732 | pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]); | |
b56a5a23 MT |
733 | if ((i = pci_save_pcie_state(dev)) != 0) |
734 | return i; | |
cc692a5f SH |
735 | if ((i = pci_save_pcix_state(dev)) != 0) |
736 | return i; | |
1da177e4 LT |
737 | return 0; |
738 | } | |
739 | ||
740 | /** | |
741 | * pci_restore_state - Restore the saved state of a PCI device | |
742 | * @dev: - PCI device that we're dealing with | |
1da177e4 LT |
743 | */ |
744 | int | |
745 | pci_restore_state(struct pci_dev *dev) | |
746 | { | |
747 | int i; | |
b4482a4b | 748 | u32 val; |
1da177e4 | 749 | |
b56a5a23 MT |
750 | /* PCI Express register must be restored first */ |
751 | pci_restore_pcie_state(dev); | |
752 | ||
8b8c8d28 YL |
753 | /* |
754 | * The Base Address register should be programmed before the command | |
755 | * register(s) | |
756 | */ | |
757 | for (i = 15; i >= 0; i--) { | |
04d9c1a1 DJ |
758 | pci_read_config_dword(dev, i * 4, &val); |
759 | if (val != dev->saved_config_space[i]) { | |
80ccba11 BH |
760 | dev_printk(KERN_DEBUG, &dev->dev, "restoring config " |
761 | "space at offset %#x (was %#x, writing %#x)\n", | |
762 | i, val, (int)dev->saved_config_space[i]); | |
04d9c1a1 DJ |
763 | pci_write_config_dword(dev,i * 4, |
764 | dev->saved_config_space[i]); | |
765 | } | |
766 | } | |
cc692a5f | 767 | pci_restore_pcix_state(dev); |
41017f0c | 768 | pci_restore_msi_state(dev); |
8fed4b65 | 769 | |
1da177e4 LT |
770 | return 0; |
771 | } | |
772 | ||
38cc1302 HS |
773 | static int do_pci_enable_device(struct pci_dev *dev, int bars) |
774 | { | |
775 | int err; | |
776 | ||
777 | err = pci_set_power_state(dev, PCI_D0); | |
778 | if (err < 0 && err != -EIO) | |
779 | return err; | |
780 | err = pcibios_enable_device(dev, bars); | |
781 | if (err < 0) | |
782 | return err; | |
783 | pci_fixup_device(pci_fixup_enable, dev); | |
784 | ||
785 | return 0; | |
786 | } | |
787 | ||
788 | /** | |
0b62e13b | 789 | * pci_reenable_device - Resume abandoned device |
38cc1302 HS |
790 | * @dev: PCI device to be resumed |
791 | * | |
792 | * Note this function is a backend of pci_default_resume and is not supposed | |
793 | * to be called by normal code, write proper resume handler and use it instead. | |
794 | */ | |
0b62e13b | 795 | int pci_reenable_device(struct pci_dev *dev) |
38cc1302 HS |
796 | { |
797 | if (atomic_read(&dev->enable_cnt)) | |
798 | return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); | |
799 | return 0; | |
800 | } | |
801 | ||
b718989d BH |
802 | static int __pci_enable_device_flags(struct pci_dev *dev, |
803 | resource_size_t flags) | |
1da177e4 LT |
804 | { |
805 | int err; | |
b718989d | 806 | int i, bars = 0; |
1da177e4 | 807 | |
9fb625c3 HS |
808 | if (atomic_add_return(1, &dev->enable_cnt) > 1) |
809 | return 0; /* already enabled */ | |
810 | ||
b718989d BH |
811 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) |
812 | if (dev->resource[i].flags & flags) | |
813 | bars |= (1 << i); | |
814 | ||
38cc1302 | 815 | err = do_pci_enable_device(dev, bars); |
95a62965 | 816 | if (err < 0) |
38cc1302 | 817 | atomic_dec(&dev->enable_cnt); |
9fb625c3 | 818 | return err; |
1da177e4 LT |
819 | } |
820 | ||
b718989d BH |
821 | /** |
822 | * pci_enable_device_io - Initialize a device for use with IO space | |
823 | * @dev: PCI device to be initialized | |
824 | * | |
825 | * Initialize device before it's used by a driver. Ask low-level code | |
826 | * to enable I/O resources. Wake up the device if it was suspended. | |
827 | * Beware, this function can fail. | |
828 | */ | |
829 | int pci_enable_device_io(struct pci_dev *dev) | |
830 | { | |
831 | return __pci_enable_device_flags(dev, IORESOURCE_IO); | |
832 | } | |
833 | ||
834 | /** | |
835 | * pci_enable_device_mem - Initialize a device for use with Memory space | |
836 | * @dev: PCI device to be initialized | |
837 | * | |
838 | * Initialize device before it's used by a driver. Ask low-level code | |
839 | * to enable Memory resources. Wake up the device if it was suspended. | |
840 | * Beware, this function can fail. | |
841 | */ | |
842 | int pci_enable_device_mem(struct pci_dev *dev) | |
843 | { | |
844 | return __pci_enable_device_flags(dev, IORESOURCE_MEM); | |
845 | } | |
846 | ||
bae94d02 IPG |
847 | /** |
848 | * pci_enable_device - Initialize device before it's used by a driver. | |
849 | * @dev: PCI device to be initialized | |
850 | * | |
851 | * Initialize device before it's used by a driver. Ask low-level code | |
852 | * to enable I/O and memory. Wake up the device if it was suspended. | |
853 | * Beware, this function can fail. | |
854 | * | |
855 | * Note we don't actually enable the device many times if we call | |
856 | * this function repeatedly (we just increment the count). | |
857 | */ | |
858 | int pci_enable_device(struct pci_dev *dev) | |
859 | { | |
b718989d | 860 | return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO); |
bae94d02 IPG |
861 | } |
862 | ||
9ac7849e TH |
863 | /* |
864 | * Managed PCI resources. This manages device on/off, intx/msi/msix | |
865 | * on/off and BAR regions. pci_dev itself records msi/msix status, so | |
866 | * there's no need to track it separately. pci_devres is initialized | |
867 | * when a device is enabled using managed PCI device enable interface. | |
868 | */ | |
869 | struct pci_devres { | |
7f375f32 TH |
870 | unsigned int enabled:1; |
871 | unsigned int pinned:1; | |
9ac7849e TH |
872 | unsigned int orig_intx:1; |
873 | unsigned int restore_intx:1; | |
874 | u32 region_mask; | |
875 | }; | |
876 | ||
877 | static void pcim_release(struct device *gendev, void *res) | |
878 | { | |
879 | struct pci_dev *dev = container_of(gendev, struct pci_dev, dev); | |
880 | struct pci_devres *this = res; | |
881 | int i; | |
882 | ||
883 | if (dev->msi_enabled) | |
884 | pci_disable_msi(dev); | |
885 | if (dev->msix_enabled) | |
886 | pci_disable_msix(dev); | |
887 | ||
888 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) | |
889 | if (this->region_mask & (1 << i)) | |
890 | pci_release_region(dev, i); | |
891 | ||
892 | if (this->restore_intx) | |
893 | pci_intx(dev, this->orig_intx); | |
894 | ||
7f375f32 | 895 | if (this->enabled && !this->pinned) |
9ac7849e TH |
896 | pci_disable_device(dev); |
897 | } | |
898 | ||
899 | static struct pci_devres * get_pci_dr(struct pci_dev *pdev) | |
900 | { | |
901 | struct pci_devres *dr, *new_dr; | |
902 | ||
903 | dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
904 | if (dr) | |
905 | return dr; | |
906 | ||
907 | new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL); | |
908 | if (!new_dr) | |
909 | return NULL; | |
910 | return devres_get(&pdev->dev, new_dr, NULL, NULL); | |
911 | } | |
912 | ||
913 | static struct pci_devres * find_pci_dr(struct pci_dev *pdev) | |
914 | { | |
915 | if (pci_is_managed(pdev)) | |
916 | return devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
917 | return NULL; | |
918 | } | |
919 | ||
920 | /** | |
921 | * pcim_enable_device - Managed pci_enable_device() | |
922 | * @pdev: PCI device to be initialized | |
923 | * | |
924 | * Managed pci_enable_device(). | |
925 | */ | |
926 | int pcim_enable_device(struct pci_dev *pdev) | |
927 | { | |
928 | struct pci_devres *dr; | |
929 | int rc; | |
930 | ||
931 | dr = get_pci_dr(pdev); | |
932 | if (unlikely(!dr)) | |
933 | return -ENOMEM; | |
b95d58ea TH |
934 | if (dr->enabled) |
935 | return 0; | |
9ac7849e TH |
936 | |
937 | rc = pci_enable_device(pdev); | |
938 | if (!rc) { | |
939 | pdev->is_managed = 1; | |
7f375f32 | 940 | dr->enabled = 1; |
9ac7849e TH |
941 | } |
942 | return rc; | |
943 | } | |
944 | ||
945 | /** | |
946 | * pcim_pin_device - Pin managed PCI device | |
947 | * @pdev: PCI device to pin | |
948 | * | |
949 | * Pin managed PCI device @pdev. Pinned device won't be disabled on | |
950 | * driver detach. @pdev must have been enabled with | |
951 | * pcim_enable_device(). | |
952 | */ | |
953 | void pcim_pin_device(struct pci_dev *pdev) | |
954 | { | |
955 | struct pci_devres *dr; | |
956 | ||
957 | dr = find_pci_dr(pdev); | |
7f375f32 | 958 | WARN_ON(!dr || !dr->enabled); |
9ac7849e | 959 | if (dr) |
7f375f32 | 960 | dr->pinned = 1; |
9ac7849e TH |
961 | } |
962 | ||
1da177e4 LT |
963 | /** |
964 | * pcibios_disable_device - disable arch specific PCI resources for device dev | |
965 | * @dev: the PCI device to disable | |
966 | * | |
967 | * Disables architecture specific PCI resources for the device. This | |
968 | * is the default implementation. Architecture implementations can | |
969 | * override this. | |
970 | */ | |
971 | void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {} | |
972 | ||
973 | /** | |
974 | * pci_disable_device - Disable PCI device after use | |
975 | * @dev: PCI device to be disabled | |
976 | * | |
977 | * Signal to the system that the PCI device is not in use by the system | |
978 | * anymore. This only involves disabling PCI bus-mastering, if active. | |
bae94d02 IPG |
979 | * |
980 | * Note we don't actually disable the device until all callers of | |
981 | * pci_device_enable() have called pci_device_disable(). | |
1da177e4 LT |
982 | */ |
983 | void | |
984 | pci_disable_device(struct pci_dev *dev) | |
985 | { | |
9ac7849e | 986 | struct pci_devres *dr; |
1da177e4 | 987 | u16 pci_command; |
99dc804d | 988 | |
9ac7849e TH |
989 | dr = find_pci_dr(dev); |
990 | if (dr) | |
7f375f32 | 991 | dr->enabled = 0; |
9ac7849e | 992 | |
bae94d02 IPG |
993 | if (atomic_sub_return(1, &dev->enable_cnt) != 0) |
994 | return; | |
995 | ||
1da177e4 LT |
996 | pci_read_config_word(dev, PCI_COMMAND, &pci_command); |
997 | if (pci_command & PCI_COMMAND_MASTER) { | |
998 | pci_command &= ~PCI_COMMAND_MASTER; | |
999 | pci_write_config_word(dev, PCI_COMMAND, pci_command); | |
1000 | } | |
ceb43744 | 1001 | dev->is_busmaster = 0; |
1da177e4 LT |
1002 | |
1003 | pcibios_disable_device(dev); | |
1004 | } | |
1005 | ||
f7bdd12d BK |
1006 | /** |
1007 | * pcibios_set_pcie_reset_state - set reset state for device dev | |
1008 | * @dev: the PCI-E device reset | |
1009 | * @state: Reset state to enter into | |
1010 | * | |
1011 | * | |
1012 | * Sets the PCI-E reset state for the device. This is the default | |
1013 | * implementation. Architecture implementations can override this. | |
1014 | */ | |
1015 | int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev, | |
1016 | enum pcie_reset_state state) | |
1017 | { | |
1018 | return -EINVAL; | |
1019 | } | |
1020 | ||
1021 | /** | |
1022 | * pci_set_pcie_reset_state - set reset state for device dev | |
1023 | * @dev: the PCI-E device reset | |
1024 | * @state: Reset state to enter into | |
1025 | * | |
1026 | * | |
1027 | * Sets the PCI reset state for the device. | |
1028 | */ | |
1029 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) | |
1030 | { | |
1031 | return pcibios_set_pcie_reset_state(dev, state); | |
1032 | } | |
1033 | ||
eb9d0fe4 RW |
1034 | /** |
1035 | * pci_pme_capable - check the capability of PCI device to generate PME# | |
1036 | * @dev: PCI device to handle. | |
eb9d0fe4 RW |
1037 | * @state: PCI state from which device will issue PME#. |
1038 | */ | |
e5899e1b | 1039 | bool pci_pme_capable(struct pci_dev *dev, pci_power_t state) |
eb9d0fe4 | 1040 | { |
337001b6 | 1041 | if (!dev->pm_cap) |
eb9d0fe4 RW |
1042 | return false; |
1043 | ||
337001b6 | 1044 | return !!(dev->pme_support & (1 << state)); |
eb9d0fe4 RW |
1045 | } |
1046 | ||
1047 | /** | |
1048 | * pci_pme_active - enable or disable PCI device's PME# function | |
1049 | * @dev: PCI device to handle. | |
eb9d0fe4 RW |
1050 | * @enable: 'true' to enable PME# generation; 'false' to disable it. |
1051 | * | |
1052 | * The caller must verify that the device is capable of generating PME# before | |
1053 | * calling this function with @enable equal to 'true'. | |
1054 | */ | |
5a6c9b60 | 1055 | void pci_pme_active(struct pci_dev *dev, bool enable) |
eb9d0fe4 RW |
1056 | { |
1057 | u16 pmcsr; | |
1058 | ||
337001b6 | 1059 | if (!dev->pm_cap) |
eb9d0fe4 RW |
1060 | return; |
1061 | ||
337001b6 | 1062 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); |
eb9d0fe4 RW |
1063 | /* Clear PME_Status by writing 1 to it and enable PME# */ |
1064 | pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; | |
1065 | if (!enable) | |
1066 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
1067 | ||
337001b6 | 1068 | pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); |
eb9d0fe4 RW |
1069 | |
1070 | dev_printk(KERN_INFO, &dev->dev, "PME# %s\n", | |
1071 | enable ? "enabled" : "disabled"); | |
1072 | } | |
1073 | ||
1da177e4 | 1074 | /** |
075c1771 DB |
1075 | * pci_enable_wake - enable PCI device as wakeup event source |
1076 | * @dev: PCI device affected | |
1077 | * @state: PCI state from which device will issue wakeup events | |
1078 | * @enable: True to enable event generation; false to disable | |
1079 | * | |
1080 | * This enables the device as a wakeup event source, or disables it. | |
1081 | * When such events involves platform-specific hooks, those hooks are | |
1082 | * called automatically by this routine. | |
1083 | * | |
1084 | * Devices with legacy power management (no standard PCI PM capabilities) | |
eb9d0fe4 | 1085 | * always require such platform hooks. |
075c1771 | 1086 | * |
eb9d0fe4 RW |
1087 | * RETURN VALUE: |
1088 | * 0 is returned on success | |
1089 | * -EINVAL is returned if device is not supposed to wake up the system | |
1090 | * Error code depending on the platform is returned if both the platform and | |
1091 | * the native mechanism fail to enable the generation of wake-up events | |
1da177e4 LT |
1092 | */ |
1093 | int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable) | |
1094 | { | |
eb9d0fe4 RW |
1095 | int error = 0; |
1096 | bool pme_done = false; | |
075c1771 | 1097 | |
bebd590c | 1098 | if (enable && !device_may_wakeup(&dev->dev)) |
eb9d0fe4 | 1099 | return -EINVAL; |
1da177e4 | 1100 | |
eb9d0fe4 RW |
1101 | /* |
1102 | * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don | |
1103 | * Anderson we should be doing PME# wake enable followed by ACPI wake | |
1104 | * enable. To disable wake-up we call the platform first, for symmetry. | |
075c1771 | 1105 | */ |
1da177e4 | 1106 | |
eb9d0fe4 RW |
1107 | if (!enable && platform_pci_can_wakeup(dev)) |
1108 | error = platform_pci_sleep_wake(dev, false); | |
1da177e4 | 1109 | |
337001b6 RW |
1110 | if (!enable || pci_pme_capable(dev, state)) { |
1111 | pci_pme_active(dev, enable); | |
eb9d0fe4 | 1112 | pme_done = true; |
075c1771 | 1113 | } |
1da177e4 | 1114 | |
eb9d0fe4 RW |
1115 | if (enable && platform_pci_can_wakeup(dev)) |
1116 | error = platform_pci_sleep_wake(dev, true); | |
1da177e4 | 1117 | |
eb9d0fe4 RW |
1118 | return pme_done ? 0 : error; |
1119 | } | |
1da177e4 | 1120 | |
0235c4fc RW |
1121 | /** |
1122 | * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold | |
1123 | * @dev: PCI device to prepare | |
1124 | * @enable: True to enable wake-up event generation; false to disable | |
1125 | * | |
1126 | * Many drivers want the device to wake up the system from D3_hot or D3_cold | |
1127 | * and this function allows them to set that up cleanly - pci_enable_wake() | |
1128 | * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI | |
1129 | * ordering constraints. | |
1130 | * | |
1131 | * This function only returns error code if the device is not capable of | |
1132 | * generating PME# from both D3_hot and D3_cold, and the platform is unable to | |
1133 | * enable wake-up power for it. | |
1134 | */ | |
1135 | int pci_wake_from_d3(struct pci_dev *dev, bool enable) | |
1136 | { | |
1137 | return pci_pme_capable(dev, PCI_D3cold) ? | |
1138 | pci_enable_wake(dev, PCI_D3cold, enable) : | |
1139 | pci_enable_wake(dev, PCI_D3hot, enable); | |
1140 | } | |
1141 | ||
404cc2d8 | 1142 | /** |
37139074 JB |
1143 | * pci_target_state - find an appropriate low power state for a given PCI dev |
1144 | * @dev: PCI device | |
1145 | * | |
1146 | * Use underlying platform code to find a supported low power state for @dev. | |
1147 | * If the platform can't manage @dev, return the deepest state from which it | |
1148 | * can generate wake events, based on any available PME info. | |
404cc2d8 | 1149 | */ |
e5899e1b | 1150 | pci_power_t pci_target_state(struct pci_dev *dev) |
404cc2d8 RW |
1151 | { |
1152 | pci_power_t target_state = PCI_D3hot; | |
404cc2d8 RW |
1153 | |
1154 | if (platform_pci_power_manageable(dev)) { | |
1155 | /* | |
1156 | * Call the platform to choose the target state of the device | |
1157 | * and enable wake-up from this state if supported. | |
1158 | */ | |
1159 | pci_power_t state = platform_pci_choose_state(dev); | |
1160 | ||
1161 | switch (state) { | |
1162 | case PCI_POWER_ERROR: | |
1163 | case PCI_UNKNOWN: | |
1164 | break; | |
1165 | case PCI_D1: | |
1166 | case PCI_D2: | |
1167 | if (pci_no_d1d2(dev)) | |
1168 | break; | |
1169 | default: | |
1170 | target_state = state; | |
404cc2d8 RW |
1171 | } |
1172 | } else if (device_may_wakeup(&dev->dev)) { | |
1173 | /* | |
1174 | * Find the deepest state from which the device can generate | |
1175 | * wake-up events, make it the target state and enable device | |
1176 | * to generate PME#. | |
1177 | */ | |
337001b6 | 1178 | if (!dev->pm_cap) |
e5899e1b | 1179 | return PCI_POWER_ERROR; |
404cc2d8 | 1180 | |
337001b6 RW |
1181 | if (dev->pme_support) { |
1182 | while (target_state | |
1183 | && !(dev->pme_support & (1 << target_state))) | |
1184 | target_state--; | |
404cc2d8 RW |
1185 | } |
1186 | } | |
1187 | ||
e5899e1b RW |
1188 | return target_state; |
1189 | } | |
1190 | ||
1191 | /** | |
1192 | * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state | |
1193 | * @dev: Device to handle. | |
1194 | * | |
1195 | * Choose the power state appropriate for the device depending on whether | |
1196 | * it can wake up the system and/or is power manageable by the platform | |
1197 | * (PCI_D3hot is the default) and put the device into that state. | |
1198 | */ | |
1199 | int pci_prepare_to_sleep(struct pci_dev *dev) | |
1200 | { | |
1201 | pci_power_t target_state = pci_target_state(dev); | |
1202 | int error; | |
1203 | ||
1204 | if (target_state == PCI_POWER_ERROR) | |
1205 | return -EIO; | |
1206 | ||
c157dfa3 RW |
1207 | pci_enable_wake(dev, target_state, true); |
1208 | ||
404cc2d8 RW |
1209 | error = pci_set_power_state(dev, target_state); |
1210 | ||
1211 | if (error) | |
1212 | pci_enable_wake(dev, target_state, false); | |
1213 | ||
1214 | return error; | |
1215 | } | |
1216 | ||
1217 | /** | |
443bd1c4 | 1218 | * pci_back_from_sleep - turn PCI device on during system-wide transition into working state |
404cc2d8 RW |
1219 | * @dev: Device to handle. |
1220 | * | |
1221 | * Disable device's sytem wake-up capability and put it into D0. | |
1222 | */ | |
1223 | int pci_back_from_sleep(struct pci_dev *dev) | |
1224 | { | |
1225 | pci_enable_wake(dev, PCI_D0, false); | |
1226 | return pci_set_power_state(dev, PCI_D0); | |
1227 | } | |
1228 | ||
eb9d0fe4 RW |
1229 | /** |
1230 | * pci_pm_init - Initialize PM functions of given PCI device | |
1231 | * @dev: PCI device to handle. | |
1232 | */ | |
1233 | void pci_pm_init(struct pci_dev *dev) | |
1234 | { | |
1235 | int pm; | |
1236 | u16 pmc; | |
1da177e4 | 1237 | |
337001b6 RW |
1238 | dev->pm_cap = 0; |
1239 | ||
eb9d0fe4 RW |
1240 | /* find PCI PM capability in list */ |
1241 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
1242 | if (!pm) | |
1243 | return; | |
1244 | /* Check device's ability to generate PME# */ | |
1245 | pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc); | |
075c1771 | 1246 | |
eb9d0fe4 RW |
1247 | if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { |
1248 | dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n", | |
1249 | pmc & PCI_PM_CAP_VER_MASK); | |
1250 | return; | |
1251 | } | |
1252 | ||
337001b6 RW |
1253 | dev->pm_cap = pm; |
1254 | ||
1255 | dev->d1_support = false; | |
1256 | dev->d2_support = false; | |
1257 | if (!pci_no_d1d2(dev)) { | |
c9ed77ee | 1258 | if (pmc & PCI_PM_CAP_D1) |
337001b6 | 1259 | dev->d1_support = true; |
c9ed77ee | 1260 | if (pmc & PCI_PM_CAP_D2) |
337001b6 | 1261 | dev->d2_support = true; |
c9ed77ee BH |
1262 | |
1263 | if (dev->d1_support || dev->d2_support) | |
1264 | dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n", | |
ec84f126 JB |
1265 | dev->d1_support ? " D1" : "", |
1266 | dev->d2_support ? " D2" : ""); | |
337001b6 RW |
1267 | } |
1268 | ||
1269 | pmc &= PCI_PM_CAP_PME_MASK; | |
1270 | if (pmc) { | |
c9ed77ee BH |
1271 | dev_info(&dev->dev, "PME# supported from%s%s%s%s%s\n", |
1272 | (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "", | |
1273 | (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "", | |
1274 | (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "", | |
1275 | (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "", | |
1276 | (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : ""); | |
337001b6 | 1277 | dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT; |
eb9d0fe4 RW |
1278 | /* |
1279 | * Make device's PM flags reflect the wake-up capability, but | |
1280 | * let the user space enable it to wake up the system as needed. | |
1281 | */ | |
1282 | device_set_wakeup_capable(&dev->dev, true); | |
1283 | device_set_wakeup_enable(&dev->dev, false); | |
1284 | /* Disable the PME# generation functionality */ | |
337001b6 RW |
1285 | pci_pme_active(dev, false); |
1286 | } else { | |
1287 | dev->pme_support = 0; | |
eb9d0fe4 | 1288 | } |
1da177e4 LT |
1289 | } |
1290 | ||
eb9c39d0 JB |
1291 | /** |
1292 | * platform_pci_wakeup_init - init platform wakeup if present | |
1293 | * @dev: PCI device | |
1294 | * | |
1295 | * Some devices don't have PCI PM caps but can still generate wakeup | |
1296 | * events through platform methods (like ACPI events). If @dev supports | |
1297 | * platform wakeup events, set the device flag to indicate as much. This | |
1298 | * may be redundant if the device also supports PCI PM caps, but double | |
1299 | * initialization should be safe in that case. | |
1300 | */ | |
1301 | void platform_pci_wakeup_init(struct pci_dev *dev) | |
1302 | { | |
1303 | if (!platform_pci_can_wakeup(dev)) | |
1304 | return; | |
1305 | ||
1306 | device_set_wakeup_capable(&dev->dev, true); | |
1307 | device_set_wakeup_enable(&dev->dev, false); | |
1308 | platform_pci_sleep_wake(dev, false); | |
1309 | } | |
1310 | ||
63f4898a RW |
1311 | /** |
1312 | * pci_add_save_buffer - allocate buffer for saving given capability registers | |
1313 | * @dev: the PCI device | |
1314 | * @cap: the capability to allocate the buffer for | |
1315 | * @size: requested size of the buffer | |
1316 | */ | |
1317 | static int pci_add_cap_save_buffer( | |
1318 | struct pci_dev *dev, char cap, unsigned int size) | |
1319 | { | |
1320 | int pos; | |
1321 | struct pci_cap_saved_state *save_state; | |
1322 | ||
1323 | pos = pci_find_capability(dev, cap); | |
1324 | if (pos <= 0) | |
1325 | return 0; | |
1326 | ||
1327 | save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL); | |
1328 | if (!save_state) | |
1329 | return -ENOMEM; | |
1330 | ||
1331 | save_state->cap_nr = cap; | |
1332 | pci_add_saved_cap(dev, save_state); | |
1333 | ||
1334 | return 0; | |
1335 | } | |
1336 | ||
1337 | /** | |
1338 | * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities | |
1339 | * @dev: the PCI device | |
1340 | */ | |
1341 | void pci_allocate_cap_save_buffers(struct pci_dev *dev) | |
1342 | { | |
1343 | int error; | |
1344 | ||
1345 | error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP, 4 * sizeof(u16)); | |
1346 | if (error) | |
1347 | dev_err(&dev->dev, | |
1348 | "unable to preallocate PCI Express save buffer\n"); | |
1349 | ||
1350 | error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16)); | |
1351 | if (error) | |
1352 | dev_err(&dev->dev, | |
1353 | "unable to preallocate PCI-X save buffer\n"); | |
1354 | } | |
1355 | ||
58c3a727 YZ |
1356 | /** |
1357 | * pci_enable_ari - enable ARI forwarding if hardware support it | |
1358 | * @dev: the PCI device | |
1359 | */ | |
1360 | void pci_enable_ari(struct pci_dev *dev) | |
1361 | { | |
1362 | int pos; | |
1363 | u32 cap; | |
1364 | u16 ctrl; | |
8113587c | 1365 | struct pci_dev *bridge; |
58c3a727 | 1366 | |
8113587c | 1367 | if (!dev->is_pcie || dev->devfn) |
58c3a727 YZ |
1368 | return; |
1369 | ||
8113587c ZY |
1370 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI); |
1371 | if (!pos) | |
58c3a727 YZ |
1372 | return; |
1373 | ||
8113587c ZY |
1374 | bridge = dev->bus->self; |
1375 | if (!bridge || !bridge->is_pcie) | |
1376 | return; | |
1377 | ||
1378 | pos = pci_find_capability(bridge, PCI_CAP_ID_EXP); | |
58c3a727 YZ |
1379 | if (!pos) |
1380 | return; | |
1381 | ||
8113587c | 1382 | pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap); |
58c3a727 YZ |
1383 | if (!(cap & PCI_EXP_DEVCAP2_ARI)) |
1384 | return; | |
1385 | ||
8113587c | 1386 | pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl); |
58c3a727 | 1387 | ctrl |= PCI_EXP_DEVCTL2_ARI; |
8113587c | 1388 | pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl); |
58c3a727 | 1389 | |
8113587c | 1390 | bridge->ari_enabled = 1; |
58c3a727 YZ |
1391 | } |
1392 | ||
57c2cf71 BH |
1393 | /** |
1394 | * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge | |
1395 | * @dev: the PCI device | |
1396 | * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD) | |
1397 | * | |
1398 | * Perform INTx swizzling for a device behind one level of bridge. This is | |
1399 | * required by section 9.1 of the PCI-to-PCI bridge specification for devices | |
1400 | * behind bridges on add-in cards. | |
1401 | */ | |
1402 | u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin) | |
1403 | { | |
1404 | return (((pin - 1) + PCI_SLOT(dev->devfn)) % 4) + 1; | |
1405 | } | |
1406 | ||
1da177e4 LT |
1407 | int |
1408 | pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) | |
1409 | { | |
1410 | u8 pin; | |
1411 | ||
514d207d | 1412 | pin = dev->pin; |
1da177e4 LT |
1413 | if (!pin) |
1414 | return -1; | |
878f2e50 | 1415 | |
1da177e4 | 1416 | while (dev->bus->self) { |
57c2cf71 | 1417 | pin = pci_swizzle_interrupt_pin(dev, pin); |
1da177e4 LT |
1418 | dev = dev->bus->self; |
1419 | } | |
1420 | *bridge = dev; | |
1421 | return pin; | |
1422 | } | |
1423 | ||
1424 | /** | |
1425 | * pci_release_region - Release a PCI bar | |
1426 | * @pdev: PCI device whose resources were previously reserved by pci_request_region | |
1427 | * @bar: BAR to release | |
1428 | * | |
1429 | * Releases the PCI I/O and memory resources previously reserved by a | |
1430 | * successful call to pci_request_region. Call this function only | |
1431 | * after all use of the PCI regions has ceased. | |
1432 | */ | |
1433 | void pci_release_region(struct pci_dev *pdev, int bar) | |
1434 | { | |
9ac7849e TH |
1435 | struct pci_devres *dr; |
1436 | ||
1da177e4 LT |
1437 | if (pci_resource_len(pdev, bar) == 0) |
1438 | return; | |
1439 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) | |
1440 | release_region(pci_resource_start(pdev, bar), | |
1441 | pci_resource_len(pdev, bar)); | |
1442 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) | |
1443 | release_mem_region(pci_resource_start(pdev, bar), | |
1444 | pci_resource_len(pdev, bar)); | |
9ac7849e TH |
1445 | |
1446 | dr = find_pci_dr(pdev); | |
1447 | if (dr) | |
1448 | dr->region_mask &= ~(1 << bar); | |
1da177e4 LT |
1449 | } |
1450 | ||
1451 | /** | |
1452 | * pci_request_region - Reserved PCI I/O and memory resource | |
1453 | * @pdev: PCI device whose resources are to be reserved | |
1454 | * @bar: BAR to be reserved | |
1455 | * @res_name: Name to be associated with resource. | |
1456 | * | |
1457 | * Mark the PCI region associated with PCI device @pdev BR @bar as | |
1458 | * being reserved by owner @res_name. Do not access any | |
1459 | * address inside the PCI regions unless this call returns | |
1460 | * successfully. | |
1461 | * | |
1462 | * Returns 0 on success, or %EBUSY on error. A warning | |
1463 | * message is also printed on failure. | |
1464 | */ | |
e8de1481 AV |
1465 | static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name, |
1466 | int exclusive) | |
1da177e4 | 1467 | { |
9ac7849e TH |
1468 | struct pci_devres *dr; |
1469 | ||
1da177e4 LT |
1470 | if (pci_resource_len(pdev, bar) == 0) |
1471 | return 0; | |
1472 | ||
1473 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { | |
1474 | if (!request_region(pci_resource_start(pdev, bar), | |
1475 | pci_resource_len(pdev, bar), res_name)) | |
1476 | goto err_out; | |
1477 | } | |
1478 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { | |
e8de1481 AV |
1479 | if (!__request_mem_region(pci_resource_start(pdev, bar), |
1480 | pci_resource_len(pdev, bar), res_name, | |
1481 | exclusive)) | |
1da177e4 LT |
1482 | goto err_out; |
1483 | } | |
9ac7849e TH |
1484 | |
1485 | dr = find_pci_dr(pdev); | |
1486 | if (dr) | |
1487 | dr->region_mask |= 1 << bar; | |
1488 | ||
1da177e4 LT |
1489 | return 0; |
1490 | ||
1491 | err_out: | |
096e6f67 | 1492 | dev_warn(&pdev->dev, "BAR %d: can't reserve %s region %pR\n", |
e4ec7a00 JB |
1493 | bar, |
1494 | pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem", | |
096e6f67 | 1495 | &pdev->resource[bar]); |
1da177e4 LT |
1496 | return -EBUSY; |
1497 | } | |
1498 | ||
e8de1481 AV |
1499 | /** |
1500 | * pci_request_region - Reserved PCI I/O and memory resource | |
1501 | * @pdev: PCI device whose resources are to be reserved | |
1502 | * @bar: BAR to be reserved | |
1503 | * @res_name: Name to be associated with resource. | |
1504 | * | |
1505 | * Mark the PCI region associated with PCI device @pdev BR @bar as | |
1506 | * being reserved by owner @res_name. Do not access any | |
1507 | * address inside the PCI regions unless this call returns | |
1508 | * successfully. | |
1509 | * | |
1510 | * Returns 0 on success, or %EBUSY on error. A warning | |
1511 | * message is also printed on failure. | |
1512 | */ | |
1513 | int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) | |
1514 | { | |
1515 | return __pci_request_region(pdev, bar, res_name, 0); | |
1516 | } | |
1517 | ||
1518 | /** | |
1519 | * pci_request_region_exclusive - Reserved PCI I/O and memory resource | |
1520 | * @pdev: PCI device whose resources are to be reserved | |
1521 | * @bar: BAR to be reserved | |
1522 | * @res_name: Name to be associated with resource. | |
1523 | * | |
1524 | * Mark the PCI region associated with PCI device @pdev BR @bar as | |
1525 | * being reserved by owner @res_name. Do not access any | |
1526 | * address inside the PCI regions unless this call returns | |
1527 | * successfully. | |
1528 | * | |
1529 | * Returns 0 on success, or %EBUSY on error. A warning | |
1530 | * message is also printed on failure. | |
1531 | * | |
1532 | * The key difference that _exclusive makes it that userspace is | |
1533 | * explicitly not allowed to map the resource via /dev/mem or | |
1534 | * sysfs. | |
1535 | */ | |
1536 | int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name) | |
1537 | { | |
1538 | return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE); | |
1539 | } | |
c87deff7 HS |
1540 | /** |
1541 | * pci_release_selected_regions - Release selected PCI I/O and memory resources | |
1542 | * @pdev: PCI device whose resources were previously reserved | |
1543 | * @bars: Bitmask of BARs to be released | |
1544 | * | |
1545 | * Release selected PCI I/O and memory resources previously reserved. | |
1546 | * Call this function only after all use of the PCI regions has ceased. | |
1547 | */ | |
1548 | void pci_release_selected_regions(struct pci_dev *pdev, int bars) | |
1549 | { | |
1550 | int i; | |
1551 | ||
1552 | for (i = 0; i < 6; i++) | |
1553 | if (bars & (1 << i)) | |
1554 | pci_release_region(pdev, i); | |
1555 | } | |
1556 | ||
e8de1481 AV |
1557 | int __pci_request_selected_regions(struct pci_dev *pdev, int bars, |
1558 | const char *res_name, int excl) | |
c87deff7 HS |
1559 | { |
1560 | int i; | |
1561 | ||
1562 | for (i = 0; i < 6; i++) | |
1563 | if (bars & (1 << i)) | |
e8de1481 | 1564 | if (__pci_request_region(pdev, i, res_name, excl)) |
c87deff7 HS |
1565 | goto err_out; |
1566 | return 0; | |
1567 | ||
1568 | err_out: | |
1569 | while(--i >= 0) | |
1570 | if (bars & (1 << i)) | |
1571 | pci_release_region(pdev, i); | |
1572 | ||
1573 | return -EBUSY; | |
1574 | } | |
1da177e4 | 1575 | |
e8de1481 AV |
1576 | |
1577 | /** | |
1578 | * pci_request_selected_regions - Reserve selected PCI I/O and memory resources | |
1579 | * @pdev: PCI device whose resources are to be reserved | |
1580 | * @bars: Bitmask of BARs to be requested | |
1581 | * @res_name: Name to be associated with resource | |
1582 | */ | |
1583 | int pci_request_selected_regions(struct pci_dev *pdev, int bars, | |
1584 | const char *res_name) | |
1585 | { | |
1586 | return __pci_request_selected_regions(pdev, bars, res_name, 0); | |
1587 | } | |
1588 | ||
1589 | int pci_request_selected_regions_exclusive(struct pci_dev *pdev, | |
1590 | int bars, const char *res_name) | |
1591 | { | |
1592 | return __pci_request_selected_regions(pdev, bars, res_name, | |
1593 | IORESOURCE_EXCLUSIVE); | |
1594 | } | |
1595 | ||
1da177e4 LT |
1596 | /** |
1597 | * pci_release_regions - Release reserved PCI I/O and memory resources | |
1598 | * @pdev: PCI device whose resources were previously reserved by pci_request_regions | |
1599 | * | |
1600 | * Releases all PCI I/O and memory resources previously reserved by a | |
1601 | * successful call to pci_request_regions. Call this function only | |
1602 | * after all use of the PCI regions has ceased. | |
1603 | */ | |
1604 | ||
1605 | void pci_release_regions(struct pci_dev *pdev) | |
1606 | { | |
c87deff7 | 1607 | pci_release_selected_regions(pdev, (1 << 6) - 1); |
1da177e4 LT |
1608 | } |
1609 | ||
1610 | /** | |
1611 | * pci_request_regions - Reserved PCI I/O and memory resources | |
1612 | * @pdev: PCI device whose resources are to be reserved | |
1613 | * @res_name: Name to be associated with resource. | |
1614 | * | |
1615 | * Mark all PCI regions associated with PCI device @pdev as | |
1616 | * being reserved by owner @res_name. Do not access any | |
1617 | * address inside the PCI regions unless this call returns | |
1618 | * successfully. | |
1619 | * | |
1620 | * Returns 0 on success, or %EBUSY on error. A warning | |
1621 | * message is also printed on failure. | |
1622 | */ | |
3c990e92 | 1623 | int pci_request_regions(struct pci_dev *pdev, const char *res_name) |
1da177e4 | 1624 | { |
c87deff7 | 1625 | return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name); |
1da177e4 LT |
1626 | } |
1627 | ||
e8de1481 AV |
1628 | /** |
1629 | * pci_request_regions_exclusive - Reserved PCI I/O and memory resources | |
1630 | * @pdev: PCI device whose resources are to be reserved | |
1631 | * @res_name: Name to be associated with resource. | |
1632 | * | |
1633 | * Mark all PCI regions associated with PCI device @pdev as | |
1634 | * being reserved by owner @res_name. Do not access any | |
1635 | * address inside the PCI regions unless this call returns | |
1636 | * successfully. | |
1637 | * | |
1638 | * pci_request_regions_exclusive() will mark the region so that | |
1639 | * /dev/mem and the sysfs MMIO access will not be allowed. | |
1640 | * | |
1641 | * Returns 0 on success, or %EBUSY on error. A warning | |
1642 | * message is also printed on failure. | |
1643 | */ | |
1644 | int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name) | |
1645 | { | |
1646 | return pci_request_selected_regions_exclusive(pdev, | |
1647 | ((1 << 6) - 1), res_name); | |
1648 | } | |
1649 | ||
1650 | ||
1da177e4 LT |
1651 | /** |
1652 | * pci_set_master - enables bus-mastering for device dev | |
1653 | * @dev: the PCI device to enable | |
1654 | * | |
1655 | * Enables bus-mastering on the device and calls pcibios_set_master() | |
1656 | * to do the needed arch specific settings. | |
1657 | */ | |
1658 | void | |
1659 | pci_set_master(struct pci_dev *dev) | |
1660 | { | |
1661 | u16 cmd; | |
1662 | ||
1663 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1664 | if (! (cmd & PCI_COMMAND_MASTER)) { | |
80ccba11 | 1665 | dev_dbg(&dev->dev, "enabling bus mastering\n"); |
1da177e4 LT |
1666 | cmd |= PCI_COMMAND_MASTER; |
1667 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1668 | } | |
1669 | dev->is_busmaster = 1; | |
1670 | pcibios_set_master(dev); | |
1671 | } | |
1672 | ||
edb2d97e MW |
1673 | #ifdef PCI_DISABLE_MWI |
1674 | int pci_set_mwi(struct pci_dev *dev) | |
1675 | { | |
1676 | return 0; | |
1677 | } | |
1678 | ||
694625c0 RD |
1679 | int pci_try_set_mwi(struct pci_dev *dev) |
1680 | { | |
1681 | return 0; | |
1682 | } | |
1683 | ||
edb2d97e MW |
1684 | void pci_clear_mwi(struct pci_dev *dev) |
1685 | { | |
1686 | } | |
1687 | ||
1688 | #else | |
ebf5a248 MW |
1689 | |
1690 | #ifndef PCI_CACHE_LINE_BYTES | |
1691 | #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES | |
1692 | #endif | |
1693 | ||
1da177e4 | 1694 | /* This can be overridden by arch code. */ |
ebf5a248 MW |
1695 | /* Don't forget this is measured in 32-bit words, not bytes */ |
1696 | u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4; | |
1da177e4 LT |
1697 | |
1698 | /** | |
edb2d97e MW |
1699 | * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed |
1700 | * @dev: the PCI device for which MWI is to be enabled | |
1da177e4 | 1701 | * |
edb2d97e MW |
1702 | * Helper function for pci_set_mwi. |
1703 | * Originally copied from drivers/net/acenic.c. | |
1da177e4 LT |
1704 | * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. |
1705 | * | |
1706 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
1707 | */ | |
1708 | static int | |
edb2d97e | 1709 | pci_set_cacheline_size(struct pci_dev *dev) |
1da177e4 LT |
1710 | { |
1711 | u8 cacheline_size; | |
1712 | ||
1713 | if (!pci_cache_line_size) | |
1714 | return -EINVAL; /* The system doesn't support MWI. */ | |
1715 | ||
1716 | /* Validate current setting: the PCI_CACHE_LINE_SIZE must be | |
1717 | equal to or multiple of the right value. */ | |
1718 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
1719 | if (cacheline_size >= pci_cache_line_size && | |
1720 | (cacheline_size % pci_cache_line_size) == 0) | |
1721 | return 0; | |
1722 | ||
1723 | /* Write the correct value. */ | |
1724 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); | |
1725 | /* Read it back. */ | |
1726 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
1727 | if (cacheline_size == pci_cache_line_size) | |
1728 | return 0; | |
1729 | ||
80ccba11 BH |
1730 | dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not " |
1731 | "supported\n", pci_cache_line_size << 2); | |
1da177e4 LT |
1732 | |
1733 | return -EINVAL; | |
1734 | } | |
1da177e4 LT |
1735 | |
1736 | /** | |
1737 | * pci_set_mwi - enables memory-write-invalidate PCI transaction | |
1738 | * @dev: the PCI device for which MWI is enabled | |
1739 | * | |
694625c0 | 1740 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. |
1da177e4 LT |
1741 | * |
1742 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
1743 | */ | |
1744 | int | |
1745 | pci_set_mwi(struct pci_dev *dev) | |
1746 | { | |
1747 | int rc; | |
1748 | u16 cmd; | |
1749 | ||
edb2d97e | 1750 | rc = pci_set_cacheline_size(dev); |
1da177e4 LT |
1751 | if (rc) |
1752 | return rc; | |
1753 | ||
1754 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1755 | if (! (cmd & PCI_COMMAND_INVALIDATE)) { | |
80ccba11 | 1756 | dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n"); |
1da177e4 LT |
1757 | cmd |= PCI_COMMAND_INVALIDATE; |
1758 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1759 | } | |
1760 | ||
1761 | return 0; | |
1762 | } | |
1763 | ||
694625c0 RD |
1764 | /** |
1765 | * pci_try_set_mwi - enables memory-write-invalidate PCI transaction | |
1766 | * @dev: the PCI device for which MWI is enabled | |
1767 | * | |
1768 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. | |
1769 | * Callers are not required to check the return value. | |
1770 | * | |
1771 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
1772 | */ | |
1773 | int pci_try_set_mwi(struct pci_dev *dev) | |
1774 | { | |
1775 | int rc = pci_set_mwi(dev); | |
1776 | return rc; | |
1777 | } | |
1778 | ||
1da177e4 LT |
1779 | /** |
1780 | * pci_clear_mwi - disables Memory-Write-Invalidate for device dev | |
1781 | * @dev: the PCI device to disable | |
1782 | * | |
1783 | * Disables PCI Memory-Write-Invalidate transaction on the device | |
1784 | */ | |
1785 | void | |
1786 | pci_clear_mwi(struct pci_dev *dev) | |
1787 | { | |
1788 | u16 cmd; | |
1789 | ||
1790 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1791 | if (cmd & PCI_COMMAND_INVALIDATE) { | |
1792 | cmd &= ~PCI_COMMAND_INVALIDATE; | |
1793 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1794 | } | |
1795 | } | |
edb2d97e | 1796 | #endif /* ! PCI_DISABLE_MWI */ |
1da177e4 | 1797 | |
a04ce0ff BR |
1798 | /** |
1799 | * pci_intx - enables/disables PCI INTx for device dev | |
8f7020d3 RD |
1800 | * @pdev: the PCI device to operate on |
1801 | * @enable: boolean: whether to enable or disable PCI INTx | |
a04ce0ff BR |
1802 | * |
1803 | * Enables/disables PCI INTx for device dev | |
1804 | */ | |
1805 | void | |
1806 | pci_intx(struct pci_dev *pdev, int enable) | |
1807 | { | |
1808 | u16 pci_command, new; | |
1809 | ||
1810 | pci_read_config_word(pdev, PCI_COMMAND, &pci_command); | |
1811 | ||
1812 | if (enable) { | |
1813 | new = pci_command & ~PCI_COMMAND_INTX_DISABLE; | |
1814 | } else { | |
1815 | new = pci_command | PCI_COMMAND_INTX_DISABLE; | |
1816 | } | |
1817 | ||
1818 | if (new != pci_command) { | |
9ac7849e TH |
1819 | struct pci_devres *dr; |
1820 | ||
2fd9d74b | 1821 | pci_write_config_word(pdev, PCI_COMMAND, new); |
9ac7849e TH |
1822 | |
1823 | dr = find_pci_dr(pdev); | |
1824 | if (dr && !dr->restore_intx) { | |
1825 | dr->restore_intx = 1; | |
1826 | dr->orig_intx = !enable; | |
1827 | } | |
a04ce0ff BR |
1828 | } |
1829 | } | |
1830 | ||
f5f2b131 EB |
1831 | /** |
1832 | * pci_msi_off - disables any msi or msix capabilities | |
8d7d86e9 | 1833 | * @dev: the PCI device to operate on |
f5f2b131 EB |
1834 | * |
1835 | * If you want to use msi see pci_enable_msi and friends. | |
1836 | * This is a lower level primitive that allows us to disable | |
1837 | * msi operation at the device level. | |
1838 | */ | |
1839 | void pci_msi_off(struct pci_dev *dev) | |
1840 | { | |
1841 | int pos; | |
1842 | u16 control; | |
1843 | ||
1844 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
1845 | if (pos) { | |
1846 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
1847 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
1848 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
1849 | } | |
1850 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
1851 | if (pos) { | |
1852 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
1853 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
1854 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
1855 | } | |
1856 | } | |
1857 | ||
1da177e4 LT |
1858 | #ifndef HAVE_ARCH_PCI_SET_DMA_MASK |
1859 | /* | |
1860 | * These can be overridden by arch-specific implementations | |
1861 | */ | |
1862 | int | |
1863 | pci_set_dma_mask(struct pci_dev *dev, u64 mask) | |
1864 | { | |
1865 | if (!pci_dma_supported(dev, mask)) | |
1866 | return -EIO; | |
1867 | ||
1868 | dev->dma_mask = mask; | |
1869 | ||
1870 | return 0; | |
1871 | } | |
1872 | ||
1da177e4 LT |
1873 | int |
1874 | pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) | |
1875 | { | |
1876 | if (!pci_dma_supported(dev, mask)) | |
1877 | return -EIO; | |
1878 | ||
1879 | dev->dev.coherent_dma_mask = mask; | |
1880 | ||
1881 | return 0; | |
1882 | } | |
1883 | #endif | |
c87deff7 | 1884 | |
4d57cdfa FT |
1885 | #ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE |
1886 | int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size) | |
1887 | { | |
1888 | return dma_set_max_seg_size(&dev->dev, size); | |
1889 | } | |
1890 | EXPORT_SYMBOL(pci_set_dma_max_seg_size); | |
1891 | #endif | |
1892 | ||
59fc67de FT |
1893 | #ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY |
1894 | int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask) | |
1895 | { | |
1896 | return dma_set_seg_boundary(&dev->dev, mask); | |
1897 | } | |
1898 | EXPORT_SYMBOL(pci_set_dma_seg_boundary); | |
1899 | #endif | |
1900 | ||
d91cdc74 | 1901 | static int __pcie_flr(struct pci_dev *dev, int probe) |
8dd7f803 SY |
1902 | { |
1903 | u16 status; | |
1904 | u32 cap; | |
1905 | int exppos = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
1906 | ||
1907 | if (!exppos) | |
1908 | return -ENOTTY; | |
1909 | pci_read_config_dword(dev, exppos + PCI_EXP_DEVCAP, &cap); | |
1910 | if (!(cap & PCI_EXP_DEVCAP_FLR)) | |
1911 | return -ENOTTY; | |
1912 | ||
d91cdc74 SY |
1913 | if (probe) |
1914 | return 0; | |
1915 | ||
8dd7f803 SY |
1916 | pci_block_user_cfg_access(dev); |
1917 | ||
1918 | /* Wait for Transaction Pending bit clean */ | |
1919 | msleep(100); | |
1920 | pci_read_config_word(dev, exppos + PCI_EXP_DEVSTA, &status); | |
1921 | if (status & PCI_EXP_DEVSTA_TRPND) { | |
1922 | dev_info(&dev->dev, "Busy after 100ms while trying to reset; " | |
1923 | "sleeping for 1 second\n"); | |
1924 | ssleep(1); | |
1925 | pci_read_config_word(dev, exppos + PCI_EXP_DEVSTA, &status); | |
1926 | if (status & PCI_EXP_DEVSTA_TRPND) | |
1927 | dev_info(&dev->dev, "Still busy after 1s; " | |
1928 | "proceeding with reset anyway\n"); | |
1929 | } | |
1930 | ||
1931 | pci_write_config_word(dev, exppos + PCI_EXP_DEVCTL, | |
1932 | PCI_EXP_DEVCTL_BCR_FLR); | |
1933 | mdelay(100); | |
1934 | ||
1935 | pci_unblock_user_cfg_access(dev); | |
1936 | return 0; | |
1937 | } | |
d91cdc74 | 1938 | |
1ca88797 SY |
1939 | static int __pci_af_flr(struct pci_dev *dev, int probe) |
1940 | { | |
1941 | int cappos = pci_find_capability(dev, PCI_CAP_ID_AF); | |
1942 | u8 status; | |
1943 | u8 cap; | |
1944 | ||
1945 | if (!cappos) | |
1946 | return -ENOTTY; | |
1947 | pci_read_config_byte(dev, cappos + PCI_AF_CAP, &cap); | |
1948 | if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) | |
1949 | return -ENOTTY; | |
1950 | ||
1951 | if (probe) | |
1952 | return 0; | |
1953 | ||
1954 | pci_block_user_cfg_access(dev); | |
1955 | ||
1956 | /* Wait for Transaction Pending bit clean */ | |
1957 | msleep(100); | |
1958 | pci_read_config_byte(dev, cappos + PCI_AF_STATUS, &status); | |
1959 | if (status & PCI_AF_STATUS_TP) { | |
1960 | dev_info(&dev->dev, "Busy after 100ms while trying to" | |
1961 | " reset; sleeping for 1 second\n"); | |
1962 | ssleep(1); | |
1963 | pci_read_config_byte(dev, | |
1964 | cappos + PCI_AF_STATUS, &status); | |
1965 | if (status & PCI_AF_STATUS_TP) | |
1966 | dev_info(&dev->dev, "Still busy after 1s; " | |
1967 | "proceeding with reset anyway\n"); | |
1968 | } | |
1969 | pci_write_config_byte(dev, cappos + PCI_AF_CTRL, PCI_AF_CTRL_FLR); | |
1970 | mdelay(100); | |
1971 | ||
1972 | pci_unblock_user_cfg_access(dev); | |
1973 | return 0; | |
1974 | } | |
1975 | ||
d91cdc74 SY |
1976 | static int __pci_reset_function(struct pci_dev *pdev, int probe) |
1977 | { | |
1978 | int res; | |
1979 | ||
1980 | res = __pcie_flr(pdev, probe); | |
1981 | if (res != -ENOTTY) | |
1982 | return res; | |
1983 | ||
1ca88797 SY |
1984 | res = __pci_af_flr(pdev, probe); |
1985 | if (res != -ENOTTY) | |
1986 | return res; | |
1987 | ||
d91cdc74 SY |
1988 | return res; |
1989 | } | |
1990 | ||
1991 | /** | |
1992 | * pci_execute_reset_function() - Reset a PCI device function | |
1993 | * @dev: Device function to reset | |
1994 | * | |
1995 | * Some devices allow an individual function to be reset without affecting | |
1996 | * other functions in the same device. The PCI device must be responsive | |
1997 | * to PCI config space in order to use this function. | |
1998 | * | |
1999 | * The device function is presumed to be unused when this function is called. | |
2000 | * Resetting the device will make the contents of PCI configuration space | |
2001 | * random, so any caller of this must be prepared to reinitialise the | |
2002 | * device including MSI, bus mastering, BARs, decoding IO and memory spaces, | |
2003 | * etc. | |
2004 | * | |
2005 | * Returns 0 if the device function was successfully reset or -ENOTTY if the | |
2006 | * device doesn't support resetting a single function. | |
2007 | */ | |
2008 | int pci_execute_reset_function(struct pci_dev *dev) | |
2009 | { | |
2010 | return __pci_reset_function(dev, 0); | |
2011 | } | |
8dd7f803 SY |
2012 | EXPORT_SYMBOL_GPL(pci_execute_reset_function); |
2013 | ||
2014 | /** | |
2015 | * pci_reset_function() - quiesce and reset a PCI device function | |
2016 | * @dev: Device function to reset | |
2017 | * | |
2018 | * Some devices allow an individual function to be reset without affecting | |
2019 | * other functions in the same device. The PCI device must be responsive | |
2020 | * to PCI config space in order to use this function. | |
2021 | * | |
2022 | * This function does not just reset the PCI portion of a device, but | |
2023 | * clears all the state associated with the device. This function differs | |
2024 | * from pci_execute_reset_function in that it saves and restores device state | |
2025 | * over the reset. | |
2026 | * | |
2027 | * Returns 0 if the device function was successfully reset or -ENOTTY if the | |
2028 | * device doesn't support resetting a single function. | |
2029 | */ | |
2030 | int pci_reset_function(struct pci_dev *dev) | |
2031 | { | |
d91cdc74 | 2032 | int r = __pci_reset_function(dev, 1); |
8dd7f803 | 2033 | |
d91cdc74 SY |
2034 | if (r < 0) |
2035 | return r; | |
8dd7f803 | 2036 | |
1df8fb3d | 2037 | if (!dev->msi_enabled && !dev->msix_enabled && dev->irq != 0) |
8dd7f803 SY |
2038 | disable_irq(dev->irq); |
2039 | pci_save_state(dev); | |
2040 | ||
2041 | pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE); | |
2042 | ||
2043 | r = pci_execute_reset_function(dev); | |
2044 | ||
2045 | pci_restore_state(dev); | |
1df8fb3d | 2046 | if (!dev->msi_enabled && !dev->msix_enabled && dev->irq != 0) |
8dd7f803 SY |
2047 | enable_irq(dev->irq); |
2048 | ||
2049 | return r; | |
2050 | } | |
2051 | EXPORT_SYMBOL_GPL(pci_reset_function); | |
2052 | ||
d556ad4b PO |
2053 | /** |
2054 | * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count | |
2055 | * @dev: PCI device to query | |
2056 | * | |
2057 | * Returns mmrbc: maximum designed memory read count in bytes | |
2058 | * or appropriate error value. | |
2059 | */ | |
2060 | int pcix_get_max_mmrbc(struct pci_dev *dev) | |
2061 | { | |
b7b095c1 | 2062 | int err, cap; |
d556ad4b PO |
2063 | u32 stat; |
2064 | ||
2065 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
2066 | if (!cap) | |
2067 | return -EINVAL; | |
2068 | ||
2069 | err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat); | |
2070 | if (err) | |
2071 | return -EINVAL; | |
2072 | ||
b7b095c1 | 2073 | return (stat & PCI_X_STATUS_MAX_READ) >> 12; |
d556ad4b PO |
2074 | } |
2075 | EXPORT_SYMBOL(pcix_get_max_mmrbc); | |
2076 | ||
2077 | /** | |
2078 | * pcix_get_mmrbc - get PCI-X maximum memory read byte count | |
2079 | * @dev: PCI device to query | |
2080 | * | |
2081 | * Returns mmrbc: maximum memory read count in bytes | |
2082 | * or appropriate error value. | |
2083 | */ | |
2084 | int pcix_get_mmrbc(struct pci_dev *dev) | |
2085 | { | |
2086 | int ret, cap; | |
2087 | u32 cmd; | |
2088 | ||
2089 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
2090 | if (!cap) | |
2091 | return -EINVAL; | |
2092 | ||
2093 | ret = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd); | |
2094 | if (!ret) | |
2095 | ret = 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2); | |
2096 | ||
2097 | return ret; | |
2098 | } | |
2099 | EXPORT_SYMBOL(pcix_get_mmrbc); | |
2100 | ||
2101 | /** | |
2102 | * pcix_set_mmrbc - set PCI-X maximum memory read byte count | |
2103 | * @dev: PCI device to query | |
2104 | * @mmrbc: maximum memory read count in bytes | |
2105 | * valid values are 512, 1024, 2048, 4096 | |
2106 | * | |
2107 | * If possible sets maximum memory read byte count, some bridges have erratas | |
2108 | * that prevent this. | |
2109 | */ | |
2110 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) | |
2111 | { | |
2112 | int cap, err = -EINVAL; | |
2113 | u32 stat, cmd, v, o; | |
2114 | ||
229f5afd | 2115 | if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc)) |
d556ad4b PO |
2116 | goto out; |
2117 | ||
2118 | v = ffs(mmrbc) - 10; | |
2119 | ||
2120 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
2121 | if (!cap) | |
2122 | goto out; | |
2123 | ||
2124 | err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat); | |
2125 | if (err) | |
2126 | goto out; | |
2127 | ||
2128 | if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21) | |
2129 | return -E2BIG; | |
2130 | ||
2131 | err = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd); | |
2132 | if (err) | |
2133 | goto out; | |
2134 | ||
2135 | o = (cmd & PCI_X_CMD_MAX_READ) >> 2; | |
2136 | if (o != v) { | |
2137 | if (v > o && dev->bus && | |
2138 | (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) | |
2139 | return -EIO; | |
2140 | ||
2141 | cmd &= ~PCI_X_CMD_MAX_READ; | |
2142 | cmd |= v << 2; | |
2143 | err = pci_write_config_dword(dev, cap + PCI_X_CMD, cmd); | |
2144 | } | |
2145 | out: | |
2146 | return err; | |
2147 | } | |
2148 | EXPORT_SYMBOL(pcix_set_mmrbc); | |
2149 | ||
2150 | /** | |
2151 | * pcie_get_readrq - get PCI Express read request size | |
2152 | * @dev: PCI device to query | |
2153 | * | |
2154 | * Returns maximum memory read request in bytes | |
2155 | * or appropriate error value. | |
2156 | */ | |
2157 | int pcie_get_readrq(struct pci_dev *dev) | |
2158 | { | |
2159 | int ret, cap; | |
2160 | u16 ctl; | |
2161 | ||
2162 | cap = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
2163 | if (!cap) | |
2164 | return -EINVAL; | |
2165 | ||
2166 | ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); | |
2167 | if (!ret) | |
2168 | ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12); | |
2169 | ||
2170 | return ret; | |
2171 | } | |
2172 | EXPORT_SYMBOL(pcie_get_readrq); | |
2173 | ||
2174 | /** | |
2175 | * pcie_set_readrq - set PCI Express maximum memory read request | |
2176 | * @dev: PCI device to query | |
42e61f4a | 2177 | * @rq: maximum memory read count in bytes |
d556ad4b PO |
2178 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
2179 | * | |
2180 | * If possible sets maximum read byte count | |
2181 | */ | |
2182 | int pcie_set_readrq(struct pci_dev *dev, int rq) | |
2183 | { | |
2184 | int cap, err = -EINVAL; | |
2185 | u16 ctl, v; | |
2186 | ||
229f5afd | 2187 | if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) |
d556ad4b PO |
2188 | goto out; |
2189 | ||
2190 | v = (ffs(rq) - 8) << 12; | |
2191 | ||
2192 | cap = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
2193 | if (!cap) | |
2194 | goto out; | |
2195 | ||
2196 | err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); | |
2197 | if (err) | |
2198 | goto out; | |
2199 | ||
2200 | if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) { | |
2201 | ctl &= ~PCI_EXP_DEVCTL_READRQ; | |
2202 | ctl |= v; | |
2203 | err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl); | |
2204 | } | |
2205 | ||
2206 | out: | |
2207 | return err; | |
2208 | } | |
2209 | EXPORT_SYMBOL(pcie_set_readrq); | |
2210 | ||
c87deff7 HS |
2211 | /** |
2212 | * pci_select_bars - Make BAR mask from the type of resource | |
f95d882d | 2213 | * @dev: the PCI device for which BAR mask is made |
c87deff7 HS |
2214 | * @flags: resource type mask to be selected |
2215 | * | |
2216 | * This helper routine makes bar mask from the type of resource. | |
2217 | */ | |
2218 | int pci_select_bars(struct pci_dev *dev, unsigned long flags) | |
2219 | { | |
2220 | int i, bars = 0; | |
2221 | for (i = 0; i < PCI_NUM_RESOURCES; i++) | |
2222 | if (pci_resource_flags(dev, i) & flags) | |
2223 | bars |= (1 << i); | |
2224 | return bars; | |
2225 | } | |
2226 | ||
613e7ed6 YZ |
2227 | /** |
2228 | * pci_resource_bar - get position of the BAR associated with a resource | |
2229 | * @dev: the PCI device | |
2230 | * @resno: the resource number | |
2231 | * @type: the BAR type to be filled in | |
2232 | * | |
2233 | * Returns BAR position in config space, or 0 if the BAR is invalid. | |
2234 | */ | |
2235 | int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type) | |
2236 | { | |
2237 | if (resno < PCI_ROM_RESOURCE) { | |
2238 | *type = pci_bar_unknown; | |
2239 | return PCI_BASE_ADDRESS_0 + 4 * resno; | |
2240 | } else if (resno == PCI_ROM_RESOURCE) { | |
2241 | *type = pci_bar_mem32; | |
2242 | return dev->rom_base_reg; | |
2243 | } | |
2244 | ||
2245 | dev_err(&dev->dev, "BAR: invalid resource #%d\n", resno); | |
2246 | return 0; | |
2247 | } | |
2248 | ||
32a2eea7 JG |
2249 | static void __devinit pci_no_domains(void) |
2250 | { | |
2251 | #ifdef CONFIG_PCI_DOMAINS | |
2252 | pci_domains_supported = 0; | |
2253 | #endif | |
2254 | } | |
2255 | ||
0ef5f8f6 AP |
2256 | /** |
2257 | * pci_ext_cfg_enabled - can we access extended PCI config space? | |
2258 | * @dev: The PCI device of the root bridge. | |
2259 | * | |
2260 | * Returns 1 if we can access PCI extended config space (offsets | |
2261 | * greater than 0xff). This is the default implementation. Architecture | |
2262 | * implementations can override this. | |
2263 | */ | |
2264 | int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev) | |
2265 | { | |
2266 | return 1; | |
2267 | } | |
2268 | ||
1da177e4 LT |
2269 | static int __devinit pci_init(void) |
2270 | { | |
2271 | struct pci_dev *dev = NULL; | |
2272 | ||
2273 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
2274 | pci_fixup_device(pci_fixup_final, dev); | |
2275 | } | |
d389fec6 | 2276 | |
1da177e4 LT |
2277 | return 0; |
2278 | } | |
2279 | ||
ad04d31e | 2280 | static int __init pci_setup(char *str) |
1da177e4 LT |
2281 | { |
2282 | while (str) { | |
2283 | char *k = strchr(str, ','); | |
2284 | if (k) | |
2285 | *k++ = 0; | |
2286 | if (*str && (str = pcibios_setup(str)) && *str) { | |
309e57df MW |
2287 | if (!strcmp(str, "nomsi")) { |
2288 | pci_no_msi(); | |
7f785763 RD |
2289 | } else if (!strcmp(str, "noaer")) { |
2290 | pci_no_aer(); | |
32a2eea7 JG |
2291 | } else if (!strcmp(str, "nodomains")) { |
2292 | pci_no_domains(); | |
4516a618 AN |
2293 | } else if (!strncmp(str, "cbiosize=", 9)) { |
2294 | pci_cardbus_io_size = memparse(str + 9, &str); | |
2295 | } else if (!strncmp(str, "cbmemsize=", 10)) { | |
2296 | pci_cardbus_mem_size = memparse(str + 10, &str); | |
309e57df MW |
2297 | } else { |
2298 | printk(KERN_ERR "PCI: Unknown option `%s'\n", | |
2299 | str); | |
2300 | } | |
1da177e4 LT |
2301 | } |
2302 | str = k; | |
2303 | } | |
0637a70a | 2304 | return 0; |
1da177e4 | 2305 | } |
0637a70a | 2306 | early_param("pci", pci_setup); |
1da177e4 LT |
2307 | |
2308 | device_initcall(pci_init); | |
1da177e4 | 2309 | |
0b62e13b | 2310 | EXPORT_SYMBOL(pci_reenable_device); |
b718989d BH |
2311 | EXPORT_SYMBOL(pci_enable_device_io); |
2312 | EXPORT_SYMBOL(pci_enable_device_mem); | |
1da177e4 | 2313 | EXPORT_SYMBOL(pci_enable_device); |
9ac7849e TH |
2314 | EXPORT_SYMBOL(pcim_enable_device); |
2315 | EXPORT_SYMBOL(pcim_pin_device); | |
1da177e4 | 2316 | EXPORT_SYMBOL(pci_disable_device); |
1da177e4 LT |
2317 | EXPORT_SYMBOL(pci_find_capability); |
2318 | EXPORT_SYMBOL(pci_bus_find_capability); | |
2319 | EXPORT_SYMBOL(pci_release_regions); | |
2320 | EXPORT_SYMBOL(pci_request_regions); | |
e8de1481 | 2321 | EXPORT_SYMBOL(pci_request_regions_exclusive); |
1da177e4 LT |
2322 | EXPORT_SYMBOL(pci_release_region); |
2323 | EXPORT_SYMBOL(pci_request_region); | |
e8de1481 | 2324 | EXPORT_SYMBOL(pci_request_region_exclusive); |
c87deff7 HS |
2325 | EXPORT_SYMBOL(pci_release_selected_regions); |
2326 | EXPORT_SYMBOL(pci_request_selected_regions); | |
e8de1481 | 2327 | EXPORT_SYMBOL(pci_request_selected_regions_exclusive); |
1da177e4 LT |
2328 | EXPORT_SYMBOL(pci_set_master); |
2329 | EXPORT_SYMBOL(pci_set_mwi); | |
694625c0 | 2330 | EXPORT_SYMBOL(pci_try_set_mwi); |
1da177e4 | 2331 | EXPORT_SYMBOL(pci_clear_mwi); |
a04ce0ff | 2332 | EXPORT_SYMBOL_GPL(pci_intx); |
1da177e4 | 2333 | EXPORT_SYMBOL(pci_set_dma_mask); |
1da177e4 LT |
2334 | EXPORT_SYMBOL(pci_set_consistent_dma_mask); |
2335 | EXPORT_SYMBOL(pci_assign_resource); | |
2336 | EXPORT_SYMBOL(pci_find_parent_resource); | |
c87deff7 | 2337 | EXPORT_SYMBOL(pci_select_bars); |
1da177e4 LT |
2338 | |
2339 | EXPORT_SYMBOL(pci_set_power_state); | |
2340 | EXPORT_SYMBOL(pci_save_state); | |
2341 | EXPORT_SYMBOL(pci_restore_state); | |
e5899e1b | 2342 | EXPORT_SYMBOL(pci_pme_capable); |
5a6c9b60 | 2343 | EXPORT_SYMBOL(pci_pme_active); |
1da177e4 | 2344 | EXPORT_SYMBOL(pci_enable_wake); |
0235c4fc | 2345 | EXPORT_SYMBOL(pci_wake_from_d3); |
e5899e1b | 2346 | EXPORT_SYMBOL(pci_target_state); |
404cc2d8 RW |
2347 | EXPORT_SYMBOL(pci_prepare_to_sleep); |
2348 | EXPORT_SYMBOL(pci_back_from_sleep); | |
f7bdd12d | 2349 | EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state); |
1da177e4 | 2350 |