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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * PCI Bus Services, see include/linux/pci.h for further explanation. |
3 | * | |
4 | * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, | |
5 | * David Mosberger-Tang | |
6 | * | |
7 | * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> | |
8 | */ | |
9 | ||
10 | #include <linux/kernel.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/pci.h> | |
075c1771 | 14 | #include <linux/pm.h> |
1da177e4 LT |
15 | #include <linux/module.h> |
16 | #include <linux/spinlock.h> | |
4e57b681 | 17 | #include <linux/string.h> |
229f5afd | 18 | #include <linux/log2.h> |
7d715a6c | 19 | #include <linux/pci-aspm.h> |
1da177e4 | 20 | #include <asm/dma.h> /* isa_dma_bridge_buggy */ |
bc56b9e0 | 21 | #include "pci.h" |
1da177e4 | 22 | |
ffadcc2f | 23 | unsigned int pci_pm_d3_delay = 10; |
1da177e4 | 24 | |
32a2eea7 JG |
25 | #ifdef CONFIG_PCI_DOMAINS |
26 | int pci_domains_supported = 1; | |
27 | #endif | |
28 | ||
4516a618 AN |
29 | #define DEFAULT_CARDBUS_IO_SIZE (256) |
30 | #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024) | |
31 | /* pci=cbmemsize=nnM,cbiosize=nn can override this */ | |
32 | unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE; | |
33 | unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE; | |
34 | ||
1da177e4 LT |
35 | /** |
36 | * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children | |
37 | * @bus: pointer to PCI bus structure to search | |
38 | * | |
39 | * Given a PCI bus, returns the highest PCI bus number present in the set | |
40 | * including the given PCI bus and its list of child PCI buses. | |
41 | */ | |
96bde06a | 42 | unsigned char pci_bus_max_busnr(struct pci_bus* bus) |
1da177e4 LT |
43 | { |
44 | struct list_head *tmp; | |
45 | unsigned char max, n; | |
46 | ||
b82db5ce | 47 | max = bus->subordinate; |
1da177e4 LT |
48 | list_for_each(tmp, &bus->children) { |
49 | n = pci_bus_max_busnr(pci_bus_b(tmp)); | |
50 | if(n > max) | |
51 | max = n; | |
52 | } | |
53 | return max; | |
54 | } | |
b82db5ce | 55 | EXPORT_SYMBOL_GPL(pci_bus_max_busnr); |
1da177e4 | 56 | |
b82db5ce | 57 | #if 0 |
1da177e4 LT |
58 | /** |
59 | * pci_max_busnr - returns maximum PCI bus number | |
60 | * | |
61 | * Returns the highest PCI bus number present in the system global list of | |
62 | * PCI buses. | |
63 | */ | |
64 | unsigned char __devinit | |
65 | pci_max_busnr(void) | |
66 | { | |
67 | struct pci_bus *bus = NULL; | |
68 | unsigned char max, n; | |
69 | ||
70 | max = 0; | |
71 | while ((bus = pci_find_next_bus(bus)) != NULL) { | |
72 | n = pci_bus_max_busnr(bus); | |
73 | if(n > max) | |
74 | max = n; | |
75 | } | |
76 | return max; | |
77 | } | |
78 | ||
54c762fe AB |
79 | #endif /* 0 */ |
80 | ||
687d5fe3 ME |
81 | #define PCI_FIND_CAP_TTL 48 |
82 | ||
83 | static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, | |
84 | u8 pos, int cap, int *ttl) | |
24a4e377 RD |
85 | { |
86 | u8 id; | |
24a4e377 | 87 | |
687d5fe3 | 88 | while ((*ttl)--) { |
24a4e377 RD |
89 | pci_bus_read_config_byte(bus, devfn, pos, &pos); |
90 | if (pos < 0x40) | |
91 | break; | |
92 | pos &= ~3; | |
93 | pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, | |
94 | &id); | |
95 | if (id == 0xff) | |
96 | break; | |
97 | if (id == cap) | |
98 | return pos; | |
99 | pos += PCI_CAP_LIST_NEXT; | |
100 | } | |
101 | return 0; | |
102 | } | |
103 | ||
687d5fe3 ME |
104 | static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, |
105 | u8 pos, int cap) | |
106 | { | |
107 | int ttl = PCI_FIND_CAP_TTL; | |
108 | ||
109 | return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); | |
110 | } | |
111 | ||
24a4e377 RD |
112 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) |
113 | { | |
114 | return __pci_find_next_cap(dev->bus, dev->devfn, | |
115 | pos + PCI_CAP_LIST_NEXT, cap); | |
116 | } | |
117 | EXPORT_SYMBOL_GPL(pci_find_next_capability); | |
118 | ||
d3bac118 ME |
119 | static int __pci_bus_find_cap_start(struct pci_bus *bus, |
120 | unsigned int devfn, u8 hdr_type) | |
1da177e4 LT |
121 | { |
122 | u16 status; | |
1da177e4 LT |
123 | |
124 | pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); | |
125 | if (!(status & PCI_STATUS_CAP_LIST)) | |
126 | return 0; | |
127 | ||
128 | switch (hdr_type) { | |
129 | case PCI_HEADER_TYPE_NORMAL: | |
130 | case PCI_HEADER_TYPE_BRIDGE: | |
d3bac118 | 131 | return PCI_CAPABILITY_LIST; |
1da177e4 | 132 | case PCI_HEADER_TYPE_CARDBUS: |
d3bac118 | 133 | return PCI_CB_CAPABILITY_LIST; |
1da177e4 LT |
134 | default: |
135 | return 0; | |
136 | } | |
d3bac118 ME |
137 | |
138 | return 0; | |
1da177e4 LT |
139 | } |
140 | ||
141 | /** | |
142 | * pci_find_capability - query for devices' capabilities | |
143 | * @dev: PCI device to query | |
144 | * @cap: capability code | |
145 | * | |
146 | * Tell if a device supports a given PCI capability. | |
147 | * Returns the address of the requested capability structure within the | |
148 | * device's PCI configuration space or 0 in case the device does not | |
149 | * support it. Possible values for @cap: | |
150 | * | |
151 | * %PCI_CAP_ID_PM Power Management | |
152 | * %PCI_CAP_ID_AGP Accelerated Graphics Port | |
153 | * %PCI_CAP_ID_VPD Vital Product Data | |
154 | * %PCI_CAP_ID_SLOTID Slot Identification | |
155 | * %PCI_CAP_ID_MSI Message Signalled Interrupts | |
156 | * %PCI_CAP_ID_CHSWP CompactPCI HotSwap | |
157 | * %PCI_CAP_ID_PCIX PCI-X | |
158 | * %PCI_CAP_ID_EXP PCI Express | |
159 | */ | |
160 | int pci_find_capability(struct pci_dev *dev, int cap) | |
161 | { | |
d3bac118 ME |
162 | int pos; |
163 | ||
164 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
165 | if (pos) | |
166 | pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); | |
167 | ||
168 | return pos; | |
1da177e4 LT |
169 | } |
170 | ||
171 | /** | |
172 | * pci_bus_find_capability - query for devices' capabilities | |
173 | * @bus: the PCI bus to query | |
174 | * @devfn: PCI device to query | |
175 | * @cap: capability code | |
176 | * | |
177 | * Like pci_find_capability() but works for pci devices that do not have a | |
178 | * pci_dev structure set up yet. | |
179 | * | |
180 | * Returns the address of the requested capability structure within the | |
181 | * device's PCI configuration space or 0 in case the device does not | |
182 | * support it. | |
183 | */ | |
184 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) | |
185 | { | |
d3bac118 | 186 | int pos; |
1da177e4 LT |
187 | u8 hdr_type; |
188 | ||
189 | pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); | |
190 | ||
d3bac118 ME |
191 | pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f); |
192 | if (pos) | |
193 | pos = __pci_find_next_cap(bus, devfn, pos, cap); | |
194 | ||
195 | return pos; | |
1da177e4 LT |
196 | } |
197 | ||
198 | /** | |
199 | * pci_find_ext_capability - Find an extended capability | |
200 | * @dev: PCI device to query | |
201 | * @cap: capability code | |
202 | * | |
203 | * Returns the address of the requested extended capability structure | |
204 | * within the device's PCI configuration space or 0 if the device does | |
205 | * not support it. Possible values for @cap: | |
206 | * | |
207 | * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting | |
208 | * %PCI_EXT_CAP_ID_VC Virtual Channel | |
209 | * %PCI_EXT_CAP_ID_DSN Device Serial Number | |
210 | * %PCI_EXT_CAP_ID_PWR Power Budgeting | |
211 | */ | |
212 | int pci_find_ext_capability(struct pci_dev *dev, int cap) | |
213 | { | |
214 | u32 header; | |
215 | int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */ | |
216 | int pos = 0x100; | |
217 | ||
218 | if (dev->cfg_size <= 256) | |
219 | return 0; | |
220 | ||
221 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
222 | return 0; | |
223 | ||
224 | /* | |
225 | * If we have no capabilities, this is indicated by cap ID, | |
226 | * cap version and next pointer all being 0. | |
227 | */ | |
228 | if (header == 0) | |
229 | return 0; | |
230 | ||
231 | while (ttl-- > 0) { | |
232 | if (PCI_EXT_CAP_ID(header) == cap) | |
233 | return pos; | |
234 | ||
235 | pos = PCI_EXT_CAP_NEXT(header); | |
236 | if (pos < 0x100) | |
237 | break; | |
238 | ||
239 | if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) | |
240 | break; | |
241 | } | |
242 | ||
243 | return 0; | |
244 | } | |
3a720d72 | 245 | EXPORT_SYMBOL_GPL(pci_find_ext_capability); |
1da177e4 | 246 | |
687d5fe3 ME |
247 | static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) |
248 | { | |
249 | int rc, ttl = PCI_FIND_CAP_TTL; | |
250 | u8 cap, mask; | |
251 | ||
252 | if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST) | |
253 | mask = HT_3BIT_CAP_MASK; | |
254 | else | |
255 | mask = HT_5BIT_CAP_MASK; | |
256 | ||
257 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, | |
258 | PCI_CAP_ID_HT, &ttl); | |
259 | while (pos) { | |
260 | rc = pci_read_config_byte(dev, pos + 3, &cap); | |
261 | if (rc != PCIBIOS_SUCCESSFUL) | |
262 | return 0; | |
263 | ||
264 | if ((cap & mask) == ht_cap) | |
265 | return pos; | |
266 | ||
47a4d5be BG |
267 | pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, |
268 | pos + PCI_CAP_LIST_NEXT, | |
687d5fe3 ME |
269 | PCI_CAP_ID_HT, &ttl); |
270 | } | |
271 | ||
272 | return 0; | |
273 | } | |
274 | /** | |
275 | * pci_find_next_ht_capability - query a device's Hypertransport capabilities | |
276 | * @dev: PCI device to query | |
277 | * @pos: Position from which to continue searching | |
278 | * @ht_cap: Hypertransport capability code | |
279 | * | |
280 | * To be used in conjunction with pci_find_ht_capability() to search for | |
281 | * all capabilities matching @ht_cap. @pos should always be a value returned | |
282 | * from pci_find_ht_capability(). | |
283 | * | |
284 | * NB. To be 100% safe against broken PCI devices, the caller should take | |
285 | * steps to avoid an infinite loop. | |
286 | */ | |
287 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap) | |
288 | { | |
289 | return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap); | |
290 | } | |
291 | EXPORT_SYMBOL_GPL(pci_find_next_ht_capability); | |
292 | ||
293 | /** | |
294 | * pci_find_ht_capability - query a device's Hypertransport capabilities | |
295 | * @dev: PCI device to query | |
296 | * @ht_cap: Hypertransport capability code | |
297 | * | |
298 | * Tell if a device supports a given Hypertransport capability. | |
299 | * Returns an address within the device's PCI configuration space | |
300 | * or 0 in case the device does not support the request capability. | |
301 | * The address points to the PCI capability, of type PCI_CAP_ID_HT, | |
302 | * which has a Hypertransport capability matching @ht_cap. | |
303 | */ | |
304 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap) | |
305 | { | |
306 | int pos; | |
307 | ||
308 | pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); | |
309 | if (pos) | |
310 | pos = __pci_find_next_ht_cap(dev, pos, ht_cap); | |
311 | ||
312 | return pos; | |
313 | } | |
314 | EXPORT_SYMBOL_GPL(pci_find_ht_capability); | |
315 | ||
1da177e4 LT |
316 | /** |
317 | * pci_find_parent_resource - return resource region of parent bus of given region | |
318 | * @dev: PCI device structure contains resources to be searched | |
319 | * @res: child resource record for which parent is sought | |
320 | * | |
321 | * For given resource region of given device, return the resource | |
322 | * region of parent bus the given region is contained in or where | |
323 | * it should be allocated from. | |
324 | */ | |
325 | struct resource * | |
326 | pci_find_parent_resource(const struct pci_dev *dev, struct resource *res) | |
327 | { | |
328 | const struct pci_bus *bus = dev->bus; | |
329 | int i; | |
330 | struct resource *best = NULL; | |
331 | ||
332 | for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) { | |
333 | struct resource *r = bus->resource[i]; | |
334 | if (!r) | |
335 | continue; | |
336 | if (res->start && !(res->start >= r->start && res->end <= r->end)) | |
337 | continue; /* Not contained */ | |
338 | if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM)) | |
339 | continue; /* Wrong type */ | |
340 | if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) | |
341 | return r; /* Exact match */ | |
342 | if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH)) | |
343 | best = r; /* Approximating prefetchable by non-prefetchable */ | |
344 | } | |
345 | return best; | |
346 | } | |
347 | ||
064b53db JL |
348 | /** |
349 | * pci_restore_bars - restore a devices BAR values (e.g. after wake-up) | |
350 | * @dev: PCI device to have its BARs restored | |
351 | * | |
352 | * Restore the BAR values for a given device, so as to make it | |
353 | * accessible by its driver. | |
354 | */ | |
ad668599 | 355 | static void |
064b53db JL |
356 | pci_restore_bars(struct pci_dev *dev) |
357 | { | |
358 | int i, numres; | |
359 | ||
360 | switch (dev->hdr_type) { | |
361 | case PCI_HEADER_TYPE_NORMAL: | |
362 | numres = 6; | |
363 | break; | |
364 | case PCI_HEADER_TYPE_BRIDGE: | |
365 | numres = 2; | |
366 | break; | |
367 | case PCI_HEADER_TYPE_CARDBUS: | |
368 | numres = 1; | |
369 | break; | |
370 | default: | |
371 | /* Should never get here, but just in case... */ | |
372 | return; | |
373 | } | |
374 | ||
375 | for (i = 0; i < numres; i ++) | |
376 | pci_update_resource(dev, &dev->resource[i], i); | |
377 | } | |
378 | ||
961d9120 RW |
379 | static struct pci_platform_pm_ops *pci_platform_pm; |
380 | ||
381 | int pci_set_platform_pm(struct pci_platform_pm_ops *ops) | |
382 | { | |
eb9d0fe4 RW |
383 | if (!ops->is_manageable || !ops->set_state || !ops->choose_state |
384 | || !ops->sleep_wake || !ops->can_wakeup) | |
961d9120 RW |
385 | return -EINVAL; |
386 | pci_platform_pm = ops; | |
387 | return 0; | |
388 | } | |
389 | ||
390 | static inline bool platform_pci_power_manageable(struct pci_dev *dev) | |
391 | { | |
392 | return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false; | |
393 | } | |
394 | ||
395 | static inline int platform_pci_set_power_state(struct pci_dev *dev, | |
396 | pci_power_t t) | |
397 | { | |
398 | return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS; | |
399 | } | |
400 | ||
401 | static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev) | |
402 | { | |
403 | return pci_platform_pm ? | |
404 | pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR; | |
405 | } | |
8f7020d3 | 406 | |
eb9d0fe4 RW |
407 | static inline bool platform_pci_can_wakeup(struct pci_dev *dev) |
408 | { | |
409 | return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false; | |
410 | } | |
411 | ||
412 | static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable) | |
413 | { | |
414 | return pci_platform_pm ? | |
415 | pci_platform_pm->sleep_wake(dev, enable) : -ENODEV; | |
416 | } | |
417 | ||
1da177e4 | 418 | /** |
44e4e66e RW |
419 | * pci_raw_set_power_state - Use PCI PM registers to set the power state of |
420 | * given PCI device | |
421 | * @dev: PCI device to handle. | |
422 | * @pm: PCI PM capability offset of the device. | |
423 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. | |
1da177e4 | 424 | * |
44e4e66e RW |
425 | * RETURN VALUE: |
426 | * -EINVAL if the requested state is invalid. | |
427 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
428 | * wrong version, or device doesn't support the requested state. | |
429 | * 0 if device already is in the requested state. | |
430 | * 0 if device's power state has been successfully changed. | |
1da177e4 | 431 | */ |
44e4e66e RW |
432 | static int |
433 | pci_raw_set_power_state(struct pci_dev *dev, int pm, pci_power_t state) | |
1da177e4 | 434 | { |
1da177e4 | 435 | u16 pmcsr, pmc; |
44e4e66e | 436 | bool need_restore = false; |
1da177e4 | 437 | |
cca03dec AL |
438 | if (!pm) |
439 | return -EIO; | |
440 | ||
44e4e66e RW |
441 | if (state < PCI_D0 || state > PCI_D3hot) |
442 | return -EINVAL; | |
443 | ||
1da177e4 LT |
444 | /* Validate current state: |
445 | * Can enter D0 from any state, but if we can only go deeper | |
446 | * to sleep if we're already in a low power state | |
447 | */ | |
44e4e66e RW |
448 | if (dev->current_state == state) { |
449 | /* we're already there */ | |
450 | return 0; | |
451 | } else if (state != PCI_D0 && dev->current_state <= PCI_D3cold | |
452 | && dev->current_state > state) { | |
80ccba11 BH |
453 | dev_err(&dev->dev, "invalid power transition " |
454 | "(from state %d to %d)\n", dev->current_state, state); | |
1da177e4 | 455 | return -EINVAL; |
44e4e66e | 456 | } |
1da177e4 | 457 | |
44e4e66e | 458 | pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc); |
ffadcc2f | 459 | |
3fe9d19f | 460 | if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { |
44e4e66e RW |
461 | dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n", |
462 | pmc & PCI_PM_CAP_VER_MASK); | |
1da177e4 LT |
463 | return -EIO; |
464 | } | |
465 | ||
466 | /* check if this device supports the desired state */ | |
44e4e66e RW |
467 | if ((state == PCI_D1 && !(pmc & PCI_PM_CAP_D1)) |
468 | || (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2))) | |
3fe9d19f | 469 | return -EIO; |
1da177e4 | 470 | |
064b53db JL |
471 | pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr); |
472 | ||
32a36585 | 473 | /* If we're (effectively) in D3, force entire word to 0. |
1da177e4 LT |
474 | * This doesn't affect PME_Status, disables PME_En, and |
475 | * sets PowerState to 0. | |
476 | */ | |
32a36585 | 477 | switch (dev->current_state) { |
d3535fbb JL |
478 | case PCI_D0: |
479 | case PCI_D1: | |
480 | case PCI_D2: | |
481 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
482 | pmcsr |= state; | |
483 | break; | |
32a36585 JL |
484 | case PCI_UNKNOWN: /* Boot-up */ |
485 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot | |
486 | && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) | |
44e4e66e | 487 | need_restore = true; |
32a36585 | 488 | /* Fall-through: force to D0 */ |
32a36585 | 489 | default: |
d3535fbb | 490 | pmcsr = 0; |
32a36585 | 491 | break; |
1da177e4 LT |
492 | } |
493 | ||
494 | /* enter specified state */ | |
495 | pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr); | |
496 | ||
497 | /* Mandatory power management transition delays */ | |
498 | /* see PCI PM 1.1 5.6.1 table 18 */ | |
499 | if (state == PCI_D3hot || dev->current_state == PCI_D3hot) | |
ffadcc2f | 500 | msleep(pci_pm_d3_delay); |
1da177e4 LT |
501 | else if (state == PCI_D2 || dev->current_state == PCI_D2) |
502 | udelay(200); | |
1da177e4 | 503 | |
b913100d | 504 | dev->current_state = state; |
064b53db JL |
505 | |
506 | /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT | |
507 | * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning | |
508 | * from D3hot to D0 _may_ perform an internal reset, thereby | |
509 | * going to "D0 Uninitialized" rather than "D0 Initialized". | |
510 | * For example, at least some versions of the 3c905B and the | |
511 | * 3c556B exhibit this behaviour. | |
512 | * | |
513 | * At least some laptop BIOSen (e.g. the Thinkpad T21) leave | |
514 | * devices in a D3hot state at boot. Consequently, we need to | |
515 | * restore at least the BARs so that the device will be | |
516 | * accessible to its driver. | |
517 | */ | |
518 | if (need_restore) | |
519 | pci_restore_bars(dev); | |
520 | ||
7d715a6c SL |
521 | if (dev->bus->self) |
522 | pcie_aspm_pm_state_change(dev->bus->self); | |
523 | ||
1da177e4 LT |
524 | return 0; |
525 | } | |
526 | ||
44e4e66e RW |
527 | /** |
528 | * pci_update_current_state - Read PCI power state of given device from its | |
529 | * PCI PM registers and cache it | |
530 | * @dev: PCI device to handle. | |
531 | * @pm: PCI PM capability offset of the device. | |
532 | */ | |
533 | static void pci_update_current_state(struct pci_dev *dev, int pm) | |
534 | { | |
535 | if (pm) { | |
536 | u16 pmcsr; | |
537 | ||
538 | pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr); | |
539 | dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); | |
540 | } | |
541 | } | |
542 | ||
543 | /** | |
544 | * pci_set_power_state - Set the power state of a PCI device | |
545 | * @dev: PCI device to handle. | |
546 | * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. | |
547 | * | |
548 | * Transition a device to a new power state, using the platform formware and/or | |
549 | * the device's PCI PM registers. | |
550 | * | |
551 | * RETURN VALUE: | |
552 | * -EINVAL if the requested state is invalid. | |
553 | * -EIO if device does not support PCI PM or its PM capabilities register has a | |
554 | * wrong version, or device doesn't support the requested state. | |
555 | * 0 if device already is in the requested state. | |
556 | * 0 if device's power state has been successfully changed. | |
557 | */ | |
558 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state) | |
559 | { | |
560 | int pm, error; | |
561 | ||
562 | /* bound the state we're entering */ | |
563 | if (state > PCI_D3hot) | |
564 | state = PCI_D3hot; | |
565 | else if (state < PCI_D0) | |
566 | state = PCI_D0; | |
567 | else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) | |
568 | /* | |
569 | * If the device or the parent bridge do not support PCI PM, | |
570 | * ignore the request if we're doing anything other than putting | |
571 | * it into D0 (which would only happen on boot). | |
572 | */ | |
573 | return 0; | |
574 | ||
575 | /* Find PCI PM capability in the list */ | |
576 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
577 | ||
578 | if (state == PCI_D0 && platform_pci_power_manageable(dev)) { | |
579 | /* | |
580 | * Allow the platform to change the state, for example via ACPI | |
581 | * _PR0, _PS0 and some such, but do not trust it. | |
582 | */ | |
583 | int ret = platform_pci_set_power_state(dev, PCI_D0); | |
584 | if (!ret) | |
585 | pci_update_current_state(dev, pm); | |
586 | } | |
587 | ||
588 | error = pci_raw_set_power_state(dev, pm, state); | |
589 | ||
590 | if (state > PCI_D0 && platform_pci_power_manageable(dev)) { | |
591 | /* Allow the platform to finalize the transition */ | |
592 | int ret = platform_pci_set_power_state(dev, state); | |
593 | if (!ret) { | |
594 | pci_update_current_state(dev, pm); | |
595 | error = 0; | |
596 | } | |
597 | } | |
598 | ||
599 | return error; | |
600 | } | |
601 | ||
1da177e4 LT |
602 | /** |
603 | * pci_choose_state - Choose the power state of a PCI device | |
604 | * @dev: PCI device to be suspended | |
605 | * @state: target sleep state for the whole system. This is the value | |
606 | * that is passed to suspend() function. | |
607 | * | |
608 | * Returns PCI power state suitable for given device and given system | |
609 | * message. | |
610 | */ | |
611 | ||
612 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) | |
613 | { | |
ab826ca4 | 614 | pci_power_t ret; |
0f64474b | 615 | |
1da177e4 LT |
616 | if (!pci_find_capability(dev, PCI_CAP_ID_PM)) |
617 | return PCI_D0; | |
618 | ||
961d9120 RW |
619 | ret = platform_pci_choose_state(dev); |
620 | if (ret != PCI_POWER_ERROR) | |
621 | return ret; | |
ca078bae PM |
622 | |
623 | switch (state.event) { | |
624 | case PM_EVENT_ON: | |
625 | return PCI_D0; | |
626 | case PM_EVENT_FREEZE: | |
b887d2e6 DB |
627 | case PM_EVENT_PRETHAW: |
628 | /* REVISIT both freeze and pre-thaw "should" use D0 */ | |
ca078bae | 629 | case PM_EVENT_SUSPEND: |
3a2d5b70 | 630 | case PM_EVENT_HIBERNATE: |
ca078bae | 631 | return PCI_D3hot; |
1da177e4 | 632 | default: |
80ccba11 BH |
633 | dev_info(&dev->dev, "unrecognized suspend event %d\n", |
634 | state.event); | |
1da177e4 LT |
635 | BUG(); |
636 | } | |
637 | return PCI_D0; | |
638 | } | |
639 | ||
640 | EXPORT_SYMBOL(pci_choose_state); | |
641 | ||
b56a5a23 MT |
642 | static int pci_save_pcie_state(struct pci_dev *dev) |
643 | { | |
644 | int pos, i = 0; | |
645 | struct pci_cap_saved_state *save_state; | |
646 | u16 *cap; | |
017fc480 | 647 | int found = 0; |
b56a5a23 MT |
648 | |
649 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
650 | if (pos <= 0) | |
651 | return 0; | |
652 | ||
9f35575d EB |
653 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); |
654 | if (!save_state) | |
655 | save_state = kzalloc(sizeof(*save_state) + sizeof(u16) * 4, GFP_KERNEL); | |
017fc480 SL |
656 | else |
657 | found = 1; | |
b56a5a23 | 658 | if (!save_state) { |
80ccba11 | 659 | dev_err(&dev->dev, "out of memory in pci_save_pcie_state\n"); |
b56a5a23 MT |
660 | return -ENOMEM; |
661 | } | |
662 | cap = (u16 *)&save_state->data[0]; | |
663 | ||
664 | pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]); | |
665 | pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]); | |
666 | pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]); | |
667 | pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]); | |
ec0a3a27 | 668 | save_state->cap_nr = PCI_CAP_ID_EXP; |
017fc480 SL |
669 | if (!found) |
670 | pci_add_saved_cap(dev, save_state); | |
b56a5a23 MT |
671 | return 0; |
672 | } | |
673 | ||
674 | static void pci_restore_pcie_state(struct pci_dev *dev) | |
675 | { | |
676 | int i = 0, pos; | |
677 | struct pci_cap_saved_state *save_state; | |
678 | u16 *cap; | |
679 | ||
680 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); | |
681 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
682 | if (!save_state || pos <= 0) | |
683 | return; | |
684 | cap = (u16 *)&save_state->data[0]; | |
685 | ||
686 | pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]); | |
687 | pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]); | |
688 | pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]); | |
689 | pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]); | |
b56a5a23 MT |
690 | } |
691 | ||
cc692a5f SH |
692 | |
693 | static int pci_save_pcix_state(struct pci_dev *dev) | |
694 | { | |
695 | int pos, i = 0; | |
696 | struct pci_cap_saved_state *save_state; | |
697 | u16 *cap; | |
017fc480 | 698 | int found = 0; |
cc692a5f SH |
699 | |
700 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
701 | if (pos <= 0) | |
702 | return 0; | |
703 | ||
f34303de | 704 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); |
9f35575d EB |
705 | if (!save_state) |
706 | save_state = kzalloc(sizeof(*save_state) + sizeof(u16), GFP_KERNEL); | |
017fc480 SL |
707 | else |
708 | found = 1; | |
cc692a5f | 709 | if (!save_state) { |
80ccba11 | 710 | dev_err(&dev->dev, "out of memory in pci_save_pcie_state\n"); |
cc692a5f SH |
711 | return -ENOMEM; |
712 | } | |
713 | cap = (u16 *)&save_state->data[0]; | |
714 | ||
715 | pci_read_config_word(dev, pos + PCI_X_CMD, &cap[i++]); | |
ec0a3a27 | 716 | save_state->cap_nr = PCI_CAP_ID_PCIX; |
017fc480 SL |
717 | if (!found) |
718 | pci_add_saved_cap(dev, save_state); | |
cc692a5f SH |
719 | return 0; |
720 | } | |
721 | ||
722 | static void pci_restore_pcix_state(struct pci_dev *dev) | |
723 | { | |
724 | int i = 0, pos; | |
725 | struct pci_cap_saved_state *save_state; | |
726 | u16 *cap; | |
727 | ||
728 | save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); | |
729 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
730 | if (!save_state || pos <= 0) | |
731 | return; | |
732 | cap = (u16 *)&save_state->data[0]; | |
733 | ||
734 | pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]); | |
cc692a5f SH |
735 | } |
736 | ||
737 | ||
1da177e4 LT |
738 | /** |
739 | * pci_save_state - save the PCI configuration space of a device before suspending | |
740 | * @dev: - PCI device that we're dealing with | |
1da177e4 LT |
741 | */ |
742 | int | |
743 | pci_save_state(struct pci_dev *dev) | |
744 | { | |
745 | int i; | |
746 | /* XXX: 100% dword access ok here? */ | |
747 | for (i = 0; i < 16; i++) | |
748 | pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]); | |
b56a5a23 MT |
749 | if ((i = pci_save_pcie_state(dev)) != 0) |
750 | return i; | |
cc692a5f SH |
751 | if ((i = pci_save_pcix_state(dev)) != 0) |
752 | return i; | |
1da177e4 LT |
753 | return 0; |
754 | } | |
755 | ||
756 | /** | |
757 | * pci_restore_state - Restore the saved state of a PCI device | |
758 | * @dev: - PCI device that we're dealing with | |
1da177e4 LT |
759 | */ |
760 | int | |
761 | pci_restore_state(struct pci_dev *dev) | |
762 | { | |
763 | int i; | |
b4482a4b | 764 | u32 val; |
1da177e4 | 765 | |
b56a5a23 MT |
766 | /* PCI Express register must be restored first */ |
767 | pci_restore_pcie_state(dev); | |
768 | ||
8b8c8d28 YL |
769 | /* |
770 | * The Base Address register should be programmed before the command | |
771 | * register(s) | |
772 | */ | |
773 | for (i = 15; i >= 0; i--) { | |
04d9c1a1 DJ |
774 | pci_read_config_dword(dev, i * 4, &val); |
775 | if (val != dev->saved_config_space[i]) { | |
80ccba11 BH |
776 | dev_printk(KERN_DEBUG, &dev->dev, "restoring config " |
777 | "space at offset %#x (was %#x, writing %#x)\n", | |
778 | i, val, (int)dev->saved_config_space[i]); | |
04d9c1a1 DJ |
779 | pci_write_config_dword(dev,i * 4, |
780 | dev->saved_config_space[i]); | |
781 | } | |
782 | } | |
cc692a5f | 783 | pci_restore_pcix_state(dev); |
41017f0c | 784 | pci_restore_msi_state(dev); |
8fed4b65 | 785 | |
1da177e4 LT |
786 | return 0; |
787 | } | |
788 | ||
38cc1302 HS |
789 | static int do_pci_enable_device(struct pci_dev *dev, int bars) |
790 | { | |
791 | int err; | |
792 | ||
793 | err = pci_set_power_state(dev, PCI_D0); | |
794 | if (err < 0 && err != -EIO) | |
795 | return err; | |
796 | err = pcibios_enable_device(dev, bars); | |
797 | if (err < 0) | |
798 | return err; | |
799 | pci_fixup_device(pci_fixup_enable, dev); | |
800 | ||
801 | return 0; | |
802 | } | |
803 | ||
804 | /** | |
0b62e13b | 805 | * pci_reenable_device - Resume abandoned device |
38cc1302 HS |
806 | * @dev: PCI device to be resumed |
807 | * | |
808 | * Note this function is a backend of pci_default_resume and is not supposed | |
809 | * to be called by normal code, write proper resume handler and use it instead. | |
810 | */ | |
0b62e13b | 811 | int pci_reenable_device(struct pci_dev *dev) |
38cc1302 HS |
812 | { |
813 | if (atomic_read(&dev->enable_cnt)) | |
814 | return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); | |
815 | return 0; | |
816 | } | |
817 | ||
b718989d BH |
818 | static int __pci_enable_device_flags(struct pci_dev *dev, |
819 | resource_size_t flags) | |
1da177e4 LT |
820 | { |
821 | int err; | |
b718989d | 822 | int i, bars = 0; |
1da177e4 | 823 | |
9fb625c3 HS |
824 | if (atomic_add_return(1, &dev->enable_cnt) > 1) |
825 | return 0; /* already enabled */ | |
826 | ||
b718989d BH |
827 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) |
828 | if (dev->resource[i].flags & flags) | |
829 | bars |= (1 << i); | |
830 | ||
38cc1302 | 831 | err = do_pci_enable_device(dev, bars); |
95a62965 | 832 | if (err < 0) |
38cc1302 | 833 | atomic_dec(&dev->enable_cnt); |
9fb625c3 | 834 | return err; |
1da177e4 LT |
835 | } |
836 | ||
b718989d BH |
837 | /** |
838 | * pci_enable_device_io - Initialize a device for use with IO space | |
839 | * @dev: PCI device to be initialized | |
840 | * | |
841 | * Initialize device before it's used by a driver. Ask low-level code | |
842 | * to enable I/O resources. Wake up the device if it was suspended. | |
843 | * Beware, this function can fail. | |
844 | */ | |
845 | int pci_enable_device_io(struct pci_dev *dev) | |
846 | { | |
847 | return __pci_enable_device_flags(dev, IORESOURCE_IO); | |
848 | } | |
849 | ||
850 | /** | |
851 | * pci_enable_device_mem - Initialize a device for use with Memory space | |
852 | * @dev: PCI device to be initialized | |
853 | * | |
854 | * Initialize device before it's used by a driver. Ask low-level code | |
855 | * to enable Memory resources. Wake up the device if it was suspended. | |
856 | * Beware, this function can fail. | |
857 | */ | |
858 | int pci_enable_device_mem(struct pci_dev *dev) | |
859 | { | |
860 | return __pci_enable_device_flags(dev, IORESOURCE_MEM); | |
861 | } | |
862 | ||
bae94d02 IPG |
863 | /** |
864 | * pci_enable_device - Initialize device before it's used by a driver. | |
865 | * @dev: PCI device to be initialized | |
866 | * | |
867 | * Initialize device before it's used by a driver. Ask low-level code | |
868 | * to enable I/O and memory. Wake up the device if it was suspended. | |
869 | * Beware, this function can fail. | |
870 | * | |
871 | * Note we don't actually enable the device many times if we call | |
872 | * this function repeatedly (we just increment the count). | |
873 | */ | |
874 | int pci_enable_device(struct pci_dev *dev) | |
875 | { | |
b718989d | 876 | return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO); |
bae94d02 IPG |
877 | } |
878 | ||
9ac7849e TH |
879 | /* |
880 | * Managed PCI resources. This manages device on/off, intx/msi/msix | |
881 | * on/off and BAR regions. pci_dev itself records msi/msix status, so | |
882 | * there's no need to track it separately. pci_devres is initialized | |
883 | * when a device is enabled using managed PCI device enable interface. | |
884 | */ | |
885 | struct pci_devres { | |
7f375f32 TH |
886 | unsigned int enabled:1; |
887 | unsigned int pinned:1; | |
9ac7849e TH |
888 | unsigned int orig_intx:1; |
889 | unsigned int restore_intx:1; | |
890 | u32 region_mask; | |
891 | }; | |
892 | ||
893 | static void pcim_release(struct device *gendev, void *res) | |
894 | { | |
895 | struct pci_dev *dev = container_of(gendev, struct pci_dev, dev); | |
896 | struct pci_devres *this = res; | |
897 | int i; | |
898 | ||
899 | if (dev->msi_enabled) | |
900 | pci_disable_msi(dev); | |
901 | if (dev->msix_enabled) | |
902 | pci_disable_msix(dev); | |
903 | ||
904 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) | |
905 | if (this->region_mask & (1 << i)) | |
906 | pci_release_region(dev, i); | |
907 | ||
908 | if (this->restore_intx) | |
909 | pci_intx(dev, this->orig_intx); | |
910 | ||
7f375f32 | 911 | if (this->enabled && !this->pinned) |
9ac7849e TH |
912 | pci_disable_device(dev); |
913 | } | |
914 | ||
915 | static struct pci_devres * get_pci_dr(struct pci_dev *pdev) | |
916 | { | |
917 | struct pci_devres *dr, *new_dr; | |
918 | ||
919 | dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
920 | if (dr) | |
921 | return dr; | |
922 | ||
923 | new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL); | |
924 | if (!new_dr) | |
925 | return NULL; | |
926 | return devres_get(&pdev->dev, new_dr, NULL, NULL); | |
927 | } | |
928 | ||
929 | static struct pci_devres * find_pci_dr(struct pci_dev *pdev) | |
930 | { | |
931 | if (pci_is_managed(pdev)) | |
932 | return devres_find(&pdev->dev, pcim_release, NULL, NULL); | |
933 | return NULL; | |
934 | } | |
935 | ||
936 | /** | |
937 | * pcim_enable_device - Managed pci_enable_device() | |
938 | * @pdev: PCI device to be initialized | |
939 | * | |
940 | * Managed pci_enable_device(). | |
941 | */ | |
942 | int pcim_enable_device(struct pci_dev *pdev) | |
943 | { | |
944 | struct pci_devres *dr; | |
945 | int rc; | |
946 | ||
947 | dr = get_pci_dr(pdev); | |
948 | if (unlikely(!dr)) | |
949 | return -ENOMEM; | |
b95d58ea TH |
950 | if (dr->enabled) |
951 | return 0; | |
9ac7849e TH |
952 | |
953 | rc = pci_enable_device(pdev); | |
954 | if (!rc) { | |
955 | pdev->is_managed = 1; | |
7f375f32 | 956 | dr->enabled = 1; |
9ac7849e TH |
957 | } |
958 | return rc; | |
959 | } | |
960 | ||
961 | /** | |
962 | * pcim_pin_device - Pin managed PCI device | |
963 | * @pdev: PCI device to pin | |
964 | * | |
965 | * Pin managed PCI device @pdev. Pinned device won't be disabled on | |
966 | * driver detach. @pdev must have been enabled with | |
967 | * pcim_enable_device(). | |
968 | */ | |
969 | void pcim_pin_device(struct pci_dev *pdev) | |
970 | { | |
971 | struct pci_devres *dr; | |
972 | ||
973 | dr = find_pci_dr(pdev); | |
7f375f32 | 974 | WARN_ON(!dr || !dr->enabled); |
9ac7849e | 975 | if (dr) |
7f375f32 | 976 | dr->pinned = 1; |
9ac7849e TH |
977 | } |
978 | ||
1da177e4 LT |
979 | /** |
980 | * pcibios_disable_device - disable arch specific PCI resources for device dev | |
981 | * @dev: the PCI device to disable | |
982 | * | |
983 | * Disables architecture specific PCI resources for the device. This | |
984 | * is the default implementation. Architecture implementations can | |
985 | * override this. | |
986 | */ | |
987 | void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {} | |
988 | ||
989 | /** | |
990 | * pci_disable_device - Disable PCI device after use | |
991 | * @dev: PCI device to be disabled | |
992 | * | |
993 | * Signal to the system that the PCI device is not in use by the system | |
994 | * anymore. This only involves disabling PCI bus-mastering, if active. | |
bae94d02 IPG |
995 | * |
996 | * Note we don't actually disable the device until all callers of | |
997 | * pci_device_enable() have called pci_device_disable(). | |
1da177e4 LT |
998 | */ |
999 | void | |
1000 | pci_disable_device(struct pci_dev *dev) | |
1001 | { | |
9ac7849e | 1002 | struct pci_devres *dr; |
1da177e4 | 1003 | u16 pci_command; |
99dc804d | 1004 | |
9ac7849e TH |
1005 | dr = find_pci_dr(dev); |
1006 | if (dr) | |
7f375f32 | 1007 | dr->enabled = 0; |
9ac7849e | 1008 | |
bae94d02 IPG |
1009 | if (atomic_sub_return(1, &dev->enable_cnt) != 0) |
1010 | return; | |
1011 | ||
1da177e4 LT |
1012 | pci_read_config_word(dev, PCI_COMMAND, &pci_command); |
1013 | if (pci_command & PCI_COMMAND_MASTER) { | |
1014 | pci_command &= ~PCI_COMMAND_MASTER; | |
1015 | pci_write_config_word(dev, PCI_COMMAND, pci_command); | |
1016 | } | |
ceb43744 | 1017 | dev->is_busmaster = 0; |
1da177e4 LT |
1018 | |
1019 | pcibios_disable_device(dev); | |
1020 | } | |
1021 | ||
f7bdd12d BK |
1022 | /** |
1023 | * pcibios_set_pcie_reset_state - set reset state for device dev | |
1024 | * @dev: the PCI-E device reset | |
1025 | * @state: Reset state to enter into | |
1026 | * | |
1027 | * | |
1028 | * Sets the PCI-E reset state for the device. This is the default | |
1029 | * implementation. Architecture implementations can override this. | |
1030 | */ | |
1031 | int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev, | |
1032 | enum pcie_reset_state state) | |
1033 | { | |
1034 | return -EINVAL; | |
1035 | } | |
1036 | ||
1037 | /** | |
1038 | * pci_set_pcie_reset_state - set reset state for device dev | |
1039 | * @dev: the PCI-E device reset | |
1040 | * @state: Reset state to enter into | |
1041 | * | |
1042 | * | |
1043 | * Sets the PCI reset state for the device. | |
1044 | */ | |
1045 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) | |
1046 | { | |
1047 | return pcibios_set_pcie_reset_state(dev, state); | |
1048 | } | |
1049 | ||
eb9d0fe4 RW |
1050 | /** |
1051 | * pci_pme_capable - check the capability of PCI device to generate PME# | |
1052 | * @dev: PCI device to handle. | |
1053 | * @pm: PCI PM capability offset of the device. | |
1054 | * @state: PCI state from which device will issue PME#. | |
1055 | */ | |
1056 | static bool pci_pme_capable(struct pci_dev *dev, int pm, pci_power_t state) | |
1057 | { | |
1058 | u16 pmc; | |
1059 | ||
1060 | if (!pm) | |
1061 | return false; | |
1062 | ||
1063 | /* Check device's ability to generate PME# from given state */ | |
1064 | pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc); | |
1065 | ||
1066 | pmc &= PCI_PM_CAP_PME_MASK; | |
1067 | pmc >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */ | |
1068 | ||
1069 | return !!(pmc & (1 << state)); | |
1070 | } | |
1071 | ||
1072 | /** | |
1073 | * pci_pme_active - enable or disable PCI device's PME# function | |
1074 | * @dev: PCI device to handle. | |
1075 | * @pm: PCI PM capability offset of the device. | |
1076 | * @enable: 'true' to enable PME# generation; 'false' to disable it. | |
1077 | * | |
1078 | * The caller must verify that the device is capable of generating PME# before | |
1079 | * calling this function with @enable equal to 'true'. | |
1080 | */ | |
1081 | static void pci_pme_active(struct pci_dev *dev, int pm, bool enable) | |
1082 | { | |
1083 | u16 pmcsr; | |
1084 | ||
1085 | if (!pm) | |
1086 | return; | |
1087 | ||
1088 | pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr); | |
1089 | /* Clear PME_Status by writing 1 to it and enable PME# */ | |
1090 | pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; | |
1091 | if (!enable) | |
1092 | pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; | |
1093 | ||
1094 | pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr); | |
1095 | ||
1096 | dev_printk(KERN_INFO, &dev->dev, "PME# %s\n", | |
1097 | enable ? "enabled" : "disabled"); | |
1098 | } | |
1099 | ||
1da177e4 | 1100 | /** |
075c1771 DB |
1101 | * pci_enable_wake - enable PCI device as wakeup event source |
1102 | * @dev: PCI device affected | |
1103 | * @state: PCI state from which device will issue wakeup events | |
1104 | * @enable: True to enable event generation; false to disable | |
1105 | * | |
1106 | * This enables the device as a wakeup event source, or disables it. | |
1107 | * When such events involves platform-specific hooks, those hooks are | |
1108 | * called automatically by this routine. | |
1109 | * | |
1110 | * Devices with legacy power management (no standard PCI PM capabilities) | |
eb9d0fe4 | 1111 | * always require such platform hooks. |
075c1771 | 1112 | * |
eb9d0fe4 RW |
1113 | * RETURN VALUE: |
1114 | * 0 is returned on success | |
1115 | * -EINVAL is returned if device is not supposed to wake up the system | |
1116 | * Error code depending on the platform is returned if both the platform and | |
1117 | * the native mechanism fail to enable the generation of wake-up events | |
1da177e4 LT |
1118 | */ |
1119 | int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable) | |
1120 | { | |
1121 | int pm; | |
eb9d0fe4 RW |
1122 | int error = 0; |
1123 | bool pme_done = false; | |
075c1771 | 1124 | |
eb9d0fe4 RW |
1125 | if (!device_may_wakeup(&dev->dev)) |
1126 | return -EINVAL; | |
1da177e4 | 1127 | |
eb9d0fe4 RW |
1128 | /* |
1129 | * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don | |
1130 | * Anderson we should be doing PME# wake enable followed by ACPI wake | |
1131 | * enable. To disable wake-up we call the platform first, for symmetry. | |
075c1771 | 1132 | */ |
1da177e4 | 1133 | |
eb9d0fe4 RW |
1134 | if (!enable && platform_pci_can_wakeup(dev)) |
1135 | error = platform_pci_sleep_wake(dev, false); | |
1da177e4 | 1136 | |
eb9d0fe4 RW |
1137 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); |
1138 | if (!enable || pci_pme_capable(dev, pm, state)) { | |
1139 | pci_pme_active(dev, pm, enable); | |
1140 | pme_done = true; | |
075c1771 | 1141 | } |
1da177e4 | 1142 | |
eb9d0fe4 RW |
1143 | if (enable && platform_pci_can_wakeup(dev)) |
1144 | error = platform_pci_sleep_wake(dev, true); | |
1da177e4 | 1145 | |
eb9d0fe4 RW |
1146 | return pme_done ? 0 : error; |
1147 | } | |
1da177e4 | 1148 | |
eb9d0fe4 RW |
1149 | /** |
1150 | * pci_pm_init - Initialize PM functions of given PCI device | |
1151 | * @dev: PCI device to handle. | |
1152 | */ | |
1153 | void pci_pm_init(struct pci_dev *dev) | |
1154 | { | |
1155 | int pm; | |
1156 | u16 pmc; | |
1da177e4 | 1157 | |
eb9d0fe4 RW |
1158 | /* find PCI PM capability in list */ |
1159 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
1160 | if (!pm) | |
1161 | return; | |
1162 | /* Check device's ability to generate PME# */ | |
1163 | pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc); | |
075c1771 | 1164 | |
eb9d0fe4 RW |
1165 | if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { |
1166 | dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n", | |
1167 | pmc & PCI_PM_CAP_VER_MASK); | |
1168 | return; | |
1169 | } | |
1170 | ||
1171 | if (pmc & PCI_PM_CAP_PME_MASK) { | |
1172 | dev_printk(KERN_INFO, &dev->dev, | |
1173 | "PME# supported from%s%s%s%s%s\n", | |
1174 | (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "", | |
1175 | (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "", | |
1176 | (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "", | |
1177 | (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "", | |
1178 | (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : ""); | |
1179 | /* | |
1180 | * Make device's PM flags reflect the wake-up capability, but | |
1181 | * let the user space enable it to wake up the system as needed. | |
1182 | */ | |
1183 | device_set_wakeup_capable(&dev->dev, true); | |
1184 | device_set_wakeup_enable(&dev->dev, false); | |
1185 | /* Disable the PME# generation functionality */ | |
1186 | pci_pme_active(dev, pm, false); | |
1187 | } | |
1da177e4 LT |
1188 | } |
1189 | ||
1190 | int | |
1191 | pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) | |
1192 | { | |
1193 | u8 pin; | |
1194 | ||
514d207d | 1195 | pin = dev->pin; |
1da177e4 LT |
1196 | if (!pin) |
1197 | return -1; | |
1198 | pin--; | |
1199 | while (dev->bus->self) { | |
1200 | pin = (pin + PCI_SLOT(dev->devfn)) % 4; | |
1201 | dev = dev->bus->self; | |
1202 | } | |
1203 | *bridge = dev; | |
1204 | return pin; | |
1205 | } | |
1206 | ||
1207 | /** | |
1208 | * pci_release_region - Release a PCI bar | |
1209 | * @pdev: PCI device whose resources were previously reserved by pci_request_region | |
1210 | * @bar: BAR to release | |
1211 | * | |
1212 | * Releases the PCI I/O and memory resources previously reserved by a | |
1213 | * successful call to pci_request_region. Call this function only | |
1214 | * after all use of the PCI regions has ceased. | |
1215 | */ | |
1216 | void pci_release_region(struct pci_dev *pdev, int bar) | |
1217 | { | |
9ac7849e TH |
1218 | struct pci_devres *dr; |
1219 | ||
1da177e4 LT |
1220 | if (pci_resource_len(pdev, bar) == 0) |
1221 | return; | |
1222 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) | |
1223 | release_region(pci_resource_start(pdev, bar), | |
1224 | pci_resource_len(pdev, bar)); | |
1225 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) | |
1226 | release_mem_region(pci_resource_start(pdev, bar), | |
1227 | pci_resource_len(pdev, bar)); | |
9ac7849e TH |
1228 | |
1229 | dr = find_pci_dr(pdev); | |
1230 | if (dr) | |
1231 | dr->region_mask &= ~(1 << bar); | |
1da177e4 LT |
1232 | } |
1233 | ||
1234 | /** | |
1235 | * pci_request_region - Reserved PCI I/O and memory resource | |
1236 | * @pdev: PCI device whose resources are to be reserved | |
1237 | * @bar: BAR to be reserved | |
1238 | * @res_name: Name to be associated with resource. | |
1239 | * | |
1240 | * Mark the PCI region associated with PCI device @pdev BR @bar as | |
1241 | * being reserved by owner @res_name. Do not access any | |
1242 | * address inside the PCI regions unless this call returns | |
1243 | * successfully. | |
1244 | * | |
1245 | * Returns 0 on success, or %EBUSY on error. A warning | |
1246 | * message is also printed on failure. | |
1247 | */ | |
3c990e92 | 1248 | int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) |
1da177e4 | 1249 | { |
9ac7849e TH |
1250 | struct pci_devres *dr; |
1251 | ||
1da177e4 LT |
1252 | if (pci_resource_len(pdev, bar) == 0) |
1253 | return 0; | |
1254 | ||
1255 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { | |
1256 | if (!request_region(pci_resource_start(pdev, bar), | |
1257 | pci_resource_len(pdev, bar), res_name)) | |
1258 | goto err_out; | |
1259 | } | |
1260 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { | |
1261 | if (!request_mem_region(pci_resource_start(pdev, bar), | |
1262 | pci_resource_len(pdev, bar), res_name)) | |
1263 | goto err_out; | |
1264 | } | |
9ac7849e TH |
1265 | |
1266 | dr = find_pci_dr(pdev); | |
1267 | if (dr) | |
1268 | dr->region_mask |= 1 << bar; | |
1269 | ||
1da177e4 LT |
1270 | return 0; |
1271 | ||
1272 | err_out: | |
80ccba11 | 1273 | dev_warn(&pdev->dev, "BAR %d: can't reserve %s region [%#llx-%#llx]\n", |
e4ec7a00 JB |
1274 | bar, |
1275 | pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem", | |
1276 | (unsigned long long)pci_resource_start(pdev, bar), | |
1277 | (unsigned long long)pci_resource_end(pdev, bar)); | |
1da177e4 LT |
1278 | return -EBUSY; |
1279 | } | |
1280 | ||
c87deff7 HS |
1281 | /** |
1282 | * pci_release_selected_regions - Release selected PCI I/O and memory resources | |
1283 | * @pdev: PCI device whose resources were previously reserved | |
1284 | * @bars: Bitmask of BARs to be released | |
1285 | * | |
1286 | * Release selected PCI I/O and memory resources previously reserved. | |
1287 | * Call this function only after all use of the PCI regions has ceased. | |
1288 | */ | |
1289 | void pci_release_selected_regions(struct pci_dev *pdev, int bars) | |
1290 | { | |
1291 | int i; | |
1292 | ||
1293 | for (i = 0; i < 6; i++) | |
1294 | if (bars & (1 << i)) | |
1295 | pci_release_region(pdev, i); | |
1296 | } | |
1297 | ||
1298 | /** | |
1299 | * pci_request_selected_regions - Reserve selected PCI I/O and memory resources | |
1300 | * @pdev: PCI device whose resources are to be reserved | |
1301 | * @bars: Bitmask of BARs to be requested | |
1302 | * @res_name: Name to be associated with resource | |
1303 | */ | |
1304 | int pci_request_selected_regions(struct pci_dev *pdev, int bars, | |
1305 | const char *res_name) | |
1306 | { | |
1307 | int i; | |
1308 | ||
1309 | for (i = 0; i < 6; i++) | |
1310 | if (bars & (1 << i)) | |
1311 | if(pci_request_region(pdev, i, res_name)) | |
1312 | goto err_out; | |
1313 | return 0; | |
1314 | ||
1315 | err_out: | |
1316 | while(--i >= 0) | |
1317 | if (bars & (1 << i)) | |
1318 | pci_release_region(pdev, i); | |
1319 | ||
1320 | return -EBUSY; | |
1321 | } | |
1da177e4 LT |
1322 | |
1323 | /** | |
1324 | * pci_release_regions - Release reserved PCI I/O and memory resources | |
1325 | * @pdev: PCI device whose resources were previously reserved by pci_request_regions | |
1326 | * | |
1327 | * Releases all PCI I/O and memory resources previously reserved by a | |
1328 | * successful call to pci_request_regions. Call this function only | |
1329 | * after all use of the PCI regions has ceased. | |
1330 | */ | |
1331 | ||
1332 | void pci_release_regions(struct pci_dev *pdev) | |
1333 | { | |
c87deff7 | 1334 | pci_release_selected_regions(pdev, (1 << 6) - 1); |
1da177e4 LT |
1335 | } |
1336 | ||
1337 | /** | |
1338 | * pci_request_regions - Reserved PCI I/O and memory resources | |
1339 | * @pdev: PCI device whose resources are to be reserved | |
1340 | * @res_name: Name to be associated with resource. | |
1341 | * | |
1342 | * Mark all PCI regions associated with PCI device @pdev as | |
1343 | * being reserved by owner @res_name. Do not access any | |
1344 | * address inside the PCI regions unless this call returns | |
1345 | * successfully. | |
1346 | * | |
1347 | * Returns 0 on success, or %EBUSY on error. A warning | |
1348 | * message is also printed on failure. | |
1349 | */ | |
3c990e92 | 1350 | int pci_request_regions(struct pci_dev *pdev, const char *res_name) |
1da177e4 | 1351 | { |
c87deff7 | 1352 | return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name); |
1da177e4 LT |
1353 | } |
1354 | ||
1355 | /** | |
1356 | * pci_set_master - enables bus-mastering for device dev | |
1357 | * @dev: the PCI device to enable | |
1358 | * | |
1359 | * Enables bus-mastering on the device and calls pcibios_set_master() | |
1360 | * to do the needed arch specific settings. | |
1361 | */ | |
1362 | void | |
1363 | pci_set_master(struct pci_dev *dev) | |
1364 | { | |
1365 | u16 cmd; | |
1366 | ||
1367 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1368 | if (! (cmd & PCI_COMMAND_MASTER)) { | |
80ccba11 | 1369 | dev_dbg(&dev->dev, "enabling bus mastering\n"); |
1da177e4 LT |
1370 | cmd |= PCI_COMMAND_MASTER; |
1371 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1372 | } | |
1373 | dev->is_busmaster = 1; | |
1374 | pcibios_set_master(dev); | |
1375 | } | |
1376 | ||
edb2d97e MW |
1377 | #ifdef PCI_DISABLE_MWI |
1378 | int pci_set_mwi(struct pci_dev *dev) | |
1379 | { | |
1380 | return 0; | |
1381 | } | |
1382 | ||
694625c0 RD |
1383 | int pci_try_set_mwi(struct pci_dev *dev) |
1384 | { | |
1385 | return 0; | |
1386 | } | |
1387 | ||
edb2d97e MW |
1388 | void pci_clear_mwi(struct pci_dev *dev) |
1389 | { | |
1390 | } | |
1391 | ||
1392 | #else | |
ebf5a248 MW |
1393 | |
1394 | #ifndef PCI_CACHE_LINE_BYTES | |
1395 | #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES | |
1396 | #endif | |
1397 | ||
1da177e4 | 1398 | /* This can be overridden by arch code. */ |
ebf5a248 MW |
1399 | /* Don't forget this is measured in 32-bit words, not bytes */ |
1400 | u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4; | |
1da177e4 LT |
1401 | |
1402 | /** | |
edb2d97e MW |
1403 | * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed |
1404 | * @dev: the PCI device for which MWI is to be enabled | |
1da177e4 | 1405 | * |
edb2d97e MW |
1406 | * Helper function for pci_set_mwi. |
1407 | * Originally copied from drivers/net/acenic.c. | |
1da177e4 LT |
1408 | * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. |
1409 | * | |
1410 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
1411 | */ | |
1412 | static int | |
edb2d97e | 1413 | pci_set_cacheline_size(struct pci_dev *dev) |
1da177e4 LT |
1414 | { |
1415 | u8 cacheline_size; | |
1416 | ||
1417 | if (!pci_cache_line_size) | |
1418 | return -EINVAL; /* The system doesn't support MWI. */ | |
1419 | ||
1420 | /* Validate current setting: the PCI_CACHE_LINE_SIZE must be | |
1421 | equal to or multiple of the right value. */ | |
1422 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
1423 | if (cacheline_size >= pci_cache_line_size && | |
1424 | (cacheline_size % pci_cache_line_size) == 0) | |
1425 | return 0; | |
1426 | ||
1427 | /* Write the correct value. */ | |
1428 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); | |
1429 | /* Read it back. */ | |
1430 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); | |
1431 | if (cacheline_size == pci_cache_line_size) | |
1432 | return 0; | |
1433 | ||
80ccba11 BH |
1434 | dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not " |
1435 | "supported\n", pci_cache_line_size << 2); | |
1da177e4 LT |
1436 | |
1437 | return -EINVAL; | |
1438 | } | |
1da177e4 LT |
1439 | |
1440 | /** | |
1441 | * pci_set_mwi - enables memory-write-invalidate PCI transaction | |
1442 | * @dev: the PCI device for which MWI is enabled | |
1443 | * | |
694625c0 | 1444 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. |
1da177e4 LT |
1445 | * |
1446 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
1447 | */ | |
1448 | int | |
1449 | pci_set_mwi(struct pci_dev *dev) | |
1450 | { | |
1451 | int rc; | |
1452 | u16 cmd; | |
1453 | ||
edb2d97e | 1454 | rc = pci_set_cacheline_size(dev); |
1da177e4 LT |
1455 | if (rc) |
1456 | return rc; | |
1457 | ||
1458 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1459 | if (! (cmd & PCI_COMMAND_INVALIDATE)) { | |
80ccba11 | 1460 | dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n"); |
1da177e4 LT |
1461 | cmd |= PCI_COMMAND_INVALIDATE; |
1462 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1463 | } | |
1464 | ||
1465 | return 0; | |
1466 | } | |
1467 | ||
694625c0 RD |
1468 | /** |
1469 | * pci_try_set_mwi - enables memory-write-invalidate PCI transaction | |
1470 | * @dev: the PCI device for which MWI is enabled | |
1471 | * | |
1472 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. | |
1473 | * Callers are not required to check the return value. | |
1474 | * | |
1475 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. | |
1476 | */ | |
1477 | int pci_try_set_mwi(struct pci_dev *dev) | |
1478 | { | |
1479 | int rc = pci_set_mwi(dev); | |
1480 | return rc; | |
1481 | } | |
1482 | ||
1da177e4 LT |
1483 | /** |
1484 | * pci_clear_mwi - disables Memory-Write-Invalidate for device dev | |
1485 | * @dev: the PCI device to disable | |
1486 | * | |
1487 | * Disables PCI Memory-Write-Invalidate transaction on the device | |
1488 | */ | |
1489 | void | |
1490 | pci_clear_mwi(struct pci_dev *dev) | |
1491 | { | |
1492 | u16 cmd; | |
1493 | ||
1494 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
1495 | if (cmd & PCI_COMMAND_INVALIDATE) { | |
1496 | cmd &= ~PCI_COMMAND_INVALIDATE; | |
1497 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1498 | } | |
1499 | } | |
edb2d97e | 1500 | #endif /* ! PCI_DISABLE_MWI */ |
1da177e4 | 1501 | |
a04ce0ff BR |
1502 | /** |
1503 | * pci_intx - enables/disables PCI INTx for device dev | |
8f7020d3 RD |
1504 | * @pdev: the PCI device to operate on |
1505 | * @enable: boolean: whether to enable or disable PCI INTx | |
a04ce0ff BR |
1506 | * |
1507 | * Enables/disables PCI INTx for device dev | |
1508 | */ | |
1509 | void | |
1510 | pci_intx(struct pci_dev *pdev, int enable) | |
1511 | { | |
1512 | u16 pci_command, new; | |
1513 | ||
1514 | pci_read_config_word(pdev, PCI_COMMAND, &pci_command); | |
1515 | ||
1516 | if (enable) { | |
1517 | new = pci_command & ~PCI_COMMAND_INTX_DISABLE; | |
1518 | } else { | |
1519 | new = pci_command | PCI_COMMAND_INTX_DISABLE; | |
1520 | } | |
1521 | ||
1522 | if (new != pci_command) { | |
9ac7849e TH |
1523 | struct pci_devres *dr; |
1524 | ||
2fd9d74b | 1525 | pci_write_config_word(pdev, PCI_COMMAND, new); |
9ac7849e TH |
1526 | |
1527 | dr = find_pci_dr(pdev); | |
1528 | if (dr && !dr->restore_intx) { | |
1529 | dr->restore_intx = 1; | |
1530 | dr->orig_intx = !enable; | |
1531 | } | |
a04ce0ff BR |
1532 | } |
1533 | } | |
1534 | ||
f5f2b131 EB |
1535 | /** |
1536 | * pci_msi_off - disables any msi or msix capabilities | |
8d7d86e9 | 1537 | * @dev: the PCI device to operate on |
f5f2b131 EB |
1538 | * |
1539 | * If you want to use msi see pci_enable_msi and friends. | |
1540 | * This is a lower level primitive that allows us to disable | |
1541 | * msi operation at the device level. | |
1542 | */ | |
1543 | void pci_msi_off(struct pci_dev *dev) | |
1544 | { | |
1545 | int pos; | |
1546 | u16 control; | |
1547 | ||
1548 | pos = pci_find_capability(dev, PCI_CAP_ID_MSI); | |
1549 | if (pos) { | |
1550 | pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); | |
1551 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
1552 | pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); | |
1553 | } | |
1554 | pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); | |
1555 | if (pos) { | |
1556 | pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); | |
1557 | control &= ~PCI_MSIX_FLAGS_ENABLE; | |
1558 | pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); | |
1559 | } | |
1560 | } | |
1561 | ||
1da177e4 LT |
1562 | #ifndef HAVE_ARCH_PCI_SET_DMA_MASK |
1563 | /* | |
1564 | * These can be overridden by arch-specific implementations | |
1565 | */ | |
1566 | int | |
1567 | pci_set_dma_mask(struct pci_dev *dev, u64 mask) | |
1568 | { | |
1569 | if (!pci_dma_supported(dev, mask)) | |
1570 | return -EIO; | |
1571 | ||
1572 | dev->dma_mask = mask; | |
1573 | ||
1574 | return 0; | |
1575 | } | |
1576 | ||
1da177e4 LT |
1577 | int |
1578 | pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) | |
1579 | { | |
1580 | if (!pci_dma_supported(dev, mask)) | |
1581 | return -EIO; | |
1582 | ||
1583 | dev->dev.coherent_dma_mask = mask; | |
1584 | ||
1585 | return 0; | |
1586 | } | |
1587 | #endif | |
c87deff7 | 1588 | |
4d57cdfa FT |
1589 | #ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE |
1590 | int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size) | |
1591 | { | |
1592 | return dma_set_max_seg_size(&dev->dev, size); | |
1593 | } | |
1594 | EXPORT_SYMBOL(pci_set_dma_max_seg_size); | |
1595 | #endif | |
1596 | ||
59fc67de FT |
1597 | #ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY |
1598 | int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask) | |
1599 | { | |
1600 | return dma_set_seg_boundary(&dev->dev, mask); | |
1601 | } | |
1602 | EXPORT_SYMBOL(pci_set_dma_seg_boundary); | |
1603 | #endif | |
1604 | ||
d556ad4b PO |
1605 | /** |
1606 | * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count | |
1607 | * @dev: PCI device to query | |
1608 | * | |
1609 | * Returns mmrbc: maximum designed memory read count in bytes | |
1610 | * or appropriate error value. | |
1611 | */ | |
1612 | int pcix_get_max_mmrbc(struct pci_dev *dev) | |
1613 | { | |
b7b095c1 | 1614 | int err, cap; |
d556ad4b PO |
1615 | u32 stat; |
1616 | ||
1617 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
1618 | if (!cap) | |
1619 | return -EINVAL; | |
1620 | ||
1621 | err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat); | |
1622 | if (err) | |
1623 | return -EINVAL; | |
1624 | ||
b7b095c1 | 1625 | return (stat & PCI_X_STATUS_MAX_READ) >> 12; |
d556ad4b PO |
1626 | } |
1627 | EXPORT_SYMBOL(pcix_get_max_mmrbc); | |
1628 | ||
1629 | /** | |
1630 | * pcix_get_mmrbc - get PCI-X maximum memory read byte count | |
1631 | * @dev: PCI device to query | |
1632 | * | |
1633 | * Returns mmrbc: maximum memory read count in bytes | |
1634 | * or appropriate error value. | |
1635 | */ | |
1636 | int pcix_get_mmrbc(struct pci_dev *dev) | |
1637 | { | |
1638 | int ret, cap; | |
1639 | u32 cmd; | |
1640 | ||
1641 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
1642 | if (!cap) | |
1643 | return -EINVAL; | |
1644 | ||
1645 | ret = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd); | |
1646 | if (!ret) | |
1647 | ret = 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2); | |
1648 | ||
1649 | return ret; | |
1650 | } | |
1651 | EXPORT_SYMBOL(pcix_get_mmrbc); | |
1652 | ||
1653 | /** | |
1654 | * pcix_set_mmrbc - set PCI-X maximum memory read byte count | |
1655 | * @dev: PCI device to query | |
1656 | * @mmrbc: maximum memory read count in bytes | |
1657 | * valid values are 512, 1024, 2048, 4096 | |
1658 | * | |
1659 | * If possible sets maximum memory read byte count, some bridges have erratas | |
1660 | * that prevent this. | |
1661 | */ | |
1662 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) | |
1663 | { | |
1664 | int cap, err = -EINVAL; | |
1665 | u32 stat, cmd, v, o; | |
1666 | ||
229f5afd | 1667 | if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc)) |
d556ad4b PO |
1668 | goto out; |
1669 | ||
1670 | v = ffs(mmrbc) - 10; | |
1671 | ||
1672 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
1673 | if (!cap) | |
1674 | goto out; | |
1675 | ||
1676 | err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat); | |
1677 | if (err) | |
1678 | goto out; | |
1679 | ||
1680 | if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21) | |
1681 | return -E2BIG; | |
1682 | ||
1683 | err = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd); | |
1684 | if (err) | |
1685 | goto out; | |
1686 | ||
1687 | o = (cmd & PCI_X_CMD_MAX_READ) >> 2; | |
1688 | if (o != v) { | |
1689 | if (v > o && dev->bus && | |
1690 | (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) | |
1691 | return -EIO; | |
1692 | ||
1693 | cmd &= ~PCI_X_CMD_MAX_READ; | |
1694 | cmd |= v << 2; | |
1695 | err = pci_write_config_dword(dev, cap + PCI_X_CMD, cmd); | |
1696 | } | |
1697 | out: | |
1698 | return err; | |
1699 | } | |
1700 | EXPORT_SYMBOL(pcix_set_mmrbc); | |
1701 | ||
1702 | /** | |
1703 | * pcie_get_readrq - get PCI Express read request size | |
1704 | * @dev: PCI device to query | |
1705 | * | |
1706 | * Returns maximum memory read request in bytes | |
1707 | * or appropriate error value. | |
1708 | */ | |
1709 | int pcie_get_readrq(struct pci_dev *dev) | |
1710 | { | |
1711 | int ret, cap; | |
1712 | u16 ctl; | |
1713 | ||
1714 | cap = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
1715 | if (!cap) | |
1716 | return -EINVAL; | |
1717 | ||
1718 | ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); | |
1719 | if (!ret) | |
1720 | ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12); | |
1721 | ||
1722 | return ret; | |
1723 | } | |
1724 | EXPORT_SYMBOL(pcie_get_readrq); | |
1725 | ||
1726 | /** | |
1727 | * pcie_set_readrq - set PCI Express maximum memory read request | |
1728 | * @dev: PCI device to query | |
42e61f4a | 1729 | * @rq: maximum memory read count in bytes |
d556ad4b PO |
1730 | * valid values are 128, 256, 512, 1024, 2048, 4096 |
1731 | * | |
1732 | * If possible sets maximum read byte count | |
1733 | */ | |
1734 | int pcie_set_readrq(struct pci_dev *dev, int rq) | |
1735 | { | |
1736 | int cap, err = -EINVAL; | |
1737 | u16 ctl, v; | |
1738 | ||
229f5afd | 1739 | if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) |
d556ad4b PO |
1740 | goto out; |
1741 | ||
1742 | v = (ffs(rq) - 8) << 12; | |
1743 | ||
1744 | cap = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
1745 | if (!cap) | |
1746 | goto out; | |
1747 | ||
1748 | err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); | |
1749 | if (err) | |
1750 | goto out; | |
1751 | ||
1752 | if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) { | |
1753 | ctl &= ~PCI_EXP_DEVCTL_READRQ; | |
1754 | ctl |= v; | |
1755 | err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl); | |
1756 | } | |
1757 | ||
1758 | out: | |
1759 | return err; | |
1760 | } | |
1761 | EXPORT_SYMBOL(pcie_set_readrq); | |
1762 | ||
c87deff7 HS |
1763 | /** |
1764 | * pci_select_bars - Make BAR mask from the type of resource | |
f95d882d | 1765 | * @dev: the PCI device for which BAR mask is made |
c87deff7 HS |
1766 | * @flags: resource type mask to be selected |
1767 | * | |
1768 | * This helper routine makes bar mask from the type of resource. | |
1769 | */ | |
1770 | int pci_select_bars(struct pci_dev *dev, unsigned long flags) | |
1771 | { | |
1772 | int i, bars = 0; | |
1773 | for (i = 0; i < PCI_NUM_RESOURCES; i++) | |
1774 | if (pci_resource_flags(dev, i) & flags) | |
1775 | bars |= (1 << i); | |
1776 | return bars; | |
1777 | } | |
1778 | ||
32a2eea7 JG |
1779 | static void __devinit pci_no_domains(void) |
1780 | { | |
1781 | #ifdef CONFIG_PCI_DOMAINS | |
1782 | pci_domains_supported = 0; | |
1783 | #endif | |
1784 | } | |
1785 | ||
1da177e4 LT |
1786 | static int __devinit pci_init(void) |
1787 | { | |
1788 | struct pci_dev *dev = NULL; | |
1789 | ||
1790 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
1791 | pci_fixup_device(pci_fixup_final, dev); | |
1792 | } | |
1793 | return 0; | |
1794 | } | |
1795 | ||
1796 | static int __devinit pci_setup(char *str) | |
1797 | { | |
1798 | while (str) { | |
1799 | char *k = strchr(str, ','); | |
1800 | if (k) | |
1801 | *k++ = 0; | |
1802 | if (*str && (str = pcibios_setup(str)) && *str) { | |
309e57df MW |
1803 | if (!strcmp(str, "nomsi")) { |
1804 | pci_no_msi(); | |
7f785763 RD |
1805 | } else if (!strcmp(str, "noaer")) { |
1806 | pci_no_aer(); | |
32a2eea7 JG |
1807 | } else if (!strcmp(str, "nodomains")) { |
1808 | pci_no_domains(); | |
4516a618 AN |
1809 | } else if (!strncmp(str, "cbiosize=", 9)) { |
1810 | pci_cardbus_io_size = memparse(str + 9, &str); | |
1811 | } else if (!strncmp(str, "cbmemsize=", 10)) { | |
1812 | pci_cardbus_mem_size = memparse(str + 10, &str); | |
309e57df MW |
1813 | } else { |
1814 | printk(KERN_ERR "PCI: Unknown option `%s'\n", | |
1815 | str); | |
1816 | } | |
1da177e4 LT |
1817 | } |
1818 | str = k; | |
1819 | } | |
0637a70a | 1820 | return 0; |
1da177e4 | 1821 | } |
0637a70a | 1822 | early_param("pci", pci_setup); |
1da177e4 LT |
1823 | |
1824 | device_initcall(pci_init); | |
1da177e4 | 1825 | |
0b62e13b | 1826 | EXPORT_SYMBOL(pci_reenable_device); |
b718989d BH |
1827 | EXPORT_SYMBOL(pci_enable_device_io); |
1828 | EXPORT_SYMBOL(pci_enable_device_mem); | |
1da177e4 | 1829 | EXPORT_SYMBOL(pci_enable_device); |
9ac7849e TH |
1830 | EXPORT_SYMBOL(pcim_enable_device); |
1831 | EXPORT_SYMBOL(pcim_pin_device); | |
1da177e4 | 1832 | EXPORT_SYMBOL(pci_disable_device); |
1da177e4 LT |
1833 | EXPORT_SYMBOL(pci_find_capability); |
1834 | EXPORT_SYMBOL(pci_bus_find_capability); | |
1835 | EXPORT_SYMBOL(pci_release_regions); | |
1836 | EXPORT_SYMBOL(pci_request_regions); | |
1837 | EXPORT_SYMBOL(pci_release_region); | |
1838 | EXPORT_SYMBOL(pci_request_region); | |
c87deff7 HS |
1839 | EXPORT_SYMBOL(pci_release_selected_regions); |
1840 | EXPORT_SYMBOL(pci_request_selected_regions); | |
1da177e4 LT |
1841 | EXPORT_SYMBOL(pci_set_master); |
1842 | EXPORT_SYMBOL(pci_set_mwi); | |
694625c0 | 1843 | EXPORT_SYMBOL(pci_try_set_mwi); |
1da177e4 | 1844 | EXPORT_SYMBOL(pci_clear_mwi); |
a04ce0ff | 1845 | EXPORT_SYMBOL_GPL(pci_intx); |
1da177e4 | 1846 | EXPORT_SYMBOL(pci_set_dma_mask); |
1da177e4 LT |
1847 | EXPORT_SYMBOL(pci_set_consistent_dma_mask); |
1848 | EXPORT_SYMBOL(pci_assign_resource); | |
1849 | EXPORT_SYMBOL(pci_find_parent_resource); | |
c87deff7 | 1850 | EXPORT_SYMBOL(pci_select_bars); |
1da177e4 LT |
1851 | |
1852 | EXPORT_SYMBOL(pci_set_power_state); | |
1853 | EXPORT_SYMBOL(pci_save_state); | |
1854 | EXPORT_SYMBOL(pci_restore_state); | |
1855 | EXPORT_SYMBOL(pci_enable_wake); | |
f7bdd12d | 1856 | EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state); |
1da177e4 | 1857 |