[mirror_ubuntu-zesty-kernel.git] / drivers / pci / pci.h

#ifndef DRIVERS_PCI_H
#define DRIVERS_PCI_H

#include <linux/workqueue.h>

#define PCI_CFG_SPACE_SIZE	256
#define PCI_CFG_SPACE_EXP_SIZE	4096

/* Functions internal to the PCI core code */

extern int pci_uevent(struct device *dev, struct kobj_uevent_env *env);
extern int pci_create_sysfs_dev_files(struct pci_dev *pdev);
extern void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
#ifndef CONFIG_DMI
static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
{ return; }
static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
{ return; }
#else
extern void pci_create_firmware_label_files(struct pci_dev *pdev);
extern void pci_remove_firmware_label_files(struct pci_dev *pdev);
#endif
extern void pci_cleanup_rom(struct pci_dev *dev);
#ifdef HAVE_PCI_MMAP
enum pci_mmap_api {
	PCI_MMAP_SYSFS,	/* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
	PCI_MMAP_PROCFS	/* mmap on /proc/bus/pci/<BDF> */
};
extern int pci_mmap_fits(struct pci_dev *pdev, int resno,
			 struct vm_area_struct *vmai,
			 enum pci_mmap_api mmap_api);
#endif
int pci_probe_reset_function(struct pci_dev *dev);

/**
 * struct pci_platform_pm_ops - Firmware PM callbacks
 *
 * @is_manageable: returns 'true' if given device is power manageable by the
 *                 platform firmware
 *
 * @set_state: invokes the platform firmware to set the device's power state
 *
 * @choose_state: returns PCI power state of given device preferred by the
 *                platform; to be used during system-wide transitions from a
 *                sleeping state to the working state and vice versa
 *
 * @can_wakeup: returns 'true' if given device is capable of waking up the
 *              system from a sleeping state
 *
 * @sleep_wake: enables/disables the system wake up capability of given device
 *
 * @run_wake: enables/disables the platform to generate run-time wake-up events
 *		for given device (the device's wake-up capability has to be
 *		enabled by @sleep_wake for this feature to work)
 *
 * If given platform is generally capable of power managing PCI devices, all of
 * these callbacks are mandatory.
 */
struct pci_platform_pm_ops {
	bool (*is_manageable)(struct pci_dev *dev);
	int (*set_state)(struct pci_dev *dev, pci_power_t state);
	pci_power_t (*choose_state)(struct pci_dev *dev);
	bool (*can_wakeup)(struct pci_dev *dev);
	int (*sleep_wake)(struct pci_dev *dev, bool enable);
	int (*run_wake)(struct pci_dev *dev, bool enable);
};

extern int pci_set_platform_pm(struct pci_platform_pm_ops *ops);
extern void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
extern void pci_disable_enabled_device(struct pci_dev *dev);
extern int pci_finish_runtime_suspend(struct pci_dev *dev);
extern int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
extern void pci_pm_init(struct pci_dev *dev);
extern void platform_pci_wakeup_init(struct pci_dev *dev);
extern void pci_allocate_cap_save_buffers(struct pci_dev *dev);

static inline bool pci_is_bridge(struct pci_dev *pci_dev)
{
	return !!(pci_dev->subordinate);
}

extern int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
extern int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
extern int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
extern int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
extern int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
extern int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);

struct pci_vpd_ops {
	ssize_t (*read)(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
	ssize_t (*write)(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
	void (*release)(struct pci_dev *dev);
};

struct pci_vpd {
	unsigned int len;
	const struct pci_vpd_ops *ops;
	struct bin_attribute *attr; /* descriptor for sysfs VPD entry */
};

extern int pci_vpd_pci22_init(struct pci_dev *dev);
static inline void pci_vpd_release(struct pci_dev *dev)
{
	if (dev->vpd)
		dev->vpd->ops->release(dev);
}

/* PCI /proc functions */
#ifdef CONFIG_PROC_FS
extern int pci_proc_attach_device(struct pci_dev *dev);
extern int pci_proc_detach_device(struct pci_dev *dev);
extern int pci_proc_detach_bus(struct pci_bus *bus);
#else
static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
#endif

/* Functions for PCI Hotplug drivers to use */
extern unsigned int pci_do_scan_bus(struct pci_bus *bus);

#ifdef HAVE_PCI_LEGACY
extern void pci_create_legacy_files(struct pci_bus *bus);
extern void pci_remove_legacy_files(struct pci_bus *bus);
#else
static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
#endif

/* Lock for read/write access to pci device and bus lists */
extern struct rw_semaphore pci_bus_sem;

extern unsigned int pci_pm_d3_delay;

#ifdef CONFIG_PCI_MSI
void pci_no_msi(void);
extern void pci_msi_init_pci_dev(struct pci_dev *dev);
#else
static inline void pci_no_msi(void) { }
static inline void pci_msi_init_pci_dev(struct pci_dev *dev) { }
#endif

#ifdef CONFIG_PCIEAER
void pci_no_aer(void);
bool pci_aer_available(void);
#else
static inline void pci_no_aer(void) { }
static inline bool pci_aer_available(void) { return false; }
#endif

static inline int pci_no_d1d2(struct pci_dev *dev)
{
	unsigned int parent_dstates = 0;

	if (dev->bus->self)
		parent_dstates = dev->bus->self->no_d1d2;
	return (dev->no_d1d2 || parent_dstates);

}
extern struct device_attribute pci_dev_attrs[];
extern struct device_attribute dev_attr_cpuaffinity;
extern struct device_attribute dev_attr_cpulistaffinity;
#ifdef CONFIG_HOTPLUG
extern struct bus_attribute pci_bus_attrs[];
#else
#define pci_bus_attrs	NULL
#endif


/**
 * pci_match_one_device - Tell if a PCI device structure has a matching
 *                        PCI device id structure
 * @id: single PCI device id structure to match
 * @dev: the PCI device structure to match against
 *
 * Returns the matching pci_device_id structure or %NULL if there is no match.
 */
static inline const struct pci_device_id *
pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
{
	if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
	    (id->device == PCI_ANY_ID || id->device == dev->device) &&
	    (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
	    (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
	    !((id->class ^ dev->class) & id->class_mask))
		return id;
	return NULL;
}

struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev);

/* PCI slot sysfs helper code */
#define to_pci_slot(s) container_of(s, struct pci_slot, kobj)

extern struct kset *pci_slots_kset;

struct pci_slot_attribute {
	struct attribute attr;
	ssize_t (*show)(struct pci_slot *, char *);
	ssize_t (*store)(struct pci_slot *, const char *, size_t);
};
#define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)

enum pci_bar_type {
	pci_bar_unknown,	/* Standard PCI BAR probe */
	pci_bar_io,		/* An io port BAR */
	pci_bar_mem32,		/* A 32-bit memory BAR */
	pci_bar_mem64,		/* A 64-bit memory BAR */
};

extern int pci_setup_device(struct pci_dev *dev);
extern int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
				struct resource *res, unsigned int reg);
extern int pci_resource_bar(struct pci_dev *dev, int resno,
			    enum pci_bar_type *type);
extern int pci_bus_add_child(struct pci_bus *bus);
extern void pci_enable_ari(struct pci_dev *dev);
/**
 * pci_ari_enabled - query ARI forwarding status
 * @bus: the PCI bus
 *
 * Returns 1 if ARI forwarding is enabled, or 0 if not enabled;
 */
static inline int pci_ari_enabled(struct pci_bus *bus)
{
	return bus->self && bus->self->ari_enabled;
}

#ifdef CONFIG_PCI_QUIRKS
extern int pci_is_reassigndev(struct pci_dev *dev);
resource_size_t pci_specified_resource_alignment(struct pci_dev *dev);
extern void pci_disable_bridge_window(struct pci_dev *dev);
#endif

/* Single Root I/O Virtualization */
struct pci_sriov {
	int pos;		/* capability position */
	int nres;		/* number of resources */
	u32 cap;		/* SR-IOV Capabilities */
	u16 ctrl;		/* SR-IOV Control */
	u16 total;		/* total VFs associated with the PF */
	u16 initial;		/* initial VFs associated with the PF */
	u16 nr_virtfn;		/* number of VFs available */
	u16 offset;		/* first VF Routing ID offset */
	u16 stride;		/* following VF stride */
	u32 pgsz;		/* page size for BAR alignment */
	u8 link;		/* Function Dependency Link */
	struct pci_dev *dev;	/* lowest numbered PF */
	struct pci_dev *self;	/* this PF */
	struct mutex lock;	/* lock for VF bus */
	struct work_struct mtask; /* VF Migration task */
	u8 __iomem *mstate;	/* VF Migration State Array */
};

/* Address Translation Service */
struct pci_ats {
	int pos;	/* capability position */
	int stu;	/* Smallest Translation Unit */
	int qdep;	/* Invalidate Queue Depth */
	int ref_cnt;	/* Physical Function reference count */
	unsigned int is_enabled:1;	/* Enable bit is set */
};

#ifdef CONFIG_PCI_IOV
extern int pci_iov_init(struct pci_dev *dev);
extern void pci_iov_release(struct pci_dev *dev);
extern int pci_iov_resource_bar(struct pci_dev *dev, int resno,
				enum pci_bar_type *type);
extern resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev,
						    int resno);
extern void pci_restore_iov_state(struct pci_dev *dev);
extern int pci_iov_bus_range(struct pci_bus *bus);

extern int pci_enable_ats(struct pci_dev *dev, int ps);
extern void pci_disable_ats(struct pci_dev *dev);
extern int pci_ats_queue_depth(struct pci_dev *dev);
/**
 * pci_ats_enabled - query the ATS status
 * @dev: the PCI device
 *
 * Returns 1 if ATS capability is enabled, or 0 if not.
 */
static inline int pci_ats_enabled(struct pci_dev *dev)
{
	return dev->ats && dev->ats->is_enabled;
}
#else
static inline int pci_iov_init(struct pci_dev *dev)
{
	return -ENODEV;
}
static inline void pci_iov_release(struct pci_dev *dev)

{
}
static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno,
				       enum pci_bar_type *type)
{
	return 0;
}
static inline void pci_restore_iov_state(struct pci_dev *dev)
{
}
static inline int pci_iov_bus_range(struct pci_bus *bus)
{
	return 0;
}

static inline int pci_enable_ats(struct pci_dev *dev, int ps)
{
	return -ENODEV;
}
static inline void pci_disable_ats(struct pci_dev *dev)
{
}
static inline int pci_ats_queue_depth(struct pci_dev *dev)
{
	return -ENODEV;
}
static inline int pci_ats_enabled(struct pci_dev *dev)
{
	return 0;
}
#endif /* CONFIG_PCI_IOV */

static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
					 struct resource *res)
{
#ifdef CONFIG_PCI_IOV
	int resno = res - dev->resource;

	if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
		return pci_sriov_resource_alignment(dev, resno);
#endif
	return resource_alignment(res);
}

extern void pci_enable_acs(struct pci_dev *dev);

struct pci_dev_reset_methods {
	u16 vendor;
	u16 device;
	int (*reset)(struct pci_dev *dev, int probe);
};

#ifdef CONFIG_PCI_QUIRKS
extern int pci_dev_specific_reset(struct pci_dev *dev, int probe);
#else
static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
{
	return -ENOTTY;
}
#endif

#endif /* DRIVERS_PCI_H */
Commit	Line	Data
557848c3 ZY	1	#ifndef DRIVERS_PCI_H
	2	#define DRIVERS_PCI_H
	3
74bb1bcc YZ	4	#include <linux/workqueue.h>
74bb1bcc YZ	5
557848c3 ZY	6	#define PCI_CFG_SPACE_SIZE 256
	7	#define PCI_CFG_SPACE_EXP_SIZE 4096
	8
1da177e4 LT	9	/* Functions internal to the PCI core code */
1da177e4 LT	10
7eff2e7a	11	extern int pci_uevent(struct device dev, struct kobj_uevent_env env);
1da177e4 LT	12	extern int pci_create_sysfs_dev_files(struct pci_dev *pdev);
1da177e4 LT	13	extern void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
911e1c9b N	14	#ifndef CONFIG_DMI
911e1c9b N	15	static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
b879743f	16	{ return; }
911e1c9b	17	static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
b879743f	18	{ return; }
911e1c9b N	19	#else
	20	extern void pci_create_firmware_label_files(struct pci_dev *pdev);
	21	extern void pci_remove_firmware_label_files(struct pci_dev *pdev);
	22	#endif
1da177e4	23	extern void pci_cleanup_rom(struct pci_dev *dev);
9eff02e2	24	#ifdef HAVE_PCI_MMAP
3b519e4e MW	25	enum pci_mmap_api {
	26	PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
	27	PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
	28	};
9eff02e2	29	extern int pci_mmap_fits(struct pci_dev *pdev, int resno,
3b519e4e MW	30	struct vm_area_struct *vmai,
3b519e4e MW	31	enum pci_mmap_api mmap_api);
9eff02e2	32	#endif
711d5779	33	int pci_probe_reset_function(struct pci_dev *dev);
ce5ccdef	34
961d9120	35	/**
b33bfdef	36	* struct pci_platform_pm_ops - Firmware PM callbacks
961d9120	37	*
b33bfdef RD	38	* @is_manageable: returns 'true' if given device is power manageable by the
b33bfdef RD	39	* platform firmware
961d9120	40	*
b33bfdef	41	* @set_state: invokes the platform firmware to set the device's power state
961d9120	42	*
b33bfdef RD	43	* @choose_state: returns PCI power state of given device preferred by the
	44	* platform; to be used during system-wide transitions from a
	45	* sleeping state to the working state and vice versa
961d9120	46	*
b33bfdef RD	47	* @can_wakeup: returns 'true' if given device is capable of waking up the
b33bfdef RD	48	* system from a sleeping state
eb9d0fe4	49	*
b33bfdef	50	* @sleep_wake: enables/disables the system wake up capability of given device
eb9d0fe4	51	*
b67ea761 RW	52	* @run_wake: enables/disables the platform to generate run-time wake-up events
	53	* for given device (the device's wake-up capability has to be
	54	* enabled by @sleep_wake for this feature to work)
	55	*
961d9120 RW	56	* If given platform is generally capable of power managing PCI devices, all of
	57	* these callbacks are mandatory.
	58	*/
	59	struct pci_platform_pm_ops {
	60	bool (is_manageable)(struct pci_dev dev);
	61	int (set_state)(struct pci_dev dev, pci_power_t state);
	62	pci_power_t (choose_state)(struct pci_dev dev);
eb9d0fe4 RW	63	bool (can_wakeup)(struct pci_dev dev);
eb9d0fe4 RW	64	int (sleep_wake)(struct pci_dev dev, bool enable);
b67ea761	65	int (run_wake)(struct pci_dev dev, bool enable);
961d9120 RW	66	};
	67
	68	extern int pci_set_platform_pm(struct pci_platform_pm_ops *ops);
73410429	69	extern void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
fa58d305	70	extern void pci_disable_enabled_device(struct pci_dev *dev);
6cbf8214	71	extern int pci_finish_runtime_suspend(struct pci_dev *dev);
b67ea761	72	extern int __pci_pme_wakeup(struct pci_dev dev, void ign);
eb9d0fe4	73	extern void pci_pm_init(struct pci_dev *dev);
eb9c39d0	74	extern void platform_pci_wakeup_init(struct pci_dev *dev);
63f4898a	75	extern void pci_allocate_cap_save_buffers(struct pci_dev *dev);
aa8c6c93 RW	76
	77	static inline bool pci_is_bridge(struct pci_dev *pci_dev)
	78	{
	79	return !!(pci_dev->subordinate);
	80	}
0f64474b	81
e04b0ea2 BK	82	extern int pci_user_read_config_byte(struct pci_dev dev, int where, u8 val);
	83	extern int pci_user_read_config_word(struct pci_dev dev, int where, u16 val);
	84	extern int pci_user_read_config_dword(struct pci_dev dev, int where, u32 val);
	85	extern int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
	86	extern int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
	87	extern int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
	88
94e61088	89	struct pci_vpd_ops {
287d19ce SH	90	ssize_t (read)(struct pci_dev dev, loff_t pos, size_t count, void *buf);
287d19ce SH	91	ssize_t (write)(struct pci_dev dev, loff_t pos, size_t count, const void *buf);
94e61088 BH	92	void (release)(struct pci_dev dev);
	93	};
	94
	95	struct pci_vpd {
99cb233d	96	unsigned int len;
287d19ce	97	const struct pci_vpd_ops *ops;
94e61088 BH	98	struct bin_attribute attr; / descriptor for sysfs VPD entry */
	99	};
	100
	101	extern int pci_vpd_pci22_init(struct pci_dev *dev);
	102	static inline void pci_vpd_release(struct pci_dev *dev)
	103	{
	104	if (dev->vpd)
	105	dev->vpd->ops->release(dev);
	106	}
	107
1da177e4 LT	108	/* PCI /proc functions */
	109	#ifdef CONFIG_PROC_FS
	110	extern int pci_proc_attach_device(struct pci_dev *dev);
	111	extern int pci_proc_detach_device(struct pci_dev *dev);
1da177e4 LT	112	extern int pci_proc_detach_bus(struct pci_bus *bus);
	113	#else
	114	static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
	115	static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
1da177e4 LT	116	static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
	117	#endif
	118
	119	/* Functions for PCI Hotplug drivers to use */
1da177e4	120	extern unsigned int pci_do_scan_bus(struct pci_bus *bus);
1da177e4	121
f19aeb1f BH	122	#ifdef HAVE_PCI_LEGACY
f19aeb1f BH	123	extern void pci_create_legacy_files(struct pci_bus *bus);
1da177e4	124	extern void pci_remove_legacy_files(struct pci_bus *bus);
f19aeb1f BH	125	#else
	126	static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
	127	static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
	128	#endif
1da177e4 LT	129
1da177e4 LT	130	/* Lock for read/write access to pci device and bus lists */
d71374da	131	extern struct rw_semaphore pci_bus_sem;
1da177e4	132
ffadcc2f	133	extern unsigned int pci_pm_d3_delay;
88187dfa	134
4b47b0ee	135	#ifdef CONFIG_PCI_MSI
309e57df	136	void pci_no_msi(void);
4aa9bc95	137	extern void pci_msi_init_pci_dev(struct pci_dev *dev);
4b47b0ee	138	#else
309e57df	139	static inline void pci_no_msi(void) { }
4aa9bc95	140	static inline void pci_msi_init_pci_dev(struct pci_dev *dev) { }
4b47b0ee	141	#endif
8fed4b65	142
7f785763 RD	143	#ifdef CONFIG_PCIEAER
7f785763 RD	144	void pci_no_aer(void);
f1a7bfaf	145	bool pci_aer_available(void);
7f785763 RD	146	#else
7f785763 RD	147	static inline void pci_no_aer(void) { }
f1a7bfaf	148	static inline bool pci_aer_available(void) { return false; }
7f785763 RD	149	#endif
7f785763 RD	150
ffadcc2f KCA	151	static inline int pci_no_d1d2(struct pci_dev *dev)
	152	{
	153	unsigned int parent_dstates = 0;
4b47b0ee	154
ffadcc2f KCA	155	if (dev->bus->self)
	156	parent_dstates = dev->bus->self->no_d1d2;
	157	return (dev->no_d1d2 \|\| parent_dstates);
	158
	159	}
1da177e4	160	extern struct device_attribute pci_dev_attrs[];
fd7d1ced	161	extern struct device_attribute dev_attr_cpuaffinity;
93ff68a5	162	extern struct device_attribute dev_attr_cpulistaffinity;
705b1aaa AC	163	#ifdef CONFIG_HOTPLUG
	164	extern struct bus_attribute pci_bus_attrs[];
	165	#else
	166	#define pci_bus_attrs NULL
	167	#endif
	168
1da177e4 LT	169
	170	/**
	171	* pci_match_one_device - Tell if a PCI device structure has a matching
	172	* PCI device id structure
	173	* @id: single PCI device id structure to match
	174	* @dev: the PCI device structure to match against
367b09fe	175	*
1da177e4 LT	176	* Returns the matching pci_device_id structure or %NULL if there is no match.
	177	*/
	178	static inline const struct pci_device_id *
	179	pci_match_one_device(const struct pci_device_id id, const struct pci_dev dev)
	180	{
	181	if ((id->vendor == PCI_ANY_ID \|\| id->vendor == dev->vendor) &&
	182	(id->device == PCI_ANY_ID \|\| id->device == dev->device) &&
	183	(id->subvendor == PCI_ANY_ID \|\| id->subvendor == dev->subsystem_vendor) &&
	184	(id->subdevice == PCI_ANY_ID \|\| id->subdevice == dev->subsystem_device) &&
	185	!((id->class ^ dev->class) & id->class_mask))
	186	return id;
	187	return NULL;
	188	}
	189
994a65e2	190	struct pci_dev pci_find_upstream_pcie_bridge(struct pci_dev pdev);
f46753c5 AC	191
	192	/* PCI slot sysfs helper code */
	193	#define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
	194
	195	extern struct kset *pci_slots_kset;
	196
	197	struct pci_slot_attribute {
	198	struct attribute attr;
	199	ssize_t (show)(struct pci_slot , char *);
	200	ssize_t (store)(struct pci_slot , const char *, size_t);
	201	};
	202	#define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
	203
0b400c7e YZ	204	enum pci_bar_type {
	205	pci_bar_unknown, /* Standard PCI BAR probe */
	206	pci_bar_io, /* An io port BAR */
	207	pci_bar_mem32, /* A 32-bit memory BAR */
	208	pci_bar_mem64, /* A 64-bit memory BAR */
	209	};
	210
480b93b7	211	extern int pci_setup_device(struct pci_dev *dev);
0b400c7e YZ	212	extern int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
0b400c7e YZ	213	struct resource *res, unsigned int reg);
613e7ed6 YZ	214	extern int pci_resource_bar(struct pci_dev *dev, int resno,
613e7ed6 YZ	215	enum pci_bar_type *type);
876e501a	216	extern int pci_bus_add_child(struct pci_bus *bus);
58c3a727 YZ	217	extern void pci_enable_ari(struct pci_dev *dev);
	218	/**
	219	* pci_ari_enabled - query ARI forwarding status
6a49d812	220	* @bus: the PCI bus
58c3a727 YZ	221	*
	222	* Returns 1 if ARI forwarding is enabled, or 0 if not enabled;
	223	*/
6a49d812	224	static inline int pci_ari_enabled(struct pci_bus *bus)
58c3a727	225	{
6a49d812	226	return bus->self && bus->self->ari_enabled;
58c3a727 YZ	227	}
58c3a727 YZ	228
32a9a682 YS	229	#ifdef CONFIG_PCI_QUIRKS
	230	extern int pci_is_reassigndev(struct pci_dev *dev);
	231	resource_size_t pci_specified_resource_alignment(struct pci_dev *dev);
	232	extern void pci_disable_bridge_window(struct pci_dev *dev);
	233	#endif
	234
d1b054da YZ	235	/* Single Root I/O Virtualization */
	236	struct pci_sriov {
	237	int pos; /* capability position */
	238	int nres; /* number of resources */
	239	u32 cap; /* SR-IOV Capabilities */
	240	u16 ctrl; /* SR-IOV Control */
	241	u16 total; /* total VFs associated with the PF */
dd7cc44d YZ	242	u16 initial; /* initial VFs associated with the PF */
dd7cc44d YZ	243	u16 nr_virtfn; /* number of VFs available */
d1b054da YZ	244	u16 offset; /* first VF Routing ID offset */
	245	u16 stride; /* following VF stride */
	246	u32 pgsz; /* page size for BAR alignment */
	247	u8 link; /* Function Dependency Link */
	248	struct pci_dev dev; / lowest numbered PF */
	249	struct pci_dev self; / this PF */
	250	struct mutex lock; /* lock for VF bus */
74bb1bcc YZ	251	struct work_struct mtask; /* VF Migration task */
74bb1bcc YZ	252	u8 __iomem mstate; / VF Migration State Array */
d1b054da YZ	253	};
d1b054da YZ	254
302b4215 YZ	255	/* Address Translation Service */
	256	struct pci_ats {
	257	int pos; /* capability position */
	258	int stu; /* Smallest Translation Unit */
	259	int qdep; /* Invalidate Queue Depth */
e277d2fc	260	int ref_cnt; /* Physical Function reference count */
8356dda2	261	unsigned int is_enabled:1; /* Enable bit is set */
302b4215 YZ	262	};
302b4215 YZ	263
d1b054da YZ	264	#ifdef CONFIG_PCI_IOV
	265	extern int pci_iov_init(struct pci_dev *dev);
	266	extern void pci_iov_release(struct pci_dev *dev);
	267	extern int pci_iov_resource_bar(struct pci_dev *dev, int resno,
	268	enum pci_bar_type *type);
0e52247a CM	269	extern resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev,
0e52247a CM	270	int resno);
8c5cdb6a	271	extern void pci_restore_iov_state(struct pci_dev *dev);
a28724b0	272	extern int pci_iov_bus_range(struct pci_bus *bus);
302b4215 YZ	273
	274	extern int pci_enable_ats(struct pci_dev *dev, int ps);
	275	extern void pci_disable_ats(struct pci_dev *dev);
	276	extern int pci_ats_queue_depth(struct pci_dev *dev);
	277	/**
	278	* pci_ats_enabled - query the ATS status
	279	* @dev: the PCI device
	280	*
	281	* Returns 1 if ATS capability is enabled, or 0 if not.
	282	*/
	283	static inline int pci_ats_enabled(struct pci_dev *dev)
	284	{
e277d2fc	285	return dev->ats && dev->ats->is_enabled;
302b4215	286	}
d1b054da YZ	287	#else
	288	static inline int pci_iov_init(struct pci_dev *dev)
	289	{
	290	return -ENODEV;
	291	}
	292	static inline void pci_iov_release(struct pci_dev *dev)
	293
	294	{
	295	}
	296	static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno,
	297	enum pci_bar_type *type)
	298	{
	299	return 0;
	300	}
8c5cdb6a YZ	301	static inline void pci_restore_iov_state(struct pci_dev *dev)
	302	{
	303	}
a28724b0 YZ	304	static inline int pci_iov_bus_range(struct pci_bus *bus)
	305	{
	306	return 0;
	307	}
302b4215 YZ	308
	309	static inline int pci_enable_ats(struct pci_dev *dev, int ps)
	310	{
	311	return -ENODEV;
	312	}
	313	static inline void pci_disable_ats(struct pci_dev *dev)
	314	{
	315	}
	316	static inline int pci_ats_queue_depth(struct pci_dev *dev)
	317	{
	318	return -ENODEV;
	319	}
	320	static inline int pci_ats_enabled(struct pci_dev *dev)
	321	{
	322	return 0;
	323	}
d1b054da YZ	324	#endif /* CONFIG_PCI_IOV */
d1b054da YZ	325
0e52247a	326	static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
6faf17f6 CW	327	struct resource *res)
	328	{
	329	#ifdef CONFIG_PCI_IOV
	330	int resno = res - dev->resource;
	331
	332	if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
	333	return pci_sriov_resource_alignment(dev, resno);
	334	#endif
	335	return resource_alignment(res);
	336	}
	337
ae21ee65 AK	338	extern void pci_enable_acs(struct pci_dev *dev);
ae21ee65 AK	339
b9c3b266 DC	340	struct pci_dev_reset_methods {
	341	u16 vendor;
	342	u16 device;
	343	int (reset)(struct pci_dev dev, int probe);
	344	};
	345
93177a74	346	#ifdef CONFIG_PCI_QUIRKS
5b889bf2	347	extern int pci_dev_specific_reset(struct pci_dev *dev, int probe);
93177a74 RW	348	#else
	349	static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
	350	{
	351	return -ENOTTY;
	352	}
	353	#endif
b9c3b266	354
557848c3	355	#endif /* DRIVERS_PCI_H */