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Commit | Line | Data |
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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
557848c3 ZY |
2 | #ifndef DRIVERS_PCI_H |
3 | #define DRIVERS_PCI_H | |
4 | ||
2209e06f AG |
5 | #include <linux/pci.h> |
6 | ||
fff905f3 WY |
7 | #define PCI_FIND_CAP_TTL 48 |
8 | ||
8531e283 LW |
9 | #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */ |
10 | ||
343e51ae | 11 | extern const unsigned char pcie_link_speed[]; |
11eb0e0e | 12 | extern bool pci_early_dump; |
343e51ae | 13 | |
7a1562d4 YL |
14 | bool pcie_cap_has_lnkctl(const struct pci_dev *dev); |
15 | ||
1da177e4 LT |
16 | /* Functions internal to the PCI core code */ |
17 | ||
f39d5b72 BH |
18 | int pci_create_sysfs_dev_files(struct pci_dev *pdev); |
19 | void pci_remove_sysfs_dev_files(struct pci_dev *pdev); | |
6058989b | 20 | #if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI) |
911e1c9b | 21 | static inline void pci_create_firmware_label_files(struct pci_dev *pdev) |
b879743f | 22 | { return; } |
911e1c9b | 23 | static inline void pci_remove_firmware_label_files(struct pci_dev *pdev) |
b879743f | 24 | { return; } |
911e1c9b | 25 | #else |
f39d5b72 BH |
26 | void pci_create_firmware_label_files(struct pci_dev *pdev); |
27 | void pci_remove_firmware_label_files(struct pci_dev *pdev); | |
911e1c9b | 28 | #endif |
f39d5b72 | 29 | void pci_cleanup_rom(struct pci_dev *dev); |
f7195824 | 30 | |
3b519e4e MW |
31 | enum pci_mmap_api { |
32 | PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */ | |
33 | PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */ | |
34 | }; | |
f39d5b72 BH |
35 | int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai, |
36 | enum pci_mmap_api mmap_api); | |
f7195824 | 37 | |
711d5779 | 38 | int pci_probe_reset_function(struct pci_dev *dev); |
381634ca | 39 | int pci_bridge_secondary_bus_reset(struct pci_dev *dev); |
c4eed62a | 40 | int pci_bus_error_reset(struct pci_dev *dev); |
ce5ccdef | 41 | |
c776dd50 KS |
42 | #define PCI_PM_D2_DELAY 200 |
43 | #define PCI_PM_D3_WAIT 10 | |
44 | #define PCI_PM_D3COLD_WAIT 100 | |
45 | #define PCI_PM_BUS_WAIT 50 | |
46 | ||
961d9120 | 47 | /** |
b33bfdef | 48 | * struct pci_platform_pm_ops - Firmware PM callbacks |
961d9120 | 49 | * |
26ad34d5 MW |
50 | * @bridge_d3: Does the bridge allow entering into D3 |
51 | * | |
b33bfdef | 52 | * @is_manageable: returns 'true' if given device is power manageable by the |
0aa0f5d1 | 53 | * platform firmware |
961d9120 | 54 | * |
b33bfdef | 55 | * @set_state: invokes the platform firmware to set the device's power state |
961d9120 | 56 | * |
cc7cc02b LW |
57 | * @get_state: queries the platform firmware for a device's current power state |
58 | * | |
b51033e0 RW |
59 | * @refresh_state: asks the platform to refresh the device's power state data |
60 | * | |
b33bfdef | 61 | * @choose_state: returns PCI power state of given device preferred by the |
0aa0f5d1 BH |
62 | * platform; to be used during system-wide transitions from a |
63 | * sleeping state to the working state and vice versa | |
961d9120 | 64 | * |
0847684c | 65 | * @set_wakeup: enables/disables wakeup capability for the device |
b67ea761 | 66 | * |
bac2a909 | 67 | * @need_resume: returns 'true' if the given device (which is currently |
0aa0f5d1 BH |
68 | * suspended) needs to be resumed to be configured for system |
69 | * wakeup. | |
bac2a909 | 70 | * |
961d9120 RW |
71 | * If given platform is generally capable of power managing PCI devices, all of |
72 | * these callbacks are mandatory. | |
73 | */ | |
74 | struct pci_platform_pm_ops { | |
26ad34d5 | 75 | bool (*bridge_d3)(struct pci_dev *dev); |
961d9120 RW |
76 | bool (*is_manageable)(struct pci_dev *dev); |
77 | int (*set_state)(struct pci_dev *dev, pci_power_t state); | |
cc7cc02b | 78 | pci_power_t (*get_state)(struct pci_dev *dev); |
b51033e0 | 79 | void (*refresh_state)(struct pci_dev *dev); |
961d9120 | 80 | pci_power_t (*choose_state)(struct pci_dev *dev); |
0847684c | 81 | int (*set_wakeup)(struct pci_dev *dev, bool enable); |
bac2a909 | 82 | bool (*need_resume)(struct pci_dev *dev); |
961d9120 RW |
83 | }; |
84 | ||
299f2ffe | 85 | int pci_set_platform_pm(const struct pci_platform_pm_ops *ops); |
f39d5b72 | 86 | void pci_update_current_state(struct pci_dev *dev, pci_power_t state); |
b51033e0 | 87 | void pci_refresh_power_state(struct pci_dev *dev); |
f39d5b72 BH |
88 | void pci_power_up(struct pci_dev *dev); |
89 | void pci_disable_enabled_device(struct pci_dev *dev); | |
90 | int pci_finish_runtime_suspend(struct pci_dev *dev); | |
dcb0453d | 91 | void pcie_clear_root_pme_status(struct pci_dev *dev); |
669696eb KS |
92 | bool pci_check_pme_status(struct pci_dev *dev); |
93 | void pci_pme_wakeup_bus(struct pci_bus *bus); | |
f39d5b72 | 94 | int __pci_pme_wakeup(struct pci_dev *dev, void *ign); |
0ce3fcaf | 95 | void pci_pme_restore(struct pci_dev *dev); |
0c7376ad RW |
96 | bool pci_dev_need_resume(struct pci_dev *dev); |
97 | void pci_dev_adjust_pme(struct pci_dev *dev); | |
2cef548a | 98 | void pci_dev_complete_resume(struct pci_dev *pci_dev); |
f39d5b72 BH |
99 | void pci_config_pm_runtime_get(struct pci_dev *dev); |
100 | void pci_config_pm_runtime_put(struct pci_dev *dev); | |
101 | void pci_pm_init(struct pci_dev *dev); | |
938174e5 | 102 | void pci_ea_init(struct pci_dev *dev); |
f39d5b72 | 103 | void pci_allocate_cap_save_buffers(struct pci_dev *dev); |
f796841e | 104 | void pci_free_cap_save_buffers(struct pci_dev *dev); |
c6a63307 | 105 | bool pci_bridge_d3_possible(struct pci_dev *dev); |
1ed276a7 | 106 | void pci_bridge_d3_update(struct pci_dev *dev); |
aa8c6c93 | 107 | |
b6e335ae RW |
108 | static inline void pci_wakeup_event(struct pci_dev *dev) |
109 | { | |
110 | /* Wait 100 ms before the system can be put into a sleep state. */ | |
111 | pm_wakeup_event(&dev->dev, 100); | |
112 | } | |
113 | ||
326c1cda | 114 | static inline bool pci_has_subordinate(struct pci_dev *pci_dev) |
aa8c6c93 RW |
115 | { |
116 | return !!(pci_dev->subordinate); | |
117 | } | |
0f64474b | 118 | |
9d26d3a8 MW |
119 | static inline bool pci_power_manageable(struct pci_dev *pci_dev) |
120 | { | |
121 | /* | |
122 | * Currently we allow normal PCI devices and PCI bridges transition | |
123 | * into D3 if their bridge_d3 is set. | |
124 | */ | |
125 | return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3; | |
126 | } | |
127 | ||
f1cd93f9 | 128 | int pci_vpd_init(struct pci_dev *dev); |
64379079 | 129 | void pci_vpd_release(struct pci_dev *dev); |
b1c615c4 BH |
130 | void pcie_vpd_create_sysfs_dev_files(struct pci_dev *dev); |
131 | void pcie_vpd_remove_sysfs_dev_files(struct pci_dev *dev); | |
94e61088 | 132 | |
440589dd KS |
133 | /* PCI Virtual Channel */ |
134 | int pci_save_vc_state(struct pci_dev *dev); | |
135 | void pci_restore_vc_state(struct pci_dev *dev); | |
136 | void pci_allocate_vc_save_buffers(struct pci_dev *dev); | |
137 | ||
1da177e4 LT |
138 | /* PCI /proc functions */ |
139 | #ifdef CONFIG_PROC_FS | |
f39d5b72 BH |
140 | int pci_proc_attach_device(struct pci_dev *dev); |
141 | int pci_proc_detach_device(struct pci_dev *dev); | |
142 | int pci_proc_detach_bus(struct pci_bus *bus); | |
1da177e4 LT |
143 | #else |
144 | static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; } | |
145 | static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; } | |
1da177e4 LT |
146 | static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; } |
147 | #endif | |
148 | ||
149 | /* Functions for PCI Hotplug drivers to use */ | |
a8e4b9c1 | 150 | int pci_hp_add_bridge(struct pci_dev *dev); |
1da177e4 | 151 | |
f19aeb1f | 152 | #ifdef HAVE_PCI_LEGACY |
f39d5b72 BH |
153 | void pci_create_legacy_files(struct pci_bus *bus); |
154 | void pci_remove_legacy_files(struct pci_bus *bus); | |
f19aeb1f BH |
155 | #else |
156 | static inline void pci_create_legacy_files(struct pci_bus *bus) { return; } | |
157 | static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; } | |
158 | #endif | |
1da177e4 LT |
159 | |
160 | /* Lock for read/write access to pci device and bus lists */ | |
d71374da | 161 | extern struct rw_semaphore pci_bus_sem; |
c4eed62a | 162 | extern struct mutex pci_slot_mutex; |
1da177e4 | 163 | |
a2e27787 JK |
164 | extern raw_spinlock_t pci_lock; |
165 | ||
ffadcc2f | 166 | extern unsigned int pci_pm_d3_delay; |
88187dfa | 167 | |
4b47b0ee | 168 | #ifdef CONFIG_PCI_MSI |
309e57df | 169 | void pci_no_msi(void); |
4b47b0ee | 170 | #else |
309e57df | 171 | static inline void pci_no_msi(void) { } |
4b47b0ee | 172 | #endif |
8fed4b65 | 173 | |
6a25f5e3 MT |
174 | static inline void pci_msi_set_enable(struct pci_dev *dev, int enable) |
175 | { | |
176 | u16 control; | |
177 | ||
178 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); | |
179 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
180 | if (enable) | |
181 | control |= PCI_MSI_FLAGS_ENABLE; | |
182 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); | |
183 | } | |
184 | ||
185 | static inline void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set) | |
186 | { | |
187 | u16 ctrl; | |
188 | ||
189 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl); | |
190 | ctrl &= ~clear; | |
191 | ctrl |= set; | |
192 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl); | |
193 | } | |
194 | ||
b55438fd | 195 | void pci_realloc_get_opt(char *); |
f483d392 | 196 | |
ffadcc2f KCA |
197 | static inline int pci_no_d1d2(struct pci_dev *dev) |
198 | { | |
199 | unsigned int parent_dstates = 0; | |
4b47b0ee | 200 | |
ffadcc2f KCA |
201 | if (dev->bus->self) |
202 | parent_dstates = dev->bus->self->no_d1d2; | |
203 | return (dev->no_d1d2 || parent_dstates); | |
204 | ||
205 | } | |
5136b2da | 206 | extern const struct attribute_group *pci_dev_groups[]; |
56039e65 | 207 | extern const struct attribute_group *pcibus_groups[]; |
69f2dc24 | 208 | extern const struct device_type pci_dev_type; |
0f49ba55 | 209 | extern const struct attribute_group *pci_bus_groups[]; |
705b1aaa | 210 | |
003d3b2c KS |
211 | extern unsigned long pci_hotplug_io_size; |
212 | extern unsigned long pci_hotplug_mem_size; | |
213 | extern unsigned long pci_hotplug_bus_size; | |
1da177e4 LT |
214 | |
215 | /** | |
216 | * pci_match_one_device - Tell if a PCI device structure has a matching | |
0aa0f5d1 | 217 | * PCI device id structure |
1da177e4 LT |
218 | * @id: single PCI device id structure to match |
219 | * @dev: the PCI device structure to match against | |
367b09fe | 220 | * |
1da177e4 LT |
221 | * Returns the matching pci_device_id structure or %NULL if there is no match. |
222 | */ | |
223 | static inline const struct pci_device_id * | |
224 | pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev) | |
225 | { | |
226 | if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) && | |
227 | (id->device == PCI_ANY_ID || id->device == dev->device) && | |
228 | (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) && | |
229 | (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) && | |
230 | !((id->class ^ dev->class) & id->class_mask)) | |
231 | return id; | |
232 | return NULL; | |
233 | } | |
234 | ||
f46753c5 AC |
235 | /* PCI slot sysfs helper code */ |
236 | #define to_pci_slot(s) container_of(s, struct pci_slot, kobj) | |
237 | ||
238 | extern struct kset *pci_slots_kset; | |
239 | ||
240 | struct pci_slot_attribute { | |
241 | struct attribute attr; | |
242 | ssize_t (*show)(struct pci_slot *, char *); | |
243 | ssize_t (*store)(struct pci_slot *, const char *, size_t); | |
244 | }; | |
245 | #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr) | |
246 | ||
0b400c7e YZ |
247 | enum pci_bar_type { |
248 | pci_bar_unknown, /* Standard PCI BAR probe */ | |
0aa0f5d1 | 249 | pci_bar_io, /* An I/O port BAR */ |
0b400c7e YZ |
250 | pci_bar_mem32, /* A 32-bit memory BAR */ |
251 | pci_bar_mem64, /* A 64-bit memory BAR */ | |
252 | }; | |
253 | ||
975e1ac1 KS |
254 | struct device *pci_get_host_bridge_device(struct pci_dev *dev); |
255 | void pci_put_host_bridge_device(struct device *dev); | |
256 | ||
62ce94a7 | 257 | int pci_configure_extended_tags(struct pci_dev *dev, void *ign); |
efdc87da YL |
258 | bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, |
259 | int crs_timeout); | |
aa667c64 JP |
260 | bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, |
261 | int crs_timeout); | |
262 | int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout); | |
263 | ||
f39d5b72 BH |
264 | int pci_setup_device(struct pci_dev *dev); |
265 | int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, | |
266 | struct resource *res, unsigned int reg); | |
f39d5b72 | 267 | void pci_configure_ari(struct pci_dev *dev); |
10874f5a | 268 | void __pci_bus_size_bridges(struct pci_bus *bus, |
d66ecb72 | 269 | struct list_head *realloc_head); |
10874f5a BH |
270 | void __pci_bus_assign_resources(const struct pci_bus *bus, |
271 | struct list_head *realloc_head, | |
272 | struct list_head *fail_head); | |
0f7e7aee | 273 | bool pci_bus_clip_resource(struct pci_dev *dev, int idx); |
939de1d6 | 274 | |
2069ecfb | 275 | void pci_reassigndev_resource_alignment(struct pci_dev *dev); |
f39d5b72 | 276 | void pci_disable_bridge_window(struct pci_dev *dev); |
ecd29c1a KS |
277 | struct pci_bus *pci_bus_get(struct pci_bus *bus); |
278 | void pci_bus_put(struct pci_bus *bus); | |
32a9a682 | 279 | |
6cf57be0 TG |
280 | /* PCIe link information */ |
281 | #define PCIE_SPEED2STR(speed) \ | |
282 | ((speed) == PCIE_SPEED_16_0GT ? "16 GT/s" : \ | |
283 | (speed) == PCIE_SPEED_8_0GT ? "8 GT/s" : \ | |
284 | (speed) == PCIE_SPEED_5_0GT ? "5 GT/s" : \ | |
285 | (speed) == PCIE_SPEED_2_5GT ? "2.5 GT/s" : \ | |
286 | "Unknown speed") | |
287 | ||
b852f63a TG |
288 | /* PCIe speed to Mb/s reduced by encoding overhead */ |
289 | #define PCIE_SPEED2MBS_ENC(speed) \ | |
290 | ((speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \ | |
291 | (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \ | |
292 | (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \ | |
293 | (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \ | |
294 | 0) | |
295 | ||
6cf57be0 | 296 | enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); |
c70b65fb | 297 | enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); |
b852f63a TG |
298 | u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed, |
299 | enum pcie_link_width *width); | |
2d1ce5ec | 300 | void __pcie_print_link_status(struct pci_dev *dev, bool verbose); |
0fa635ae | 301 | void pcie_report_downtraining(struct pci_dev *dev); |
5da78d95 | 302 | void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); |
6cf57be0 | 303 | |
d1b054da YZ |
304 | /* Single Root I/O Virtualization */ |
305 | struct pci_sriov { | |
0aa0f5d1 BH |
306 | int pos; /* Capability position */ |
307 | int nres; /* Number of resources */ | |
308 | u32 cap; /* SR-IOV Capabilities */ | |
309 | u16 ctrl; /* SR-IOV Control */ | |
310 | u16 total_VFs; /* Total VFs associated with the PF */ | |
311 | u16 initial_VFs; /* Initial VFs associated with the PF */ | |
312 | u16 num_VFs; /* Number of VFs available */ | |
313 | u16 offset; /* First VF Routing ID offset */ | |
314 | u16 stride; /* Following VF stride */ | |
315 | u16 vf_device; /* VF device ID */ | |
316 | u32 pgsz; /* Page size for BAR alignment */ | |
317 | u8 link; /* Function Dependency Link */ | |
318 | u8 max_VF_buses; /* Max buses consumed by VFs */ | |
319 | u16 driver_max_VFs; /* Max num VFs driver supports */ | |
320 | struct pci_dev *dev; /* Lowest numbered PF */ | |
321 | struct pci_dev *self; /* This PF */ | |
cf0921be KA |
322 | u32 class; /* VF device */ |
323 | u8 hdr_type; /* VF header type */ | |
324 | u16 subsystem_vendor; /* VF subsystem vendor */ | |
325 | u16 subsystem_device; /* VF subsystem device */ | |
0aa0f5d1 BH |
326 | resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */ |
327 | bool drivers_autoprobe; /* Auto probing of VFs by driver */ | |
d1b054da YZ |
328 | }; |
329 | ||
a6bd101b KB |
330 | /** |
331 | * pci_dev_set_io_state - Set the new error state if possible. | |
332 | * | |
333 | * @dev - pci device to set new error_state | |
334 | * @new - the state we want dev to be in | |
335 | * | |
336 | * Must be called with device_lock held. | |
337 | * | |
338 | * Returns true if state has been changed to the requested state. | |
339 | */ | |
340 | static inline bool pci_dev_set_io_state(struct pci_dev *dev, | |
341 | pci_channel_state_t new) | |
342 | { | |
343 | bool changed = false; | |
344 | ||
345 | device_lock_assert(&dev->dev); | |
346 | switch (new) { | |
347 | case pci_channel_io_perm_failure: | |
348 | switch (dev->error_state) { | |
349 | case pci_channel_io_frozen: | |
350 | case pci_channel_io_normal: | |
351 | case pci_channel_io_perm_failure: | |
352 | changed = true; | |
353 | break; | |
354 | } | |
355 | break; | |
356 | case pci_channel_io_frozen: | |
357 | switch (dev->error_state) { | |
358 | case pci_channel_io_frozen: | |
359 | case pci_channel_io_normal: | |
360 | changed = true; | |
361 | break; | |
362 | } | |
363 | break; | |
364 | case pci_channel_io_normal: | |
365 | switch (dev->error_state) { | |
366 | case pci_channel_io_frozen: | |
367 | case pci_channel_io_normal: | |
368 | changed = true; | |
369 | break; | |
370 | } | |
371 | break; | |
372 | } | |
373 | if (changed) | |
374 | dev->error_state = new; | |
375 | return changed; | |
376 | } | |
89ee9f76 KB |
377 | |
378 | static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused) | |
379 | { | |
a6bd101b KB |
380 | device_lock(&dev->dev); |
381 | pci_dev_set_io_state(dev, pci_channel_io_perm_failure); | |
382 | device_unlock(&dev->dev); | |
383 | ||
89ee9f76 KB |
384 | return 0; |
385 | } | |
386 | ||
387 | static inline bool pci_dev_is_disconnected(const struct pci_dev *dev) | |
388 | { | |
a6bd101b | 389 | return dev->error_state == pci_channel_io_perm_failure; |
89ee9f76 KB |
390 | } |
391 | ||
a6bd101b KB |
392 | /* pci_dev priv_flags */ |
393 | #define PCI_DEV_ADDED 0 | |
394 | ||
44bda4b7 HV |
395 | static inline void pci_dev_assign_added(struct pci_dev *dev, bool added) |
396 | { | |
397 | assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added); | |
398 | } | |
399 | ||
400 | static inline bool pci_dev_is_added(const struct pci_dev *dev) | |
401 | { | |
402 | return test_bit(PCI_DEV_ADDED, &dev->priv_flags); | |
403 | } | |
404 | ||
1e451160 KB |
405 | #ifdef CONFIG_PCIEAER |
406 | #include <linux/aer.h> | |
407 | ||
408 | #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */ | |
409 | ||
410 | struct aer_err_info { | |
411 | struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES]; | |
412 | int error_dev_num; | |
413 | ||
414 | unsigned int id:16; | |
415 | ||
416 | unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */ | |
417 | unsigned int __pad1:5; | |
418 | unsigned int multi_error_valid:1; | |
419 | ||
420 | unsigned int first_error:5; | |
421 | unsigned int __pad2:2; | |
422 | unsigned int tlp_header_valid:1; | |
423 | ||
424 | unsigned int status; /* COR/UNCOR Error Status */ | |
425 | unsigned int mask; /* COR/UNCOR Error Mask */ | |
426 | struct aer_header_log_regs tlp; /* TLP Header */ | |
427 | }; | |
428 | ||
429 | int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info); | |
430 | void aer_print_error(struct pci_dev *dev, struct aer_err_info *info); | |
431 | #endif /* CONFIG_PCIEAER */ | |
432 | ||
4f802170 KB |
433 | #ifdef CONFIG_PCIE_DPC |
434 | void pci_save_dpc_state(struct pci_dev *dev); | |
435 | void pci_restore_dpc_state(struct pci_dev *dev); | |
436 | #else | |
437 | static inline void pci_save_dpc_state(struct pci_dev *dev) {} | |
438 | static inline void pci_restore_dpc_state(struct pci_dev *dev) {} | |
439 | #endif | |
440 | ||
1900ca13 | 441 | #ifdef CONFIG_PCI_ATS |
f39d5b72 | 442 | void pci_restore_ats_state(struct pci_dev *dev); |
1900ca13 HX |
443 | #else |
444 | static inline void pci_restore_ats_state(struct pci_dev *dev) | |
445 | { | |
446 | } | |
447 | #endif /* CONFIG_PCI_ATS */ | |
448 | ||
d1b054da | 449 | #ifdef CONFIG_PCI_IOV |
f39d5b72 BH |
450 | int pci_iov_init(struct pci_dev *dev); |
451 | void pci_iov_release(struct pci_dev *dev); | |
38972375 | 452 | void pci_iov_remove(struct pci_dev *dev); |
6ffa2489 | 453 | void pci_iov_update_resource(struct pci_dev *dev, int resno); |
f39d5b72 BH |
454 | resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno); |
455 | void pci_restore_iov_state(struct pci_dev *dev); | |
456 | int pci_iov_bus_range(struct pci_bus *bus); | |
302b4215 | 457 | |
d1b054da YZ |
458 | #else |
459 | static inline int pci_iov_init(struct pci_dev *dev) | |
460 | { | |
461 | return -ENODEV; | |
462 | } | |
463 | static inline void pci_iov_release(struct pci_dev *dev) | |
464 | ||
38972375 JK |
465 | { |
466 | } | |
467 | static inline void pci_iov_remove(struct pci_dev *dev) | |
d1b054da YZ |
468 | { |
469 | } | |
8c5cdb6a YZ |
470 | static inline void pci_restore_iov_state(struct pci_dev *dev) |
471 | { | |
472 | } | |
a28724b0 YZ |
473 | static inline int pci_iov_bus_range(struct pci_bus *bus) |
474 | { | |
475 | return 0; | |
476 | } | |
302b4215 | 477 | |
d1b054da YZ |
478 | #endif /* CONFIG_PCI_IOV */ |
479 | ||
f39d5b72 | 480 | unsigned long pci_cardbus_resource_alignment(struct resource *); |
0a2daa1c | 481 | |
0e52247a | 482 | static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, |
f39d5b72 | 483 | struct resource *res) |
6faf17f6 CW |
484 | { |
485 | #ifdef CONFIG_PCI_IOV | |
486 | int resno = res - dev->resource; | |
487 | ||
488 | if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END) | |
489 | return pci_sriov_resource_alignment(dev, resno); | |
490 | #endif | |
0aa0f5d1 | 491 | if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS) |
0a2daa1c | 492 | return pci_cardbus_resource_alignment(res); |
6faf17f6 CW |
493 | return resource_alignment(res); |
494 | } | |
495 | ||
f39d5b72 | 496 | void pci_enable_acs(struct pci_dev *dev); |
bd2e9567 BH |
497 | #ifdef CONFIG_PCI_QUIRKS |
498 | int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); | |
499 | int pci_dev_specific_enable_acs(struct pci_dev *dev); | |
73c47dde | 500 | int pci_dev_specific_disable_acs_redir(struct pci_dev *dev); |
bd2e9567 BH |
501 | #else |
502 | static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, | |
503 | u16 acs_flags) | |
504 | { | |
505 | return -ENOTTY; | |
506 | } | |
507 | static inline int pci_dev_specific_enable_acs(struct pci_dev *dev) | |
508 | { | |
509 | return -ENOTTY; | |
510 | } | |
73c47dde LG |
511 | static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) |
512 | { | |
513 | return -ENOTTY; | |
514 | } | |
bd2e9567 | 515 | #endif |
ae21ee65 | 516 | |
2e28bc84 | 517 | /* PCI error reporting and recovery */ |
bdb5ac85 KB |
518 | void pcie_do_recovery(struct pci_dev *dev, enum pci_channel_state state, |
519 | u32 service); | |
2e28bc84 | 520 | |
c2bf1fc2 | 521 | bool pcie_wait_for_link_delay(struct pci_dev *pdev, bool active, int delay); |
9f5a70f1 | 522 | bool pcie_wait_for_link(struct pci_dev *pdev, bool active); |
7d8e7d19 BH |
523 | #ifdef CONFIG_PCIEASPM |
524 | void pcie_aspm_init_link_state(struct pci_dev *pdev); | |
525 | void pcie_aspm_exit_link_state(struct pci_dev *pdev); | |
526 | void pcie_aspm_pm_state_change(struct pci_dev *pdev); | |
527 | void pcie_aspm_powersave_config_link(struct pci_dev *pdev); | |
528 | #else | |
529 | static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { } | |
530 | static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { } | |
531 | static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { } | |
532 | static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { } | |
533 | #endif | |
534 | ||
535 | #ifdef CONFIG_PCIEASPM_DEBUG | |
536 | void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev); | |
537 | void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev); | |
538 | #else | |
539 | static inline void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev) { } | |
540 | static inline void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev) { } | |
541 | #endif | |
542 | ||
9bb04a0c JY |
543 | #ifdef CONFIG_PCIE_PTM |
544 | void pci_ptm_init(struct pci_dev *dev); | |
545 | #else | |
546 | static inline void pci_ptm_init(struct pci_dev *dev) { } | |
547 | #endif | |
548 | ||
b9c3b266 DC |
549 | struct pci_dev_reset_methods { |
550 | u16 vendor; | |
551 | u16 device; | |
552 | int (*reset)(struct pci_dev *dev, int probe); | |
553 | }; | |
554 | ||
93177a74 | 555 | #ifdef CONFIG_PCI_QUIRKS |
f39d5b72 | 556 | int pci_dev_specific_reset(struct pci_dev *dev, int probe); |
93177a74 RW |
557 | #else |
558 | static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe) | |
559 | { | |
560 | return -ENOTTY; | |
561 | } | |
562 | #endif | |
b9c3b266 | 563 | |
169de969 DL |
564 | #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64) |
565 | int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment, | |
566 | struct resource *res); | |
567 | #endif | |
568 | ||
276b738d CK |
569 | u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar); |
570 | int pci_rebar_get_current_size(struct pci_dev *pdev, int bar); | |
571 | int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size); | |
572 | static inline u64 pci_rebar_size_to_bytes(int size) | |
573 | { | |
574 | return 1ULL << (size + 20); | |
575 | } | |
576 | ||
9e2aee80 RH |
577 | struct device_node; |
578 | ||
579 | #ifdef CONFIG_OF | |
580 | int of_pci_parse_bus_range(struct device_node *node, struct resource *res); | |
581 | int of_get_pci_domain_nr(struct device_node *node); | |
582 | int of_pci_get_max_link_speed(struct device_node *node); | |
583 | ||
584 | #else | |
585 | static inline int | |
586 | of_pci_parse_bus_range(struct device_node *node, struct resource *res) | |
587 | { | |
588 | return -EINVAL; | |
589 | } | |
590 | ||
591 | static inline int | |
592 | of_get_pci_domain_nr(struct device_node *node) | |
593 | { | |
594 | return -1; | |
595 | } | |
596 | ||
597 | static inline int | |
598 | of_pci_get_max_link_speed(struct device_node *node) | |
599 | { | |
600 | return -EINVAL; | |
601 | } | |
602 | #endif /* CONFIG_OF */ | |
603 | ||
604 | #if defined(CONFIG_OF_ADDRESS) | |
f03c7aa4 | 605 | int devm_of_pci_get_host_bridge_resources(struct device *dev, |
9e2aee80 RH |
606 | unsigned char busno, unsigned char bus_max, |
607 | struct list_head *resources, resource_size_t *io_base); | |
608 | #else | |
f03c7aa4 | 609 | static inline int devm_of_pci_get_host_bridge_resources(struct device *dev, |
9e2aee80 RH |
610 | unsigned char busno, unsigned char bus_max, |
611 | struct list_head *resources, resource_size_t *io_base) | |
612 | { | |
613 | return -EINVAL; | |
614 | } | |
615 | #endif | |
616 | ||
60ed982a RJ |
617 | #ifdef CONFIG_PCIEAER |
618 | void pci_no_aer(void); | |
619 | void pci_aer_init(struct pci_dev *dev); | |
db89ccbe | 620 | void pci_aer_exit(struct pci_dev *dev); |
81aa5206 | 621 | extern const struct attribute_group aer_stats_attr_group; |
7ab92e89 | 622 | void pci_aer_clear_fatal_status(struct pci_dev *dev); |
ec752f5d | 623 | void pci_aer_clear_device_status(struct pci_dev *dev); |
60ed982a RJ |
624 | #else |
625 | static inline void pci_no_aer(void) { } | |
31f996ef | 626 | static inline void pci_aer_init(struct pci_dev *d) { } |
db89ccbe | 627 | static inline void pci_aer_exit(struct pci_dev *d) { } |
7ab92e89 | 628 | static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } |
ec752f5d | 629 | static inline void pci_aer_clear_device_status(struct pci_dev *dev) { } |
60ed982a RJ |
630 | #endif |
631 | ||
557848c3 | 632 | #endif /* DRIVERS_PCI_H */ |