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Commit | Line | Data |
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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
557848c3 ZY |
2 | #ifndef DRIVERS_PCI_H |
3 | #define DRIVERS_PCI_H | |
4 | ||
fff905f3 WY |
5 | #define PCI_FIND_CAP_TTL 48 |
6 | ||
8531e283 LW |
7 | #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */ |
8 | ||
343e51ae | 9 | extern const unsigned char pcie_link_speed[]; |
11eb0e0e | 10 | extern bool pci_early_dump; |
343e51ae | 11 | |
7a1562d4 YL |
12 | bool pcie_cap_has_lnkctl(const struct pci_dev *dev); |
13 | ||
1da177e4 LT |
14 | /* Functions internal to the PCI core code */ |
15 | ||
f39d5b72 BH |
16 | int pci_create_sysfs_dev_files(struct pci_dev *pdev); |
17 | void pci_remove_sysfs_dev_files(struct pci_dev *pdev); | |
6058989b | 18 | #if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI) |
911e1c9b | 19 | static inline void pci_create_firmware_label_files(struct pci_dev *pdev) |
b879743f | 20 | { return; } |
911e1c9b | 21 | static inline void pci_remove_firmware_label_files(struct pci_dev *pdev) |
b879743f | 22 | { return; } |
911e1c9b | 23 | #else |
f39d5b72 BH |
24 | void pci_create_firmware_label_files(struct pci_dev *pdev); |
25 | void pci_remove_firmware_label_files(struct pci_dev *pdev); | |
911e1c9b | 26 | #endif |
f39d5b72 | 27 | void pci_cleanup_rom(struct pci_dev *dev); |
f7195824 | 28 | |
3b519e4e MW |
29 | enum pci_mmap_api { |
30 | PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */ | |
31 | PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */ | |
32 | }; | |
f39d5b72 BH |
33 | int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai, |
34 | enum pci_mmap_api mmap_api); | |
f7195824 | 35 | |
711d5779 | 36 | int pci_probe_reset_function(struct pci_dev *dev); |
381634ca | 37 | int pci_bridge_secondary_bus_reset(struct pci_dev *dev); |
c4eed62a | 38 | int pci_bus_error_reset(struct pci_dev *dev); |
ce5ccdef | 39 | |
961d9120 | 40 | /** |
b33bfdef | 41 | * struct pci_platform_pm_ops - Firmware PM callbacks |
961d9120 | 42 | * |
b33bfdef | 43 | * @is_manageable: returns 'true' if given device is power manageable by the |
0aa0f5d1 | 44 | * platform firmware |
961d9120 | 45 | * |
b33bfdef | 46 | * @set_state: invokes the platform firmware to set the device's power state |
961d9120 | 47 | * |
cc7cc02b LW |
48 | * @get_state: queries the platform firmware for a device's current power state |
49 | * | |
b33bfdef | 50 | * @choose_state: returns PCI power state of given device preferred by the |
0aa0f5d1 BH |
51 | * platform; to be used during system-wide transitions from a |
52 | * sleeping state to the working state and vice versa | |
961d9120 | 53 | * |
0847684c | 54 | * @set_wakeup: enables/disables wakeup capability for the device |
b67ea761 | 55 | * |
bac2a909 | 56 | * @need_resume: returns 'true' if the given device (which is currently |
0aa0f5d1 BH |
57 | * suspended) needs to be resumed to be configured for system |
58 | * wakeup. | |
bac2a909 | 59 | * |
961d9120 RW |
60 | * If given platform is generally capable of power managing PCI devices, all of |
61 | * these callbacks are mandatory. | |
62 | */ | |
63 | struct pci_platform_pm_ops { | |
64 | bool (*is_manageable)(struct pci_dev *dev); | |
65 | int (*set_state)(struct pci_dev *dev, pci_power_t state); | |
cc7cc02b | 66 | pci_power_t (*get_state)(struct pci_dev *dev); |
961d9120 | 67 | pci_power_t (*choose_state)(struct pci_dev *dev); |
0847684c | 68 | int (*set_wakeup)(struct pci_dev *dev, bool enable); |
bac2a909 | 69 | bool (*need_resume)(struct pci_dev *dev); |
961d9120 RW |
70 | }; |
71 | ||
299f2ffe | 72 | int pci_set_platform_pm(const struct pci_platform_pm_ops *ops); |
f39d5b72 BH |
73 | void pci_update_current_state(struct pci_dev *dev, pci_power_t state); |
74 | void pci_power_up(struct pci_dev *dev); | |
75 | void pci_disable_enabled_device(struct pci_dev *dev); | |
76 | int pci_finish_runtime_suspend(struct pci_dev *dev); | |
dcb0453d | 77 | void pcie_clear_root_pme_status(struct pci_dev *dev); |
f39d5b72 | 78 | int __pci_pme_wakeup(struct pci_dev *dev, void *ign); |
0ce3fcaf | 79 | void pci_pme_restore(struct pci_dev *dev); |
bac2a909 | 80 | bool pci_dev_keep_suspended(struct pci_dev *dev); |
2cef548a | 81 | void pci_dev_complete_resume(struct pci_dev *pci_dev); |
f39d5b72 BH |
82 | void pci_config_pm_runtime_get(struct pci_dev *dev); |
83 | void pci_config_pm_runtime_put(struct pci_dev *dev); | |
84 | void pci_pm_init(struct pci_dev *dev); | |
938174e5 | 85 | void pci_ea_init(struct pci_dev *dev); |
f39d5b72 | 86 | void pci_allocate_cap_save_buffers(struct pci_dev *dev); |
f796841e | 87 | void pci_free_cap_save_buffers(struct pci_dev *dev); |
c6a63307 | 88 | bool pci_bridge_d3_possible(struct pci_dev *dev); |
1ed276a7 | 89 | void pci_bridge_d3_update(struct pci_dev *dev); |
aa8c6c93 | 90 | |
b6e335ae RW |
91 | static inline void pci_wakeup_event(struct pci_dev *dev) |
92 | { | |
93 | /* Wait 100 ms before the system can be put into a sleep state. */ | |
94 | pm_wakeup_event(&dev->dev, 100); | |
95 | } | |
96 | ||
326c1cda | 97 | static inline bool pci_has_subordinate(struct pci_dev *pci_dev) |
aa8c6c93 RW |
98 | { |
99 | return !!(pci_dev->subordinate); | |
100 | } | |
0f64474b | 101 | |
9d26d3a8 MW |
102 | static inline bool pci_power_manageable(struct pci_dev *pci_dev) |
103 | { | |
104 | /* | |
105 | * Currently we allow normal PCI devices and PCI bridges transition | |
106 | * into D3 if their bridge_d3 is set. | |
107 | */ | |
108 | return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3; | |
109 | } | |
110 | ||
f1cd93f9 | 111 | int pci_vpd_init(struct pci_dev *dev); |
64379079 | 112 | void pci_vpd_release(struct pci_dev *dev); |
b1c615c4 BH |
113 | void pcie_vpd_create_sysfs_dev_files(struct pci_dev *dev); |
114 | void pcie_vpd_remove_sysfs_dev_files(struct pci_dev *dev); | |
94e61088 | 115 | |
1da177e4 LT |
116 | /* PCI /proc functions */ |
117 | #ifdef CONFIG_PROC_FS | |
f39d5b72 BH |
118 | int pci_proc_attach_device(struct pci_dev *dev); |
119 | int pci_proc_detach_device(struct pci_dev *dev); | |
120 | int pci_proc_detach_bus(struct pci_bus *bus); | |
1da177e4 LT |
121 | #else |
122 | static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; } | |
123 | static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; } | |
1da177e4 LT |
124 | static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; } |
125 | #endif | |
126 | ||
127 | /* Functions for PCI Hotplug drivers to use */ | |
a8e4b9c1 | 128 | int pci_hp_add_bridge(struct pci_dev *dev); |
1da177e4 | 129 | |
f19aeb1f | 130 | #ifdef HAVE_PCI_LEGACY |
f39d5b72 BH |
131 | void pci_create_legacy_files(struct pci_bus *bus); |
132 | void pci_remove_legacy_files(struct pci_bus *bus); | |
f19aeb1f BH |
133 | #else |
134 | static inline void pci_create_legacy_files(struct pci_bus *bus) { return; } | |
135 | static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; } | |
136 | #endif | |
1da177e4 LT |
137 | |
138 | /* Lock for read/write access to pci device and bus lists */ | |
d71374da | 139 | extern struct rw_semaphore pci_bus_sem; |
c4eed62a | 140 | extern struct mutex pci_slot_mutex; |
1da177e4 | 141 | |
a2e27787 JK |
142 | extern raw_spinlock_t pci_lock; |
143 | ||
ffadcc2f | 144 | extern unsigned int pci_pm_d3_delay; |
88187dfa | 145 | |
4b47b0ee | 146 | #ifdef CONFIG_PCI_MSI |
309e57df | 147 | void pci_no_msi(void); |
4b47b0ee | 148 | #else |
309e57df | 149 | static inline void pci_no_msi(void) { } |
4b47b0ee | 150 | #endif |
8fed4b65 | 151 | |
6a25f5e3 MT |
152 | static inline void pci_msi_set_enable(struct pci_dev *dev, int enable) |
153 | { | |
154 | u16 control; | |
155 | ||
156 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); | |
157 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
158 | if (enable) | |
159 | control |= PCI_MSI_FLAGS_ENABLE; | |
160 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); | |
161 | } | |
162 | ||
163 | static inline void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set) | |
164 | { | |
165 | u16 ctrl; | |
166 | ||
167 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl); | |
168 | ctrl &= ~clear; | |
169 | ctrl |= set; | |
170 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl); | |
171 | } | |
172 | ||
b55438fd | 173 | void pci_realloc_get_opt(char *); |
f483d392 | 174 | |
ffadcc2f KCA |
175 | static inline int pci_no_d1d2(struct pci_dev *dev) |
176 | { | |
177 | unsigned int parent_dstates = 0; | |
4b47b0ee | 178 | |
ffadcc2f KCA |
179 | if (dev->bus->self) |
180 | parent_dstates = dev->bus->self->no_d1d2; | |
181 | return (dev->no_d1d2 || parent_dstates); | |
182 | ||
183 | } | |
5136b2da | 184 | extern const struct attribute_group *pci_dev_groups[]; |
56039e65 | 185 | extern const struct attribute_group *pcibus_groups[]; |
69f2dc24 | 186 | extern const struct device_type pci_dev_type; |
0f49ba55 | 187 | extern const struct attribute_group *pci_bus_groups[]; |
705b1aaa | 188 | |
1da177e4 LT |
189 | |
190 | /** | |
191 | * pci_match_one_device - Tell if a PCI device structure has a matching | |
0aa0f5d1 | 192 | * PCI device id structure |
1da177e4 LT |
193 | * @id: single PCI device id structure to match |
194 | * @dev: the PCI device structure to match against | |
367b09fe | 195 | * |
1da177e4 LT |
196 | * Returns the matching pci_device_id structure or %NULL if there is no match. |
197 | */ | |
198 | static inline const struct pci_device_id * | |
199 | pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev) | |
200 | { | |
201 | if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) && | |
202 | (id->device == PCI_ANY_ID || id->device == dev->device) && | |
203 | (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) && | |
204 | (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) && | |
205 | !((id->class ^ dev->class) & id->class_mask)) | |
206 | return id; | |
207 | return NULL; | |
208 | } | |
209 | ||
f46753c5 AC |
210 | /* PCI slot sysfs helper code */ |
211 | #define to_pci_slot(s) container_of(s, struct pci_slot, kobj) | |
212 | ||
213 | extern struct kset *pci_slots_kset; | |
214 | ||
215 | struct pci_slot_attribute { | |
216 | struct attribute attr; | |
217 | ssize_t (*show)(struct pci_slot *, char *); | |
218 | ssize_t (*store)(struct pci_slot *, const char *, size_t); | |
219 | }; | |
220 | #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr) | |
221 | ||
0b400c7e YZ |
222 | enum pci_bar_type { |
223 | pci_bar_unknown, /* Standard PCI BAR probe */ | |
0aa0f5d1 | 224 | pci_bar_io, /* An I/O port BAR */ |
0b400c7e YZ |
225 | pci_bar_mem32, /* A 32-bit memory BAR */ |
226 | pci_bar_mem64, /* A 64-bit memory BAR */ | |
227 | }; | |
228 | ||
62ce94a7 | 229 | int pci_configure_extended_tags(struct pci_dev *dev, void *ign); |
efdc87da YL |
230 | bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, |
231 | int crs_timeout); | |
aa667c64 JP |
232 | bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, |
233 | int crs_timeout); | |
234 | int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout); | |
235 | ||
f39d5b72 BH |
236 | int pci_setup_device(struct pci_dev *dev); |
237 | int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, | |
238 | struct resource *res, unsigned int reg); | |
f39d5b72 | 239 | void pci_configure_ari(struct pci_dev *dev); |
10874f5a | 240 | void __pci_bus_size_bridges(struct pci_bus *bus, |
d66ecb72 | 241 | struct list_head *realloc_head); |
10874f5a BH |
242 | void __pci_bus_assign_resources(const struct pci_bus *bus, |
243 | struct list_head *realloc_head, | |
244 | struct list_head *fail_head); | |
0f7e7aee | 245 | bool pci_bus_clip_resource(struct pci_dev *dev, int idx); |
939de1d6 | 246 | |
2069ecfb | 247 | void pci_reassigndev_resource_alignment(struct pci_dev *dev); |
f39d5b72 | 248 | void pci_disable_bridge_window(struct pci_dev *dev); |
32a9a682 | 249 | |
6cf57be0 TG |
250 | /* PCIe link information */ |
251 | #define PCIE_SPEED2STR(speed) \ | |
252 | ((speed) == PCIE_SPEED_16_0GT ? "16 GT/s" : \ | |
253 | (speed) == PCIE_SPEED_8_0GT ? "8 GT/s" : \ | |
254 | (speed) == PCIE_SPEED_5_0GT ? "5 GT/s" : \ | |
255 | (speed) == PCIE_SPEED_2_5GT ? "2.5 GT/s" : \ | |
256 | "Unknown speed") | |
257 | ||
b852f63a TG |
258 | /* PCIe speed to Mb/s reduced by encoding overhead */ |
259 | #define PCIE_SPEED2MBS_ENC(speed) \ | |
260 | ((speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \ | |
261 | (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \ | |
262 | (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \ | |
263 | (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \ | |
264 | 0) | |
265 | ||
6cf57be0 | 266 | enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); |
c70b65fb | 267 | enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); |
b852f63a TG |
268 | u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed, |
269 | enum pcie_link_width *width); | |
2d1ce5ec | 270 | void __pcie_print_link_status(struct pci_dev *dev, bool verbose); |
6cf57be0 | 271 | |
d1b054da YZ |
272 | /* Single Root I/O Virtualization */ |
273 | struct pci_sriov { | |
0aa0f5d1 BH |
274 | int pos; /* Capability position */ |
275 | int nres; /* Number of resources */ | |
276 | u32 cap; /* SR-IOV Capabilities */ | |
277 | u16 ctrl; /* SR-IOV Control */ | |
278 | u16 total_VFs; /* Total VFs associated with the PF */ | |
279 | u16 initial_VFs; /* Initial VFs associated with the PF */ | |
280 | u16 num_VFs; /* Number of VFs available */ | |
281 | u16 offset; /* First VF Routing ID offset */ | |
282 | u16 stride; /* Following VF stride */ | |
283 | u16 vf_device; /* VF device ID */ | |
284 | u32 pgsz; /* Page size for BAR alignment */ | |
285 | u8 link; /* Function Dependency Link */ | |
286 | u8 max_VF_buses; /* Max buses consumed by VFs */ | |
287 | u16 driver_max_VFs; /* Max num VFs driver supports */ | |
288 | struct pci_dev *dev; /* Lowest numbered PF */ | |
289 | struct pci_dev *self; /* This PF */ | |
cf0921be KA |
290 | u32 class; /* VF device */ |
291 | u8 hdr_type; /* VF header type */ | |
292 | u16 subsystem_vendor; /* VF subsystem vendor */ | |
293 | u16 subsystem_device; /* VF subsystem device */ | |
0aa0f5d1 BH |
294 | resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */ |
295 | bool drivers_autoprobe; /* Auto probing of VFs by driver */ | |
d1b054da YZ |
296 | }; |
297 | ||
89ee9f76 KB |
298 | /* pci_dev priv_flags */ |
299 | #define PCI_DEV_DISCONNECTED 0 | |
44bda4b7 | 300 | #define PCI_DEV_ADDED 1 |
89ee9f76 KB |
301 | |
302 | static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused) | |
303 | { | |
304 | set_bit(PCI_DEV_DISCONNECTED, &dev->priv_flags); | |
305 | return 0; | |
306 | } | |
307 | ||
308 | static inline bool pci_dev_is_disconnected(const struct pci_dev *dev) | |
309 | { | |
310 | return test_bit(PCI_DEV_DISCONNECTED, &dev->priv_flags); | |
311 | } | |
312 | ||
44bda4b7 HV |
313 | static inline void pci_dev_assign_added(struct pci_dev *dev, bool added) |
314 | { | |
315 | assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added); | |
316 | } | |
317 | ||
318 | static inline bool pci_dev_is_added(const struct pci_dev *dev) | |
319 | { | |
320 | return test_bit(PCI_DEV_ADDED, &dev->priv_flags); | |
321 | } | |
322 | ||
1e451160 KB |
323 | #ifdef CONFIG_PCIEAER |
324 | #include <linux/aer.h> | |
325 | ||
326 | #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */ | |
327 | ||
328 | struct aer_err_info { | |
329 | struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES]; | |
330 | int error_dev_num; | |
331 | ||
332 | unsigned int id:16; | |
333 | ||
334 | unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */ | |
335 | unsigned int __pad1:5; | |
336 | unsigned int multi_error_valid:1; | |
337 | ||
338 | unsigned int first_error:5; | |
339 | unsigned int __pad2:2; | |
340 | unsigned int tlp_header_valid:1; | |
341 | ||
342 | unsigned int status; /* COR/UNCOR Error Status */ | |
343 | unsigned int mask; /* COR/UNCOR Error Mask */ | |
344 | struct aer_header_log_regs tlp; /* TLP Header */ | |
345 | }; | |
346 | ||
347 | int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info); | |
348 | void aer_print_error(struct pci_dev *dev, struct aer_err_info *info); | |
349 | #endif /* CONFIG_PCIEAER */ | |
350 | ||
4f802170 KB |
351 | #ifdef CONFIG_PCIE_DPC |
352 | void pci_save_dpc_state(struct pci_dev *dev); | |
353 | void pci_restore_dpc_state(struct pci_dev *dev); | |
354 | #else | |
355 | static inline void pci_save_dpc_state(struct pci_dev *dev) {} | |
356 | static inline void pci_restore_dpc_state(struct pci_dev *dev) {} | |
357 | #endif | |
358 | ||
1900ca13 | 359 | #ifdef CONFIG_PCI_ATS |
f39d5b72 | 360 | void pci_restore_ats_state(struct pci_dev *dev); |
1900ca13 HX |
361 | #else |
362 | static inline void pci_restore_ats_state(struct pci_dev *dev) | |
363 | { | |
364 | } | |
365 | #endif /* CONFIG_PCI_ATS */ | |
366 | ||
d1b054da | 367 | #ifdef CONFIG_PCI_IOV |
f39d5b72 BH |
368 | int pci_iov_init(struct pci_dev *dev); |
369 | void pci_iov_release(struct pci_dev *dev); | |
38972375 | 370 | void pci_iov_remove(struct pci_dev *dev); |
6ffa2489 | 371 | void pci_iov_update_resource(struct pci_dev *dev, int resno); |
f39d5b72 BH |
372 | resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno); |
373 | void pci_restore_iov_state(struct pci_dev *dev); | |
374 | int pci_iov_bus_range(struct pci_bus *bus); | |
302b4215 | 375 | |
d1b054da YZ |
376 | #else |
377 | static inline int pci_iov_init(struct pci_dev *dev) | |
378 | { | |
379 | return -ENODEV; | |
380 | } | |
381 | static inline void pci_iov_release(struct pci_dev *dev) | |
382 | ||
38972375 JK |
383 | { |
384 | } | |
385 | static inline void pci_iov_remove(struct pci_dev *dev) | |
d1b054da YZ |
386 | { |
387 | } | |
8c5cdb6a YZ |
388 | static inline void pci_restore_iov_state(struct pci_dev *dev) |
389 | { | |
390 | } | |
a28724b0 YZ |
391 | static inline int pci_iov_bus_range(struct pci_bus *bus) |
392 | { | |
393 | return 0; | |
394 | } | |
302b4215 | 395 | |
d1b054da YZ |
396 | #endif /* CONFIG_PCI_IOV */ |
397 | ||
f39d5b72 | 398 | unsigned long pci_cardbus_resource_alignment(struct resource *); |
0a2daa1c | 399 | |
0e52247a | 400 | static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, |
f39d5b72 | 401 | struct resource *res) |
6faf17f6 CW |
402 | { |
403 | #ifdef CONFIG_PCI_IOV | |
404 | int resno = res - dev->resource; | |
405 | ||
406 | if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END) | |
407 | return pci_sriov_resource_alignment(dev, resno); | |
408 | #endif | |
0aa0f5d1 | 409 | if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS) |
0a2daa1c | 410 | return pci_cardbus_resource_alignment(res); |
6faf17f6 CW |
411 | return resource_alignment(res); |
412 | } | |
413 | ||
f39d5b72 | 414 | void pci_enable_acs(struct pci_dev *dev); |
bd2e9567 BH |
415 | #ifdef CONFIG_PCI_QUIRKS |
416 | int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); | |
417 | int pci_dev_specific_enable_acs(struct pci_dev *dev); | |
73c47dde | 418 | int pci_dev_specific_disable_acs_redir(struct pci_dev *dev); |
bd2e9567 BH |
419 | #else |
420 | static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, | |
421 | u16 acs_flags) | |
422 | { | |
423 | return -ENOTTY; | |
424 | } | |
425 | static inline int pci_dev_specific_enable_acs(struct pci_dev *dev) | |
426 | { | |
427 | return -ENOTTY; | |
428 | } | |
73c47dde LG |
429 | static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) |
430 | { | |
431 | return -ENOTTY; | |
432 | } | |
bd2e9567 | 433 | #endif |
ae21ee65 | 434 | |
2e28bc84 | 435 | /* PCI error reporting and recovery */ |
bdb5ac85 KB |
436 | void pcie_do_recovery(struct pci_dev *dev, enum pci_channel_state state, |
437 | u32 service); | |
2e28bc84 | 438 | |
9f5a70f1 | 439 | bool pcie_wait_for_link(struct pci_dev *pdev, bool active); |
7d8e7d19 BH |
440 | #ifdef CONFIG_PCIEASPM |
441 | void pcie_aspm_init_link_state(struct pci_dev *pdev); | |
442 | void pcie_aspm_exit_link_state(struct pci_dev *pdev); | |
443 | void pcie_aspm_pm_state_change(struct pci_dev *pdev); | |
444 | void pcie_aspm_powersave_config_link(struct pci_dev *pdev); | |
445 | #else | |
446 | static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { } | |
447 | static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { } | |
448 | static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { } | |
449 | static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { } | |
450 | #endif | |
451 | ||
452 | #ifdef CONFIG_PCIEASPM_DEBUG | |
453 | void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev); | |
454 | void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev); | |
455 | #else | |
456 | static inline void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev) { } | |
457 | static inline void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev) { } | |
458 | #endif | |
459 | ||
9bb04a0c JY |
460 | #ifdef CONFIG_PCIE_PTM |
461 | void pci_ptm_init(struct pci_dev *dev); | |
462 | #else | |
463 | static inline void pci_ptm_init(struct pci_dev *dev) { } | |
464 | #endif | |
465 | ||
b9c3b266 DC |
466 | struct pci_dev_reset_methods { |
467 | u16 vendor; | |
468 | u16 device; | |
469 | int (*reset)(struct pci_dev *dev, int probe); | |
470 | }; | |
471 | ||
93177a74 | 472 | #ifdef CONFIG_PCI_QUIRKS |
f39d5b72 | 473 | int pci_dev_specific_reset(struct pci_dev *dev, int probe); |
93177a74 RW |
474 | #else |
475 | static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe) | |
476 | { | |
477 | return -ENOTTY; | |
478 | } | |
479 | #endif | |
b9c3b266 | 480 | |
169de969 DL |
481 | #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64) |
482 | int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment, | |
483 | struct resource *res); | |
484 | #endif | |
485 | ||
276b738d CK |
486 | u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar); |
487 | int pci_rebar_get_current_size(struct pci_dev *pdev, int bar); | |
488 | int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size); | |
489 | static inline u64 pci_rebar_size_to_bytes(int size) | |
490 | { | |
491 | return 1ULL << (size + 20); | |
492 | } | |
493 | ||
9e2aee80 RH |
494 | struct device_node; |
495 | ||
496 | #ifdef CONFIG_OF | |
497 | int of_pci_parse_bus_range(struct device_node *node, struct resource *res); | |
498 | int of_get_pci_domain_nr(struct device_node *node); | |
499 | int of_pci_get_max_link_speed(struct device_node *node); | |
500 | ||
501 | #else | |
502 | static inline int | |
503 | of_pci_parse_bus_range(struct device_node *node, struct resource *res) | |
504 | { | |
505 | return -EINVAL; | |
506 | } | |
507 | ||
508 | static inline int | |
509 | of_get_pci_domain_nr(struct device_node *node) | |
510 | { | |
511 | return -1; | |
512 | } | |
513 | ||
514 | static inline int | |
515 | of_pci_get_max_link_speed(struct device_node *node) | |
516 | { | |
517 | return -EINVAL; | |
518 | } | |
519 | #endif /* CONFIG_OF */ | |
520 | ||
521 | #if defined(CONFIG_OF_ADDRESS) | |
f03c7aa4 | 522 | int devm_of_pci_get_host_bridge_resources(struct device *dev, |
9e2aee80 RH |
523 | unsigned char busno, unsigned char bus_max, |
524 | struct list_head *resources, resource_size_t *io_base); | |
525 | #else | |
f03c7aa4 | 526 | static inline int devm_of_pci_get_host_bridge_resources(struct device *dev, |
9e2aee80 RH |
527 | unsigned char busno, unsigned char bus_max, |
528 | struct list_head *resources, resource_size_t *io_base) | |
529 | { | |
530 | return -EINVAL; | |
531 | } | |
532 | #endif | |
533 | ||
60ed982a RJ |
534 | #ifdef CONFIG_PCIEAER |
535 | void pci_no_aer(void); | |
536 | void pci_aer_init(struct pci_dev *dev); | |
db89ccbe | 537 | void pci_aer_exit(struct pci_dev *dev); |
81aa5206 | 538 | extern const struct attribute_group aer_stats_attr_group; |
7ab92e89 | 539 | void pci_aer_clear_fatal_status(struct pci_dev *dev); |
ec752f5d | 540 | void pci_aer_clear_device_status(struct pci_dev *dev); |
60ed982a RJ |
541 | #else |
542 | static inline void pci_no_aer(void) { } | |
543 | static inline int pci_aer_init(struct pci_dev *d) { return -ENODEV; } | |
db89ccbe | 544 | static inline void pci_aer_exit(struct pci_dev *d) { } |
7ab92e89 | 545 | static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } |
ec752f5d | 546 | static inline void pci_aer_clear_device_status(struct pci_dev *dev) { } |
60ed982a RJ |
547 | #endif |
548 | ||
557848c3 | 549 | #endif /* DRIVERS_PCI_H */ |