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Commit | Line | Data |
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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
557848c3 ZY |
2 | #ifndef DRIVERS_PCI_H |
3 | #define DRIVERS_PCI_H | |
4 | ||
2209e06f AG |
5 | #include <linux/pci.h> |
6 | ||
f8bf2aeb JS |
7 | /* Number of possible devfns: 0.0 to 1f.7 inclusive */ |
8 | #define MAX_NR_DEVFNS 256 | |
9 | ||
fff905f3 WY |
10 | #define PCI_FIND_CAP_TTL 48 |
11 | ||
8531e283 LW |
12 | #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */ |
13 | ||
343e51ae | 14 | extern const unsigned char pcie_link_speed[]; |
11eb0e0e | 15 | extern bool pci_early_dump; |
343e51ae | 16 | |
7a1562d4 | 17 | bool pcie_cap_has_lnkctl(const struct pci_dev *dev); |
af65d1ad | 18 | bool pcie_cap_has_rtctl(const struct pci_dev *dev); |
7a1562d4 | 19 | |
1da177e4 LT |
20 | /* Functions internal to the PCI core code */ |
21 | ||
f39d5b72 BH |
22 | int pci_create_sysfs_dev_files(struct pci_dev *pdev); |
23 | void pci_remove_sysfs_dev_files(struct pci_dev *pdev); | |
f39d5b72 | 24 | void pci_cleanup_rom(struct pci_dev *dev); |
506140f9 KW |
25 | #ifdef CONFIG_DMI |
26 | extern const struct attribute_group pci_dev_smbios_attr_group; | |
27 | #endif | |
f7195824 | 28 | |
3b519e4e MW |
29 | enum pci_mmap_api { |
30 | PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */ | |
31 | PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */ | |
32 | }; | |
f39d5b72 BH |
33 | int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai, |
34 | enum pci_mmap_api mmap_api); | |
f7195824 | 35 | |
711d5779 | 36 | int pci_probe_reset_function(struct pci_dev *dev); |
381634ca | 37 | int pci_bridge_secondary_bus_reset(struct pci_dev *dev); |
c4eed62a | 38 | int pci_bus_error_reset(struct pci_dev *dev); |
ce5ccdef | 39 | |
638c133e BH |
40 | #define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */ |
41 | #define PCI_PM_D3HOT_WAIT 10 /* msec */ | |
42 | #define PCI_PM_D3COLD_WAIT 100 /* msec */ | |
c776dd50 | 43 | |
961d9120 | 44 | /** |
b33bfdef | 45 | * struct pci_platform_pm_ops - Firmware PM callbacks |
961d9120 | 46 | * |
26ad34d5 MW |
47 | * @bridge_d3: Does the bridge allow entering into D3 |
48 | * | |
b33bfdef | 49 | * @is_manageable: returns 'true' if given device is power manageable by the |
0aa0f5d1 | 50 | * platform firmware |
961d9120 | 51 | * |
b33bfdef | 52 | * @set_state: invokes the platform firmware to set the device's power state |
961d9120 | 53 | * |
cc7cc02b LW |
54 | * @get_state: queries the platform firmware for a device's current power state |
55 | * | |
b51033e0 RW |
56 | * @refresh_state: asks the platform to refresh the device's power state data |
57 | * | |
b33bfdef | 58 | * @choose_state: returns PCI power state of given device preferred by the |
0aa0f5d1 BH |
59 | * platform; to be used during system-wide transitions from a |
60 | * sleeping state to the working state and vice versa | |
961d9120 | 61 | * |
0847684c | 62 | * @set_wakeup: enables/disables wakeup capability for the device |
b67ea761 | 63 | * |
bac2a909 | 64 | * @need_resume: returns 'true' if the given device (which is currently |
0aa0f5d1 BH |
65 | * suspended) needs to be resumed to be configured for system |
66 | * wakeup. | |
bac2a909 | 67 | * |
961d9120 RW |
68 | * If given platform is generally capable of power managing PCI devices, all of |
69 | * these callbacks are mandatory. | |
70 | */ | |
71 | struct pci_platform_pm_ops { | |
26ad34d5 | 72 | bool (*bridge_d3)(struct pci_dev *dev); |
961d9120 RW |
73 | bool (*is_manageable)(struct pci_dev *dev); |
74 | int (*set_state)(struct pci_dev *dev, pci_power_t state); | |
cc7cc02b | 75 | pci_power_t (*get_state)(struct pci_dev *dev); |
b51033e0 | 76 | void (*refresh_state)(struct pci_dev *dev); |
961d9120 | 77 | pci_power_t (*choose_state)(struct pci_dev *dev); |
0847684c | 78 | int (*set_wakeup)(struct pci_dev *dev, bool enable); |
bac2a909 | 79 | bool (*need_resume)(struct pci_dev *dev); |
961d9120 RW |
80 | }; |
81 | ||
299f2ffe | 82 | int pci_set_platform_pm(const struct pci_platform_pm_ops *ops); |
f39d5b72 | 83 | void pci_update_current_state(struct pci_dev *dev, pci_power_t state); |
b51033e0 | 84 | void pci_refresh_power_state(struct pci_dev *dev); |
adfac8f6 | 85 | int pci_power_up(struct pci_dev *dev); |
f39d5b72 BH |
86 | void pci_disable_enabled_device(struct pci_dev *dev); |
87 | int pci_finish_runtime_suspend(struct pci_dev *dev); | |
600a5b4f | 88 | void pcie_clear_device_status(struct pci_dev *dev); |
dcb0453d | 89 | void pcie_clear_root_pme_status(struct pci_dev *dev); |
669696eb KS |
90 | bool pci_check_pme_status(struct pci_dev *dev); |
91 | void pci_pme_wakeup_bus(struct pci_bus *bus); | |
f39d5b72 | 92 | int __pci_pme_wakeup(struct pci_dev *dev, void *ign); |
0ce3fcaf | 93 | void pci_pme_restore(struct pci_dev *dev); |
0c7376ad RW |
94 | bool pci_dev_need_resume(struct pci_dev *dev); |
95 | void pci_dev_adjust_pme(struct pci_dev *dev); | |
2cef548a | 96 | void pci_dev_complete_resume(struct pci_dev *pci_dev); |
f39d5b72 BH |
97 | void pci_config_pm_runtime_get(struct pci_dev *dev); |
98 | void pci_config_pm_runtime_put(struct pci_dev *dev); | |
99 | void pci_pm_init(struct pci_dev *dev); | |
938174e5 | 100 | void pci_ea_init(struct pci_dev *dev); |
cbc40d5c BH |
101 | void pci_msi_init(struct pci_dev *dev); |
102 | void pci_msix_init(struct pci_dev *dev); | |
f39d5b72 | 103 | void pci_allocate_cap_save_buffers(struct pci_dev *dev); |
f796841e | 104 | void pci_free_cap_save_buffers(struct pci_dev *dev); |
c6a63307 | 105 | bool pci_bridge_d3_possible(struct pci_dev *dev); |
1ed276a7 | 106 | void pci_bridge_d3_update(struct pci_dev *dev); |
ad9001f2 | 107 | void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev); |
aa8c6c93 | 108 | |
b6e335ae RW |
109 | static inline void pci_wakeup_event(struct pci_dev *dev) |
110 | { | |
111 | /* Wait 100 ms before the system can be put into a sleep state. */ | |
112 | pm_wakeup_event(&dev->dev, 100); | |
113 | } | |
114 | ||
326c1cda | 115 | static inline bool pci_has_subordinate(struct pci_dev *pci_dev) |
aa8c6c93 RW |
116 | { |
117 | return !!(pci_dev->subordinate); | |
118 | } | |
0f64474b | 119 | |
9d26d3a8 MW |
120 | static inline bool pci_power_manageable(struct pci_dev *pci_dev) |
121 | { | |
122 | /* | |
123 | * Currently we allow normal PCI devices and PCI bridges transition | |
124 | * into D3 if their bridge_d3 is set. | |
125 | */ | |
126 | return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3; | |
127 | } | |
128 | ||
984998e3 MW |
129 | static inline bool pcie_downstream_port(const struct pci_dev *dev) |
130 | { | |
131 | int type = pci_pcie_type(dev); | |
132 | ||
133 | return type == PCI_EXP_TYPE_ROOT_PORT || | |
134 | type == PCI_EXP_TYPE_DOWNSTREAM || | |
135 | type == PCI_EXP_TYPE_PCIE_BRIDGE; | |
136 | } | |
137 | ||
e947e7b1 | 138 | void pci_vpd_init(struct pci_dev *dev); |
64379079 | 139 | void pci_vpd_release(struct pci_dev *dev); |
d93f8399 | 140 | extern const struct attribute_group pci_dev_vpd_attr_group; |
94e61088 | 141 | |
440589dd KS |
142 | /* PCI Virtual Channel */ |
143 | int pci_save_vc_state(struct pci_dev *dev); | |
144 | void pci_restore_vc_state(struct pci_dev *dev); | |
145 | void pci_allocate_vc_save_buffers(struct pci_dev *dev); | |
146 | ||
1da177e4 LT |
147 | /* PCI /proc functions */ |
148 | #ifdef CONFIG_PROC_FS | |
f39d5b72 BH |
149 | int pci_proc_attach_device(struct pci_dev *dev); |
150 | int pci_proc_detach_device(struct pci_dev *dev); | |
151 | int pci_proc_detach_bus(struct pci_bus *bus); | |
1da177e4 LT |
152 | #else |
153 | static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; } | |
154 | static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; } | |
1da177e4 LT |
155 | static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; } |
156 | #endif | |
157 | ||
158 | /* Functions for PCI Hotplug drivers to use */ | |
a8e4b9c1 | 159 | int pci_hp_add_bridge(struct pci_dev *dev); |
1da177e4 | 160 | |
f19aeb1f | 161 | #ifdef HAVE_PCI_LEGACY |
f39d5b72 BH |
162 | void pci_create_legacy_files(struct pci_bus *bus); |
163 | void pci_remove_legacy_files(struct pci_bus *bus); | |
f19aeb1f BH |
164 | #else |
165 | static inline void pci_create_legacy_files(struct pci_bus *bus) { return; } | |
166 | static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; } | |
167 | #endif | |
1da177e4 LT |
168 | |
169 | /* Lock for read/write access to pci device and bus lists */ | |
d71374da | 170 | extern struct rw_semaphore pci_bus_sem; |
c4eed62a | 171 | extern struct mutex pci_slot_mutex; |
1da177e4 | 172 | |
a2e27787 JK |
173 | extern raw_spinlock_t pci_lock; |
174 | ||
3789af9a | 175 | extern unsigned int pci_pm_d3hot_delay; |
88187dfa | 176 | |
4b47b0ee | 177 | #ifdef CONFIG_PCI_MSI |
309e57df | 178 | void pci_no_msi(void); |
4b47b0ee | 179 | #else |
309e57df | 180 | static inline void pci_no_msi(void) { } |
4b47b0ee | 181 | #endif |
8fed4b65 | 182 | |
b55438fd | 183 | void pci_realloc_get_opt(char *); |
f483d392 | 184 | |
ffadcc2f KCA |
185 | static inline int pci_no_d1d2(struct pci_dev *dev) |
186 | { | |
187 | unsigned int parent_dstates = 0; | |
4b47b0ee | 188 | |
ffadcc2f KCA |
189 | if (dev->bus->self) |
190 | parent_dstates = dev->bus->self->no_d1d2; | |
191 | return (dev->no_d1d2 || parent_dstates); | |
192 | ||
193 | } | |
5136b2da | 194 | extern const struct attribute_group *pci_dev_groups[]; |
56039e65 | 195 | extern const struct attribute_group *pcibus_groups[]; |
69f2dc24 | 196 | extern const struct device_type pci_dev_type; |
0f49ba55 | 197 | extern const struct attribute_group *pci_bus_groups[]; |
705b1aaa | 198 | |
003d3b2c | 199 | extern unsigned long pci_hotplug_io_size; |
d7b8a217 NJ |
200 | extern unsigned long pci_hotplug_mmio_size; |
201 | extern unsigned long pci_hotplug_mmio_pref_size; | |
003d3b2c | 202 | extern unsigned long pci_hotplug_bus_size; |
1da177e4 LT |
203 | |
204 | /** | |
205 | * pci_match_one_device - Tell if a PCI device structure has a matching | |
0aa0f5d1 | 206 | * PCI device id structure |
1da177e4 LT |
207 | * @id: single PCI device id structure to match |
208 | * @dev: the PCI device structure to match against | |
367b09fe | 209 | * |
1da177e4 LT |
210 | * Returns the matching pci_device_id structure or %NULL if there is no match. |
211 | */ | |
212 | static inline const struct pci_device_id * | |
213 | pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev) | |
214 | { | |
215 | if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) && | |
216 | (id->device == PCI_ANY_ID || id->device == dev->device) && | |
217 | (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) && | |
218 | (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) && | |
219 | !((id->class ^ dev->class) & id->class_mask)) | |
220 | return id; | |
221 | return NULL; | |
222 | } | |
223 | ||
f46753c5 AC |
224 | /* PCI slot sysfs helper code */ |
225 | #define to_pci_slot(s) container_of(s, struct pci_slot, kobj) | |
226 | ||
227 | extern struct kset *pci_slots_kset; | |
228 | ||
229 | struct pci_slot_attribute { | |
230 | struct attribute attr; | |
231 | ssize_t (*show)(struct pci_slot *, char *); | |
232 | ssize_t (*store)(struct pci_slot *, const char *, size_t); | |
233 | }; | |
234 | #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr) | |
235 | ||
0b400c7e YZ |
236 | enum pci_bar_type { |
237 | pci_bar_unknown, /* Standard PCI BAR probe */ | |
0aa0f5d1 | 238 | pci_bar_io, /* An I/O port BAR */ |
0b400c7e YZ |
239 | pci_bar_mem32, /* A 32-bit memory BAR */ |
240 | pci_bar_mem64, /* A 64-bit memory BAR */ | |
241 | }; | |
242 | ||
975e1ac1 KS |
243 | struct device *pci_get_host_bridge_device(struct pci_dev *dev); |
244 | void pci_put_host_bridge_device(struct device *dev); | |
245 | ||
62ce94a7 | 246 | int pci_configure_extended_tags(struct pci_dev *dev, void *ign); |
efdc87da YL |
247 | bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, |
248 | int crs_timeout); | |
aa667c64 JP |
249 | bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, |
250 | int crs_timeout); | |
251 | int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout); | |
252 | ||
f39d5b72 BH |
253 | int pci_setup_device(struct pci_dev *dev); |
254 | int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, | |
255 | struct resource *res, unsigned int reg); | |
f39d5b72 | 256 | void pci_configure_ari(struct pci_dev *dev); |
10874f5a | 257 | void __pci_bus_size_bridges(struct pci_bus *bus, |
d66ecb72 | 258 | struct list_head *realloc_head); |
10874f5a BH |
259 | void __pci_bus_assign_resources(const struct pci_bus *bus, |
260 | struct list_head *realloc_head, | |
261 | struct list_head *fail_head); | |
0f7e7aee | 262 | bool pci_bus_clip_resource(struct pci_dev *dev, int idx); |
939de1d6 | 263 | |
2069ecfb | 264 | void pci_reassigndev_resource_alignment(struct pci_dev *dev); |
f39d5b72 | 265 | void pci_disable_bridge_window(struct pci_dev *dev); |
ecd29c1a KS |
266 | struct pci_bus *pci_bus_get(struct pci_bus *bus); |
267 | void pci_bus_put(struct pci_bus *bus); | |
32a9a682 | 268 | |
757bfaa2 YY |
269 | /* PCIe link information from Link Capabilities 2 */ |
270 | #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \ | |
34191749 GP |
271 | ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \ |
272 | (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \ | |
757bfaa2 YY |
273 | (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \ |
274 | (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \ | |
275 | (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \ | |
276 | (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \ | |
277 | PCI_SPEED_UNKNOWN) | |
6cf57be0 | 278 | |
b852f63a TG |
279 | /* PCIe speed to Mb/s reduced by encoding overhead */ |
280 | #define PCIE_SPEED2MBS_ENC(speed) \ | |
34191749 GP |
281 | ((speed) == PCIE_SPEED_64_0GT ? 64000*128/130 : \ |
282 | (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \ | |
9cb3985a | 283 | (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \ |
b852f63a TG |
284 | (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \ |
285 | (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \ | |
286 | (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \ | |
287 | 0) | |
288 | ||
e56faff5 | 289 | const char *pci_speed_string(enum pci_bus_speed speed); |
6cf57be0 | 290 | enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); |
c70b65fb | 291 | enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); |
b852f63a TG |
292 | u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed, |
293 | enum pcie_link_width *width); | |
2d1ce5ec | 294 | void __pcie_print_link_status(struct pci_dev *dev, bool verbose); |
0fa635ae | 295 | void pcie_report_downtraining(struct pci_dev *dev); |
5da78d95 | 296 | void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); |
6cf57be0 | 297 | |
d1b054da YZ |
298 | /* Single Root I/O Virtualization */ |
299 | struct pci_sriov { | |
0aa0f5d1 BH |
300 | int pos; /* Capability position */ |
301 | int nres; /* Number of resources */ | |
302 | u32 cap; /* SR-IOV Capabilities */ | |
303 | u16 ctrl; /* SR-IOV Control */ | |
304 | u16 total_VFs; /* Total VFs associated with the PF */ | |
305 | u16 initial_VFs; /* Initial VFs associated with the PF */ | |
306 | u16 num_VFs; /* Number of VFs available */ | |
307 | u16 offset; /* First VF Routing ID offset */ | |
308 | u16 stride; /* Following VF stride */ | |
309 | u16 vf_device; /* VF device ID */ | |
310 | u32 pgsz; /* Page size for BAR alignment */ | |
311 | u8 link; /* Function Dependency Link */ | |
312 | u8 max_VF_buses; /* Max buses consumed by VFs */ | |
313 | u16 driver_max_VFs; /* Max num VFs driver supports */ | |
314 | struct pci_dev *dev; /* Lowest numbered PF */ | |
315 | struct pci_dev *self; /* This PF */ | |
cf0921be KA |
316 | u32 class; /* VF device */ |
317 | u8 hdr_type; /* VF header type */ | |
318 | u16 subsystem_vendor; /* VF subsystem vendor */ | |
319 | u16 subsystem_device; /* VF subsystem device */ | |
0aa0f5d1 BH |
320 | resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */ |
321 | bool drivers_autoprobe; /* Auto probing of VFs by driver */ | |
d1b054da YZ |
322 | }; |
323 | ||
a6bd101b KB |
324 | /** |
325 | * pci_dev_set_io_state - Set the new error state if possible. | |
326 | * | |
327 | * @dev - pci device to set new error_state | |
328 | * @new - the state we want dev to be in | |
329 | * | |
330 | * Must be called with device_lock held. | |
331 | * | |
332 | * Returns true if state has been changed to the requested state. | |
333 | */ | |
334 | static inline bool pci_dev_set_io_state(struct pci_dev *dev, | |
335 | pci_channel_state_t new) | |
336 | { | |
337 | bool changed = false; | |
338 | ||
339 | device_lock_assert(&dev->dev); | |
340 | switch (new) { | |
341 | case pci_channel_io_perm_failure: | |
342 | switch (dev->error_state) { | |
343 | case pci_channel_io_frozen: | |
344 | case pci_channel_io_normal: | |
345 | case pci_channel_io_perm_failure: | |
346 | changed = true; | |
347 | break; | |
348 | } | |
349 | break; | |
350 | case pci_channel_io_frozen: | |
351 | switch (dev->error_state) { | |
352 | case pci_channel_io_frozen: | |
353 | case pci_channel_io_normal: | |
354 | changed = true; | |
355 | break; | |
356 | } | |
357 | break; | |
358 | case pci_channel_io_normal: | |
359 | switch (dev->error_state) { | |
360 | case pci_channel_io_frozen: | |
361 | case pci_channel_io_normal: | |
362 | changed = true; | |
363 | break; | |
364 | } | |
365 | break; | |
366 | } | |
367 | if (changed) | |
368 | dev->error_state = new; | |
369 | return changed; | |
370 | } | |
89ee9f76 KB |
371 | |
372 | static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused) | |
373 | { | |
a6bd101b KB |
374 | device_lock(&dev->dev); |
375 | pci_dev_set_io_state(dev, pci_channel_io_perm_failure); | |
376 | device_unlock(&dev->dev); | |
377 | ||
89ee9f76 KB |
378 | return 0; |
379 | } | |
380 | ||
381 | static inline bool pci_dev_is_disconnected(const struct pci_dev *dev) | |
382 | { | |
a6bd101b | 383 | return dev->error_state == pci_channel_io_perm_failure; |
89ee9f76 KB |
384 | } |
385 | ||
a6bd101b KB |
386 | /* pci_dev priv_flags */ |
387 | #define PCI_DEV_ADDED 0 | |
a97396c6 LW |
388 | #define PCI_DPC_RECOVERED 1 |
389 | #define PCI_DPC_RECOVERING 2 | |
a6bd101b | 390 | |
44bda4b7 HV |
391 | static inline void pci_dev_assign_added(struct pci_dev *dev, bool added) |
392 | { | |
393 | assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added); | |
394 | } | |
395 | ||
396 | static inline bool pci_dev_is_added(const struct pci_dev *dev) | |
397 | { | |
398 | return test_bit(PCI_DEV_ADDED, &dev->priv_flags); | |
399 | } | |
400 | ||
1e451160 KB |
401 | #ifdef CONFIG_PCIEAER |
402 | #include <linux/aer.h> | |
403 | ||
404 | #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */ | |
405 | ||
406 | struct aer_err_info { | |
407 | struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES]; | |
408 | int error_dev_num; | |
409 | ||
410 | unsigned int id:16; | |
411 | ||
412 | unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */ | |
413 | unsigned int __pad1:5; | |
414 | unsigned int multi_error_valid:1; | |
415 | ||
416 | unsigned int first_error:5; | |
417 | unsigned int __pad2:2; | |
418 | unsigned int tlp_header_valid:1; | |
419 | ||
420 | unsigned int status; /* COR/UNCOR Error Status */ | |
421 | unsigned int mask; /* COR/UNCOR Error Mask */ | |
422 | struct aer_header_log_regs tlp; /* TLP Header */ | |
423 | }; | |
424 | ||
425 | int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info); | |
426 | void aer_print_error(struct pci_dev *dev, struct aer_err_info *info); | |
427 | #endif /* CONFIG_PCIEAER */ | |
428 | ||
90655631 SK |
429 | #ifdef CONFIG_PCIEPORTBUS |
430 | /* Cached RCEC Endpoint Association */ | |
431 | struct rcec_ea { | |
432 | u8 nextbusn; | |
433 | u8 lastbusn; | |
434 | u32 bitmap; | |
435 | }; | |
436 | #endif | |
437 | ||
4f802170 KB |
438 | #ifdef CONFIG_PCIE_DPC |
439 | void pci_save_dpc_state(struct pci_dev *dev); | |
440 | void pci_restore_dpc_state(struct pci_dev *dev); | |
27005618 | 441 | void pci_dpc_init(struct pci_dev *pdev); |
aea47413 KS |
442 | void dpc_process_error(struct pci_dev *pdev); |
443 | pci_ers_result_t dpc_reset_link(struct pci_dev *pdev); | |
a97396c6 | 444 | bool pci_dpc_recovered(struct pci_dev *pdev); |
4f802170 KB |
445 | #else |
446 | static inline void pci_save_dpc_state(struct pci_dev *dev) {} | |
447 | static inline void pci_restore_dpc_state(struct pci_dev *dev) {} | |
27005618 | 448 | static inline void pci_dpc_init(struct pci_dev *pdev) {} |
a97396c6 | 449 | static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; } |
4f802170 KB |
450 | #endif |
451 | ||
90655631 SK |
452 | #ifdef CONFIG_PCIEPORTBUS |
453 | void pci_rcec_init(struct pci_dev *dev); | |
454 | void pci_rcec_exit(struct pci_dev *dev); | |
507b460f | 455 | void pcie_link_rcec(struct pci_dev *rcec); |
af113553 SK |
456 | void pcie_walk_rcec(struct pci_dev *rcec, |
457 | int (*cb)(struct pci_dev *, void *), | |
458 | void *userdata); | |
90655631 SK |
459 | #else |
460 | static inline void pci_rcec_init(struct pci_dev *dev) {} | |
461 | static inline void pci_rcec_exit(struct pci_dev *dev) {} | |
507b460f | 462 | static inline void pcie_link_rcec(struct pci_dev *rcec) {} |
af113553 SK |
463 | static inline void pcie_walk_rcec(struct pci_dev *rcec, |
464 | int (*cb)(struct pci_dev *, void *), | |
465 | void *userdata) {} | |
90655631 SK |
466 | #endif |
467 | ||
1900ca13 | 468 | #ifdef CONFIG_PCI_ATS |
b92b512a KS |
469 | /* Address Translation Service */ |
470 | void pci_ats_init(struct pci_dev *dev); | |
f39d5b72 | 471 | void pci_restore_ats_state(struct pci_dev *dev); |
1900ca13 | 472 | #else |
b92b512a KS |
473 | static inline void pci_ats_init(struct pci_dev *d) { } |
474 | static inline void pci_restore_ats_state(struct pci_dev *dev) { } | |
1900ca13 HX |
475 | #endif /* CONFIG_PCI_ATS */ |
476 | ||
c065190b KS |
477 | #ifdef CONFIG_PCI_PRI |
478 | void pci_pri_init(struct pci_dev *dev); | |
fef2dd8b | 479 | void pci_restore_pri_state(struct pci_dev *pdev); |
c065190b KS |
480 | #else |
481 | static inline void pci_pri_init(struct pci_dev *dev) { } | |
fef2dd8b | 482 | static inline void pci_restore_pri_state(struct pci_dev *pdev) { } |
c065190b KS |
483 | #endif |
484 | ||
751035b8 KS |
485 | #ifdef CONFIG_PCI_PASID |
486 | void pci_pasid_init(struct pci_dev *dev); | |
fef2dd8b | 487 | void pci_restore_pasid_state(struct pci_dev *pdev); |
751035b8 KS |
488 | #else |
489 | static inline void pci_pasid_init(struct pci_dev *dev) { } | |
fef2dd8b | 490 | static inline void pci_restore_pasid_state(struct pci_dev *pdev) { } |
751035b8 KS |
491 | #endif |
492 | ||
d1b054da | 493 | #ifdef CONFIG_PCI_IOV |
f39d5b72 BH |
494 | int pci_iov_init(struct pci_dev *dev); |
495 | void pci_iov_release(struct pci_dev *dev); | |
38972375 | 496 | void pci_iov_remove(struct pci_dev *dev); |
6ffa2489 | 497 | void pci_iov_update_resource(struct pci_dev *dev, int resno); |
f39d5b72 BH |
498 | resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno); |
499 | void pci_restore_iov_state(struct pci_dev *dev); | |
500 | int pci_iov_bus_range(struct pci_bus *bus); | |
c3d5c2d9 LR |
501 | extern const struct attribute_group sriov_pf_dev_attr_group; |
502 | extern const struct attribute_group sriov_vf_dev_attr_group; | |
d1b054da YZ |
503 | #else |
504 | static inline int pci_iov_init(struct pci_dev *dev) | |
505 | { | |
506 | return -ENODEV; | |
507 | } | |
508 | static inline void pci_iov_release(struct pci_dev *dev) | |
509 | ||
38972375 JK |
510 | { |
511 | } | |
512 | static inline void pci_iov_remove(struct pci_dev *dev) | |
d1b054da YZ |
513 | { |
514 | } | |
8c5cdb6a YZ |
515 | static inline void pci_restore_iov_state(struct pci_dev *dev) |
516 | { | |
517 | } | |
a28724b0 YZ |
518 | static inline int pci_iov_bus_range(struct pci_bus *bus) |
519 | { | |
520 | return 0; | |
521 | } | |
302b4215 | 522 | |
d1b054da YZ |
523 | #endif /* CONFIG_PCI_IOV */ |
524 | ||
39850ed5 DB |
525 | #ifdef CONFIG_PCIE_PTM |
526 | void pci_save_ptm_state(struct pci_dev *dev); | |
527 | void pci_restore_ptm_state(struct pci_dev *dev); | |
a697f072 | 528 | void pci_disable_ptm(struct pci_dev *dev); |
39850ed5 DB |
529 | #else |
530 | static inline void pci_save_ptm_state(struct pci_dev *dev) { } | |
531 | static inline void pci_restore_ptm_state(struct pci_dev *dev) { } | |
a697f072 | 532 | static inline void pci_disable_ptm(struct pci_dev *dev) { } |
39850ed5 DB |
533 | #endif |
534 | ||
f39d5b72 | 535 | unsigned long pci_cardbus_resource_alignment(struct resource *); |
0a2daa1c | 536 | |
0e52247a | 537 | static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, |
f39d5b72 | 538 | struct resource *res) |
6faf17f6 CW |
539 | { |
540 | #ifdef CONFIG_PCI_IOV | |
541 | int resno = res - dev->resource; | |
542 | ||
543 | if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END) | |
544 | return pci_sriov_resource_alignment(dev, resno); | |
545 | #endif | |
0aa0f5d1 | 546 | if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS) |
0a2daa1c | 547 | return pci_cardbus_resource_alignment(res); |
6faf17f6 CW |
548 | return resource_alignment(res); |
549 | } | |
550 | ||
52fbf5bd | 551 | void pci_acs_init(struct pci_dev *dev); |
bd2e9567 BH |
552 | #ifdef CONFIG_PCI_QUIRKS |
553 | int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); | |
554 | int pci_dev_specific_enable_acs(struct pci_dev *dev); | |
73c47dde | 555 | int pci_dev_specific_disable_acs_redir(struct pci_dev *dev); |
bd2e9567 BH |
556 | #else |
557 | static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, | |
558 | u16 acs_flags) | |
559 | { | |
560 | return -ENOTTY; | |
561 | } | |
562 | static inline int pci_dev_specific_enable_acs(struct pci_dev *dev) | |
563 | { | |
564 | return -ENOTTY; | |
565 | } | |
73c47dde LG |
566 | static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) |
567 | { | |
568 | return -ENOTTY; | |
569 | } | |
bd2e9567 | 570 | #endif |
ae21ee65 | 571 | |
2e28bc84 | 572 | /* PCI error reporting and recovery */ |
e8e5ff2a | 573 | pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, |
8f1bbfbc SK |
574 | pci_channel_state_t state, |
575 | pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev)); | |
2e28bc84 | 576 | |
9f5a70f1 | 577 | bool pcie_wait_for_link(struct pci_dev *pdev, bool active); |
7d8e7d19 BH |
578 | #ifdef CONFIG_PCIEASPM |
579 | void pcie_aspm_init_link_state(struct pci_dev *pdev); | |
580 | void pcie_aspm_exit_link_state(struct pci_dev *pdev); | |
581 | void pcie_aspm_pm_state_change(struct pci_dev *pdev); | |
582 | void pcie_aspm_powersave_config_link(struct pci_dev *pdev); | |
583 | #else | |
584 | static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { } | |
585 | static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { } | |
586 | static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { } | |
587 | static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { } | |
588 | #endif | |
589 | ||
72bde9ce KS |
590 | #ifdef CONFIG_PCIE_ECRC |
591 | void pcie_set_ecrc_checking(struct pci_dev *dev); | |
592 | void pcie_ecrc_get_policy(char *str); | |
593 | #else | |
594 | static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } | |
595 | static inline void pcie_ecrc_get_policy(char *str) { } | |
596 | #endif | |
597 | ||
9bb04a0c JY |
598 | #ifdef CONFIG_PCIE_PTM |
599 | void pci_ptm_init(struct pci_dev *dev); | |
ac6c26da | 600 | int pci_enable_ptm(struct pci_dev *dev, u8 *granularity); |
9bb04a0c JY |
601 | #else |
602 | static inline void pci_ptm_init(struct pci_dev *dev) { } | |
ac6c26da KS |
603 | static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) |
604 | { return -EINVAL; } | |
9bb04a0c JY |
605 | #endif |
606 | ||
b9c3b266 DC |
607 | struct pci_dev_reset_methods { |
608 | u16 vendor; | |
609 | u16 device; | |
610 | int (*reset)(struct pci_dev *dev, int probe); | |
611 | }; | |
612 | ||
93177a74 | 613 | #ifdef CONFIG_PCI_QUIRKS |
f39d5b72 | 614 | int pci_dev_specific_reset(struct pci_dev *dev, int probe); |
93177a74 RW |
615 | #else |
616 | static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe) | |
617 | { | |
618 | return -ENOTTY; | |
619 | } | |
620 | #endif | |
b9c3b266 | 621 | |
169de969 DL |
622 | #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64) |
623 | int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment, | |
624 | struct resource *res); | |
16f7ae59 AB |
625 | #else |
626 | static inline int acpi_get_rc_resources(struct device *dev, const char *hid, | |
627 | u16 segment, struct resource *res) | |
628 | { | |
629 | return -ENODEV; | |
630 | } | |
169de969 DL |
631 | #endif |
632 | ||
276b738d CK |
633 | int pci_rebar_get_current_size(struct pci_dev *pdev, int bar); |
634 | int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size); | |
635 | static inline u64 pci_rebar_size_to_bytes(int size) | |
636 | { | |
637 | return 1ULL << (size + 20); | |
638 | } | |
639 | ||
9e2aee80 RH |
640 | struct device_node; |
641 | ||
642 | #ifdef CONFIG_OF | |
643 | int of_pci_parse_bus_range(struct device_node *node, struct resource *res); | |
644 | int of_get_pci_domain_nr(struct device_node *node); | |
645 | int of_pci_get_max_link_speed(struct device_node *node); | |
621f7e35 KS |
646 | void pci_set_of_node(struct pci_dev *dev); |
647 | void pci_release_of_node(struct pci_dev *dev); | |
648 | void pci_set_bus_of_node(struct pci_bus *bus); | |
649 | void pci_release_bus_of_node(struct pci_bus *bus); | |
9e2aee80 | 650 | |
669cbc70 RH |
651 | int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge); |
652 | ||
9e2aee80 RH |
653 | #else |
654 | static inline int | |
655 | of_pci_parse_bus_range(struct device_node *node, struct resource *res) | |
656 | { | |
657 | return -EINVAL; | |
658 | } | |
659 | ||
660 | static inline int | |
661 | of_get_pci_domain_nr(struct device_node *node) | |
662 | { | |
663 | return -1; | |
664 | } | |
665 | ||
666 | static inline int | |
667 | of_pci_get_max_link_speed(struct device_node *node) | |
668 | { | |
669 | return -EINVAL; | |
670 | } | |
621f7e35 KS |
671 | |
672 | static inline void pci_set_of_node(struct pci_dev *dev) { } | |
673 | static inline void pci_release_of_node(struct pci_dev *dev) { } | |
674 | static inline void pci_set_bus_of_node(struct pci_bus *bus) { } | |
675 | static inline void pci_release_bus_of_node(struct pci_bus *bus) { } | |
669cbc70 RH |
676 | |
677 | static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge) | |
678 | { | |
679 | return 0; | |
680 | } | |
681 | ||
9e2aee80 RH |
682 | #endif /* CONFIG_OF */ |
683 | ||
60ed982a RJ |
684 | #ifdef CONFIG_PCIEAER |
685 | void pci_no_aer(void); | |
686 | void pci_aer_init(struct pci_dev *dev); | |
db89ccbe | 687 | void pci_aer_exit(struct pci_dev *dev); |
81aa5206 | 688 | extern const struct attribute_group aer_stats_attr_group; |
7ab92e89 | 689 | void pci_aer_clear_fatal_status(struct pci_dev *dev); |
894020fd | 690 | int pci_aer_clear_status(struct pci_dev *dev); |
20e15e67 | 691 | int pci_aer_raw_clear_status(struct pci_dev *dev); |
60ed982a RJ |
692 | #else |
693 | static inline void pci_no_aer(void) { } | |
31f996ef | 694 | static inline void pci_aer_init(struct pci_dev *d) { } |
db89ccbe | 695 | static inline void pci_aer_exit(struct pci_dev *d) { } |
7ab92e89 | 696 | static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } |
894020fd | 697 | static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; } |
20e15e67 | 698 | static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; } |
60ed982a RJ |
699 | #endif |
700 | ||
8c3aac6e | 701 | #ifdef CONFIG_ACPI |
4a2dbedd | 702 | int pci_acpi_program_hp_params(struct pci_dev *dev); |
506140f9 | 703 | extern const struct attribute_group pci_dev_acpi_attr_group; |
8c3aac6e | 704 | #else |
4a2dbedd | 705 | static inline int pci_acpi_program_hp_params(struct pci_dev *dev) |
8c3aac6e KW |
706 | { |
707 | return -ENODEV; | |
708 | } | |
709 | #endif | |
710 | ||
72ea91af HK |
711 | #ifdef CONFIG_PCIEASPM |
712 | extern const struct attribute_group aspm_ctrl_attr_group; | |
713 | #endif | |
714 | ||
557848c3 | 715 | #endif /* DRIVERS_PCI_H */ |