[mirror_ubuntu-artful-kernel.git] / drivers / pci / pci.h

#ifndef DRIVERS_PCI_H
#define DRIVERS_PCI_H

#define PCI_FIND_CAP_TTL	48

#define PCI_VSEC_ID_INTEL_TBT	0x1234	/* Thunderbolt */

extern const unsigned char pcie_link_speed[];

bool pcie_cap_has_lnkctl(const struct pci_dev *dev);

/* Functions internal to the PCI core code */

int pci_create_sysfs_dev_files(struct pci_dev *pdev);
void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
#if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI)
static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
{ return; }
static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
{ return; }
#else
void pci_create_firmware_label_files(struct pci_dev *pdev);
void pci_remove_firmware_label_files(struct pci_dev *pdev);
#endif
void pci_cleanup_rom(struct pci_dev *dev);

enum pci_mmap_api {
	PCI_MMAP_SYSFS,	/* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
	PCI_MMAP_PROCFS	/* mmap on /proc/bus/pci/<BDF> */
};
int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
		  enum pci_mmap_api mmap_api);

int pci_probe_reset_function(struct pci_dev *dev);

/**
 * struct pci_platform_pm_ops - Firmware PM callbacks
 *
 * @is_manageable: returns 'true' if given device is power manageable by the
 *                 platform firmware
 *
 * @set_state: invokes the platform firmware to set the device's power state
 *
 * @get_state: queries the platform firmware for a device's current power state
 *
 * @choose_state: returns PCI power state of given device preferred by the
 *                platform; to be used during system-wide transitions from a
 *                sleeping state to the working state and vice versa
 *
 * @set_wakeup: enables/disables wakeup capability for the device
 *
 * @need_resume: returns 'true' if the given device (which is currently
 *		suspended) needs to be resumed to be configured for system
 *		wakeup.
 *
 * If given platform is generally capable of power managing PCI devices, all of
 * these callbacks are mandatory.
 */
struct pci_platform_pm_ops {
	bool (*is_manageable)(struct pci_dev *dev);
	int (*set_state)(struct pci_dev *dev, pci_power_t state);
	pci_power_t (*get_state)(struct pci_dev *dev);
	pci_power_t (*choose_state)(struct pci_dev *dev);
	int (*set_wakeup)(struct pci_dev *dev, bool enable);
	bool (*need_resume)(struct pci_dev *dev);
};

int pci_set_platform_pm(const struct pci_platform_pm_ops *ops);
void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
void pci_power_up(struct pci_dev *dev);
void pci_disable_enabled_device(struct pci_dev *dev);
int pci_finish_runtime_suspend(struct pci_dev *dev);
int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
void pci_pme_restore(struct pci_dev *dev);
bool pci_dev_keep_suspended(struct pci_dev *dev);
void pci_dev_complete_resume(struct pci_dev *pci_dev);
void pci_config_pm_runtime_get(struct pci_dev *dev);
void pci_config_pm_runtime_put(struct pci_dev *dev);
void pci_pm_init(struct pci_dev *dev);
void pci_ea_init(struct pci_dev *dev);
void pci_allocate_cap_save_buffers(struct pci_dev *dev);
void pci_free_cap_save_buffers(struct pci_dev *dev);
bool pci_bridge_d3_possible(struct pci_dev *dev);
void pci_bridge_d3_update(struct pci_dev *dev);

static inline void pci_wakeup_event(struct pci_dev *dev)
{
	/* Wait 100 ms before the system can be put into a sleep state. */
	pm_wakeup_event(&dev->dev, 100);
}

static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
{
	return !!(pci_dev->subordinate);
}

static inline bool pci_power_manageable(struct pci_dev *pci_dev)
{
	/*
	 * Currently we allow normal PCI devices and PCI bridges transition
	 * into D3 if their bridge_d3 is set.
	 */
	return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
}

struct pci_vpd_ops {
	ssize_t (*read)(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
	ssize_t (*write)(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
	int (*set_size)(struct pci_dev *dev, size_t len);
};

struct pci_vpd {
	const struct pci_vpd_ops *ops;
	struct bin_attribute *attr; /* descriptor for sysfs VPD entry */
	struct mutex	lock;
	unsigned int	len;
	u16		flag;
	u8		cap;
	u8		busy:1;
	u8		valid:1;
};

int pci_vpd_init(struct pci_dev *dev);
void pci_vpd_release(struct pci_dev *dev);

/* PCI /proc functions */
#ifdef CONFIG_PROC_FS
int pci_proc_attach_device(struct pci_dev *dev);
int pci_proc_detach_device(struct pci_dev *dev);
int pci_proc_detach_bus(struct pci_bus *bus);
#else
static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
#endif

/* Functions for PCI Hotplug drivers to use */
int pci_hp_add_bridge(struct pci_dev *dev);

#ifdef HAVE_PCI_LEGACY
void pci_create_legacy_files(struct pci_bus *bus);
void pci_remove_legacy_files(struct pci_bus *bus);
#else
static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
#endif

/* Lock for read/write access to pci device and bus lists */
extern struct rw_semaphore pci_bus_sem;

extern raw_spinlock_t pci_lock;

extern unsigned int pci_pm_d3_delay;

#ifdef CONFIG_PCI_MSI
void pci_no_msi(void);
#else
static inline void pci_no_msi(void) { }
#endif

static inline void pci_msi_set_enable(struct pci_dev *dev, int enable)
{
	u16 control;

	pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
	control &= ~PCI_MSI_FLAGS_ENABLE;
	if (enable)
		control |= PCI_MSI_FLAGS_ENABLE;
	pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
}

static inline void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set)
{
	u16 ctrl;

	pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
	ctrl &= ~clear;
	ctrl |= set;
	pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl);
}

void pci_realloc_get_opt(char *);

static inline int pci_no_d1d2(struct pci_dev *dev)
{
	unsigned int parent_dstates = 0;

	if (dev->bus->self)
		parent_dstates = dev->bus->self->no_d1d2;
	return (dev->no_d1d2 || parent_dstates);

}
extern const struct attribute_group *pci_dev_groups[];
extern const struct attribute_group *pcibus_groups[];
extern struct device_type pci_dev_type;
extern const struct attribute_group *pci_bus_groups[];


/**
 * pci_match_one_device - Tell if a PCI device structure has a matching
 *                        PCI device id structure
 * @id: single PCI device id structure to match
 * @dev: the PCI device structure to match against
 *
 * Returns the matching pci_device_id structure or %NULL if there is no match.
 */
static inline const struct pci_device_id *
pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
{
	if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
	    (id->device == PCI_ANY_ID || id->device == dev->device) &&
	    (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
	    (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
	    !((id->class ^ dev->class) & id->class_mask))
		return id;
	return NULL;
}

/* PCI slot sysfs helper code */
#define to_pci_slot(s) container_of(s, struct pci_slot, kobj)

extern struct kset *pci_slots_kset;

struct pci_slot_attribute {
	struct attribute attr;
	ssize_t (*show)(struct pci_slot *, char *);
	ssize_t (*store)(struct pci_slot *, const char *, size_t);
};
#define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)

enum pci_bar_type {
	pci_bar_unknown,	/* Standard PCI BAR probe */
	pci_bar_io,		/* An io port BAR */
	pci_bar_mem32,		/* A 32-bit memory BAR */
	pci_bar_mem64,		/* A 64-bit memory BAR */
};

bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
				int crs_timeout);
int pci_setup_device(struct pci_dev *dev);
int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
		    struct resource *res, unsigned int reg);
void pci_configure_ari(struct pci_dev *dev);
void __pci_bus_size_bridges(struct pci_bus *bus,
			struct list_head *realloc_head);
void __pci_bus_assign_resources(const struct pci_bus *bus,
				struct list_head *realloc_head,
				struct list_head *fail_head);
bool pci_bus_clip_resource(struct pci_dev *dev, int idx);

void pci_reassigndev_resource_alignment(struct pci_dev *dev);
void pci_disable_bridge_window(struct pci_dev *dev);

/* Single Root I/O Virtualization */
struct pci_sriov {
	int pos;		/* capability position */
	int nres;		/* number of resources */
	u32 cap;		/* SR-IOV Capabilities */
	u16 ctrl;		/* SR-IOV Control */
	u16 total_VFs;		/* total VFs associated with the PF */
	u16 initial_VFs;	/* initial VFs associated with the PF */
	u16 num_VFs;		/* number of VFs available */
	u16 offset;		/* first VF Routing ID offset */
	u16 stride;		/* following VF stride */
	u32 pgsz;		/* page size for BAR alignment */
	u8 link;		/* Function Dependency Link */
	u8 max_VF_buses;	/* max buses consumed by VFs */
	u16 driver_max_VFs;	/* max num VFs driver supports */
	struct pci_dev *dev;	/* lowest numbered PF */
	struct pci_dev *self;	/* this PF */
	resource_size_t barsz[PCI_SRIOV_NUM_BARS];	/* VF BAR size */
	bool drivers_autoprobe;	/* auto probing of VFs by driver */
};

/* pci_dev priv_flags */
#define PCI_DEV_DISCONNECTED 0

static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused)
{
	set_bit(PCI_DEV_DISCONNECTED, &dev->priv_flags);
	return 0;
}

static inline bool pci_dev_is_disconnected(const struct pci_dev *dev)
{
	return test_bit(PCI_DEV_DISCONNECTED, &dev->priv_flags);
}

#ifdef CONFIG_PCI_ATS
void pci_restore_ats_state(struct pci_dev *dev);
#else
static inline void pci_restore_ats_state(struct pci_dev *dev)
{
}
#endif /* CONFIG_PCI_ATS */

#ifdef CONFIG_PCI_IOV
int pci_iov_init(struct pci_dev *dev);
void pci_iov_release(struct pci_dev *dev);
void pci_iov_update_resource(struct pci_dev *dev, int resno);
resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
void pci_restore_iov_state(struct pci_dev *dev);
int pci_iov_bus_range(struct pci_bus *bus);

#else
static inline int pci_iov_init(struct pci_dev *dev)
{
	return -ENODEV;
}
static inline void pci_iov_release(struct pci_dev *dev)

{
}
static inline void pci_restore_iov_state(struct pci_dev *dev)
{
}
static inline int pci_iov_bus_range(struct pci_bus *bus)
{
	return 0;
}

#endif /* CONFIG_PCI_IOV */

unsigned long pci_cardbus_resource_alignment(struct resource *);

static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
						     struct resource *res)
{
#ifdef CONFIG_PCI_IOV
	int resno = res - dev->resource;

	if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
		return pci_sriov_resource_alignment(dev, resno);
#endif
	if (dev->class >> 8  == PCI_CLASS_BRIDGE_CARDBUS)
		return pci_cardbus_resource_alignment(res);
	return resource_alignment(res);
}

void pci_enable_acs(struct pci_dev *dev);

#ifdef CONFIG_PCIE_PTM
void pci_ptm_init(struct pci_dev *dev);
#else
static inline void pci_ptm_init(struct pci_dev *dev) { }
#endif

struct pci_dev_reset_methods {
	u16 vendor;
	u16 device;
	int (*reset)(struct pci_dev *dev, int probe);
};

#ifdef CONFIG_PCI_QUIRKS
int pci_dev_specific_reset(struct pci_dev *dev, int probe);
#else
static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
{
	return -ENOTTY;
}
#endif

#if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
			  struct resource *res);
#endif

#endif /* DRIVERS_PCI_H */
Commit	Line	Data
557848c3 ZY	1	#ifndef DRIVERS_PCI_H
	2	#define DRIVERS_PCI_H
	3
fff905f3 WY	4	#define PCI_FIND_CAP_TTL 48
fff905f3 WY	5
8531e283 LW	6	#define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */
8531e283 LW	7
343e51ae JK	8	extern const unsigned char pcie_link_speed[];
343e51ae JK	9
7a1562d4 YL	10	bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
7a1562d4 YL	11
1da177e4 LT	12	/* Functions internal to the PCI core code */
1da177e4 LT	13
f39d5b72 BH	14	int pci_create_sysfs_dev_files(struct pci_dev *pdev);
f39d5b72 BH	15	void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
6058989b	16	#if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI)
911e1c9b	17	static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
b879743f	18	{ return; }
911e1c9b	19	static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
b879743f	20	{ return; }
911e1c9b	21	#else
f39d5b72 BH	22	void pci_create_firmware_label_files(struct pci_dev *pdev);
f39d5b72 BH	23	void pci_remove_firmware_label_files(struct pci_dev *pdev);
911e1c9b	24	#endif
f39d5b72	25	void pci_cleanup_rom(struct pci_dev *dev);
f7195824	26
3b519e4e MW	27	enum pci_mmap_api {
	28	PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
	29	PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
	30	};
f39d5b72 BH	31	int pci_mmap_fits(struct pci_dev pdev, int resno, struct vm_area_struct vmai,
f39d5b72 BH	32	enum pci_mmap_api mmap_api);
f7195824	33
711d5779	34	int pci_probe_reset_function(struct pci_dev *dev);
ce5ccdef	35
961d9120	36	/**
b33bfdef	37	* struct pci_platform_pm_ops - Firmware PM callbacks
961d9120	38	*
b33bfdef RD	39	* @is_manageable: returns 'true' if given device is power manageable by the
b33bfdef RD	40	* platform firmware
961d9120	41	*
b33bfdef	42	* @set_state: invokes the platform firmware to set the device's power state
961d9120	43	*
cc7cc02b LW	44	* @get_state: queries the platform firmware for a device's current power state
cc7cc02b LW	45	*
b33bfdef RD	46	* @choose_state: returns PCI power state of given device preferred by the
	47	* platform; to be used during system-wide transitions from a
	48	* sleeping state to the working state and vice versa
961d9120	49	*
0847684c	50	* @set_wakeup: enables/disables wakeup capability for the device
b67ea761	51	*
bac2a909 RW	52	* @need_resume: returns 'true' if the given device (which is currently
	53	* suspended) needs to be resumed to be configured for system
	54	* wakeup.
	55	*
961d9120 RW	56	* If given platform is generally capable of power managing PCI devices, all of
	57	* these callbacks are mandatory.
	58	*/
	59	struct pci_platform_pm_ops {
	60	bool (is_manageable)(struct pci_dev dev);
	61	int (set_state)(struct pci_dev dev, pci_power_t state);
cc7cc02b	62	pci_power_t (get_state)(struct pci_dev dev);
961d9120	63	pci_power_t (choose_state)(struct pci_dev dev);
0847684c	64	int (set_wakeup)(struct pci_dev dev, bool enable);
bac2a909	65	bool (need_resume)(struct pci_dev dev);
961d9120 RW	66	};
961d9120 RW	67
299f2ffe	68	int pci_set_platform_pm(const struct pci_platform_pm_ops *ops);
f39d5b72 BH	69	void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
	70	void pci_power_up(struct pci_dev *dev);
	71	void pci_disable_enabled_device(struct pci_dev *dev);
	72	int pci_finish_runtime_suspend(struct pci_dev *dev);
	73	int __pci_pme_wakeup(struct pci_dev dev, void ign);
0ce3fcaf	74	void pci_pme_restore(struct pci_dev *dev);
bac2a909	75	bool pci_dev_keep_suspended(struct pci_dev *dev);
2cef548a	76	void pci_dev_complete_resume(struct pci_dev *pci_dev);
f39d5b72 BH	77	void pci_config_pm_runtime_get(struct pci_dev *dev);
	78	void pci_config_pm_runtime_put(struct pci_dev *dev);
	79	void pci_pm_init(struct pci_dev *dev);
938174e5	80	void pci_ea_init(struct pci_dev *dev);
f39d5b72	81	void pci_allocate_cap_save_buffers(struct pci_dev *dev);
f796841e	82	void pci_free_cap_save_buffers(struct pci_dev *dev);
c6a63307	83	bool pci_bridge_d3_possible(struct pci_dev *dev);
1ed276a7	84	void pci_bridge_d3_update(struct pci_dev *dev);
aa8c6c93	85
b6e335ae RW	86	static inline void pci_wakeup_event(struct pci_dev *dev)
	87	{
	88	/* Wait 100 ms before the system can be put into a sleep state. */
	89	pm_wakeup_event(&dev->dev, 100);
	90	}
	91
326c1cda	92	static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
aa8c6c93 RW	93	{
	94	return !!(pci_dev->subordinate);
	95	}
0f64474b	96
9d26d3a8 MW	97	static inline bool pci_power_manageable(struct pci_dev *pci_dev)
	98	{
	99	/*
	100	* Currently we allow normal PCI devices and PCI bridges transition
	101	* into D3 if their bridge_d3 is set.
	102	*/
	103	return !pci_has_subordinate(pci_dev) \|\| pci_dev->bridge_d3;
	104	}
	105
94e61088	106	struct pci_vpd_ops {
287d19ce SH	107	ssize_t (read)(struct pci_dev dev, loff_t pos, size_t count, void *buf);
287d19ce SH	108	ssize_t (write)(struct pci_dev dev, loff_t pos, size_t count, const void *buf);
cb92148b	109	int (set_size)(struct pci_dev dev, size_t len);
94e61088 BH	110	};
	111
	112	struct pci_vpd {
287d19ce	113	const struct pci_vpd_ops *ops;
94e61088	114	struct bin_attribute attr; / descriptor for sysfs VPD entry */
408641e9 BH	115	struct mutex lock;
	116	unsigned int len;
	117	u16 flag;
	118	u8 cap;
	119	u8 busy:1;
	120	u8 valid:1;
94e61088 BH	121	};
94e61088 BH	122
f1cd93f9	123	int pci_vpd_init(struct pci_dev *dev);
64379079	124	void pci_vpd_release(struct pci_dev *dev);
94e61088	125
1da177e4 LT	126	/* PCI /proc functions */
1da177e4 LT	127	#ifdef CONFIG_PROC_FS
f39d5b72 BH	128	int pci_proc_attach_device(struct pci_dev *dev);
	129	int pci_proc_detach_device(struct pci_dev *dev);
	130	int pci_proc_detach_bus(struct pci_bus *bus);
1da177e4 LT	131	#else
	132	static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
	133	static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
1da177e4 LT	134	static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
	135	#endif
	136
	137	/* Functions for PCI Hotplug drivers to use */
a8e4b9c1	138	int pci_hp_add_bridge(struct pci_dev *dev);
1da177e4	139
f19aeb1f	140	#ifdef HAVE_PCI_LEGACY
f39d5b72 BH	141	void pci_create_legacy_files(struct pci_bus *bus);
f39d5b72 BH	142	void pci_remove_legacy_files(struct pci_bus *bus);
f19aeb1f BH	143	#else
	144	static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
	145	static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
	146	#endif
1da177e4 LT	147
1da177e4 LT	148	/* Lock for read/write access to pci device and bus lists */
d71374da	149	extern struct rw_semaphore pci_bus_sem;
1da177e4	150
a2e27787 JK	151	extern raw_spinlock_t pci_lock;
a2e27787 JK	152
ffadcc2f	153	extern unsigned int pci_pm_d3_delay;
88187dfa	154
4b47b0ee	155	#ifdef CONFIG_PCI_MSI
309e57df	156	void pci_no_msi(void);
4b47b0ee	157	#else
309e57df	158	static inline void pci_no_msi(void) { }
4b47b0ee	159	#endif
8fed4b65	160
6a25f5e3 MT	161	static inline void pci_msi_set_enable(struct pci_dev *dev, int enable)
	162	{
	163	u16 control;
	164
	165	pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
	166	control &= ~PCI_MSI_FLAGS_ENABLE;
	167	if (enable)
	168	control \|= PCI_MSI_FLAGS_ENABLE;
	169	pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
	170	}
	171
	172	static inline void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set)
	173	{
	174	u16 ctrl;
	175
	176	pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
	177	ctrl &= ~clear;
	178	ctrl \|= set;
	179	pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl);
	180	}
	181
b55438fd	182	void pci_realloc_get_opt(char *);
f483d392	183
ffadcc2f KCA	184	static inline int pci_no_d1d2(struct pci_dev *dev)
	185	{
	186	unsigned int parent_dstates = 0;
4b47b0ee	187
ffadcc2f KCA	188	if (dev->bus->self)
	189	parent_dstates = dev->bus->self->no_d1d2;
	190	return (dev->no_d1d2 \|\| parent_dstates);
	191
	192	}
5136b2da	193	extern const struct attribute_group *pci_dev_groups[];
56039e65	194	extern const struct attribute_group *pcibus_groups[];
4e15c46b	195	extern struct device_type pci_dev_type;
0f49ba55	196	extern const struct attribute_group *pci_bus_groups[];
705b1aaa	197
1da177e4 LT	198
	199	/**
	200	* pci_match_one_device - Tell if a PCI device structure has a matching
	201	* PCI device id structure
	202	* @id: single PCI device id structure to match
	203	* @dev: the PCI device structure to match against
367b09fe	204	*
1da177e4 LT	205	* Returns the matching pci_device_id structure or %NULL if there is no match.
	206	*/
	207	static inline const struct pci_device_id *
	208	pci_match_one_device(const struct pci_device_id id, const struct pci_dev dev)
	209	{
	210	if ((id->vendor == PCI_ANY_ID \|\| id->vendor == dev->vendor) &&
	211	(id->device == PCI_ANY_ID \|\| id->device == dev->device) &&
	212	(id->subvendor == PCI_ANY_ID \|\| id->subvendor == dev->subsystem_vendor) &&
	213	(id->subdevice == PCI_ANY_ID \|\| id->subdevice == dev->subsystem_device) &&
	214	!((id->class ^ dev->class) & id->class_mask))
	215	return id;
	216	return NULL;
	217	}
	218
f46753c5 AC	219	/* PCI slot sysfs helper code */
	220	#define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
	221
	222	extern struct kset *pci_slots_kset;
	223
	224	struct pci_slot_attribute {
	225	struct attribute attr;
	226	ssize_t (show)(struct pci_slot , char *);
	227	ssize_t (store)(struct pci_slot , const char *, size_t);
	228	};
	229	#define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
	230
0b400c7e YZ	231	enum pci_bar_type {
	232	pci_bar_unknown, /* Standard PCI BAR probe */
	233	pci_bar_io, /* An io port BAR */
	234	pci_bar_mem32, /* A 32-bit memory BAR */
	235	pci_bar_mem64, /* A 64-bit memory BAR */
	236	};
	237
efdc87da YL	238	bool pci_bus_read_dev_vendor_id(struct pci_bus bus, int devfn, u32 pl,
efdc87da YL	239	int crs_timeout);
f39d5b72 BH	240	int pci_setup_device(struct pci_dev *dev);
	241	int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
	242	struct resource *res, unsigned int reg);
f39d5b72	243	void pci_configure_ari(struct pci_dev *dev);
10874f5a	244	void __pci_bus_size_bridges(struct pci_bus *bus,
d66ecb72	245	struct list_head *realloc_head);
10874f5a BH	246	void __pci_bus_assign_resources(const struct pci_bus *bus,
	247	struct list_head *realloc_head,
	248	struct list_head *fail_head);
0f7e7aee	249	bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
939de1d6	250
2069ecfb	251	void pci_reassigndev_resource_alignment(struct pci_dev *dev);
f39d5b72	252	void pci_disable_bridge_window(struct pci_dev *dev);
32a9a682	253
d1b054da YZ	254	/* Single Root I/O Virtualization */
	255	struct pci_sriov {
	256	int pos; /* capability position */
	257	int nres; /* number of resources */
	258	u32 cap; /* SR-IOV Capabilities */
	259	u16 ctrl; /* SR-IOV Control */
6b136724 BH	260	u16 total_VFs; /* total VFs associated with the PF */
	261	u16 initial_VFs; /* initial VFs associated with the PF */
	262	u16 num_VFs; /* number of VFs available */
d1b054da YZ	263	u16 offset; /* first VF Routing ID offset */
	264	u16 stride; /* following VF stride */
	265	u32 pgsz; /* page size for BAR alignment */
	266	u8 link; /* Function Dependency Link */
4449f079	267	u8 max_VF_buses; /* max buses consumed by VFs */
6b136724	268	u16 driver_max_VFs; /* max num VFs driver supports */
d1b054da YZ	269	struct pci_dev dev; / lowest numbered PF */
d1b054da YZ	270	struct pci_dev self; / this PF */
0e6c9122	271	resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
0e7df224	272	bool drivers_autoprobe; /* auto probing of VFs by driver */
d1b054da YZ	273	};
d1b054da YZ	274
89ee9f76 KB	275	/* pci_dev priv_flags */
	276	#define PCI_DEV_DISCONNECTED 0
	277
	278	static inline int pci_dev_set_disconnected(struct pci_dev dev, void unused)
	279	{
	280	set_bit(PCI_DEV_DISCONNECTED, &dev->priv_flags);
	281	return 0;
	282	}
	283
	284	static inline bool pci_dev_is_disconnected(const struct pci_dev *dev)
	285	{
	286	return test_bit(PCI_DEV_DISCONNECTED, &dev->priv_flags);
	287	}
	288
1900ca13	289	#ifdef CONFIG_PCI_ATS
f39d5b72	290	void pci_restore_ats_state(struct pci_dev *dev);
1900ca13 HX	291	#else
	292	static inline void pci_restore_ats_state(struct pci_dev *dev)
	293	{
	294	}
	295	#endif /* CONFIG_PCI_ATS */
	296
d1b054da	297	#ifdef CONFIG_PCI_IOV
f39d5b72 BH	298	int pci_iov_init(struct pci_dev *dev);
f39d5b72 BH	299	void pci_iov_release(struct pci_dev *dev);
6ffa2489	300	void pci_iov_update_resource(struct pci_dev *dev, int resno);
f39d5b72 BH	301	resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
	302	void pci_restore_iov_state(struct pci_dev *dev);
	303	int pci_iov_bus_range(struct pci_bus *bus);
302b4215	304
d1b054da YZ	305	#else
	306	static inline int pci_iov_init(struct pci_dev *dev)
	307	{
	308	return -ENODEV;
	309	}
	310	static inline void pci_iov_release(struct pci_dev *dev)
	311
	312	{
	313	}
8c5cdb6a YZ	314	static inline void pci_restore_iov_state(struct pci_dev *dev)
	315	{
	316	}
a28724b0 YZ	317	static inline int pci_iov_bus_range(struct pci_bus *bus)
	318	{
	319	return 0;
	320	}
302b4215	321
d1b054da YZ	322	#endif /* CONFIG_PCI_IOV */
d1b054da YZ	323
f39d5b72	324	unsigned long pci_cardbus_resource_alignment(struct resource *);
0a2daa1c	325
0e52247a	326	static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
f39d5b72	327	struct resource *res)
6faf17f6 CW	328	{
	329	#ifdef CONFIG_PCI_IOV
	330	int resno = res - dev->resource;
	331
	332	if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
	333	return pci_sriov_resource_alignment(dev, resno);
	334	#endif
0a2daa1c RP	335	if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
0a2daa1c RP	336	return pci_cardbus_resource_alignment(res);
6faf17f6 CW	337	return resource_alignment(res);
	338	}
	339
f39d5b72	340	void pci_enable_acs(struct pci_dev *dev);
ae21ee65	341
9bb04a0c JY	342	#ifdef CONFIG_PCIE_PTM
	343	void pci_ptm_init(struct pci_dev *dev);
	344	#else
	345	static inline void pci_ptm_init(struct pci_dev *dev) { }
	346	#endif
	347
b9c3b266 DC	348	struct pci_dev_reset_methods {
	349	u16 vendor;
	350	u16 device;
	351	int (reset)(struct pci_dev dev, int probe);
	352	};
	353
93177a74	354	#ifdef CONFIG_PCI_QUIRKS
f39d5b72	355	int pci_dev_specific_reset(struct pci_dev *dev, int probe);
93177a74 RW	356	#else
	357	static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
	358	{
	359	return -ENOTTY;
	360	}
	361	#endif
b9c3b266	362
169de969 DL	363	#if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
	364	int acpi_get_rc_resources(struct device dev, const char hid, u16 segment,
	365	struct resource *res);
	366	#endif
	367
557848c3	368	#endif /* DRIVERS_PCI_H */