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Commit | Line | Data |
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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
557848c3 ZY |
2 | #ifndef DRIVERS_PCI_H |
3 | #define DRIVERS_PCI_H | |
4 | ||
2209e06f AG |
5 | #include <linux/pci.h> |
6 | ||
f8bf2aeb JS |
7 | /* Number of possible devfns: 0.0 to 1f.7 inclusive */ |
8 | #define MAX_NR_DEVFNS 256 | |
9 | ||
fff905f3 WY |
10 | #define PCI_FIND_CAP_TTL 48 |
11 | ||
8531e283 LW |
12 | #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */ |
13 | ||
343e51ae | 14 | extern const unsigned char pcie_link_speed[]; |
11eb0e0e | 15 | extern bool pci_early_dump; |
343e51ae | 16 | |
7a1562d4 | 17 | bool pcie_cap_has_lnkctl(const struct pci_dev *dev); |
af65d1ad | 18 | bool pcie_cap_has_rtctl(const struct pci_dev *dev); |
7a1562d4 | 19 | |
1da177e4 LT |
20 | /* Functions internal to the PCI core code */ |
21 | ||
f39d5b72 BH |
22 | int pci_create_sysfs_dev_files(struct pci_dev *pdev); |
23 | void pci_remove_sysfs_dev_files(struct pci_dev *pdev); | |
6058989b | 24 | #if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI) |
911e1c9b | 25 | static inline void pci_create_firmware_label_files(struct pci_dev *pdev) |
b879743f | 26 | { return; } |
911e1c9b | 27 | static inline void pci_remove_firmware_label_files(struct pci_dev *pdev) |
b879743f | 28 | { return; } |
911e1c9b | 29 | #else |
f39d5b72 BH |
30 | void pci_create_firmware_label_files(struct pci_dev *pdev); |
31 | void pci_remove_firmware_label_files(struct pci_dev *pdev); | |
911e1c9b | 32 | #endif |
f39d5b72 | 33 | void pci_cleanup_rom(struct pci_dev *dev); |
f7195824 | 34 | |
3b519e4e MW |
35 | enum pci_mmap_api { |
36 | PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */ | |
37 | PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */ | |
38 | }; | |
f39d5b72 BH |
39 | int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai, |
40 | enum pci_mmap_api mmap_api); | |
f7195824 | 41 | |
711d5779 | 42 | int pci_probe_reset_function(struct pci_dev *dev); |
381634ca | 43 | int pci_bridge_secondary_bus_reset(struct pci_dev *dev); |
c4eed62a | 44 | int pci_bus_error_reset(struct pci_dev *dev); |
ce5ccdef | 45 | |
638c133e BH |
46 | #define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */ |
47 | #define PCI_PM_D3HOT_WAIT 10 /* msec */ | |
48 | #define PCI_PM_D3COLD_WAIT 100 /* msec */ | |
c776dd50 | 49 | |
961d9120 | 50 | /** |
b33bfdef | 51 | * struct pci_platform_pm_ops - Firmware PM callbacks |
961d9120 | 52 | * |
26ad34d5 MW |
53 | * @bridge_d3: Does the bridge allow entering into D3 |
54 | * | |
b33bfdef | 55 | * @is_manageable: returns 'true' if given device is power manageable by the |
0aa0f5d1 | 56 | * platform firmware |
961d9120 | 57 | * |
b33bfdef | 58 | * @set_state: invokes the platform firmware to set the device's power state |
961d9120 | 59 | * |
cc7cc02b LW |
60 | * @get_state: queries the platform firmware for a device's current power state |
61 | * | |
b51033e0 RW |
62 | * @refresh_state: asks the platform to refresh the device's power state data |
63 | * | |
b33bfdef | 64 | * @choose_state: returns PCI power state of given device preferred by the |
0aa0f5d1 BH |
65 | * platform; to be used during system-wide transitions from a |
66 | * sleeping state to the working state and vice versa | |
961d9120 | 67 | * |
0847684c | 68 | * @set_wakeup: enables/disables wakeup capability for the device |
b67ea761 | 69 | * |
bac2a909 | 70 | * @need_resume: returns 'true' if the given device (which is currently |
0aa0f5d1 BH |
71 | * suspended) needs to be resumed to be configured for system |
72 | * wakeup. | |
bac2a909 | 73 | * |
961d9120 RW |
74 | * If given platform is generally capable of power managing PCI devices, all of |
75 | * these callbacks are mandatory. | |
76 | */ | |
77 | struct pci_platform_pm_ops { | |
26ad34d5 | 78 | bool (*bridge_d3)(struct pci_dev *dev); |
961d9120 RW |
79 | bool (*is_manageable)(struct pci_dev *dev); |
80 | int (*set_state)(struct pci_dev *dev, pci_power_t state); | |
cc7cc02b | 81 | pci_power_t (*get_state)(struct pci_dev *dev); |
b51033e0 | 82 | void (*refresh_state)(struct pci_dev *dev); |
961d9120 | 83 | pci_power_t (*choose_state)(struct pci_dev *dev); |
0847684c | 84 | int (*set_wakeup)(struct pci_dev *dev, bool enable); |
bac2a909 | 85 | bool (*need_resume)(struct pci_dev *dev); |
961d9120 RW |
86 | }; |
87 | ||
299f2ffe | 88 | int pci_set_platform_pm(const struct pci_platform_pm_ops *ops); |
f39d5b72 | 89 | void pci_update_current_state(struct pci_dev *dev, pci_power_t state); |
b51033e0 | 90 | void pci_refresh_power_state(struct pci_dev *dev); |
adfac8f6 | 91 | int pci_power_up(struct pci_dev *dev); |
f39d5b72 BH |
92 | void pci_disable_enabled_device(struct pci_dev *dev); |
93 | int pci_finish_runtime_suspend(struct pci_dev *dev); | |
600a5b4f | 94 | void pcie_clear_device_status(struct pci_dev *dev); |
dcb0453d | 95 | void pcie_clear_root_pme_status(struct pci_dev *dev); |
669696eb KS |
96 | bool pci_check_pme_status(struct pci_dev *dev); |
97 | void pci_pme_wakeup_bus(struct pci_bus *bus); | |
f39d5b72 | 98 | int __pci_pme_wakeup(struct pci_dev *dev, void *ign); |
0ce3fcaf | 99 | void pci_pme_restore(struct pci_dev *dev); |
0c7376ad RW |
100 | bool pci_dev_need_resume(struct pci_dev *dev); |
101 | void pci_dev_adjust_pme(struct pci_dev *dev); | |
2cef548a | 102 | void pci_dev_complete_resume(struct pci_dev *pci_dev); |
f39d5b72 BH |
103 | void pci_config_pm_runtime_get(struct pci_dev *dev); |
104 | void pci_config_pm_runtime_put(struct pci_dev *dev); | |
105 | void pci_pm_init(struct pci_dev *dev); | |
938174e5 | 106 | void pci_ea_init(struct pci_dev *dev); |
f39d5b72 | 107 | void pci_allocate_cap_save_buffers(struct pci_dev *dev); |
f796841e | 108 | void pci_free_cap_save_buffers(struct pci_dev *dev); |
c6a63307 | 109 | bool pci_bridge_d3_possible(struct pci_dev *dev); |
1ed276a7 | 110 | void pci_bridge_d3_update(struct pci_dev *dev); |
ad9001f2 | 111 | void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev); |
aa8c6c93 | 112 | |
b6e335ae RW |
113 | static inline void pci_wakeup_event(struct pci_dev *dev) |
114 | { | |
115 | /* Wait 100 ms before the system can be put into a sleep state. */ | |
116 | pm_wakeup_event(&dev->dev, 100); | |
117 | } | |
118 | ||
326c1cda | 119 | static inline bool pci_has_subordinate(struct pci_dev *pci_dev) |
aa8c6c93 RW |
120 | { |
121 | return !!(pci_dev->subordinate); | |
122 | } | |
0f64474b | 123 | |
9d26d3a8 MW |
124 | static inline bool pci_power_manageable(struct pci_dev *pci_dev) |
125 | { | |
126 | /* | |
127 | * Currently we allow normal PCI devices and PCI bridges transition | |
128 | * into D3 if their bridge_d3 is set. | |
129 | */ | |
130 | return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3; | |
131 | } | |
132 | ||
984998e3 MW |
133 | static inline bool pcie_downstream_port(const struct pci_dev *dev) |
134 | { | |
135 | int type = pci_pcie_type(dev); | |
136 | ||
137 | return type == PCI_EXP_TYPE_ROOT_PORT || | |
138 | type == PCI_EXP_TYPE_DOWNSTREAM || | |
139 | type == PCI_EXP_TYPE_PCIE_BRIDGE; | |
140 | } | |
141 | ||
f1cd93f9 | 142 | int pci_vpd_init(struct pci_dev *dev); |
64379079 | 143 | void pci_vpd_release(struct pci_dev *dev); |
b1c615c4 BH |
144 | void pcie_vpd_create_sysfs_dev_files(struct pci_dev *dev); |
145 | void pcie_vpd_remove_sysfs_dev_files(struct pci_dev *dev); | |
94e61088 | 146 | |
440589dd KS |
147 | /* PCI Virtual Channel */ |
148 | int pci_save_vc_state(struct pci_dev *dev); | |
149 | void pci_restore_vc_state(struct pci_dev *dev); | |
150 | void pci_allocate_vc_save_buffers(struct pci_dev *dev); | |
151 | ||
1da177e4 LT |
152 | /* PCI /proc functions */ |
153 | #ifdef CONFIG_PROC_FS | |
f39d5b72 BH |
154 | int pci_proc_attach_device(struct pci_dev *dev); |
155 | int pci_proc_detach_device(struct pci_dev *dev); | |
156 | int pci_proc_detach_bus(struct pci_bus *bus); | |
1da177e4 LT |
157 | #else |
158 | static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; } | |
159 | static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; } | |
1da177e4 LT |
160 | static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; } |
161 | #endif | |
162 | ||
163 | /* Functions for PCI Hotplug drivers to use */ | |
a8e4b9c1 | 164 | int pci_hp_add_bridge(struct pci_dev *dev); |
1da177e4 | 165 | |
f19aeb1f | 166 | #ifdef HAVE_PCI_LEGACY |
f39d5b72 BH |
167 | void pci_create_legacy_files(struct pci_bus *bus); |
168 | void pci_remove_legacy_files(struct pci_bus *bus); | |
f19aeb1f BH |
169 | #else |
170 | static inline void pci_create_legacy_files(struct pci_bus *bus) { return; } | |
171 | static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; } | |
172 | #endif | |
1da177e4 LT |
173 | |
174 | /* Lock for read/write access to pci device and bus lists */ | |
d71374da | 175 | extern struct rw_semaphore pci_bus_sem; |
c4eed62a | 176 | extern struct mutex pci_slot_mutex; |
1da177e4 | 177 | |
a2e27787 JK |
178 | extern raw_spinlock_t pci_lock; |
179 | ||
3789af9a | 180 | extern unsigned int pci_pm_d3hot_delay; |
88187dfa | 181 | |
4b47b0ee | 182 | #ifdef CONFIG_PCI_MSI |
309e57df | 183 | void pci_no_msi(void); |
4b47b0ee | 184 | #else |
309e57df | 185 | static inline void pci_no_msi(void) { } |
4b47b0ee | 186 | #endif |
8fed4b65 | 187 | |
6a25f5e3 MT |
188 | static inline void pci_msi_set_enable(struct pci_dev *dev, int enable) |
189 | { | |
190 | u16 control; | |
191 | ||
192 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); | |
193 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
194 | if (enable) | |
195 | control |= PCI_MSI_FLAGS_ENABLE; | |
196 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); | |
197 | } | |
198 | ||
199 | static inline void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set) | |
200 | { | |
201 | u16 ctrl; | |
202 | ||
203 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl); | |
204 | ctrl &= ~clear; | |
205 | ctrl |= set; | |
206 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl); | |
207 | } | |
208 | ||
b55438fd | 209 | void pci_realloc_get_opt(char *); |
f483d392 | 210 | |
ffadcc2f KCA |
211 | static inline int pci_no_d1d2(struct pci_dev *dev) |
212 | { | |
213 | unsigned int parent_dstates = 0; | |
4b47b0ee | 214 | |
ffadcc2f KCA |
215 | if (dev->bus->self) |
216 | parent_dstates = dev->bus->self->no_d1d2; | |
217 | return (dev->no_d1d2 || parent_dstates); | |
218 | ||
219 | } | |
5136b2da | 220 | extern const struct attribute_group *pci_dev_groups[]; |
56039e65 | 221 | extern const struct attribute_group *pcibus_groups[]; |
69f2dc24 | 222 | extern const struct device_type pci_dev_type; |
0f49ba55 | 223 | extern const struct attribute_group *pci_bus_groups[]; |
705b1aaa | 224 | |
003d3b2c | 225 | extern unsigned long pci_hotplug_io_size; |
d7b8a217 NJ |
226 | extern unsigned long pci_hotplug_mmio_size; |
227 | extern unsigned long pci_hotplug_mmio_pref_size; | |
003d3b2c | 228 | extern unsigned long pci_hotplug_bus_size; |
1da177e4 LT |
229 | |
230 | /** | |
231 | * pci_match_one_device - Tell if a PCI device structure has a matching | |
0aa0f5d1 | 232 | * PCI device id structure |
1da177e4 LT |
233 | * @id: single PCI device id structure to match |
234 | * @dev: the PCI device structure to match against | |
367b09fe | 235 | * |
1da177e4 LT |
236 | * Returns the matching pci_device_id structure or %NULL if there is no match. |
237 | */ | |
238 | static inline const struct pci_device_id * | |
239 | pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev) | |
240 | { | |
241 | if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) && | |
242 | (id->device == PCI_ANY_ID || id->device == dev->device) && | |
243 | (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) && | |
244 | (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) && | |
245 | !((id->class ^ dev->class) & id->class_mask)) | |
246 | return id; | |
247 | return NULL; | |
248 | } | |
249 | ||
f46753c5 AC |
250 | /* PCI slot sysfs helper code */ |
251 | #define to_pci_slot(s) container_of(s, struct pci_slot, kobj) | |
252 | ||
253 | extern struct kset *pci_slots_kset; | |
254 | ||
255 | struct pci_slot_attribute { | |
256 | struct attribute attr; | |
257 | ssize_t (*show)(struct pci_slot *, char *); | |
258 | ssize_t (*store)(struct pci_slot *, const char *, size_t); | |
259 | }; | |
260 | #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr) | |
261 | ||
0b400c7e YZ |
262 | enum pci_bar_type { |
263 | pci_bar_unknown, /* Standard PCI BAR probe */ | |
0aa0f5d1 | 264 | pci_bar_io, /* An I/O port BAR */ |
0b400c7e YZ |
265 | pci_bar_mem32, /* A 32-bit memory BAR */ |
266 | pci_bar_mem64, /* A 64-bit memory BAR */ | |
267 | }; | |
268 | ||
975e1ac1 KS |
269 | struct device *pci_get_host_bridge_device(struct pci_dev *dev); |
270 | void pci_put_host_bridge_device(struct device *dev); | |
271 | ||
62ce94a7 | 272 | int pci_configure_extended_tags(struct pci_dev *dev, void *ign); |
efdc87da YL |
273 | bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, |
274 | int crs_timeout); | |
aa667c64 JP |
275 | bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, |
276 | int crs_timeout); | |
277 | int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout); | |
278 | ||
f39d5b72 BH |
279 | int pci_setup_device(struct pci_dev *dev); |
280 | int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, | |
281 | struct resource *res, unsigned int reg); | |
f39d5b72 | 282 | void pci_configure_ari(struct pci_dev *dev); |
10874f5a | 283 | void __pci_bus_size_bridges(struct pci_bus *bus, |
d66ecb72 | 284 | struct list_head *realloc_head); |
10874f5a BH |
285 | void __pci_bus_assign_resources(const struct pci_bus *bus, |
286 | struct list_head *realloc_head, | |
287 | struct list_head *fail_head); | |
0f7e7aee | 288 | bool pci_bus_clip_resource(struct pci_dev *dev, int idx); |
939de1d6 | 289 | |
2069ecfb | 290 | void pci_reassigndev_resource_alignment(struct pci_dev *dev); |
f39d5b72 | 291 | void pci_disable_bridge_window(struct pci_dev *dev); |
ecd29c1a KS |
292 | struct pci_bus *pci_bus_get(struct pci_bus *bus); |
293 | void pci_bus_put(struct pci_bus *bus); | |
32a9a682 | 294 | |
757bfaa2 YY |
295 | /* PCIe link information from Link Capabilities 2 */ |
296 | #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \ | |
297 | ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \ | |
298 | (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \ | |
299 | (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \ | |
300 | (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \ | |
301 | (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \ | |
302 | PCI_SPEED_UNKNOWN) | |
6cf57be0 | 303 | |
b852f63a TG |
304 | /* PCIe speed to Mb/s reduced by encoding overhead */ |
305 | #define PCIE_SPEED2MBS_ENC(speed) \ | |
9cb3985a YY |
306 | ((speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \ |
307 | (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \ | |
b852f63a TG |
308 | (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \ |
309 | (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \ | |
310 | (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \ | |
311 | 0) | |
312 | ||
e56faff5 | 313 | const char *pci_speed_string(enum pci_bus_speed speed); |
6cf57be0 | 314 | enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); |
c70b65fb | 315 | enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); |
b852f63a TG |
316 | u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed, |
317 | enum pcie_link_width *width); | |
2d1ce5ec | 318 | void __pcie_print_link_status(struct pci_dev *dev, bool verbose); |
0fa635ae | 319 | void pcie_report_downtraining(struct pci_dev *dev); |
5da78d95 | 320 | void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); |
6cf57be0 | 321 | |
d1b054da YZ |
322 | /* Single Root I/O Virtualization */ |
323 | struct pci_sriov { | |
0aa0f5d1 BH |
324 | int pos; /* Capability position */ |
325 | int nres; /* Number of resources */ | |
326 | u32 cap; /* SR-IOV Capabilities */ | |
327 | u16 ctrl; /* SR-IOV Control */ | |
328 | u16 total_VFs; /* Total VFs associated with the PF */ | |
329 | u16 initial_VFs; /* Initial VFs associated with the PF */ | |
330 | u16 num_VFs; /* Number of VFs available */ | |
331 | u16 offset; /* First VF Routing ID offset */ | |
332 | u16 stride; /* Following VF stride */ | |
333 | u16 vf_device; /* VF device ID */ | |
334 | u32 pgsz; /* Page size for BAR alignment */ | |
335 | u8 link; /* Function Dependency Link */ | |
336 | u8 max_VF_buses; /* Max buses consumed by VFs */ | |
337 | u16 driver_max_VFs; /* Max num VFs driver supports */ | |
338 | struct pci_dev *dev; /* Lowest numbered PF */ | |
339 | struct pci_dev *self; /* This PF */ | |
cf0921be KA |
340 | u32 class; /* VF device */ |
341 | u8 hdr_type; /* VF header type */ | |
342 | u16 subsystem_vendor; /* VF subsystem vendor */ | |
343 | u16 subsystem_device; /* VF subsystem device */ | |
0aa0f5d1 BH |
344 | resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */ |
345 | bool drivers_autoprobe; /* Auto probing of VFs by driver */ | |
d1b054da YZ |
346 | }; |
347 | ||
a6bd101b KB |
348 | /** |
349 | * pci_dev_set_io_state - Set the new error state if possible. | |
350 | * | |
351 | * @dev - pci device to set new error_state | |
352 | * @new - the state we want dev to be in | |
353 | * | |
354 | * Must be called with device_lock held. | |
355 | * | |
356 | * Returns true if state has been changed to the requested state. | |
357 | */ | |
358 | static inline bool pci_dev_set_io_state(struct pci_dev *dev, | |
359 | pci_channel_state_t new) | |
360 | { | |
361 | bool changed = false; | |
362 | ||
363 | device_lock_assert(&dev->dev); | |
364 | switch (new) { | |
365 | case pci_channel_io_perm_failure: | |
366 | switch (dev->error_state) { | |
367 | case pci_channel_io_frozen: | |
368 | case pci_channel_io_normal: | |
369 | case pci_channel_io_perm_failure: | |
370 | changed = true; | |
371 | break; | |
372 | } | |
373 | break; | |
374 | case pci_channel_io_frozen: | |
375 | switch (dev->error_state) { | |
376 | case pci_channel_io_frozen: | |
377 | case pci_channel_io_normal: | |
378 | changed = true; | |
379 | break; | |
380 | } | |
381 | break; | |
382 | case pci_channel_io_normal: | |
383 | switch (dev->error_state) { | |
384 | case pci_channel_io_frozen: | |
385 | case pci_channel_io_normal: | |
386 | changed = true; | |
387 | break; | |
388 | } | |
389 | break; | |
390 | } | |
391 | if (changed) | |
392 | dev->error_state = new; | |
393 | return changed; | |
394 | } | |
89ee9f76 KB |
395 | |
396 | static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused) | |
397 | { | |
a6bd101b KB |
398 | device_lock(&dev->dev); |
399 | pci_dev_set_io_state(dev, pci_channel_io_perm_failure); | |
400 | device_unlock(&dev->dev); | |
401 | ||
89ee9f76 KB |
402 | return 0; |
403 | } | |
404 | ||
405 | static inline bool pci_dev_is_disconnected(const struct pci_dev *dev) | |
406 | { | |
a6bd101b | 407 | return dev->error_state == pci_channel_io_perm_failure; |
89ee9f76 KB |
408 | } |
409 | ||
a6bd101b KB |
410 | /* pci_dev priv_flags */ |
411 | #define PCI_DEV_ADDED 0 | |
412 | ||
44bda4b7 HV |
413 | static inline void pci_dev_assign_added(struct pci_dev *dev, bool added) |
414 | { | |
415 | assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added); | |
416 | } | |
417 | ||
418 | static inline bool pci_dev_is_added(const struct pci_dev *dev) | |
419 | { | |
420 | return test_bit(PCI_DEV_ADDED, &dev->priv_flags); | |
421 | } | |
422 | ||
1e451160 KB |
423 | #ifdef CONFIG_PCIEAER |
424 | #include <linux/aer.h> | |
425 | ||
426 | #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */ | |
427 | ||
428 | struct aer_err_info { | |
429 | struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES]; | |
430 | int error_dev_num; | |
431 | ||
432 | unsigned int id:16; | |
433 | ||
434 | unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */ | |
435 | unsigned int __pad1:5; | |
436 | unsigned int multi_error_valid:1; | |
437 | ||
438 | unsigned int first_error:5; | |
439 | unsigned int __pad2:2; | |
440 | unsigned int tlp_header_valid:1; | |
441 | ||
442 | unsigned int status; /* COR/UNCOR Error Status */ | |
443 | unsigned int mask; /* COR/UNCOR Error Mask */ | |
444 | struct aer_header_log_regs tlp; /* TLP Header */ | |
445 | }; | |
446 | ||
447 | int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info); | |
448 | void aer_print_error(struct pci_dev *dev, struct aer_err_info *info); | |
449 | #endif /* CONFIG_PCIEAER */ | |
450 | ||
4f802170 KB |
451 | #ifdef CONFIG_PCIE_DPC |
452 | void pci_save_dpc_state(struct pci_dev *dev); | |
453 | void pci_restore_dpc_state(struct pci_dev *dev); | |
27005618 | 454 | void pci_dpc_init(struct pci_dev *pdev); |
aea47413 KS |
455 | void dpc_process_error(struct pci_dev *pdev); |
456 | pci_ers_result_t dpc_reset_link(struct pci_dev *pdev); | |
4f802170 KB |
457 | #else |
458 | static inline void pci_save_dpc_state(struct pci_dev *dev) {} | |
459 | static inline void pci_restore_dpc_state(struct pci_dev *dev) {} | |
27005618 | 460 | static inline void pci_dpc_init(struct pci_dev *pdev) {} |
4f802170 KB |
461 | #endif |
462 | ||
1900ca13 | 463 | #ifdef CONFIG_PCI_ATS |
b92b512a KS |
464 | /* Address Translation Service */ |
465 | void pci_ats_init(struct pci_dev *dev); | |
f39d5b72 | 466 | void pci_restore_ats_state(struct pci_dev *dev); |
1900ca13 | 467 | #else |
b92b512a KS |
468 | static inline void pci_ats_init(struct pci_dev *d) { } |
469 | static inline void pci_restore_ats_state(struct pci_dev *dev) { } | |
1900ca13 HX |
470 | #endif /* CONFIG_PCI_ATS */ |
471 | ||
c065190b KS |
472 | #ifdef CONFIG_PCI_PRI |
473 | void pci_pri_init(struct pci_dev *dev); | |
fef2dd8b | 474 | void pci_restore_pri_state(struct pci_dev *pdev); |
c065190b KS |
475 | #else |
476 | static inline void pci_pri_init(struct pci_dev *dev) { } | |
fef2dd8b | 477 | static inline void pci_restore_pri_state(struct pci_dev *pdev) { } |
c065190b KS |
478 | #endif |
479 | ||
751035b8 KS |
480 | #ifdef CONFIG_PCI_PASID |
481 | void pci_pasid_init(struct pci_dev *dev); | |
fef2dd8b | 482 | void pci_restore_pasid_state(struct pci_dev *pdev); |
751035b8 KS |
483 | #else |
484 | static inline void pci_pasid_init(struct pci_dev *dev) { } | |
fef2dd8b | 485 | static inline void pci_restore_pasid_state(struct pci_dev *pdev) { } |
751035b8 KS |
486 | #endif |
487 | ||
d1b054da | 488 | #ifdef CONFIG_PCI_IOV |
f39d5b72 BH |
489 | int pci_iov_init(struct pci_dev *dev); |
490 | void pci_iov_release(struct pci_dev *dev); | |
38972375 | 491 | void pci_iov_remove(struct pci_dev *dev); |
6ffa2489 | 492 | void pci_iov_update_resource(struct pci_dev *dev, int resno); |
f39d5b72 BH |
493 | resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno); |
494 | void pci_restore_iov_state(struct pci_dev *dev); | |
495 | int pci_iov_bus_range(struct pci_bus *bus); | |
aaee0c1f | 496 | extern const struct attribute_group sriov_dev_attr_group; |
d1b054da YZ |
497 | #else |
498 | static inline int pci_iov_init(struct pci_dev *dev) | |
499 | { | |
500 | return -ENODEV; | |
501 | } | |
502 | static inline void pci_iov_release(struct pci_dev *dev) | |
503 | ||
38972375 JK |
504 | { |
505 | } | |
506 | static inline void pci_iov_remove(struct pci_dev *dev) | |
d1b054da YZ |
507 | { |
508 | } | |
8c5cdb6a YZ |
509 | static inline void pci_restore_iov_state(struct pci_dev *dev) |
510 | { | |
511 | } | |
a28724b0 YZ |
512 | static inline int pci_iov_bus_range(struct pci_bus *bus) |
513 | { | |
514 | return 0; | |
515 | } | |
302b4215 | 516 | |
d1b054da YZ |
517 | #endif /* CONFIG_PCI_IOV */ |
518 | ||
f39d5b72 | 519 | unsigned long pci_cardbus_resource_alignment(struct resource *); |
0a2daa1c | 520 | |
0e52247a | 521 | static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, |
f39d5b72 | 522 | struct resource *res) |
6faf17f6 CW |
523 | { |
524 | #ifdef CONFIG_PCI_IOV | |
525 | int resno = res - dev->resource; | |
526 | ||
527 | if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END) | |
528 | return pci_sriov_resource_alignment(dev, resno); | |
529 | #endif | |
0aa0f5d1 | 530 | if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS) |
0a2daa1c | 531 | return pci_cardbus_resource_alignment(res); |
6faf17f6 CW |
532 | return resource_alignment(res); |
533 | } | |
534 | ||
52fbf5bd | 535 | void pci_acs_init(struct pci_dev *dev); |
bd2e9567 BH |
536 | #ifdef CONFIG_PCI_QUIRKS |
537 | int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); | |
538 | int pci_dev_specific_enable_acs(struct pci_dev *dev); | |
73c47dde | 539 | int pci_dev_specific_disable_acs_redir(struct pci_dev *dev); |
bd2e9567 BH |
540 | #else |
541 | static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, | |
542 | u16 acs_flags) | |
543 | { | |
544 | return -ENOTTY; | |
545 | } | |
546 | static inline int pci_dev_specific_enable_acs(struct pci_dev *dev) | |
547 | { | |
548 | return -ENOTTY; | |
549 | } | |
73c47dde LG |
550 | static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) |
551 | { | |
552 | return -ENOTTY; | |
553 | } | |
bd2e9567 | 554 | #endif |
ae21ee65 | 555 | |
2e28bc84 | 556 | /* PCI error reporting and recovery */ |
e8e5ff2a | 557 | pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, |
16d79cd4 | 558 | pci_channel_state_t state, |
e8e5ff2a | 559 | pci_ers_result_t (*reset_link)(struct pci_dev *pdev)); |
2e28bc84 | 560 | |
9f5a70f1 | 561 | bool pcie_wait_for_link(struct pci_dev *pdev, bool active); |
7d8e7d19 BH |
562 | #ifdef CONFIG_PCIEASPM |
563 | void pcie_aspm_init_link_state(struct pci_dev *pdev); | |
564 | void pcie_aspm_exit_link_state(struct pci_dev *pdev); | |
565 | void pcie_aspm_pm_state_change(struct pci_dev *pdev); | |
566 | void pcie_aspm_powersave_config_link(struct pci_dev *pdev); | |
567 | #else | |
568 | static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { } | |
569 | static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { } | |
570 | static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { } | |
571 | static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { } | |
572 | #endif | |
573 | ||
72bde9ce KS |
574 | #ifdef CONFIG_PCIE_ECRC |
575 | void pcie_set_ecrc_checking(struct pci_dev *dev); | |
576 | void pcie_ecrc_get_policy(char *str); | |
577 | #else | |
578 | static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } | |
579 | static inline void pcie_ecrc_get_policy(char *str) { } | |
580 | #endif | |
581 | ||
9bb04a0c JY |
582 | #ifdef CONFIG_PCIE_PTM |
583 | void pci_ptm_init(struct pci_dev *dev); | |
ac6c26da | 584 | int pci_enable_ptm(struct pci_dev *dev, u8 *granularity); |
9bb04a0c JY |
585 | #else |
586 | static inline void pci_ptm_init(struct pci_dev *dev) { } | |
ac6c26da KS |
587 | static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) |
588 | { return -EINVAL; } | |
9bb04a0c JY |
589 | #endif |
590 | ||
b9c3b266 DC |
591 | struct pci_dev_reset_methods { |
592 | u16 vendor; | |
593 | u16 device; | |
594 | int (*reset)(struct pci_dev *dev, int probe); | |
595 | }; | |
596 | ||
93177a74 | 597 | #ifdef CONFIG_PCI_QUIRKS |
f39d5b72 | 598 | int pci_dev_specific_reset(struct pci_dev *dev, int probe); |
93177a74 RW |
599 | #else |
600 | static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe) | |
601 | { | |
602 | return -ENOTTY; | |
603 | } | |
604 | #endif | |
b9c3b266 | 605 | |
169de969 DL |
606 | #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64) |
607 | int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment, | |
608 | struct resource *res); | |
609 | #endif | |
610 | ||
276b738d CK |
611 | u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar); |
612 | int pci_rebar_get_current_size(struct pci_dev *pdev, int bar); | |
613 | int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size); | |
614 | static inline u64 pci_rebar_size_to_bytes(int size) | |
615 | { | |
616 | return 1ULL << (size + 20); | |
617 | } | |
618 | ||
9e2aee80 RH |
619 | struct device_node; |
620 | ||
621 | #ifdef CONFIG_OF | |
622 | int of_pci_parse_bus_range(struct device_node *node, struct resource *res); | |
623 | int of_get_pci_domain_nr(struct device_node *node); | |
624 | int of_pci_get_max_link_speed(struct device_node *node); | |
621f7e35 KS |
625 | void pci_set_of_node(struct pci_dev *dev); |
626 | void pci_release_of_node(struct pci_dev *dev); | |
627 | void pci_set_bus_of_node(struct pci_bus *bus); | |
628 | void pci_release_bus_of_node(struct pci_bus *bus); | |
9e2aee80 | 629 | |
669cbc70 RH |
630 | int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge); |
631 | ||
9e2aee80 RH |
632 | #else |
633 | static inline int | |
634 | of_pci_parse_bus_range(struct device_node *node, struct resource *res) | |
635 | { | |
636 | return -EINVAL; | |
637 | } | |
638 | ||
639 | static inline int | |
640 | of_get_pci_domain_nr(struct device_node *node) | |
641 | { | |
642 | return -1; | |
643 | } | |
644 | ||
645 | static inline int | |
646 | of_pci_get_max_link_speed(struct device_node *node) | |
647 | { | |
648 | return -EINVAL; | |
649 | } | |
621f7e35 KS |
650 | |
651 | static inline void pci_set_of_node(struct pci_dev *dev) { } | |
652 | static inline void pci_release_of_node(struct pci_dev *dev) { } | |
653 | static inline void pci_set_bus_of_node(struct pci_bus *bus) { } | |
654 | static inline void pci_release_bus_of_node(struct pci_bus *bus) { } | |
669cbc70 RH |
655 | |
656 | static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge) | |
657 | { | |
658 | return 0; | |
659 | } | |
660 | ||
9e2aee80 RH |
661 | #endif /* CONFIG_OF */ |
662 | ||
60ed982a RJ |
663 | #ifdef CONFIG_PCIEAER |
664 | void pci_no_aer(void); | |
665 | void pci_aer_init(struct pci_dev *dev); | |
db89ccbe | 666 | void pci_aer_exit(struct pci_dev *dev); |
81aa5206 | 667 | extern const struct attribute_group aer_stats_attr_group; |
7ab92e89 | 668 | void pci_aer_clear_fatal_status(struct pci_dev *dev); |
894020fd | 669 | int pci_aer_clear_status(struct pci_dev *dev); |
20e15e67 | 670 | int pci_aer_raw_clear_status(struct pci_dev *dev); |
60ed982a RJ |
671 | #else |
672 | static inline void pci_no_aer(void) { } | |
31f996ef | 673 | static inline void pci_aer_init(struct pci_dev *d) { } |
db89ccbe | 674 | static inline void pci_aer_exit(struct pci_dev *d) { } |
7ab92e89 | 675 | static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } |
894020fd | 676 | static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; } |
20e15e67 | 677 | static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; } |
60ed982a RJ |
678 | #endif |
679 | ||
8c3aac6e | 680 | #ifdef CONFIG_ACPI |
4a2dbedd | 681 | int pci_acpi_program_hp_params(struct pci_dev *dev); |
8c3aac6e | 682 | #else |
4a2dbedd | 683 | static inline int pci_acpi_program_hp_params(struct pci_dev *dev) |
8c3aac6e KW |
684 | { |
685 | return -ENODEV; | |
686 | } | |
687 | #endif | |
688 | ||
72ea91af HK |
689 | #ifdef CONFIG_PCIEASPM |
690 | extern const struct attribute_group aspm_ctrl_attr_group; | |
691 | #endif | |
692 | ||
557848c3 | 693 | #endif /* DRIVERS_PCI_H */ |