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557848c3 ZY |
1 | #ifndef DRIVERS_PCI_H |
2 | #define DRIVERS_PCI_H | |
3 | ||
4 | #define PCI_CFG_SPACE_SIZE 256 | |
5 | #define PCI_CFG_SPACE_EXP_SIZE 4096 | |
6 | ||
1da177e4 LT |
7 | /* Functions internal to the PCI core code */ |
8 | ||
7eff2e7a | 9 | extern int pci_uevent(struct device *dev, struct kobj_uevent_env *env); |
1da177e4 LT |
10 | extern int pci_create_sysfs_dev_files(struct pci_dev *pdev); |
11 | extern void pci_remove_sysfs_dev_files(struct pci_dev *pdev); | |
12 | extern void pci_cleanup_rom(struct pci_dev *dev); | |
9eff02e2 JB |
13 | #ifdef HAVE_PCI_MMAP |
14 | extern int pci_mmap_fits(struct pci_dev *pdev, int resno, | |
15 | struct vm_area_struct *vma); | |
16 | #endif | |
ce5ccdef | 17 | |
961d9120 | 18 | /** |
b33bfdef | 19 | * struct pci_platform_pm_ops - Firmware PM callbacks |
961d9120 | 20 | * |
b33bfdef RD |
21 | * @is_manageable: returns 'true' if given device is power manageable by the |
22 | * platform firmware | |
961d9120 | 23 | * |
b33bfdef | 24 | * @set_state: invokes the platform firmware to set the device's power state |
961d9120 | 25 | * |
b33bfdef RD |
26 | * @choose_state: returns PCI power state of given device preferred by the |
27 | * platform; to be used during system-wide transitions from a | |
28 | * sleeping state to the working state and vice versa | |
961d9120 | 29 | * |
b33bfdef RD |
30 | * @can_wakeup: returns 'true' if given device is capable of waking up the |
31 | * system from a sleeping state | |
eb9d0fe4 | 32 | * |
b33bfdef | 33 | * @sleep_wake: enables/disables the system wake up capability of given device |
eb9d0fe4 | 34 | * |
961d9120 RW |
35 | * If given platform is generally capable of power managing PCI devices, all of |
36 | * these callbacks are mandatory. | |
37 | */ | |
38 | struct pci_platform_pm_ops { | |
39 | bool (*is_manageable)(struct pci_dev *dev); | |
40 | int (*set_state)(struct pci_dev *dev, pci_power_t state); | |
41 | pci_power_t (*choose_state)(struct pci_dev *dev); | |
eb9d0fe4 RW |
42 | bool (*can_wakeup)(struct pci_dev *dev); |
43 | int (*sleep_wake)(struct pci_dev *dev, bool enable); | |
961d9120 RW |
44 | }; |
45 | ||
46 | extern int pci_set_platform_pm(struct pci_platform_pm_ops *ops); | |
73410429 | 47 | extern void pci_update_current_state(struct pci_dev *dev, pci_power_t state); |
fa58d305 | 48 | extern void pci_disable_enabled_device(struct pci_dev *dev); |
eb9d0fe4 | 49 | extern void pci_pm_init(struct pci_dev *dev); |
eb9c39d0 | 50 | extern void platform_pci_wakeup_init(struct pci_dev *dev); |
63f4898a | 51 | extern void pci_allocate_cap_save_buffers(struct pci_dev *dev); |
aa8c6c93 RW |
52 | extern int pci_restore_standard_config(struct pci_dev *dev); |
53 | ||
54 | static inline bool pci_is_bridge(struct pci_dev *pci_dev) | |
55 | { | |
56 | return !!(pci_dev->subordinate); | |
57 | } | |
0f64474b | 58 | |
e04b0ea2 BK |
59 | extern int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); |
60 | extern int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); | |
61 | extern int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); | |
62 | extern int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); | |
63 | extern int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); | |
64 | extern int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); | |
65 | ||
94e61088 | 66 | struct pci_vpd_ops { |
287d19ce SH |
67 | ssize_t (*read)(struct pci_dev *dev, loff_t pos, size_t count, void *buf); |
68 | ssize_t (*write)(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); | |
94e61088 BH |
69 | void (*release)(struct pci_dev *dev); |
70 | }; | |
71 | ||
72 | struct pci_vpd { | |
99cb233d | 73 | unsigned int len; |
287d19ce | 74 | const struct pci_vpd_ops *ops; |
94e61088 BH |
75 | struct bin_attribute *attr; /* descriptor for sysfs VPD entry */ |
76 | }; | |
77 | ||
78 | extern int pci_vpd_pci22_init(struct pci_dev *dev); | |
79 | static inline void pci_vpd_release(struct pci_dev *dev) | |
80 | { | |
81 | if (dev->vpd) | |
82 | dev->vpd->ops->release(dev); | |
83 | } | |
84 | ||
1da177e4 LT |
85 | /* PCI /proc functions */ |
86 | #ifdef CONFIG_PROC_FS | |
87 | extern int pci_proc_attach_device(struct pci_dev *dev); | |
88 | extern int pci_proc_detach_device(struct pci_dev *dev); | |
1da177e4 LT |
89 | extern int pci_proc_detach_bus(struct pci_bus *bus); |
90 | #else | |
91 | static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; } | |
92 | static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; } | |
1da177e4 LT |
93 | static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; } |
94 | #endif | |
95 | ||
96 | /* Functions for PCI Hotplug drivers to use */ | |
1da177e4 | 97 | extern unsigned int pci_do_scan_bus(struct pci_bus *bus); |
1da177e4 | 98 | |
f19aeb1f BH |
99 | #ifdef HAVE_PCI_LEGACY |
100 | extern void pci_create_legacy_files(struct pci_bus *bus); | |
1da177e4 | 101 | extern void pci_remove_legacy_files(struct pci_bus *bus); |
f19aeb1f BH |
102 | #else |
103 | static inline void pci_create_legacy_files(struct pci_bus *bus) { return; } | |
104 | static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; } | |
105 | #endif | |
1da177e4 LT |
106 | |
107 | /* Lock for read/write access to pci device and bus lists */ | |
d71374da | 108 | extern struct rw_semaphore pci_bus_sem; |
1da177e4 | 109 | |
ffadcc2f | 110 | extern unsigned int pci_pm_d3_delay; |
88187dfa | 111 | |
4b47b0ee | 112 | #ifdef CONFIG_PCI_MSI |
309e57df | 113 | void pci_no_msi(void); |
4aa9bc95 | 114 | extern void pci_msi_init_pci_dev(struct pci_dev *dev); |
4b47b0ee | 115 | #else |
309e57df | 116 | static inline void pci_no_msi(void) { } |
4aa9bc95 | 117 | static inline void pci_msi_init_pci_dev(struct pci_dev *dev) { } |
4b47b0ee | 118 | #endif |
8fed4b65 | 119 | |
7f785763 RD |
120 | #ifdef CONFIG_PCIEAER |
121 | void pci_no_aer(void); | |
122 | #else | |
123 | static inline void pci_no_aer(void) { } | |
124 | #endif | |
125 | ||
ffadcc2f KCA |
126 | static inline int pci_no_d1d2(struct pci_dev *dev) |
127 | { | |
128 | unsigned int parent_dstates = 0; | |
4b47b0ee | 129 | |
ffadcc2f KCA |
130 | if (dev->bus->self) |
131 | parent_dstates = dev->bus->self->no_d1d2; | |
132 | return (dev->no_d1d2 || parent_dstates); | |
133 | ||
134 | } | |
1da177e4 LT |
135 | extern int pcie_mch_quirk; |
136 | extern struct device_attribute pci_dev_attrs[]; | |
fd7d1ced | 137 | extern struct device_attribute dev_attr_cpuaffinity; |
93ff68a5 | 138 | extern struct device_attribute dev_attr_cpulistaffinity; |
1da177e4 LT |
139 | |
140 | /** | |
141 | * pci_match_one_device - Tell if a PCI device structure has a matching | |
142 | * PCI device id structure | |
143 | * @id: single PCI device id structure to match | |
144 | * @dev: the PCI device structure to match against | |
367b09fe | 145 | * |
1da177e4 LT |
146 | * Returns the matching pci_device_id structure or %NULL if there is no match. |
147 | */ | |
148 | static inline const struct pci_device_id * | |
149 | pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev) | |
150 | { | |
151 | if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) && | |
152 | (id->device == PCI_ANY_ID || id->device == dev->device) && | |
153 | (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) && | |
154 | (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) && | |
155 | !((id->class ^ dev->class) & id->class_mask)) | |
156 | return id; | |
157 | return NULL; | |
158 | } | |
159 | ||
994a65e2 | 160 | struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev); |
f46753c5 AC |
161 | |
162 | /* PCI slot sysfs helper code */ | |
163 | #define to_pci_slot(s) container_of(s, struct pci_slot, kobj) | |
164 | ||
165 | extern struct kset *pci_slots_kset; | |
166 | ||
167 | struct pci_slot_attribute { | |
168 | struct attribute attr; | |
169 | ssize_t (*show)(struct pci_slot *, char *); | |
170 | ssize_t (*store)(struct pci_slot *, const char *, size_t); | |
171 | }; | |
172 | #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr) | |
173 | ||
0b400c7e YZ |
174 | enum pci_bar_type { |
175 | pci_bar_unknown, /* Standard PCI BAR probe */ | |
176 | pci_bar_io, /* An io port BAR */ | |
177 | pci_bar_mem32, /* A 32-bit memory BAR */ | |
178 | pci_bar_mem64, /* A 64-bit memory BAR */ | |
179 | }; | |
180 | ||
181 | extern int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, | |
182 | struct resource *res, unsigned int reg); | |
613e7ed6 YZ |
183 | extern int pci_resource_bar(struct pci_dev *dev, int resno, |
184 | enum pci_bar_type *type); | |
876e501a | 185 | extern int pci_bus_add_child(struct pci_bus *bus); |
58c3a727 YZ |
186 | extern void pci_enable_ari(struct pci_dev *dev); |
187 | /** | |
188 | * pci_ari_enabled - query ARI forwarding status | |
6a49d812 | 189 | * @bus: the PCI bus |
58c3a727 YZ |
190 | * |
191 | * Returns 1 if ARI forwarding is enabled, or 0 if not enabled; | |
192 | */ | |
6a49d812 | 193 | static inline int pci_ari_enabled(struct pci_bus *bus) |
58c3a727 | 194 | { |
6a49d812 | 195 | return bus->self && bus->self->ari_enabled; |
58c3a727 YZ |
196 | } |
197 | ||
32a9a682 YS |
198 | #ifdef CONFIG_PCI_QUIRKS |
199 | extern int pci_is_reassigndev(struct pci_dev *dev); | |
200 | resource_size_t pci_specified_resource_alignment(struct pci_dev *dev); | |
201 | extern void pci_disable_bridge_window(struct pci_dev *dev); | |
202 | #endif | |
203 | ||
d1b054da YZ |
204 | /* Single Root I/O Virtualization */ |
205 | struct pci_sriov { | |
206 | int pos; /* capability position */ | |
207 | int nres; /* number of resources */ | |
208 | u32 cap; /* SR-IOV Capabilities */ | |
209 | u16 ctrl; /* SR-IOV Control */ | |
210 | u16 total; /* total VFs associated with the PF */ | |
211 | u16 offset; /* first VF Routing ID offset */ | |
212 | u16 stride; /* following VF stride */ | |
213 | u32 pgsz; /* page size for BAR alignment */ | |
214 | u8 link; /* Function Dependency Link */ | |
215 | struct pci_dev *dev; /* lowest numbered PF */ | |
216 | struct pci_dev *self; /* this PF */ | |
217 | struct mutex lock; /* lock for VF bus */ | |
218 | }; | |
219 | ||
220 | #ifdef CONFIG_PCI_IOV | |
221 | extern int pci_iov_init(struct pci_dev *dev); | |
222 | extern void pci_iov_release(struct pci_dev *dev); | |
223 | extern int pci_iov_resource_bar(struct pci_dev *dev, int resno, | |
224 | enum pci_bar_type *type); | |
225 | #else | |
226 | static inline int pci_iov_init(struct pci_dev *dev) | |
227 | { | |
228 | return -ENODEV; | |
229 | } | |
230 | static inline void pci_iov_release(struct pci_dev *dev) | |
231 | ||
232 | { | |
233 | } | |
234 | static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno, | |
235 | enum pci_bar_type *type) | |
236 | { | |
237 | return 0; | |
238 | } | |
239 | #endif /* CONFIG_PCI_IOV */ | |
240 | ||
557848c3 | 241 | #endif /* DRIVERS_PCI_H */ |