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Commit | Line | Data |
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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
557848c3 ZY |
2 | #ifndef DRIVERS_PCI_H |
3 | #define DRIVERS_PCI_H | |
4 | ||
2209e06f AG |
5 | #include <linux/pci.h> |
6 | ||
fff905f3 WY |
7 | #define PCI_FIND_CAP_TTL 48 |
8 | ||
8531e283 LW |
9 | #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */ |
10 | ||
343e51ae | 11 | extern const unsigned char pcie_link_speed[]; |
11eb0e0e | 12 | extern bool pci_early_dump; |
343e51ae | 13 | |
7a1562d4 YL |
14 | bool pcie_cap_has_lnkctl(const struct pci_dev *dev); |
15 | ||
1da177e4 LT |
16 | /* Functions internal to the PCI core code */ |
17 | ||
f39d5b72 BH |
18 | int pci_create_sysfs_dev_files(struct pci_dev *pdev); |
19 | void pci_remove_sysfs_dev_files(struct pci_dev *pdev); | |
6058989b | 20 | #if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI) |
911e1c9b | 21 | static inline void pci_create_firmware_label_files(struct pci_dev *pdev) |
b879743f | 22 | { return; } |
911e1c9b | 23 | static inline void pci_remove_firmware_label_files(struct pci_dev *pdev) |
b879743f | 24 | { return; } |
911e1c9b | 25 | #else |
f39d5b72 BH |
26 | void pci_create_firmware_label_files(struct pci_dev *pdev); |
27 | void pci_remove_firmware_label_files(struct pci_dev *pdev); | |
911e1c9b | 28 | #endif |
f39d5b72 | 29 | void pci_cleanup_rom(struct pci_dev *dev); |
f7195824 | 30 | |
3b519e4e MW |
31 | enum pci_mmap_api { |
32 | PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */ | |
33 | PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */ | |
34 | }; | |
f39d5b72 BH |
35 | int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai, |
36 | enum pci_mmap_api mmap_api); | |
f7195824 | 37 | |
711d5779 | 38 | int pci_probe_reset_function(struct pci_dev *dev); |
381634ca | 39 | int pci_bridge_secondary_bus_reset(struct pci_dev *dev); |
c4eed62a | 40 | int pci_bus_error_reset(struct pci_dev *dev); |
ce5ccdef | 41 | |
961d9120 | 42 | /** |
b33bfdef | 43 | * struct pci_platform_pm_ops - Firmware PM callbacks |
961d9120 | 44 | * |
26ad34d5 MW |
45 | * @bridge_d3: Does the bridge allow entering into D3 |
46 | * | |
b33bfdef | 47 | * @is_manageable: returns 'true' if given device is power manageable by the |
0aa0f5d1 | 48 | * platform firmware |
961d9120 | 49 | * |
b33bfdef | 50 | * @set_state: invokes the platform firmware to set the device's power state |
961d9120 | 51 | * |
cc7cc02b LW |
52 | * @get_state: queries the platform firmware for a device's current power state |
53 | * | |
b51033e0 RW |
54 | * @refresh_state: asks the platform to refresh the device's power state data |
55 | * | |
b33bfdef | 56 | * @choose_state: returns PCI power state of given device preferred by the |
0aa0f5d1 BH |
57 | * platform; to be used during system-wide transitions from a |
58 | * sleeping state to the working state and vice versa | |
961d9120 | 59 | * |
0847684c | 60 | * @set_wakeup: enables/disables wakeup capability for the device |
b67ea761 | 61 | * |
bac2a909 | 62 | * @need_resume: returns 'true' if the given device (which is currently |
0aa0f5d1 BH |
63 | * suspended) needs to be resumed to be configured for system |
64 | * wakeup. | |
bac2a909 | 65 | * |
961d9120 RW |
66 | * If given platform is generally capable of power managing PCI devices, all of |
67 | * these callbacks are mandatory. | |
68 | */ | |
69 | struct pci_platform_pm_ops { | |
26ad34d5 | 70 | bool (*bridge_d3)(struct pci_dev *dev); |
961d9120 RW |
71 | bool (*is_manageable)(struct pci_dev *dev); |
72 | int (*set_state)(struct pci_dev *dev, pci_power_t state); | |
cc7cc02b | 73 | pci_power_t (*get_state)(struct pci_dev *dev); |
b51033e0 | 74 | void (*refresh_state)(struct pci_dev *dev); |
961d9120 | 75 | pci_power_t (*choose_state)(struct pci_dev *dev); |
0847684c | 76 | int (*set_wakeup)(struct pci_dev *dev, bool enable); |
bac2a909 | 77 | bool (*need_resume)(struct pci_dev *dev); |
961d9120 RW |
78 | }; |
79 | ||
299f2ffe | 80 | int pci_set_platform_pm(const struct pci_platform_pm_ops *ops); |
f39d5b72 | 81 | void pci_update_current_state(struct pci_dev *dev, pci_power_t state); |
b51033e0 | 82 | void pci_refresh_power_state(struct pci_dev *dev); |
f39d5b72 BH |
83 | void pci_power_up(struct pci_dev *dev); |
84 | void pci_disable_enabled_device(struct pci_dev *dev); | |
85 | int pci_finish_runtime_suspend(struct pci_dev *dev); | |
dcb0453d | 86 | void pcie_clear_root_pme_status(struct pci_dev *dev); |
f39d5b72 | 87 | int __pci_pme_wakeup(struct pci_dev *dev, void *ign); |
0ce3fcaf | 88 | void pci_pme_restore(struct pci_dev *dev); |
0c7376ad RW |
89 | bool pci_dev_need_resume(struct pci_dev *dev); |
90 | void pci_dev_adjust_pme(struct pci_dev *dev); | |
2cef548a | 91 | void pci_dev_complete_resume(struct pci_dev *pci_dev); |
f39d5b72 BH |
92 | void pci_config_pm_runtime_get(struct pci_dev *dev); |
93 | void pci_config_pm_runtime_put(struct pci_dev *dev); | |
94 | void pci_pm_init(struct pci_dev *dev); | |
938174e5 | 95 | void pci_ea_init(struct pci_dev *dev); |
f39d5b72 | 96 | void pci_allocate_cap_save_buffers(struct pci_dev *dev); |
f796841e | 97 | void pci_free_cap_save_buffers(struct pci_dev *dev); |
c6a63307 | 98 | bool pci_bridge_d3_possible(struct pci_dev *dev); |
1ed276a7 | 99 | void pci_bridge_d3_update(struct pci_dev *dev); |
aa8c6c93 | 100 | |
b6e335ae RW |
101 | static inline void pci_wakeup_event(struct pci_dev *dev) |
102 | { | |
103 | /* Wait 100 ms before the system can be put into a sleep state. */ | |
104 | pm_wakeup_event(&dev->dev, 100); | |
105 | } | |
106 | ||
326c1cda | 107 | static inline bool pci_has_subordinate(struct pci_dev *pci_dev) |
aa8c6c93 RW |
108 | { |
109 | return !!(pci_dev->subordinate); | |
110 | } | |
0f64474b | 111 | |
9d26d3a8 MW |
112 | static inline bool pci_power_manageable(struct pci_dev *pci_dev) |
113 | { | |
114 | /* | |
115 | * Currently we allow normal PCI devices and PCI bridges transition | |
116 | * into D3 if their bridge_d3 is set. | |
117 | */ | |
118 | return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3; | |
119 | } | |
120 | ||
f1cd93f9 | 121 | int pci_vpd_init(struct pci_dev *dev); |
64379079 | 122 | void pci_vpd_release(struct pci_dev *dev); |
b1c615c4 BH |
123 | void pcie_vpd_create_sysfs_dev_files(struct pci_dev *dev); |
124 | void pcie_vpd_remove_sysfs_dev_files(struct pci_dev *dev); | |
94e61088 | 125 | |
1da177e4 LT |
126 | /* PCI /proc functions */ |
127 | #ifdef CONFIG_PROC_FS | |
f39d5b72 BH |
128 | int pci_proc_attach_device(struct pci_dev *dev); |
129 | int pci_proc_detach_device(struct pci_dev *dev); | |
130 | int pci_proc_detach_bus(struct pci_bus *bus); | |
1da177e4 LT |
131 | #else |
132 | static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; } | |
133 | static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; } | |
1da177e4 LT |
134 | static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; } |
135 | #endif | |
136 | ||
137 | /* Functions for PCI Hotplug drivers to use */ | |
a8e4b9c1 | 138 | int pci_hp_add_bridge(struct pci_dev *dev); |
1da177e4 | 139 | |
f19aeb1f | 140 | #ifdef HAVE_PCI_LEGACY |
f39d5b72 BH |
141 | void pci_create_legacy_files(struct pci_bus *bus); |
142 | void pci_remove_legacy_files(struct pci_bus *bus); | |
f19aeb1f BH |
143 | #else |
144 | static inline void pci_create_legacy_files(struct pci_bus *bus) { return; } | |
145 | static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; } | |
146 | #endif | |
1da177e4 LT |
147 | |
148 | /* Lock for read/write access to pci device and bus lists */ | |
d71374da | 149 | extern struct rw_semaphore pci_bus_sem; |
c4eed62a | 150 | extern struct mutex pci_slot_mutex; |
1da177e4 | 151 | |
a2e27787 JK |
152 | extern raw_spinlock_t pci_lock; |
153 | ||
ffadcc2f | 154 | extern unsigned int pci_pm_d3_delay; |
88187dfa | 155 | |
4b47b0ee | 156 | #ifdef CONFIG_PCI_MSI |
309e57df | 157 | void pci_no_msi(void); |
4b47b0ee | 158 | #else |
309e57df | 159 | static inline void pci_no_msi(void) { } |
4b47b0ee | 160 | #endif |
8fed4b65 | 161 | |
6a25f5e3 MT |
162 | static inline void pci_msi_set_enable(struct pci_dev *dev, int enable) |
163 | { | |
164 | u16 control; | |
165 | ||
166 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); | |
167 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
168 | if (enable) | |
169 | control |= PCI_MSI_FLAGS_ENABLE; | |
170 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); | |
171 | } | |
172 | ||
173 | static inline void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set) | |
174 | { | |
175 | u16 ctrl; | |
176 | ||
177 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl); | |
178 | ctrl &= ~clear; | |
179 | ctrl |= set; | |
180 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl); | |
181 | } | |
182 | ||
b55438fd | 183 | void pci_realloc_get_opt(char *); |
f483d392 | 184 | |
ffadcc2f KCA |
185 | static inline int pci_no_d1d2(struct pci_dev *dev) |
186 | { | |
187 | unsigned int parent_dstates = 0; | |
4b47b0ee | 188 | |
ffadcc2f KCA |
189 | if (dev->bus->self) |
190 | parent_dstates = dev->bus->self->no_d1d2; | |
191 | return (dev->no_d1d2 || parent_dstates); | |
192 | ||
193 | } | |
5136b2da | 194 | extern const struct attribute_group *pci_dev_groups[]; |
56039e65 | 195 | extern const struct attribute_group *pcibus_groups[]; |
69f2dc24 | 196 | extern const struct device_type pci_dev_type; |
0f49ba55 | 197 | extern const struct attribute_group *pci_bus_groups[]; |
705b1aaa | 198 | |
1da177e4 LT |
199 | |
200 | /** | |
201 | * pci_match_one_device - Tell if a PCI device structure has a matching | |
0aa0f5d1 | 202 | * PCI device id structure |
1da177e4 LT |
203 | * @id: single PCI device id structure to match |
204 | * @dev: the PCI device structure to match against | |
367b09fe | 205 | * |
1da177e4 LT |
206 | * Returns the matching pci_device_id structure or %NULL if there is no match. |
207 | */ | |
208 | static inline const struct pci_device_id * | |
209 | pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev) | |
210 | { | |
211 | if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) && | |
212 | (id->device == PCI_ANY_ID || id->device == dev->device) && | |
213 | (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) && | |
214 | (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) && | |
215 | !((id->class ^ dev->class) & id->class_mask)) | |
216 | return id; | |
217 | return NULL; | |
218 | } | |
219 | ||
f46753c5 AC |
220 | /* PCI slot sysfs helper code */ |
221 | #define to_pci_slot(s) container_of(s, struct pci_slot, kobj) | |
222 | ||
223 | extern struct kset *pci_slots_kset; | |
224 | ||
225 | struct pci_slot_attribute { | |
226 | struct attribute attr; | |
227 | ssize_t (*show)(struct pci_slot *, char *); | |
228 | ssize_t (*store)(struct pci_slot *, const char *, size_t); | |
229 | }; | |
230 | #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr) | |
231 | ||
0b400c7e YZ |
232 | enum pci_bar_type { |
233 | pci_bar_unknown, /* Standard PCI BAR probe */ | |
0aa0f5d1 | 234 | pci_bar_io, /* An I/O port BAR */ |
0b400c7e YZ |
235 | pci_bar_mem32, /* A 32-bit memory BAR */ |
236 | pci_bar_mem64, /* A 64-bit memory BAR */ | |
237 | }; | |
238 | ||
62ce94a7 | 239 | int pci_configure_extended_tags(struct pci_dev *dev, void *ign); |
efdc87da YL |
240 | bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, |
241 | int crs_timeout); | |
aa667c64 JP |
242 | bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, |
243 | int crs_timeout); | |
244 | int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout); | |
245 | ||
f39d5b72 BH |
246 | int pci_setup_device(struct pci_dev *dev); |
247 | int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, | |
248 | struct resource *res, unsigned int reg); | |
f39d5b72 | 249 | void pci_configure_ari(struct pci_dev *dev); |
10874f5a | 250 | void __pci_bus_size_bridges(struct pci_bus *bus, |
d66ecb72 | 251 | struct list_head *realloc_head); |
10874f5a BH |
252 | void __pci_bus_assign_resources(const struct pci_bus *bus, |
253 | struct list_head *realloc_head, | |
254 | struct list_head *fail_head); | |
0f7e7aee | 255 | bool pci_bus_clip_resource(struct pci_dev *dev, int idx); |
939de1d6 | 256 | |
2069ecfb | 257 | void pci_reassigndev_resource_alignment(struct pci_dev *dev); |
f39d5b72 | 258 | void pci_disable_bridge_window(struct pci_dev *dev); |
32a9a682 | 259 | |
6cf57be0 TG |
260 | /* PCIe link information */ |
261 | #define PCIE_SPEED2STR(speed) \ | |
262 | ((speed) == PCIE_SPEED_16_0GT ? "16 GT/s" : \ | |
263 | (speed) == PCIE_SPEED_8_0GT ? "8 GT/s" : \ | |
264 | (speed) == PCIE_SPEED_5_0GT ? "5 GT/s" : \ | |
265 | (speed) == PCIE_SPEED_2_5GT ? "2.5 GT/s" : \ | |
266 | "Unknown speed") | |
267 | ||
b852f63a TG |
268 | /* PCIe speed to Mb/s reduced by encoding overhead */ |
269 | #define PCIE_SPEED2MBS_ENC(speed) \ | |
270 | ((speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \ | |
271 | (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \ | |
272 | (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \ | |
273 | (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \ | |
274 | 0) | |
275 | ||
6cf57be0 | 276 | enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); |
c70b65fb | 277 | enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); |
b852f63a TG |
278 | u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed, |
279 | enum pcie_link_width *width); | |
2d1ce5ec | 280 | void __pcie_print_link_status(struct pci_dev *dev, bool verbose); |
0fa635ae | 281 | void pcie_report_downtraining(struct pci_dev *dev); |
6cf57be0 | 282 | |
d1b054da YZ |
283 | /* Single Root I/O Virtualization */ |
284 | struct pci_sriov { | |
0aa0f5d1 BH |
285 | int pos; /* Capability position */ |
286 | int nres; /* Number of resources */ | |
287 | u32 cap; /* SR-IOV Capabilities */ | |
288 | u16 ctrl; /* SR-IOV Control */ | |
289 | u16 total_VFs; /* Total VFs associated with the PF */ | |
290 | u16 initial_VFs; /* Initial VFs associated with the PF */ | |
291 | u16 num_VFs; /* Number of VFs available */ | |
292 | u16 offset; /* First VF Routing ID offset */ | |
293 | u16 stride; /* Following VF stride */ | |
294 | u16 vf_device; /* VF device ID */ | |
295 | u32 pgsz; /* Page size for BAR alignment */ | |
296 | u8 link; /* Function Dependency Link */ | |
297 | u8 max_VF_buses; /* Max buses consumed by VFs */ | |
298 | u16 driver_max_VFs; /* Max num VFs driver supports */ | |
299 | struct pci_dev *dev; /* Lowest numbered PF */ | |
300 | struct pci_dev *self; /* This PF */ | |
cf0921be KA |
301 | u32 class; /* VF device */ |
302 | u8 hdr_type; /* VF header type */ | |
303 | u16 subsystem_vendor; /* VF subsystem vendor */ | |
304 | u16 subsystem_device; /* VF subsystem device */ | |
0aa0f5d1 BH |
305 | resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */ |
306 | bool drivers_autoprobe; /* Auto probing of VFs by driver */ | |
d1b054da YZ |
307 | }; |
308 | ||
a6bd101b KB |
309 | /** |
310 | * pci_dev_set_io_state - Set the new error state if possible. | |
311 | * | |
312 | * @dev - pci device to set new error_state | |
313 | * @new - the state we want dev to be in | |
314 | * | |
315 | * Must be called with device_lock held. | |
316 | * | |
317 | * Returns true if state has been changed to the requested state. | |
318 | */ | |
319 | static inline bool pci_dev_set_io_state(struct pci_dev *dev, | |
320 | pci_channel_state_t new) | |
321 | { | |
322 | bool changed = false; | |
323 | ||
324 | device_lock_assert(&dev->dev); | |
325 | switch (new) { | |
326 | case pci_channel_io_perm_failure: | |
327 | switch (dev->error_state) { | |
328 | case pci_channel_io_frozen: | |
329 | case pci_channel_io_normal: | |
330 | case pci_channel_io_perm_failure: | |
331 | changed = true; | |
332 | break; | |
333 | } | |
334 | break; | |
335 | case pci_channel_io_frozen: | |
336 | switch (dev->error_state) { | |
337 | case pci_channel_io_frozen: | |
338 | case pci_channel_io_normal: | |
339 | changed = true; | |
340 | break; | |
341 | } | |
342 | break; | |
343 | case pci_channel_io_normal: | |
344 | switch (dev->error_state) { | |
345 | case pci_channel_io_frozen: | |
346 | case pci_channel_io_normal: | |
347 | changed = true; | |
348 | break; | |
349 | } | |
350 | break; | |
351 | } | |
352 | if (changed) | |
353 | dev->error_state = new; | |
354 | return changed; | |
355 | } | |
89ee9f76 KB |
356 | |
357 | static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused) | |
358 | { | |
a6bd101b KB |
359 | device_lock(&dev->dev); |
360 | pci_dev_set_io_state(dev, pci_channel_io_perm_failure); | |
361 | device_unlock(&dev->dev); | |
362 | ||
89ee9f76 KB |
363 | return 0; |
364 | } | |
365 | ||
366 | static inline bool pci_dev_is_disconnected(const struct pci_dev *dev) | |
367 | { | |
a6bd101b | 368 | return dev->error_state == pci_channel_io_perm_failure; |
89ee9f76 KB |
369 | } |
370 | ||
a6bd101b KB |
371 | /* pci_dev priv_flags */ |
372 | #define PCI_DEV_ADDED 0 | |
373 | ||
44bda4b7 HV |
374 | static inline void pci_dev_assign_added(struct pci_dev *dev, bool added) |
375 | { | |
376 | assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added); | |
377 | } | |
378 | ||
379 | static inline bool pci_dev_is_added(const struct pci_dev *dev) | |
380 | { | |
381 | return test_bit(PCI_DEV_ADDED, &dev->priv_flags); | |
382 | } | |
383 | ||
1e451160 KB |
384 | #ifdef CONFIG_PCIEAER |
385 | #include <linux/aer.h> | |
386 | ||
387 | #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */ | |
388 | ||
389 | struct aer_err_info { | |
390 | struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES]; | |
391 | int error_dev_num; | |
392 | ||
393 | unsigned int id:16; | |
394 | ||
395 | unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */ | |
396 | unsigned int __pad1:5; | |
397 | unsigned int multi_error_valid:1; | |
398 | ||
399 | unsigned int first_error:5; | |
400 | unsigned int __pad2:2; | |
401 | unsigned int tlp_header_valid:1; | |
402 | ||
403 | unsigned int status; /* COR/UNCOR Error Status */ | |
404 | unsigned int mask; /* COR/UNCOR Error Mask */ | |
405 | struct aer_header_log_regs tlp; /* TLP Header */ | |
406 | }; | |
407 | ||
408 | int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info); | |
409 | void aer_print_error(struct pci_dev *dev, struct aer_err_info *info); | |
410 | #endif /* CONFIG_PCIEAER */ | |
411 | ||
4f802170 KB |
412 | #ifdef CONFIG_PCIE_DPC |
413 | void pci_save_dpc_state(struct pci_dev *dev); | |
414 | void pci_restore_dpc_state(struct pci_dev *dev); | |
415 | #else | |
416 | static inline void pci_save_dpc_state(struct pci_dev *dev) {} | |
417 | static inline void pci_restore_dpc_state(struct pci_dev *dev) {} | |
418 | #endif | |
419 | ||
1900ca13 | 420 | #ifdef CONFIG_PCI_ATS |
f39d5b72 | 421 | void pci_restore_ats_state(struct pci_dev *dev); |
1900ca13 HX |
422 | #else |
423 | static inline void pci_restore_ats_state(struct pci_dev *dev) | |
424 | { | |
425 | } | |
426 | #endif /* CONFIG_PCI_ATS */ | |
427 | ||
d1b054da | 428 | #ifdef CONFIG_PCI_IOV |
f39d5b72 BH |
429 | int pci_iov_init(struct pci_dev *dev); |
430 | void pci_iov_release(struct pci_dev *dev); | |
38972375 | 431 | void pci_iov_remove(struct pci_dev *dev); |
6ffa2489 | 432 | void pci_iov_update_resource(struct pci_dev *dev, int resno); |
f39d5b72 BH |
433 | resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno); |
434 | void pci_restore_iov_state(struct pci_dev *dev); | |
435 | int pci_iov_bus_range(struct pci_bus *bus); | |
302b4215 | 436 | |
d1b054da YZ |
437 | #else |
438 | static inline int pci_iov_init(struct pci_dev *dev) | |
439 | { | |
440 | return -ENODEV; | |
441 | } | |
442 | static inline void pci_iov_release(struct pci_dev *dev) | |
443 | ||
38972375 JK |
444 | { |
445 | } | |
446 | static inline void pci_iov_remove(struct pci_dev *dev) | |
d1b054da YZ |
447 | { |
448 | } | |
8c5cdb6a YZ |
449 | static inline void pci_restore_iov_state(struct pci_dev *dev) |
450 | { | |
451 | } | |
a28724b0 YZ |
452 | static inline int pci_iov_bus_range(struct pci_bus *bus) |
453 | { | |
454 | return 0; | |
455 | } | |
302b4215 | 456 | |
d1b054da YZ |
457 | #endif /* CONFIG_PCI_IOV */ |
458 | ||
f39d5b72 | 459 | unsigned long pci_cardbus_resource_alignment(struct resource *); |
0a2daa1c | 460 | |
0e52247a | 461 | static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, |
f39d5b72 | 462 | struct resource *res) |
6faf17f6 CW |
463 | { |
464 | #ifdef CONFIG_PCI_IOV | |
465 | int resno = res - dev->resource; | |
466 | ||
467 | if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END) | |
468 | return pci_sriov_resource_alignment(dev, resno); | |
469 | #endif | |
0aa0f5d1 | 470 | if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS) |
0a2daa1c | 471 | return pci_cardbus_resource_alignment(res); |
6faf17f6 CW |
472 | return resource_alignment(res); |
473 | } | |
474 | ||
f39d5b72 | 475 | void pci_enable_acs(struct pci_dev *dev); |
bd2e9567 BH |
476 | #ifdef CONFIG_PCI_QUIRKS |
477 | int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); | |
478 | int pci_dev_specific_enable_acs(struct pci_dev *dev); | |
73c47dde | 479 | int pci_dev_specific_disable_acs_redir(struct pci_dev *dev); |
bd2e9567 BH |
480 | #else |
481 | static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, | |
482 | u16 acs_flags) | |
483 | { | |
484 | return -ENOTTY; | |
485 | } | |
486 | static inline int pci_dev_specific_enable_acs(struct pci_dev *dev) | |
487 | { | |
488 | return -ENOTTY; | |
489 | } | |
73c47dde LG |
490 | static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) |
491 | { | |
492 | return -ENOTTY; | |
493 | } | |
bd2e9567 | 494 | #endif |
ae21ee65 | 495 | |
2e28bc84 | 496 | /* PCI error reporting and recovery */ |
bdb5ac85 KB |
497 | void pcie_do_recovery(struct pci_dev *dev, enum pci_channel_state state, |
498 | u32 service); | |
2e28bc84 | 499 | |
c2bf1fc2 | 500 | bool pcie_wait_for_link_delay(struct pci_dev *pdev, bool active, int delay); |
9f5a70f1 | 501 | bool pcie_wait_for_link(struct pci_dev *pdev, bool active); |
7d8e7d19 BH |
502 | #ifdef CONFIG_PCIEASPM |
503 | void pcie_aspm_init_link_state(struct pci_dev *pdev); | |
504 | void pcie_aspm_exit_link_state(struct pci_dev *pdev); | |
505 | void pcie_aspm_pm_state_change(struct pci_dev *pdev); | |
506 | void pcie_aspm_powersave_config_link(struct pci_dev *pdev); | |
507 | #else | |
508 | static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { } | |
509 | static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { } | |
510 | static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { } | |
511 | static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { } | |
512 | #endif | |
513 | ||
514 | #ifdef CONFIG_PCIEASPM_DEBUG | |
515 | void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev); | |
516 | void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev); | |
517 | #else | |
518 | static inline void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev) { } | |
519 | static inline void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev) { } | |
520 | #endif | |
521 | ||
9bb04a0c JY |
522 | #ifdef CONFIG_PCIE_PTM |
523 | void pci_ptm_init(struct pci_dev *dev); | |
524 | #else | |
525 | static inline void pci_ptm_init(struct pci_dev *dev) { } | |
526 | #endif | |
527 | ||
b9c3b266 DC |
528 | struct pci_dev_reset_methods { |
529 | u16 vendor; | |
530 | u16 device; | |
531 | int (*reset)(struct pci_dev *dev, int probe); | |
532 | }; | |
533 | ||
93177a74 | 534 | #ifdef CONFIG_PCI_QUIRKS |
f39d5b72 | 535 | int pci_dev_specific_reset(struct pci_dev *dev, int probe); |
93177a74 RW |
536 | #else |
537 | static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe) | |
538 | { | |
539 | return -ENOTTY; | |
540 | } | |
541 | #endif | |
b9c3b266 | 542 | |
169de969 DL |
543 | #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64) |
544 | int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment, | |
545 | struct resource *res); | |
546 | #endif | |
547 | ||
276b738d CK |
548 | u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar); |
549 | int pci_rebar_get_current_size(struct pci_dev *pdev, int bar); | |
550 | int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size); | |
551 | static inline u64 pci_rebar_size_to_bytes(int size) | |
552 | { | |
553 | return 1ULL << (size + 20); | |
554 | } | |
555 | ||
9e2aee80 RH |
556 | struct device_node; |
557 | ||
558 | #ifdef CONFIG_OF | |
559 | int of_pci_parse_bus_range(struct device_node *node, struct resource *res); | |
560 | int of_get_pci_domain_nr(struct device_node *node); | |
561 | int of_pci_get_max_link_speed(struct device_node *node); | |
562 | ||
563 | #else | |
564 | static inline int | |
565 | of_pci_parse_bus_range(struct device_node *node, struct resource *res) | |
566 | { | |
567 | return -EINVAL; | |
568 | } | |
569 | ||
570 | static inline int | |
571 | of_get_pci_domain_nr(struct device_node *node) | |
572 | { | |
573 | return -1; | |
574 | } | |
575 | ||
576 | static inline int | |
577 | of_pci_get_max_link_speed(struct device_node *node) | |
578 | { | |
579 | return -EINVAL; | |
580 | } | |
581 | #endif /* CONFIG_OF */ | |
582 | ||
583 | #if defined(CONFIG_OF_ADDRESS) | |
f03c7aa4 | 584 | int devm_of_pci_get_host_bridge_resources(struct device *dev, |
9e2aee80 RH |
585 | unsigned char busno, unsigned char bus_max, |
586 | struct list_head *resources, resource_size_t *io_base); | |
587 | #else | |
f03c7aa4 | 588 | static inline int devm_of_pci_get_host_bridge_resources(struct device *dev, |
9e2aee80 RH |
589 | unsigned char busno, unsigned char bus_max, |
590 | struct list_head *resources, resource_size_t *io_base) | |
591 | { | |
592 | return -EINVAL; | |
593 | } | |
594 | #endif | |
595 | ||
60ed982a RJ |
596 | #ifdef CONFIG_PCIEAER |
597 | void pci_no_aer(void); | |
598 | void pci_aer_init(struct pci_dev *dev); | |
db89ccbe | 599 | void pci_aer_exit(struct pci_dev *dev); |
81aa5206 | 600 | extern const struct attribute_group aer_stats_attr_group; |
7ab92e89 | 601 | void pci_aer_clear_fatal_status(struct pci_dev *dev); |
ec752f5d | 602 | void pci_aer_clear_device_status(struct pci_dev *dev); |
60ed982a RJ |
603 | #else |
604 | static inline void pci_no_aer(void) { } | |
31f996ef | 605 | static inline void pci_aer_init(struct pci_dev *d) { } |
db89ccbe | 606 | static inline void pci_aer_exit(struct pci_dev *d) { } |
7ab92e89 | 607 | static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } |
ec752f5d | 608 | static inline void pci_aer_clear_device_status(struct pci_dev *dev) { } |
60ed982a RJ |
609 | #endif |
610 | ||
557848c3 | 611 | #endif /* DRIVERS_PCI_H */ |