[mirror_ubuntu-focal-kernel.git] / drivers / pci / pci.h

#ifndef DRIVERS_PCI_H
#define DRIVERS_PCI_H

#define PCI_CFG_SPACE_SIZE	256
#define PCI_CFG_SPACE_EXP_SIZE	4096

#define PCI_FIND_CAP_TTL	48

extern const unsigned char pcie_link_speed[];

bool pcie_cap_has_lnkctl(const struct pci_dev *dev);

/* Functions internal to the PCI core code */

int pci_create_sysfs_dev_files(struct pci_dev *pdev);
void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
#if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI)
static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
{ return; }
static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
{ return; }
#else
void pci_create_firmware_label_files(struct pci_dev *pdev);
void pci_remove_firmware_label_files(struct pci_dev *pdev);
#endif
void pci_cleanup_rom(struct pci_dev *dev);
#ifdef HAVE_PCI_MMAP
enum pci_mmap_api {
	PCI_MMAP_SYSFS,	/* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
	PCI_MMAP_PROCFS	/* mmap on /proc/bus/pci/<BDF> */
};
int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
		  enum pci_mmap_api mmap_api);
#endif
int pci_probe_reset_function(struct pci_dev *dev);

/**
 * struct pci_platform_pm_ops - Firmware PM callbacks
 *
 * @is_manageable: returns 'true' if given device is power manageable by the
 *                 platform firmware
 *
 * @set_state: invokes the platform firmware to set the device's power state
 *
 * @choose_state: returns PCI power state of given device preferred by the
 *                platform; to be used during system-wide transitions from a
 *                sleeping state to the working state and vice versa
 *
 * @sleep_wake: enables/disables the system wake up capability of given device
 *
 * @run_wake: enables/disables the platform to generate run-time wake-up events
 *		for given device (the device's wake-up capability has to be
 *		enabled by @sleep_wake for this feature to work)
 *
 * @need_resume: returns 'true' if the given device (which is currently
 *		suspended) needs to be resumed to be configured for system
 *		wakeup.
 *
 * If given platform is generally capable of power managing PCI devices, all of
 * these callbacks are mandatory.
 */
struct pci_platform_pm_ops {
	bool (*is_manageable)(struct pci_dev *dev);
	int (*set_state)(struct pci_dev *dev, pci_power_t state);
	pci_power_t (*choose_state)(struct pci_dev *dev);
	int (*sleep_wake)(struct pci_dev *dev, bool enable);
	int (*run_wake)(struct pci_dev *dev, bool enable);
	bool (*need_resume)(struct pci_dev *dev);
};

int pci_set_platform_pm(const struct pci_platform_pm_ops *ops);
void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
void pci_power_up(struct pci_dev *dev);
void pci_disable_enabled_device(struct pci_dev *dev);
int pci_finish_runtime_suspend(struct pci_dev *dev);
int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
bool pci_dev_keep_suspended(struct pci_dev *dev);
void pci_dev_complete_resume(struct pci_dev *pci_dev);
void pci_config_pm_runtime_get(struct pci_dev *dev);
void pci_config_pm_runtime_put(struct pci_dev *dev);
void pci_pm_init(struct pci_dev *dev);
void pci_ea_init(struct pci_dev *dev);
void pci_allocate_cap_save_buffers(struct pci_dev *dev);
void pci_free_cap_save_buffers(struct pci_dev *dev);

static inline void pci_wakeup_event(struct pci_dev *dev)
{
	/* Wait 100 ms before the system can be put into a sleep state. */
	pm_wakeup_event(&dev->dev, 100);
}

static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
{
	return !!(pci_dev->subordinate);
}

struct pci_vpd_ops {
	ssize_t (*read)(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
	ssize_t (*write)(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
};

struct pci_vpd {
	unsigned int len;
	const struct pci_vpd_ops *ops;
	struct bin_attribute *attr; /* descriptor for sysfs VPD entry */
};

int pci_vpd_init(struct pci_dev *dev);
void pci_vpd_release(struct pci_dev *dev);

/* PCI /proc functions */
#ifdef CONFIG_PROC_FS
int pci_proc_attach_device(struct pci_dev *dev);
int pci_proc_detach_device(struct pci_dev *dev);
int pci_proc_detach_bus(struct pci_bus *bus);
#else
static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
#endif

/* Functions for PCI Hotplug drivers to use */
int pci_hp_add_bridge(struct pci_dev *dev);

#ifdef HAVE_PCI_LEGACY
void pci_create_legacy_files(struct pci_bus *bus);
void pci_remove_legacy_files(struct pci_bus *bus);
#else
static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
#endif

/* Lock for read/write access to pci device and bus lists */
extern struct rw_semaphore pci_bus_sem;

extern raw_spinlock_t pci_lock;

extern unsigned int pci_pm_d3_delay;

#ifdef CONFIG_PCI_MSI
void pci_no_msi(void);
#else
static inline void pci_no_msi(void) { }
#endif

static inline void pci_msi_set_enable(struct pci_dev *dev, int enable)
{
	u16 control;

	pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
	control &= ~PCI_MSI_FLAGS_ENABLE;
	if (enable)
		control |= PCI_MSI_FLAGS_ENABLE;
	pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
}

static inline void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set)
{
	u16 ctrl;

	pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
	ctrl &= ~clear;
	ctrl |= set;
	pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl);
}

void pci_realloc_get_opt(char *);

static inline int pci_no_d1d2(struct pci_dev *dev)
{
	unsigned int parent_dstates = 0;

	if (dev->bus->self)
		parent_dstates = dev->bus->self->no_d1d2;
	return (dev->no_d1d2 || parent_dstates);

}
extern const struct attribute_group *pci_dev_groups[];
extern const struct attribute_group *pcibus_groups[];
extern struct device_type pci_dev_type;
extern const struct attribute_group *pci_bus_groups[];


/**
 * pci_match_one_device - Tell if a PCI device structure has a matching
 *                        PCI device id structure
 * @id: single PCI device id structure to match
 * @dev: the PCI device structure to match against
 *
 * Returns the matching pci_device_id structure or %NULL if there is no match.
 */
static inline const struct pci_device_id *
pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
{
	if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
	    (id->device == PCI_ANY_ID || id->device == dev->device) &&
	    (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
	    (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
	    !((id->class ^ dev->class) & id->class_mask))
		return id;
	return NULL;
}

/* PCI slot sysfs helper code */
#define to_pci_slot(s) container_of(s, struct pci_slot, kobj)

extern struct kset *pci_slots_kset;

struct pci_slot_attribute {
	struct attribute attr;
	ssize_t (*show)(struct pci_slot *, char *);
	ssize_t (*store)(struct pci_slot *, const char *, size_t);
};
#define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)

enum pci_bar_type {
	pci_bar_unknown,	/* Standard PCI BAR probe */
	pci_bar_io,		/* An io port BAR */
	pci_bar_mem32,		/* A 32-bit memory BAR */
	pci_bar_mem64,		/* A 64-bit memory BAR */
};

bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
				int crs_timeout);
int pci_setup_device(struct pci_dev *dev);
int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
		    struct resource *res, unsigned int reg);
int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type);
void pci_configure_ari(struct pci_dev *dev);
void __pci_bus_size_bridges(struct pci_bus *bus,
			struct list_head *realloc_head);
void __pci_bus_assign_resources(const struct pci_bus *bus,
				struct list_head *realloc_head,
				struct list_head *fail_head);
bool pci_bus_clip_resource(struct pci_dev *dev, int idx);

void pci_reassigndev_resource_alignment(struct pci_dev *dev);
void pci_disable_bridge_window(struct pci_dev *dev);

/* Single Root I/O Virtualization */
struct pci_sriov {
	int pos;		/* capability position */
	int nres;		/* number of resources */
	u32 cap;		/* SR-IOV Capabilities */
	u16 ctrl;		/* SR-IOV Control */
	u16 total_VFs;		/* total VFs associated with the PF */
	u16 initial_VFs;	/* initial VFs associated with the PF */
	u16 num_VFs;		/* number of VFs available */
	u16 offset;		/* first VF Routing ID offset */
	u16 stride;		/* following VF stride */
	u32 pgsz;		/* page size for BAR alignment */
	u8 link;		/* Function Dependency Link */
	u8 max_VF_buses;	/* max buses consumed by VFs */
	u16 driver_max_VFs;	/* max num VFs driver supports */
	struct pci_dev *dev;	/* lowest numbered PF */
	struct pci_dev *self;	/* this PF */
	struct mutex lock;	/* lock for VF bus */
	resource_size_t barsz[PCI_SRIOV_NUM_BARS];	/* VF BAR size */
};

#ifdef CONFIG_PCI_ATS
void pci_restore_ats_state(struct pci_dev *dev);
#else
static inline void pci_restore_ats_state(struct pci_dev *dev)
{
}
#endif /* CONFIG_PCI_ATS */

#ifdef CONFIG_PCI_IOV
int pci_iov_init(struct pci_dev *dev);
void pci_iov_release(struct pci_dev *dev);
int pci_iov_resource_bar(struct pci_dev *dev, int resno);
resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
void pci_restore_iov_state(struct pci_dev *dev);
int pci_iov_bus_range(struct pci_bus *bus);

#else
static inline int pci_iov_init(struct pci_dev *dev)
{
	return -ENODEV;
}
static inline void pci_iov_release(struct pci_dev *dev)

{
}
static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno)
{
	return 0;
}
static inline void pci_restore_iov_state(struct pci_dev *dev)
{
}
static inline int pci_iov_bus_range(struct pci_bus *bus)
{
	return 0;
}

#endif /* CONFIG_PCI_IOV */

unsigned long pci_cardbus_resource_alignment(struct resource *);

static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
						     struct resource *res)
{
#ifdef CONFIG_PCI_IOV
	int resno = res - dev->resource;

	if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
		return pci_sriov_resource_alignment(dev, resno);
#endif
	if (dev->class >> 8  == PCI_CLASS_BRIDGE_CARDBUS)
		return pci_cardbus_resource_alignment(res);
	return resource_alignment(res);
}

void pci_enable_acs(struct pci_dev *dev);

struct pci_dev_reset_methods {
	u16 vendor;
	u16 device;
	int (*reset)(struct pci_dev *dev, int probe);
};

#ifdef CONFIG_PCI_QUIRKS
int pci_dev_specific_reset(struct pci_dev *dev, int probe);
#else
static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
{
	return -ENOTTY;
}
#endif

#endif /* DRIVERS_PCI_H */
Commit	Line	Data
557848c3 ZY	1	#ifndef DRIVERS_PCI_H
	2	#define DRIVERS_PCI_H
	3
	4	#define PCI_CFG_SPACE_SIZE 256
	5	#define PCI_CFG_SPACE_EXP_SIZE 4096
	6
fff905f3 WY	7	#define PCI_FIND_CAP_TTL 48
fff905f3 WY	8
343e51ae JK	9	extern const unsigned char pcie_link_speed[];
343e51ae JK	10
7a1562d4 YL	11	bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
7a1562d4 YL	12
1da177e4 LT	13	/* Functions internal to the PCI core code */
1da177e4 LT	14
f39d5b72 BH	15	int pci_create_sysfs_dev_files(struct pci_dev *pdev);
f39d5b72 BH	16	void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
6058989b	17	#if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI)
911e1c9b	18	static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
b879743f	19	{ return; }
911e1c9b	20	static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
b879743f	21	{ return; }
911e1c9b	22	#else
f39d5b72 BH	23	void pci_create_firmware_label_files(struct pci_dev *pdev);
f39d5b72 BH	24	void pci_remove_firmware_label_files(struct pci_dev *pdev);
911e1c9b	25	#endif
f39d5b72	26	void pci_cleanup_rom(struct pci_dev *dev);
9eff02e2	27	#ifdef HAVE_PCI_MMAP
3b519e4e MW	28	enum pci_mmap_api {
	29	PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
	30	PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
	31	};
f39d5b72 BH	32	int pci_mmap_fits(struct pci_dev pdev, int resno, struct vm_area_struct vmai,
f39d5b72 BH	33	enum pci_mmap_api mmap_api);
9eff02e2	34	#endif
711d5779	35	int pci_probe_reset_function(struct pci_dev *dev);
ce5ccdef	36
961d9120	37	/**
b33bfdef	38	* struct pci_platform_pm_ops - Firmware PM callbacks
961d9120	39	*
b33bfdef RD	40	* @is_manageable: returns 'true' if given device is power manageable by the
b33bfdef RD	41	* platform firmware
961d9120	42	*
b33bfdef	43	* @set_state: invokes the platform firmware to set the device's power state
961d9120	44	*
b33bfdef RD	45	* @choose_state: returns PCI power state of given device preferred by the
	46	* platform; to be used during system-wide transitions from a
	47	* sleeping state to the working state and vice versa
961d9120	48	*
b33bfdef	49	* @sleep_wake: enables/disables the system wake up capability of given device
eb9d0fe4	50	*
b67ea761 RW	51	* @run_wake: enables/disables the platform to generate run-time wake-up events
	52	* for given device (the device's wake-up capability has to be
	53	* enabled by @sleep_wake for this feature to work)
	54	*
bac2a909 RW	55	* @need_resume: returns 'true' if the given device (which is currently
	56	* suspended) needs to be resumed to be configured for system
	57	* wakeup.
	58	*
961d9120 RW	59	* If given platform is generally capable of power managing PCI devices, all of
	60	* these callbacks are mandatory.
	61	*/
	62	struct pci_platform_pm_ops {
	63	bool (is_manageable)(struct pci_dev dev);
	64	int (set_state)(struct pci_dev dev, pci_power_t state);
	65	pci_power_t (choose_state)(struct pci_dev dev);
eb9d0fe4	66	int (sleep_wake)(struct pci_dev dev, bool enable);
b67ea761	67	int (run_wake)(struct pci_dev dev, bool enable);
bac2a909	68	bool (need_resume)(struct pci_dev dev);
961d9120 RW	69	};
961d9120 RW	70
299f2ffe	71	int pci_set_platform_pm(const struct pci_platform_pm_ops *ops);
f39d5b72 BH	72	void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
	73	void pci_power_up(struct pci_dev *dev);
	74	void pci_disable_enabled_device(struct pci_dev *dev);
	75	int pci_finish_runtime_suspend(struct pci_dev *dev);
	76	int __pci_pme_wakeup(struct pci_dev dev, void ign);
bac2a909	77	bool pci_dev_keep_suspended(struct pci_dev *dev);
2cef548a	78	void pci_dev_complete_resume(struct pci_dev *pci_dev);
f39d5b72 BH	79	void pci_config_pm_runtime_get(struct pci_dev *dev);
	80	void pci_config_pm_runtime_put(struct pci_dev *dev);
	81	void pci_pm_init(struct pci_dev *dev);
938174e5	82	void pci_ea_init(struct pci_dev *dev);
f39d5b72	83	void pci_allocate_cap_save_buffers(struct pci_dev *dev);
f796841e	84	void pci_free_cap_save_buffers(struct pci_dev *dev);
aa8c6c93	85
b6e335ae RW	86	static inline void pci_wakeup_event(struct pci_dev *dev)
	87	{
	88	/* Wait 100 ms before the system can be put into a sleep state. */
	89	pm_wakeup_event(&dev->dev, 100);
	90	}
	91
326c1cda	92	static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
aa8c6c93 RW	93	{
	94	return !!(pci_dev->subordinate);
	95	}
0f64474b	96
94e61088	97	struct pci_vpd_ops {
287d19ce SH	98	ssize_t (read)(struct pci_dev dev, loff_t pos, size_t count, void *buf);
287d19ce SH	99	ssize_t (write)(struct pci_dev dev, loff_t pos, size_t count, const void *buf);
94e61088 BH	100	};
	101
	102	struct pci_vpd {
99cb233d	103	unsigned int len;
287d19ce	104	const struct pci_vpd_ops *ops;
94e61088 BH	105	struct bin_attribute attr; / descriptor for sysfs VPD entry */
	106	};
	107
f1cd93f9	108	int pci_vpd_init(struct pci_dev *dev);
64379079	109	void pci_vpd_release(struct pci_dev *dev);
94e61088	110
1da177e4 LT	111	/* PCI /proc functions */
1da177e4 LT	112	#ifdef CONFIG_PROC_FS
f39d5b72 BH	113	int pci_proc_attach_device(struct pci_dev *dev);
	114	int pci_proc_detach_device(struct pci_dev *dev);
	115	int pci_proc_detach_bus(struct pci_bus *bus);
1da177e4 LT	116	#else
	117	static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
	118	static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
1da177e4 LT	119	static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
	120	#endif
	121
	122	/* Functions for PCI Hotplug drivers to use */
a8e4b9c1	123	int pci_hp_add_bridge(struct pci_dev *dev);
1da177e4	124
f19aeb1f	125	#ifdef HAVE_PCI_LEGACY
f39d5b72 BH	126	void pci_create_legacy_files(struct pci_bus *bus);
f39d5b72 BH	127	void pci_remove_legacy_files(struct pci_bus *bus);
f19aeb1f BH	128	#else
	129	static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
	130	static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
	131	#endif
1da177e4 LT	132
1da177e4 LT	133	/* Lock for read/write access to pci device and bus lists */
d71374da	134	extern struct rw_semaphore pci_bus_sem;
1da177e4	135
a2e27787 JK	136	extern raw_spinlock_t pci_lock;
a2e27787 JK	137
ffadcc2f	138	extern unsigned int pci_pm_d3_delay;
88187dfa	139
4b47b0ee	140	#ifdef CONFIG_PCI_MSI
309e57df	141	void pci_no_msi(void);
4b47b0ee	142	#else
309e57df	143	static inline void pci_no_msi(void) { }
4b47b0ee	144	#endif
8fed4b65	145
6a25f5e3 MT	146	static inline void pci_msi_set_enable(struct pci_dev *dev, int enable)
	147	{
	148	u16 control;
	149
	150	pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
	151	control &= ~PCI_MSI_FLAGS_ENABLE;
	152	if (enable)
	153	control \|= PCI_MSI_FLAGS_ENABLE;
	154	pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
	155	}
	156
	157	static inline void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set)
	158	{
	159	u16 ctrl;
	160
	161	pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
	162	ctrl &= ~clear;
	163	ctrl \|= set;
	164	pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl);
	165	}
	166
b55438fd	167	void pci_realloc_get_opt(char *);
f483d392	168
ffadcc2f KCA	169	static inline int pci_no_d1d2(struct pci_dev *dev)
	170	{
	171	unsigned int parent_dstates = 0;
4b47b0ee	172
ffadcc2f KCA	173	if (dev->bus->self)
	174	parent_dstates = dev->bus->self->no_d1d2;
	175	return (dev->no_d1d2 \|\| parent_dstates);
	176
	177	}
5136b2da	178	extern const struct attribute_group *pci_dev_groups[];
56039e65	179	extern const struct attribute_group *pcibus_groups[];
4e15c46b	180	extern struct device_type pci_dev_type;
0f49ba55	181	extern const struct attribute_group *pci_bus_groups[];
705b1aaa	182
1da177e4 LT	183
	184	/**
	185	* pci_match_one_device - Tell if a PCI device structure has a matching
	186	* PCI device id structure
	187	* @id: single PCI device id structure to match
	188	* @dev: the PCI device structure to match against
367b09fe	189	*
1da177e4 LT	190	* Returns the matching pci_device_id structure or %NULL if there is no match.
	191	*/
	192	static inline const struct pci_device_id *
	193	pci_match_one_device(const struct pci_device_id id, const struct pci_dev dev)
	194	{
	195	if ((id->vendor == PCI_ANY_ID \|\| id->vendor == dev->vendor) &&
	196	(id->device == PCI_ANY_ID \|\| id->device == dev->device) &&
	197	(id->subvendor == PCI_ANY_ID \|\| id->subvendor == dev->subsystem_vendor) &&
	198	(id->subdevice == PCI_ANY_ID \|\| id->subdevice == dev->subsystem_device) &&
	199	!((id->class ^ dev->class) & id->class_mask))
	200	return id;
	201	return NULL;
	202	}
	203
f46753c5 AC	204	/* PCI slot sysfs helper code */
	205	#define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
	206
	207	extern struct kset *pci_slots_kset;
	208
	209	struct pci_slot_attribute {
	210	struct attribute attr;
	211	ssize_t (show)(struct pci_slot , char *);
	212	ssize_t (store)(struct pci_slot , const char *, size_t);
	213	};
	214	#define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
	215
0b400c7e YZ	216	enum pci_bar_type {
	217	pci_bar_unknown, /* Standard PCI BAR probe */
	218	pci_bar_io, /* An io port BAR */
	219	pci_bar_mem32, /* A 32-bit memory BAR */
	220	pci_bar_mem64, /* A 64-bit memory BAR */
	221	};
	222
efdc87da YL	223	bool pci_bus_read_dev_vendor_id(struct pci_bus bus, int devfn, u32 pl,
efdc87da YL	224	int crs_timeout);
f39d5b72 BH	225	int pci_setup_device(struct pci_dev *dev);
	226	int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
	227	struct resource *res, unsigned int reg);
	228	int pci_resource_bar(struct pci_dev dev, int resno, enum pci_bar_type type);
	229	void pci_configure_ari(struct pci_dev *dev);
10874f5a	230	void __pci_bus_size_bridges(struct pci_bus *bus,
d66ecb72	231	struct list_head *realloc_head);
10874f5a BH	232	void __pci_bus_assign_resources(const struct pci_bus *bus,
	233	struct list_head *realloc_head,
	234	struct list_head *fail_head);
0f7e7aee	235	bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
939de1d6	236
2069ecfb	237	void pci_reassigndev_resource_alignment(struct pci_dev *dev);
f39d5b72	238	void pci_disable_bridge_window(struct pci_dev *dev);
32a9a682	239
d1b054da YZ	240	/* Single Root I/O Virtualization */
	241	struct pci_sriov {
	242	int pos; /* capability position */
	243	int nres; /* number of resources */
	244	u32 cap; /* SR-IOV Capabilities */
	245	u16 ctrl; /* SR-IOV Control */
6b136724 BH	246	u16 total_VFs; /* total VFs associated with the PF */
	247	u16 initial_VFs; /* initial VFs associated with the PF */
	248	u16 num_VFs; /* number of VFs available */
d1b054da YZ	249	u16 offset; /* first VF Routing ID offset */
	250	u16 stride; /* following VF stride */
	251	u32 pgsz; /* page size for BAR alignment */
	252	u8 link; /* Function Dependency Link */
4449f079	253	u8 max_VF_buses; /* max buses consumed by VFs */
6b136724	254	u16 driver_max_VFs; /* max num VFs driver supports */
d1b054da YZ	255	struct pci_dev dev; / lowest numbered PF */
	256	struct pci_dev self; / this PF */
	257	struct mutex lock; /* lock for VF bus */
0e6c9122	258	resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
d1b054da YZ	259	};
d1b054da YZ	260
1900ca13	261	#ifdef CONFIG_PCI_ATS
f39d5b72	262	void pci_restore_ats_state(struct pci_dev *dev);
1900ca13 HX	263	#else
	264	static inline void pci_restore_ats_state(struct pci_dev *dev)
	265	{
	266	}
	267	#endif /* CONFIG_PCI_ATS */
	268
d1b054da	269	#ifdef CONFIG_PCI_IOV
f39d5b72 BH	270	int pci_iov_init(struct pci_dev *dev);
f39d5b72 BH	271	void pci_iov_release(struct pci_dev *dev);
26ff46c6	272	int pci_iov_resource_bar(struct pci_dev *dev, int resno);
f39d5b72 BH	273	resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
	274	void pci_restore_iov_state(struct pci_dev *dev);
	275	int pci_iov_bus_range(struct pci_bus *bus);
302b4215	276
d1b054da YZ	277	#else
	278	static inline int pci_iov_init(struct pci_dev *dev)
	279	{
	280	return -ENODEV;
	281	}
	282	static inline void pci_iov_release(struct pci_dev *dev)
	283
	284	{
	285	}
26ff46c6	286	static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno)
d1b054da YZ	287	{
	288	return 0;
	289	}
8c5cdb6a YZ	290	static inline void pci_restore_iov_state(struct pci_dev *dev)
	291	{
	292	}
a28724b0 YZ	293	static inline int pci_iov_bus_range(struct pci_bus *bus)
	294	{
	295	return 0;
	296	}
302b4215	297
d1b054da YZ	298	#endif /* CONFIG_PCI_IOV */
d1b054da YZ	299
f39d5b72	300	unsigned long pci_cardbus_resource_alignment(struct resource *);
0a2daa1c	301
0e52247a	302	static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
f39d5b72	303	struct resource *res)
6faf17f6 CW	304	{
	305	#ifdef CONFIG_PCI_IOV
	306	int resno = res - dev->resource;
	307
	308	if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
	309	return pci_sriov_resource_alignment(dev, resno);
	310	#endif
0a2daa1c RP	311	if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
0a2daa1c RP	312	return pci_cardbus_resource_alignment(res);
6faf17f6 CW	313	return resource_alignment(res);
	314	}
	315
f39d5b72	316	void pci_enable_acs(struct pci_dev *dev);
ae21ee65	317
b9c3b266 DC	318	struct pci_dev_reset_methods {
	319	u16 vendor;
	320	u16 device;
	321	int (reset)(struct pci_dev dev, int probe);
	322	};
	323
93177a74	324	#ifdef CONFIG_PCI_QUIRKS
f39d5b72	325	int pci_dev_specific_reset(struct pci_dev *dev, int probe);
93177a74 RW	326	#else
	327	static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
	328	{
	329	return -ENOTTY;
	330	}
	331	#endif
b9c3b266	332
557848c3	333	#endif /* DRIVERS_PCI_H */