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Commit | Line | Data |
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557848c3 ZY |
1 | #ifndef DRIVERS_PCI_H |
2 | #define DRIVERS_PCI_H | |
3 | ||
fff905f3 WY |
4 | #define PCI_FIND_CAP_TTL 48 |
5 | ||
343e51ae JK |
6 | extern const unsigned char pcie_link_speed[]; |
7 | ||
7a1562d4 YL |
8 | bool pcie_cap_has_lnkctl(const struct pci_dev *dev); |
9 | ||
1da177e4 LT |
10 | /* Functions internal to the PCI core code */ |
11 | ||
f39d5b72 BH |
12 | int pci_create_sysfs_dev_files(struct pci_dev *pdev); |
13 | void pci_remove_sysfs_dev_files(struct pci_dev *pdev); | |
6058989b | 14 | #if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI) |
911e1c9b | 15 | static inline void pci_create_firmware_label_files(struct pci_dev *pdev) |
b879743f | 16 | { return; } |
911e1c9b | 17 | static inline void pci_remove_firmware_label_files(struct pci_dev *pdev) |
b879743f | 18 | { return; } |
911e1c9b | 19 | #else |
f39d5b72 BH |
20 | void pci_create_firmware_label_files(struct pci_dev *pdev); |
21 | void pci_remove_firmware_label_files(struct pci_dev *pdev); | |
911e1c9b | 22 | #endif |
f39d5b72 | 23 | void pci_cleanup_rom(struct pci_dev *dev); |
9eff02e2 | 24 | #ifdef HAVE_PCI_MMAP |
3b519e4e MW |
25 | enum pci_mmap_api { |
26 | PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */ | |
27 | PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */ | |
28 | }; | |
f39d5b72 BH |
29 | int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai, |
30 | enum pci_mmap_api mmap_api); | |
9eff02e2 | 31 | #endif |
711d5779 | 32 | int pci_probe_reset_function(struct pci_dev *dev); |
ce5ccdef | 33 | |
961d9120 | 34 | /** |
b33bfdef | 35 | * struct pci_platform_pm_ops - Firmware PM callbacks |
961d9120 | 36 | * |
b33bfdef RD |
37 | * @is_manageable: returns 'true' if given device is power manageable by the |
38 | * platform firmware | |
961d9120 | 39 | * |
b33bfdef | 40 | * @set_state: invokes the platform firmware to set the device's power state |
961d9120 | 41 | * |
cc7cc02b LW |
42 | * @get_state: queries the platform firmware for a device's current power state |
43 | * | |
b33bfdef RD |
44 | * @choose_state: returns PCI power state of given device preferred by the |
45 | * platform; to be used during system-wide transitions from a | |
46 | * sleeping state to the working state and vice versa | |
961d9120 | 47 | * |
b33bfdef | 48 | * @sleep_wake: enables/disables the system wake up capability of given device |
eb9d0fe4 | 49 | * |
b67ea761 RW |
50 | * @run_wake: enables/disables the platform to generate run-time wake-up events |
51 | * for given device (the device's wake-up capability has to be | |
52 | * enabled by @sleep_wake for this feature to work) | |
53 | * | |
bac2a909 RW |
54 | * @need_resume: returns 'true' if the given device (which is currently |
55 | * suspended) needs to be resumed to be configured for system | |
56 | * wakeup. | |
57 | * | |
961d9120 RW |
58 | * If given platform is generally capable of power managing PCI devices, all of |
59 | * these callbacks are mandatory. | |
60 | */ | |
61 | struct pci_platform_pm_ops { | |
62 | bool (*is_manageable)(struct pci_dev *dev); | |
63 | int (*set_state)(struct pci_dev *dev, pci_power_t state); | |
cc7cc02b | 64 | pci_power_t (*get_state)(struct pci_dev *dev); |
961d9120 | 65 | pci_power_t (*choose_state)(struct pci_dev *dev); |
eb9d0fe4 | 66 | int (*sleep_wake)(struct pci_dev *dev, bool enable); |
b67ea761 | 67 | int (*run_wake)(struct pci_dev *dev, bool enable); |
bac2a909 | 68 | bool (*need_resume)(struct pci_dev *dev); |
961d9120 RW |
69 | }; |
70 | ||
299f2ffe | 71 | int pci_set_platform_pm(const struct pci_platform_pm_ops *ops); |
f39d5b72 BH |
72 | void pci_update_current_state(struct pci_dev *dev, pci_power_t state); |
73 | void pci_power_up(struct pci_dev *dev); | |
74 | void pci_disable_enabled_device(struct pci_dev *dev); | |
75 | int pci_finish_runtime_suspend(struct pci_dev *dev); | |
76 | int __pci_pme_wakeup(struct pci_dev *dev, void *ign); | |
bac2a909 | 77 | bool pci_dev_keep_suspended(struct pci_dev *dev); |
2cef548a | 78 | void pci_dev_complete_resume(struct pci_dev *pci_dev); |
f39d5b72 BH |
79 | void pci_config_pm_runtime_get(struct pci_dev *dev); |
80 | void pci_config_pm_runtime_put(struct pci_dev *dev); | |
81 | void pci_pm_init(struct pci_dev *dev); | |
938174e5 | 82 | void pci_ea_init(struct pci_dev *dev); |
f39d5b72 | 83 | void pci_allocate_cap_save_buffers(struct pci_dev *dev); |
f796841e | 84 | void pci_free_cap_save_buffers(struct pci_dev *dev); |
c6a63307 | 85 | bool pci_bridge_d3_possible(struct pci_dev *dev); |
1ed276a7 | 86 | void pci_bridge_d3_update(struct pci_dev *dev); |
aa8c6c93 | 87 | |
b6e335ae RW |
88 | static inline void pci_wakeup_event(struct pci_dev *dev) |
89 | { | |
90 | /* Wait 100 ms before the system can be put into a sleep state. */ | |
91 | pm_wakeup_event(&dev->dev, 100); | |
92 | } | |
93 | ||
326c1cda | 94 | static inline bool pci_has_subordinate(struct pci_dev *pci_dev) |
aa8c6c93 RW |
95 | { |
96 | return !!(pci_dev->subordinate); | |
97 | } | |
0f64474b | 98 | |
9d26d3a8 MW |
99 | static inline bool pci_power_manageable(struct pci_dev *pci_dev) |
100 | { | |
101 | /* | |
102 | * Currently we allow normal PCI devices and PCI bridges transition | |
103 | * into D3 if their bridge_d3 is set. | |
104 | */ | |
105 | return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3; | |
106 | } | |
107 | ||
94e61088 | 108 | struct pci_vpd_ops { |
287d19ce SH |
109 | ssize_t (*read)(struct pci_dev *dev, loff_t pos, size_t count, void *buf); |
110 | ssize_t (*write)(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); | |
cb92148b | 111 | int (*set_size)(struct pci_dev *dev, size_t len); |
94e61088 BH |
112 | }; |
113 | ||
114 | struct pci_vpd { | |
287d19ce | 115 | const struct pci_vpd_ops *ops; |
94e61088 | 116 | struct bin_attribute *attr; /* descriptor for sysfs VPD entry */ |
408641e9 BH |
117 | struct mutex lock; |
118 | unsigned int len; | |
119 | u16 flag; | |
120 | u8 cap; | |
121 | u8 busy:1; | |
122 | u8 valid:1; | |
94e61088 BH |
123 | }; |
124 | ||
f1cd93f9 | 125 | int pci_vpd_init(struct pci_dev *dev); |
64379079 | 126 | void pci_vpd_release(struct pci_dev *dev); |
94e61088 | 127 | |
1da177e4 LT |
128 | /* PCI /proc functions */ |
129 | #ifdef CONFIG_PROC_FS | |
f39d5b72 BH |
130 | int pci_proc_attach_device(struct pci_dev *dev); |
131 | int pci_proc_detach_device(struct pci_dev *dev); | |
132 | int pci_proc_detach_bus(struct pci_bus *bus); | |
1da177e4 LT |
133 | #else |
134 | static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; } | |
135 | static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; } | |
1da177e4 LT |
136 | static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; } |
137 | #endif | |
138 | ||
139 | /* Functions for PCI Hotplug drivers to use */ | |
a8e4b9c1 | 140 | int pci_hp_add_bridge(struct pci_dev *dev); |
1da177e4 | 141 | |
f19aeb1f | 142 | #ifdef HAVE_PCI_LEGACY |
f39d5b72 BH |
143 | void pci_create_legacy_files(struct pci_bus *bus); |
144 | void pci_remove_legacy_files(struct pci_bus *bus); | |
f19aeb1f BH |
145 | #else |
146 | static inline void pci_create_legacy_files(struct pci_bus *bus) { return; } | |
147 | static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; } | |
148 | #endif | |
1da177e4 LT |
149 | |
150 | /* Lock for read/write access to pci device and bus lists */ | |
d71374da | 151 | extern struct rw_semaphore pci_bus_sem; |
1da177e4 | 152 | |
a2e27787 JK |
153 | extern raw_spinlock_t pci_lock; |
154 | ||
ffadcc2f | 155 | extern unsigned int pci_pm_d3_delay; |
88187dfa | 156 | |
4b47b0ee | 157 | #ifdef CONFIG_PCI_MSI |
309e57df | 158 | void pci_no_msi(void); |
4b47b0ee | 159 | #else |
309e57df | 160 | static inline void pci_no_msi(void) { } |
4b47b0ee | 161 | #endif |
8fed4b65 | 162 | |
6a25f5e3 MT |
163 | static inline void pci_msi_set_enable(struct pci_dev *dev, int enable) |
164 | { | |
165 | u16 control; | |
166 | ||
167 | pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); | |
168 | control &= ~PCI_MSI_FLAGS_ENABLE; | |
169 | if (enable) | |
170 | control |= PCI_MSI_FLAGS_ENABLE; | |
171 | pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); | |
172 | } | |
173 | ||
174 | static inline void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set) | |
175 | { | |
176 | u16 ctrl; | |
177 | ||
178 | pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl); | |
179 | ctrl &= ~clear; | |
180 | ctrl |= set; | |
181 | pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl); | |
182 | } | |
183 | ||
b55438fd | 184 | void pci_realloc_get_opt(char *); |
f483d392 | 185 | |
ffadcc2f KCA |
186 | static inline int pci_no_d1d2(struct pci_dev *dev) |
187 | { | |
188 | unsigned int parent_dstates = 0; | |
4b47b0ee | 189 | |
ffadcc2f KCA |
190 | if (dev->bus->self) |
191 | parent_dstates = dev->bus->self->no_d1d2; | |
192 | return (dev->no_d1d2 || parent_dstates); | |
193 | ||
194 | } | |
5136b2da | 195 | extern const struct attribute_group *pci_dev_groups[]; |
56039e65 | 196 | extern const struct attribute_group *pcibus_groups[]; |
4e15c46b | 197 | extern struct device_type pci_dev_type; |
0f49ba55 | 198 | extern const struct attribute_group *pci_bus_groups[]; |
705b1aaa | 199 | |
1da177e4 LT |
200 | |
201 | /** | |
202 | * pci_match_one_device - Tell if a PCI device structure has a matching | |
203 | * PCI device id structure | |
204 | * @id: single PCI device id structure to match | |
205 | * @dev: the PCI device structure to match against | |
367b09fe | 206 | * |
1da177e4 LT |
207 | * Returns the matching pci_device_id structure or %NULL if there is no match. |
208 | */ | |
209 | static inline const struct pci_device_id * | |
210 | pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev) | |
211 | { | |
212 | if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) && | |
213 | (id->device == PCI_ANY_ID || id->device == dev->device) && | |
214 | (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) && | |
215 | (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) && | |
216 | !((id->class ^ dev->class) & id->class_mask)) | |
217 | return id; | |
218 | return NULL; | |
219 | } | |
220 | ||
f46753c5 AC |
221 | /* PCI slot sysfs helper code */ |
222 | #define to_pci_slot(s) container_of(s, struct pci_slot, kobj) | |
223 | ||
224 | extern struct kset *pci_slots_kset; | |
225 | ||
226 | struct pci_slot_attribute { | |
227 | struct attribute attr; | |
228 | ssize_t (*show)(struct pci_slot *, char *); | |
229 | ssize_t (*store)(struct pci_slot *, const char *, size_t); | |
230 | }; | |
231 | #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr) | |
232 | ||
0b400c7e YZ |
233 | enum pci_bar_type { |
234 | pci_bar_unknown, /* Standard PCI BAR probe */ | |
235 | pci_bar_io, /* An io port BAR */ | |
236 | pci_bar_mem32, /* A 32-bit memory BAR */ | |
237 | pci_bar_mem64, /* A 64-bit memory BAR */ | |
238 | }; | |
239 | ||
efdc87da YL |
240 | bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, |
241 | int crs_timeout); | |
f39d5b72 BH |
242 | int pci_setup_device(struct pci_dev *dev); |
243 | int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, | |
244 | struct resource *res, unsigned int reg); | |
f39d5b72 | 245 | void pci_configure_ari(struct pci_dev *dev); |
10874f5a | 246 | void __pci_bus_size_bridges(struct pci_bus *bus, |
d66ecb72 | 247 | struct list_head *realloc_head); |
10874f5a BH |
248 | void __pci_bus_assign_resources(const struct pci_bus *bus, |
249 | struct list_head *realloc_head, | |
250 | struct list_head *fail_head); | |
0f7e7aee | 251 | bool pci_bus_clip_resource(struct pci_dev *dev, int idx); |
939de1d6 | 252 | |
2069ecfb | 253 | void pci_reassigndev_resource_alignment(struct pci_dev *dev); |
f39d5b72 | 254 | void pci_disable_bridge_window(struct pci_dev *dev); |
32a9a682 | 255 | |
d1b054da YZ |
256 | /* Single Root I/O Virtualization */ |
257 | struct pci_sriov { | |
258 | int pos; /* capability position */ | |
259 | int nres; /* number of resources */ | |
260 | u32 cap; /* SR-IOV Capabilities */ | |
261 | u16 ctrl; /* SR-IOV Control */ | |
6b136724 BH |
262 | u16 total_VFs; /* total VFs associated with the PF */ |
263 | u16 initial_VFs; /* initial VFs associated with the PF */ | |
264 | u16 num_VFs; /* number of VFs available */ | |
d1b054da YZ |
265 | u16 offset; /* first VF Routing ID offset */ |
266 | u16 stride; /* following VF stride */ | |
267 | u32 pgsz; /* page size for BAR alignment */ | |
268 | u8 link; /* Function Dependency Link */ | |
4449f079 | 269 | u8 max_VF_buses; /* max buses consumed by VFs */ |
6b136724 | 270 | u16 driver_max_VFs; /* max num VFs driver supports */ |
d1b054da YZ |
271 | struct pci_dev *dev; /* lowest numbered PF */ |
272 | struct pci_dev *self; /* this PF */ | |
5b0948df | 273 | struct mutex lock; /* lock for setting sriov_numvfs in sysfs */ |
0e6c9122 | 274 | resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */ |
d1b054da YZ |
275 | }; |
276 | ||
1900ca13 | 277 | #ifdef CONFIG_PCI_ATS |
f39d5b72 | 278 | void pci_restore_ats_state(struct pci_dev *dev); |
1900ca13 HX |
279 | #else |
280 | static inline void pci_restore_ats_state(struct pci_dev *dev) | |
281 | { | |
282 | } | |
283 | #endif /* CONFIG_PCI_ATS */ | |
284 | ||
d1b054da | 285 | #ifdef CONFIG_PCI_IOV |
f39d5b72 BH |
286 | int pci_iov_init(struct pci_dev *dev); |
287 | void pci_iov_release(struct pci_dev *dev); | |
6ffa2489 | 288 | void pci_iov_update_resource(struct pci_dev *dev, int resno); |
f39d5b72 BH |
289 | resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno); |
290 | void pci_restore_iov_state(struct pci_dev *dev); | |
291 | int pci_iov_bus_range(struct pci_bus *bus); | |
302b4215 | 292 | |
d1b054da YZ |
293 | #else |
294 | static inline int pci_iov_init(struct pci_dev *dev) | |
295 | { | |
296 | return -ENODEV; | |
297 | } | |
298 | static inline void pci_iov_release(struct pci_dev *dev) | |
299 | ||
300 | { | |
301 | } | |
8c5cdb6a YZ |
302 | static inline void pci_restore_iov_state(struct pci_dev *dev) |
303 | { | |
304 | } | |
a28724b0 YZ |
305 | static inline int pci_iov_bus_range(struct pci_bus *bus) |
306 | { | |
307 | return 0; | |
308 | } | |
302b4215 | 309 | |
d1b054da YZ |
310 | #endif /* CONFIG_PCI_IOV */ |
311 | ||
f39d5b72 | 312 | unsigned long pci_cardbus_resource_alignment(struct resource *); |
0a2daa1c | 313 | |
0e52247a | 314 | static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, |
f39d5b72 | 315 | struct resource *res) |
6faf17f6 CW |
316 | { |
317 | #ifdef CONFIG_PCI_IOV | |
318 | int resno = res - dev->resource; | |
319 | ||
320 | if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END) | |
321 | return pci_sriov_resource_alignment(dev, resno); | |
322 | #endif | |
0a2daa1c RP |
323 | if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS) |
324 | return pci_cardbus_resource_alignment(res); | |
6faf17f6 CW |
325 | return resource_alignment(res); |
326 | } | |
327 | ||
f39d5b72 | 328 | void pci_enable_acs(struct pci_dev *dev); |
ae21ee65 | 329 | |
9bb04a0c JY |
330 | #ifdef CONFIG_PCIE_PTM |
331 | void pci_ptm_init(struct pci_dev *dev); | |
332 | #else | |
333 | static inline void pci_ptm_init(struct pci_dev *dev) { } | |
334 | #endif | |
335 | ||
b9c3b266 DC |
336 | struct pci_dev_reset_methods { |
337 | u16 vendor; | |
338 | u16 device; | |
339 | int (*reset)(struct pci_dev *dev, int probe); | |
340 | }; | |
341 | ||
93177a74 | 342 | #ifdef CONFIG_PCI_QUIRKS |
f39d5b72 | 343 | int pci_dev_specific_reset(struct pci_dev *dev, int probe); |
93177a74 RW |
344 | #else |
345 | static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe) | |
346 | { | |
347 | return -ENOTTY; | |
348 | } | |
349 | #endif | |
b9c3b266 | 350 | |
169de969 DL |
351 | #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64) |
352 | int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment, | |
353 | struct resource *res); | |
354 | #endif | |
355 | ||
557848c3 | 356 | #endif /* DRIVERS_PCI_H */ |