[mirror_ubuntu-bionic-kernel.git] / drivers / pci / pcie / aer / aer_inject.c

/*
 * PCIe AER software error injection support.
 *
 * Debuging PCIe AER code is quite difficult because it is hard to
 * trigger various real hardware errors. Software based error
 * injection can fake almost all kinds of errors with the help of a
 * user space helper tool aer-inject, which can be gotten from:
 *   http://www.kernel.org/pub/linux/utils/pci/aer-inject/
 *
 * Copyright 2009 Intel Corporation.
 *     Huang Ying <ying.huang@intel.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; version 2
 * of the License.
 *
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/miscdevice.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/fs.h>
#include <linux/uaccess.h>
#include <linux/stddef.h>
#include <linux/device.h>
#include "aerdrv.h"

/* Override the existing corrected and uncorrected error masks */
static bool aer_mask_override;
module_param(aer_mask_override, bool, 0);

struct aer_error_inj {
	u8 bus;
	u8 dev;
	u8 fn;
	u32 uncor_status;
	u32 cor_status;
	u32 header_log0;
	u32 header_log1;
	u32 header_log2;
	u32 header_log3;
	u32 domain;
};

struct aer_error {
	struct list_head list;
	u32 domain;
	unsigned int bus;
	unsigned int devfn;
	int pos_cap_err;

	u32 uncor_status;
	u32 cor_status;
	u32 header_log0;
	u32 header_log1;
	u32 header_log2;
	u32 header_log3;
	u32 root_status;
	u32 source_id;
};

struct pci_bus_ops {
	struct list_head list;
	struct pci_bus *bus;
	struct pci_ops *ops;
};

static LIST_HEAD(einjected);

static LIST_HEAD(pci_bus_ops_list);

/* Protect einjected and pci_bus_ops_list */
static DEFINE_SPINLOCK(inject_lock);

static void aer_error_init(struct aer_error *err, u32 domain,
			   unsigned int bus, unsigned int devfn,
			   int pos_cap_err)
{
	INIT_LIST_HEAD(&err->list);
	err->domain = domain;
	err->bus = bus;
	err->devfn = devfn;
	err->pos_cap_err = pos_cap_err;
}

/* inject_lock must be held before calling */
static struct aer_error *__find_aer_error(u32 domain, unsigned int bus,
					  unsigned int devfn)
{
	struct aer_error *err;

	list_for_each_entry(err, &einjected, list) {
		if (domain == err->domain &&
		    bus == err->bus &&
		    devfn == err->devfn)
			return err;
	}
	return NULL;
}

/* inject_lock must be held before calling */
static struct aer_error *__find_aer_error_by_dev(struct pci_dev *dev)
{
	int domain = pci_domain_nr(dev->bus);
	if (domain < 0)
		return NULL;
	return __find_aer_error(domain, dev->bus->number, dev->devfn);
}

/* inject_lock must be held before calling */
static struct pci_ops *__find_pci_bus_ops(struct pci_bus *bus)
{
	struct pci_bus_ops *bus_ops;

	list_for_each_entry(bus_ops, &pci_bus_ops_list, list) {
		if (bus_ops->bus == bus)
			return bus_ops->ops;
	}
	return NULL;
}

static struct pci_bus_ops *pci_bus_ops_pop(void)
{
	unsigned long flags;
	struct pci_bus_ops *bus_ops;

	spin_lock_irqsave(&inject_lock, flags);
	bus_ops = list_first_entry_or_null(&pci_bus_ops_list,
					   struct pci_bus_ops, list);
	if (bus_ops)
		list_del(&bus_ops->list);
	spin_unlock_irqrestore(&inject_lock, flags);
	return bus_ops;
}

static u32 *find_pci_config_dword(struct aer_error *err, int where,
				  int *prw1cs)
{
	int rw1cs = 0;
	u32 *target = NULL;

	if (err->pos_cap_err == -1)
		return NULL;

	switch (where - err->pos_cap_err) {
	case PCI_ERR_UNCOR_STATUS:
		target = &err->uncor_status;
		rw1cs = 1;
		break;
	case PCI_ERR_COR_STATUS:
		target = &err->cor_status;
		rw1cs = 1;
		break;
	case PCI_ERR_HEADER_LOG:
		target = &err->header_log0;
		break;
	case PCI_ERR_HEADER_LOG+4:
		target = &err->header_log1;
		break;
	case PCI_ERR_HEADER_LOG+8:
		target = &err->header_log2;
		break;
	case PCI_ERR_HEADER_LOG+12:
		target = &err->header_log3;
		break;
	case PCI_ERR_ROOT_STATUS:
		target = &err->root_status;
		rw1cs = 1;
		break;
	case PCI_ERR_ROOT_ERR_SRC:
		target = &err->source_id;
		break;
	}
	if (prw1cs)
		*prw1cs = rw1cs;
	return target;
}

static int aer_inj_read_config(struct pci_bus *bus, unsigned int devfn,
			       int where, int size, u32 *val)
{
	u32 *sim;
	struct aer_error *err;
	unsigned long flags;
	struct pci_ops *ops;
	struct pci_ops *my_ops;
	int domain;
	int rv;

	spin_lock_irqsave(&inject_lock, flags);
	if (size != sizeof(u32))
		goto out;
	domain = pci_domain_nr(bus);
	if (domain < 0)
		goto out;
	err = __find_aer_error(domain, bus->number, devfn);
	if (!err)
		goto out;

	sim = find_pci_config_dword(err, where, NULL);
	if (sim) {
		*val = *sim;
		spin_unlock_irqrestore(&inject_lock, flags);
		return 0;
	}
out:
	ops = __find_pci_bus_ops(bus);
	/*
	 * pci_lock must already be held, so we can directly
	 * manipulate bus->ops.  Many config access functions,
	 * including pci_generic_config_read() require the original
	 * bus->ops be installed to function, so temporarily put them
	 * back.
	 */
	my_ops = bus->ops;
	bus->ops = ops;
	rv = ops->read(bus, devfn, where, size, val);
	bus->ops = my_ops;
	spin_unlock_irqrestore(&inject_lock, flags);
	return rv;
}

static int aer_inj_write_config(struct pci_bus *bus, unsigned int devfn,
				int where, int size, u32 val)
{
	u32 *sim;
	struct aer_error *err;
	unsigned long flags;
	int rw1cs;
	struct pci_ops *ops;
	struct pci_ops *my_ops;
	int domain;
	int rv;

	spin_lock_irqsave(&inject_lock, flags);
	if (size != sizeof(u32))
		goto out;
	domain = pci_domain_nr(bus);
	if (domain < 0)
		goto out;
	err = __find_aer_error(domain, bus->number, devfn);
	if (!err)
		goto out;

	sim = find_pci_config_dword(err, where, &rw1cs);
	if (sim) {
		if (rw1cs)
			*sim ^= val;
		else
			*sim = val;
		spin_unlock_irqrestore(&inject_lock, flags);
		return 0;
	}
out:
	ops = __find_pci_bus_ops(bus);
	/*
	 * pci_lock must already be held, so we can directly
	 * manipulate bus->ops.  Many config access functions,
	 * including pci_generic_config_write() require the original
	 * bus->ops be installed to function, so temporarily put them
	 * back.
	 */
	my_ops = bus->ops;
	bus->ops = ops;
	rv = ops->write(bus, devfn, where, size, val);
	bus->ops = my_ops;
	spin_unlock_irqrestore(&inject_lock, flags);
	return rv;
}

static struct pci_ops aer_inj_pci_ops = {
	.read = aer_inj_read_config,
	.write = aer_inj_write_config,
};

static void pci_bus_ops_init(struct pci_bus_ops *bus_ops,
			     struct pci_bus *bus,
			     struct pci_ops *ops)
{
	INIT_LIST_HEAD(&bus_ops->list);
	bus_ops->bus = bus;
	bus_ops->ops = ops;
}

static int pci_bus_set_aer_ops(struct pci_bus *bus)
{
	struct pci_ops *ops;
	struct pci_bus_ops *bus_ops;
	unsigned long flags;

	bus_ops = kmalloc(sizeof(*bus_ops), GFP_KERNEL);
	if (!bus_ops)
		return -ENOMEM;
	ops = pci_bus_set_ops(bus, &aer_inj_pci_ops);
	spin_lock_irqsave(&inject_lock, flags);
	if (ops == &aer_inj_pci_ops)
		goto out;
	pci_bus_ops_init(bus_ops, bus, ops);
	list_add(&bus_ops->list, &pci_bus_ops_list);
	bus_ops = NULL;
out:
	spin_unlock_irqrestore(&inject_lock, flags);
	kfree(bus_ops);
	return 0;
}

static int find_aer_device_iter(struct device *device, void *data)
{
	struct pcie_device **result = data;
	struct pcie_device *pcie_dev;

	if (device->bus == &pcie_port_bus_type) {
		pcie_dev = to_pcie_device(device);
		if (pcie_dev->service & PCIE_PORT_SERVICE_AER) {
			*result = pcie_dev;
			return 1;
		}
	}
	return 0;
}

static int find_aer_device(struct pci_dev *dev, struct pcie_device **result)
{
	return device_for_each_child(&dev->dev, result, find_aer_device_iter);
}

static int aer_inject(struct aer_error_inj *einj)
{
	struct aer_error *err, *rperr;
	struct aer_error *err_alloc = NULL, *rperr_alloc = NULL;
	struct pci_dev *dev, *rpdev;
	struct pcie_device *edev;
	unsigned long flags;
	unsigned int devfn = PCI_DEVFN(einj->dev, einj->fn);
	int pos_cap_err, rp_pos_cap_err;
	u32 sever, cor_mask, uncor_mask, cor_mask_orig = 0, uncor_mask_orig = 0;
	int ret = 0;

	dev = pci_get_domain_bus_and_slot(einj->domain, einj->bus, devfn);
	if (!dev)
		return -ENODEV;
	rpdev = pcie_find_root_port(dev);
	if (!rpdev) {
		dev_err(&dev->dev, "aer_inject: Root port not found\n");
		ret = -ENODEV;
		goto out_put;
	}

	pos_cap_err = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
	if (!pos_cap_err) {
		dev_err(&dev->dev, "aer_inject: Device doesn't support AER\n");
		ret = -EPROTONOSUPPORT;
		goto out_put;
	}
	pci_read_config_dword(dev, pos_cap_err + PCI_ERR_UNCOR_SEVER, &sever);
	pci_read_config_dword(dev, pos_cap_err + PCI_ERR_COR_MASK, &cor_mask);
	pci_read_config_dword(dev, pos_cap_err + PCI_ERR_UNCOR_MASK,
			      &uncor_mask);

	rp_pos_cap_err = pci_find_ext_capability(rpdev, PCI_EXT_CAP_ID_ERR);
	if (!rp_pos_cap_err) {
		dev_err(&rpdev->dev,
			"aer_inject: Root port doesn't support AER\n");
		ret = -EPROTONOSUPPORT;
		goto out_put;
	}

	err_alloc =  kzalloc(sizeof(struct aer_error), GFP_KERNEL);
	if (!err_alloc) {
		ret = -ENOMEM;
		goto out_put;
	}
	rperr_alloc =  kzalloc(sizeof(struct aer_error), GFP_KERNEL);
	if (!rperr_alloc) {
		ret = -ENOMEM;
		goto out_put;
	}

	if (aer_mask_override) {
		cor_mask_orig = cor_mask;
		cor_mask &= !(einj->cor_status);
		pci_write_config_dword(dev, pos_cap_err + PCI_ERR_COR_MASK,
				       cor_mask);

		uncor_mask_orig = uncor_mask;
		uncor_mask &= !(einj->uncor_status);
		pci_write_config_dword(dev, pos_cap_err + PCI_ERR_UNCOR_MASK,
				       uncor_mask);
	}

	spin_lock_irqsave(&inject_lock, flags);

	err = __find_aer_error_by_dev(dev);
	if (!err) {
		err = err_alloc;
		err_alloc = NULL;
		aer_error_init(err, einj->domain, einj->bus, devfn,
			       pos_cap_err);
		list_add(&err->list, &einjected);
	}
	err->uncor_status |= einj->uncor_status;
	err->cor_status |= einj->cor_status;
	err->header_log0 = einj->header_log0;
	err->header_log1 = einj->header_log1;
	err->header_log2 = einj->header_log2;
	err->header_log3 = einj->header_log3;

	if (!aer_mask_override && einj->cor_status &&
	    !(einj->cor_status & ~cor_mask)) {
		ret = -EINVAL;
		dev_warn(&dev->dev,
			 "aer_inject: The correctable error(s) is masked by device\n");
		spin_unlock_irqrestore(&inject_lock, flags);
		goto out_put;
	}
	if (!aer_mask_override && einj->uncor_status &&
	    !(einj->uncor_status & ~uncor_mask)) {
		ret = -EINVAL;
		dev_warn(&dev->dev,
			 "aer_inject: The uncorrectable error(s) is masked by device\n");
		spin_unlock_irqrestore(&inject_lock, flags);
		goto out_put;
	}

	rperr = __find_aer_error_by_dev(rpdev);
	if (!rperr) {
		rperr = rperr_alloc;
		rperr_alloc = NULL;
		aer_error_init(rperr, pci_domain_nr(rpdev->bus),
			       rpdev->bus->number, rpdev->devfn,
			       rp_pos_cap_err);
		list_add(&rperr->list, &einjected);
	}
	if (einj->cor_status) {
		if (rperr->root_status & PCI_ERR_ROOT_COR_RCV)
			rperr->root_status |= PCI_ERR_ROOT_MULTI_COR_RCV;
		else
			rperr->root_status |= PCI_ERR_ROOT_COR_RCV;
		rperr->source_id &= 0xffff0000;
		rperr->source_id |= (einj->bus << 8) | devfn;
	}
	if (einj->uncor_status) {
		if (rperr->root_status & PCI_ERR_ROOT_UNCOR_RCV)
			rperr->root_status |= PCI_ERR_ROOT_MULTI_UNCOR_RCV;
		if (sever & einj->uncor_status) {
			rperr->root_status |= PCI_ERR_ROOT_FATAL_RCV;
			if (!(rperr->root_status & PCI_ERR_ROOT_UNCOR_RCV))
				rperr->root_status |= PCI_ERR_ROOT_FIRST_FATAL;
		} else
			rperr->root_status |= PCI_ERR_ROOT_NONFATAL_RCV;
		rperr->root_status |= PCI_ERR_ROOT_UNCOR_RCV;
		rperr->source_id &= 0x0000ffff;
		rperr->source_id |= ((einj->bus << 8) | devfn) << 16;
	}
	spin_unlock_irqrestore(&inject_lock, flags);

	if (aer_mask_override) {
		pci_write_config_dword(dev, pos_cap_err + PCI_ERR_COR_MASK,
				       cor_mask_orig);
		pci_write_config_dword(dev, pos_cap_err + PCI_ERR_UNCOR_MASK,
				       uncor_mask_orig);
	}

	ret = pci_bus_set_aer_ops(dev->bus);
	if (ret)
		goto out_put;
	ret = pci_bus_set_aer_ops(rpdev->bus);
	if (ret)
		goto out_put;

	if (find_aer_device(rpdev, &edev)) {
		if (!get_service_data(edev)) {
			dev_warn(&edev->device,
				 "aer_inject: AER service is not initialized\n");
			ret = -EPROTONOSUPPORT;
			goto out_put;
		}
		dev_info(&edev->device,
			 "aer_inject: Injecting errors %08x/%08x into device %s\n",
			 einj->cor_status, einj->uncor_status, pci_name(dev));
		aer_irq(-1, edev);
	} else {
		dev_err(&rpdev->dev, "aer_inject: AER device not found\n");
		ret = -ENODEV;
	}
out_put:
	kfree(err_alloc);
	kfree(rperr_alloc);
	pci_dev_put(dev);
	return ret;
}

static ssize_t aer_inject_write(struct file *filp, const char __user *ubuf,
				size_t usize, loff_t *off)
{
	struct aer_error_inj einj;
	int ret;

	if (!capable(CAP_SYS_ADMIN))
		return -EPERM;
	if (usize < offsetof(struct aer_error_inj, domain) ||
	    usize > sizeof(einj))
		return -EINVAL;

	memset(&einj, 0, sizeof(einj));
	if (copy_from_user(&einj, ubuf, usize))
		return -EFAULT;

	ret = aer_inject(&einj);
	return ret ? ret : usize;
}

static const struct file_operations aer_inject_fops = {
	.write = aer_inject_write,
	.owner = THIS_MODULE,
	.llseek = noop_llseek,
};

static struct miscdevice aer_inject_device = {
	.minor = MISC_DYNAMIC_MINOR,
	.name = "aer_inject",
	.fops = &aer_inject_fops,
};

static int __init aer_inject_init(void)
{
	return misc_register(&aer_inject_device);
}

static void __exit aer_inject_exit(void)
{
	struct aer_error *err, *err_next;
	unsigned long flags;
	struct pci_bus_ops *bus_ops;

	misc_deregister(&aer_inject_device);

	while ((bus_ops = pci_bus_ops_pop())) {
		pci_bus_set_ops(bus_ops->bus, bus_ops->ops);
		kfree(bus_ops);
	}

	spin_lock_irqsave(&inject_lock, flags);
	list_for_each_entry_safe(err, err_next, &einjected, list) {
		list_del(&err->list);
		kfree(err);
	}
	spin_unlock_irqrestore(&inject_lock, flags);
}

module_init(aer_inject_init);
module_exit(aer_inject_exit);

MODULE_DESCRIPTION("PCIe AER software error injector");
MODULE_LICENSE("GPL");
Commit	Line	Data
c465def6	1	/*
45e829ea	2	* PCIe AER software error injection support.
c465def6	3	*
45e829ea	4	* Debuging PCIe AER code is quite difficult because it is hard to
c465def6 HY	5	* trigger various real hardware errors. Software based error
	6	* injection can fake almost all kinds of errors with the help of a
	7	* user space helper tool aer-inject, which can be gotten from:
	8	* http://www.kernel.org/pub/linux/utils/pci/aer-inject/
	9	*
	10	* Copyright 2009 Intel Corporation.
	11	* Huang Ying <ying.huang@intel.com>
	12	*
	13	* This program is free software; you can redistribute it and/or
	14	* modify it under the terms of the GNU General Public License
	15	* as published by the Free Software Foundation; version 2
	16	* of the License.
	17	*
	18	*/
	19
	20	#include <linux/module.h>
	21	#include <linux/init.h>
	22	#include <linux/miscdevice.h>
	23	#include <linux/pci.h>
5a0e3ad6	24	#include <linux/slab.h>
c465def6	25	#include <linux/fs.h>
c9a91883	26	#include <linux/uaccess.h>
cc5d153a	27	#include <linux/stddef.h>
3bc11851	28	#include <linux/device.h>
c465def6 HY	29	#include "aerdrv.h"
c465def6 HY	30
457d9d08	31	/* Override the existing corrected and uncorrected error masks */
90ab5ee9	32	static bool aer_mask_override;
457d9d08 PB	33	module_param(aer_mask_override, bool, 0);
457d9d08 PB	34
c9a91883	35	struct aer_error_inj {
c465def6 HY	36	u8 bus;
	37	u8 dev;
	38	u8 fn;
	39	u32 uncor_status;
	40	u32 cor_status;
	41	u32 header_log0;
	42	u32 header_log1;
	43	u32 header_log2;
	44	u32 header_log3;
28ef241f	45	u32 domain;
c465def6 HY	46	};
c465def6 HY	47
c9a91883	48	struct aer_error {
c465def6	49	struct list_head list;
28ef241f	50	u32 domain;
c465def6 HY	51	unsigned int bus;
	52	unsigned int devfn;
	53	int pos_cap_err;
	54
	55	u32 uncor_status;
	56	u32 cor_status;
	57	u32 header_log0;
	58	u32 header_log1;
	59	u32 header_log2;
	60	u32 header_log3;
	61	u32 root_status;
	62	u32 source_id;
	63	};
	64
c9a91883	65	struct pci_bus_ops {
c465def6 HY	66	struct list_head list;
	67	struct pci_bus *bus;
	68	struct pci_ops *ops;
	69	};
	70
	71	static LIST_HEAD(einjected);
	72
	73	static LIST_HEAD(pci_bus_ops_list);
	74
	75	/* Protect einjected and pci_bus_ops_list */
	76	static DEFINE_SPINLOCK(inject_lock);
	77
28ef241f	78	static void aer_error_init(struct aer_error *err, u32 domain,
cc5d153a AP	79	unsigned int bus, unsigned int devfn,
cc5d153a AP	80	int pos_cap_err)
c465def6 HY	81	{
c465def6 HY	82	INIT_LIST_HEAD(&err->list);
cc5d153a	83	err->domain = domain;
c465def6 HY	84	err->bus = bus;
	85	err->devfn = devfn;
	86	err->pos_cap_err = pos_cap_err;
	87	}
	88
	89	/* inject_lock must be held before calling */
28ef241f	90	static struct aer_error *__find_aer_error(u32 domain, unsigned int bus,
cc5d153a	91	unsigned int devfn)
c465def6 HY	92	{
	93	struct aer_error *err;
	94
	95	list_for_each_entry(err, &einjected, list) {
cc5d153a AP	96	if (domain == err->domain &&
	97	bus == err->bus &&
	98	devfn == err->devfn)
c465def6 HY	99	return err;
	100	}
	101	return NULL;
	102	}
	103
	104	/* inject_lock must be held before calling */
	105	static struct aer_error __find_aer_error_by_dev(struct pci_dev dev)
	106	{
cc5d153a AP	107	int domain = pci_domain_nr(dev->bus);
	108	if (domain < 0)
	109	return NULL;
28ef241f	110	return __find_aer_error(domain, dev->bus->number, dev->devfn);
c465def6 HY	111	}
	112
	113	/* inject_lock must be held before calling */
	114	static struct pci_ops __find_pci_bus_ops(struct pci_bus bus)
	115	{
	116	struct pci_bus_ops *bus_ops;
	117
	118	list_for_each_entry(bus_ops, &pci_bus_ops_list, list) {
	119	if (bus_ops->bus == bus)
	120	return bus_ops->ops;
	121	}
	122	return NULL;
	123	}
	124
	125	static struct pci_bus_ops *pci_bus_ops_pop(void)
	126	{
	127	unsigned long flags;
0e6053dc	128	struct pci_bus_ops *bus_ops;
c465def6 HY	129
c465def6 HY	130	spin_lock_irqsave(&inject_lock, flags);
0e6053dc GT	131	bus_ops = list_first_entry_or_null(&pci_bus_ops_list,
	132	struct pci_bus_ops, list);
	133	if (bus_ops)
	134	list_del(&bus_ops->list);
c465def6 HY	135	spin_unlock_irqrestore(&inject_lock, flags);
	136	return bus_ops;
	137	}
	138
	139	static u32 find_pci_config_dword(struct aer_error err, int where,
	140	int *prw1cs)
	141	{
	142	int rw1cs = 0;
	143	u32 *target = NULL;
	144
	145	if (err->pos_cap_err == -1)
	146	return NULL;
	147
	148	switch (where - err->pos_cap_err) {
	149	case PCI_ERR_UNCOR_STATUS:
	150	target = &err->uncor_status;
	151	rw1cs = 1;
	152	break;
	153	case PCI_ERR_COR_STATUS:
	154	target = &err->cor_status;
	155	rw1cs = 1;
	156	break;
	157	case PCI_ERR_HEADER_LOG:
	158	target = &err->header_log0;
	159	break;
	160	case PCI_ERR_HEADER_LOG+4:
	161	target = &err->header_log1;
	162	break;
	163	case PCI_ERR_HEADER_LOG+8:
c9a91883	164	target = &err->header_log2;
c465def6 HY	165	break;
	166	case PCI_ERR_HEADER_LOG+12:
	167	target = &err->header_log3;
	168	break;
	169	case PCI_ERR_ROOT_STATUS:
	170	target = &err->root_status;
	171	rw1cs = 1;
	172	break;
f647a44f	173	case PCI_ERR_ROOT_ERR_SRC:
c465def6 HY	174	target = &err->source_id;
	175	break;
	176	}
	177	if (prw1cs)
	178	*prw1cs = rw1cs;
	179	return target;
	180	}
	181
3b0a6d1a BH	182	static int aer_inj_read_config(struct pci_bus *bus, unsigned int devfn,
3b0a6d1a BH	183	int where, int size, u32 *val)
c465def6 HY	184	{
	185	u32 *sim;
	186	struct aer_error *err;
	187	unsigned long flags;
	188	struct pci_ops *ops;
7e8fbdc6	189	struct pci_ops *my_ops;
cc5d153a	190	int domain;
7e8fbdc6	191	int rv;
c465def6 HY	192
	193	spin_lock_irqsave(&inject_lock, flags);
	194	if (size != sizeof(u32))
	195	goto out;
cc5d153a AP	196	domain = pci_domain_nr(bus);
	197	if (domain < 0)
	198	goto out;
28ef241f	199	err = __find_aer_error(domain, bus->number, devfn);
c465def6 HY	200	if (!err)
	201	goto out;
	202
	203	sim = find_pci_config_dword(err, where, NULL);
	204	if (sim) {
	205	val = sim;
	206	spin_unlock_irqrestore(&inject_lock, flags);
	207	return 0;
	208	}
	209	out:
	210	ops = __find_pci_bus_ops(bus);
7e8fbdc6 DD	211	/*
	212	* pci_lock must already be held, so we can directly
	213	* manipulate bus->ops. Many config access functions,
	214	* including pci_generic_config_read() require the original
	215	* bus->ops be installed to function, so temporarily put them
	216	* back.
	217	*/
	218	my_ops = bus->ops;
	219	bus->ops = ops;
	220	rv = ops->read(bus, devfn, where, size, val);
	221	bus->ops = my_ops;
c465def6	222	spin_unlock_irqrestore(&inject_lock, flags);
7e8fbdc6	223	return rv;
c465def6 HY	224	}
c465def6 HY	225
3b0a6d1a BH	226	static int aer_inj_write_config(struct pci_bus *bus, unsigned int devfn,
3b0a6d1a BH	227	int where, int size, u32 val)
c465def6 HY	228	{
	229	u32 *sim;
	230	struct aer_error *err;
	231	unsigned long flags;
	232	int rw1cs;
	233	struct pci_ops *ops;
7e8fbdc6	234	struct pci_ops *my_ops;
cc5d153a	235	int domain;
7e8fbdc6	236	int rv;
c465def6 HY	237
	238	spin_lock_irqsave(&inject_lock, flags);
	239	if (size != sizeof(u32))
	240	goto out;
cc5d153a AP	241	domain = pci_domain_nr(bus);
	242	if (domain < 0)
	243	goto out;
28ef241f	244	err = __find_aer_error(domain, bus->number, devfn);
c465def6 HY	245	if (!err)
	246	goto out;
	247
	248	sim = find_pci_config_dword(err, where, &rw1cs);
	249	if (sim) {
	250	if (rw1cs)
	251	*sim ^= val;
	252	else
	253	*sim = val;
	254	spin_unlock_irqrestore(&inject_lock, flags);
	255	return 0;
	256	}
	257	out:
	258	ops = __find_pci_bus_ops(bus);
7e8fbdc6 DD	259	/*
	260	* pci_lock must already be held, so we can directly
	261	* manipulate bus->ops. Many config access functions,
	262	* including pci_generic_config_write() require the original
	263	* bus->ops be installed to function, so temporarily put them
	264	* back.
	265	*/
	266	my_ops = bus->ops;
	267	bus->ops = ops;
	268	rv = ops->write(bus, devfn, where, size, val);
	269	bus->ops = my_ops;
c465def6	270	spin_unlock_irqrestore(&inject_lock, flags);
7e8fbdc6	271	return rv;
c465def6 HY	272	}
c465def6 HY	273
3b0a6d1a BH	274	static struct pci_ops aer_inj_pci_ops = {
	275	.read = aer_inj_read_config,
	276	.write = aer_inj_write_config,
c465def6 HY	277	};
	278
	279	static void pci_bus_ops_init(struct pci_bus_ops *bus_ops,
	280	struct pci_bus *bus,
	281	struct pci_ops *ops)
	282	{
	283	INIT_LIST_HEAD(&bus_ops->list);
	284	bus_ops->bus = bus;
	285	bus_ops->ops = ops;
	286	}
	287
	288	static int pci_bus_set_aer_ops(struct pci_bus *bus)
	289	{
	290	struct pci_ops *ops;
	291	struct pci_bus_ops *bus_ops;
	292	unsigned long flags;
	293
	294	bus_ops = kmalloc(sizeof(*bus_ops), GFP_KERNEL);
	295	if (!bus_ops)
	296	return -ENOMEM;
3b0a6d1a	297	ops = pci_bus_set_ops(bus, &aer_inj_pci_ops);
c465def6	298	spin_lock_irqsave(&inject_lock, flags);
3b0a6d1a	299	if (ops == &aer_inj_pci_ops)
c465def6 HY	300	goto out;
	301	pci_bus_ops_init(bus_ops, bus, ops);
	302	list_add(&bus_ops->list, &pci_bus_ops_list);
	303	bus_ops = NULL;
	304	out:
	305	spin_unlock_irqrestore(&inject_lock, flags);
c9a91883	306	kfree(bus_ops);
c465def6 HY	307	return 0;
	308	}
	309
c465def6 HY	310	static int find_aer_device_iter(struct device device, void data)
	311	{
	312	struct pcie_device **result = data;
	313	struct pcie_device *pcie_dev;
	314
	315	if (device->bus == &pcie_port_bus_type) {
	316	pcie_dev = to_pcie_device(device);
	317	if (pcie_dev->service & PCIE_PORT_SERVICE_AER) {
	318	*result = pcie_dev;
	319	return 1;
	320	}
	321	}
	322	return 0;
	323	}
	324
	325	static int find_aer_device(struct pci_dev dev, struct pcie_device *result)
	326	{
	327	return device_for_each_child(&dev->dev, result, find_aer_device_iter);
	328	}
	329
	330	static int aer_inject(struct aer_error_inj *einj)
	331	{
	332	struct aer_error err, rperr;
	333	struct aer_error err_alloc = NULL, rperr_alloc = NULL;
	334	struct pci_dev dev, rpdev;
	335	struct pcie_device *edev;
	336	unsigned long flags;
	337	unsigned int devfn = PCI_DEVFN(einj->dev, einj->fn);
	338	int pos_cap_err, rp_pos_cap_err;
40294d8f	339	u32 sever, cor_mask, uncor_mask, cor_mask_orig = 0, uncor_mask_orig = 0;
c465def6 HY	340	int ret = 0;
c465def6 HY	341
28ef241f	342	dev = pci_get_domain_bus_and_slot(einj->domain, einj->bus, devfn);
c465def6	343	if (!dev)
1d024355	344	return -ENODEV;
c465def6 HY	345	rpdev = pcie_find_root_port(dev);
c465def6 HY	346	if (!rpdev) {
96b45ea5	347	dev_err(&dev->dev, "aer_inject: Root port not found\n");
e82b14bd	348	ret = -ENODEV;
c465def6 HY	349	goto out_put;
	350	}
	351
	352	pos_cap_err = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
	353	if (!pos_cap_err) {
96b45ea5	354	dev_err(&dev->dev, "aer_inject: Device doesn't support AER\n");
20ac75e5	355	ret = -EPROTONOSUPPORT;
c465def6 HY	356	goto out_put;
	357	}
	358	pci_read_config_dword(dev, pos_cap_err + PCI_ERR_UNCOR_SEVER, &sever);
bd1f46de AP	359	pci_read_config_dword(dev, pos_cap_err + PCI_ERR_COR_MASK, &cor_mask);
	360	pci_read_config_dword(dev, pos_cap_err + PCI_ERR_UNCOR_MASK,
	361	&uncor_mask);
c465def6 HY	362
	363	rp_pos_cap_err = pci_find_ext_capability(rpdev, PCI_EXT_CAP_ID_ERR);
	364	if (!rp_pos_cap_err) {
96b45ea5 JD	365	dev_err(&rpdev->dev,
96b45ea5 JD	366	"aer_inject: Root port doesn't support AER\n");
20ac75e5	367	ret = -EPROTONOSUPPORT;
c465def6 HY	368	goto out_put;
	369	}
	370
	371	err_alloc = kzalloc(sizeof(struct aer_error), GFP_KERNEL);
	372	if (!err_alloc) {
	373	ret = -ENOMEM;
	374	goto out_put;
	375	}
	376	rperr_alloc = kzalloc(sizeof(struct aer_error), GFP_KERNEL);
	377	if (!rperr_alloc) {
	378	ret = -ENOMEM;
	379	goto out_put;
	380	}
	381
457d9d08 PB	382	if (aer_mask_override) {
	383	cor_mask_orig = cor_mask;
	384	cor_mask &= !(einj->cor_status);
	385	pci_write_config_dword(dev, pos_cap_err + PCI_ERR_COR_MASK,
	386	cor_mask);
	387
	388	uncor_mask_orig = uncor_mask;
	389	uncor_mask &= !(einj->uncor_status);
	390	pci_write_config_dword(dev, pos_cap_err + PCI_ERR_UNCOR_MASK,
	391	uncor_mask);
	392	}
	393
c465def6 HY	394	spin_lock_irqsave(&inject_lock, flags);
	395
	396	err = __find_aer_error_by_dev(dev);
	397	if (!err) {
	398	err = err_alloc;
	399	err_alloc = NULL;
cc5d153a AP	400	aer_error_init(err, einj->domain, einj->bus, devfn,
cc5d153a AP	401	pos_cap_err);
c465def6 HY	402	list_add(&err->list, &einjected);
	403	}
	404	err->uncor_status \|= einj->uncor_status;
	405	err->cor_status \|= einj->cor_status;
	406	err->header_log0 = einj->header_log0;
	407	err->header_log1 = einj->header_log1;
	408	err->header_log2 = einj->header_log2;
	409	err->header_log3 = einj->header_log3;
	410
457d9d08 PB	411	if (!aer_mask_override && einj->cor_status &&
457d9d08 PB	412	!(einj->cor_status & ~cor_mask)) {
b49bfd32	413	ret = -EINVAL;
3bc11851 JD	414	dev_warn(&dev->dev,
3bc11851 JD	415	"aer_inject: The correctable error(s) is masked by device\n");
b49bfd32 YS	416	spin_unlock_irqrestore(&inject_lock, flags);
	417	goto out_put;
	418	}
457d9d08 PB	419	if (!aer_mask_override && einj->uncor_status &&
457d9d08 PB	420	!(einj->uncor_status & ~uncor_mask)) {
b49bfd32	421	ret = -EINVAL;
3bc11851 JD	422	dev_warn(&dev->dev,
3bc11851 JD	423	"aer_inject: The uncorrectable error(s) is masked by device\n");
b49bfd32 YS	424	spin_unlock_irqrestore(&inject_lock, flags);
	425	goto out_put;
	426	}
	427
c465def6 HY	428	rperr = __find_aer_error_by_dev(rpdev);
	429	if (!rperr) {
	430	rperr = rperr_alloc;
	431	rperr_alloc = NULL;
cc5d153a AP	432	aer_error_init(rperr, pci_domain_nr(rpdev->bus),
cc5d153a AP	433	rpdev->bus->number, rpdev->devfn,
c465def6 HY	434	rp_pos_cap_err);
	435	list_add(&rperr->list, &einjected);
	436	}
	437	if (einj->cor_status) {
	438	if (rperr->root_status & PCI_ERR_ROOT_COR_RCV)
	439	rperr->root_status \|= PCI_ERR_ROOT_MULTI_COR_RCV;
	440	else
	441	rperr->root_status \|= PCI_ERR_ROOT_COR_RCV;
	442	rperr->source_id &= 0xffff0000;
	443	rperr->source_id \|= (einj->bus << 8) \| devfn;
	444	}
	445	if (einj->uncor_status) {
	446	if (rperr->root_status & PCI_ERR_ROOT_UNCOR_RCV)
	447	rperr->root_status \|= PCI_ERR_ROOT_MULTI_UNCOR_RCV;
	448	if (sever & einj->uncor_status) {
	449	rperr->root_status \|= PCI_ERR_ROOT_FATAL_RCV;
	450	if (!(rperr->root_status & PCI_ERR_ROOT_UNCOR_RCV))
	451	rperr->root_status \|= PCI_ERR_ROOT_FIRST_FATAL;
	452	} else
	453	rperr->root_status \|= PCI_ERR_ROOT_NONFATAL_RCV;
	454	rperr->root_status \|= PCI_ERR_ROOT_UNCOR_RCV;
	455	rperr->source_id &= 0x0000ffff;
	456	rperr->source_id \|= ((einj->bus << 8) \| devfn) << 16;
	457	}
	458	spin_unlock_irqrestore(&inject_lock, flags);
	459
457d9d08 PB	460	if (aer_mask_override) {
	461	pci_write_config_dword(dev, pos_cap_err + PCI_ERR_COR_MASK,
	462	cor_mask_orig);
	463	pci_write_config_dword(dev, pos_cap_err + PCI_ERR_UNCOR_MASK,
	464	uncor_mask_orig);
	465	}
	466
c465def6 HY	467	ret = pci_bus_set_aer_ops(dev->bus);
	468	if (ret)
	469	goto out_put;
	470	ret = pci_bus_set_aer_ops(rpdev->bus);
	471	if (ret)
	472	goto out_put;
	473
46256f83 YS	474	if (find_aer_device(rpdev, &edev)) {
46256f83 YS	475	if (!get_service_data(edev)) {
3bc11851 JD	476	dev_warn(&edev->device,
3bc11851 JD	477	"aer_inject: AER service is not initialized\n");
20ac75e5	478	ret = -EPROTONOSUPPORT;
46256f83 YS	479	goto out_put;
46256f83 YS	480	}
8e47e15e JD	481	dev_info(&edev->device,
	482	"aer_inject: Injecting errors %08x/%08x into device %s\n",
	483	einj->cor_status, einj->uncor_status, pci_name(dev));
c465def6	484	aer_irq(-1, edev);
96b45ea5 JD	485	} else {
96b45ea5 JD	486	dev_err(&rpdev->dev, "aer_inject: AER device not found\n");
20ac75e5	487	ret = -ENODEV;
96b45ea5	488	}
c465def6	489	out_put:
c9a91883 HS	490	kfree(err_alloc);
c9a91883 HS	491	kfree(rperr_alloc);
c465def6 HY	492	pci_dev_put(dev);
	493	return ret;
	494	}
	495
	496	static ssize_t aer_inject_write(struct file filp, const char __user ubuf,
	497	size_t usize, loff_t *off)
	498	{
	499	struct aer_error_inj einj;
	500	int ret;
	501
	502	if (!capable(CAP_SYS_ADMIN))
	503	return -EPERM;
cc5d153a AP	504	if (usize < offsetof(struct aer_error_inj, domain) \|\|
cc5d153a AP	505	usize > sizeof(einj))
c465def6 HY	506	return -EINVAL;
c465def6 HY	507
cc5d153a	508	memset(&einj, 0, sizeof(einj));
c465def6 HY	509	if (copy_from_user(&einj, ubuf, usize))
	510	return -EFAULT;
	511
	512	ret = aer_inject(&einj);
	513	return ret ? ret : usize;
	514	}
	515
	516	static const struct file_operations aer_inject_fops = {
	517	.write = aer_inject_write,
	518	.owner = THIS_MODULE,
6038f373	519	.llseek = noop_llseek,
c465def6 HY	520	};
	521
	522	static struct miscdevice aer_inject_device = {
	523	.minor = MISC_DYNAMIC_MINOR,
	524	.name = "aer_inject",
	525	.fops = &aer_inject_fops,
	526	};
	527
	528	static int __init aer_inject_init(void)
	529	{
	530	return misc_register(&aer_inject_device);
	531	}
	532
	533	static void __exit aer_inject_exit(void)
	534	{
	535	struct aer_error err, err_next;
	536	unsigned long flags;
	537	struct pci_bus_ops *bus_ops;
	538
	539	misc_deregister(&aer_inject_device);
	540
	541	while ((bus_ops = pci_bus_ops_pop())) {
	542	pci_bus_set_ops(bus_ops->bus, bus_ops->ops);
	543	kfree(bus_ops);
	544	}
	545
	546	spin_lock_irqsave(&inject_lock, flags);
476f644e	547	list_for_each_entry_safe(err, err_next, &einjected, list) {
c465def6 HY	548	list_del(&err->list);
	549	kfree(err);
	550	}
	551	spin_unlock_irqrestore(&inject_lock, flags);
	552	}
	553
	554	module_init(aer_inject_init);
	555	module_exit(aer_inject_exit);
	556
7e8af37a	557	MODULE_DESCRIPTION("PCIe AER software error injector");
c465def6	558	MODULE_LICENSE("GPL");