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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
7d715a6c SL |
2 | /* |
3 | * File: drivers/pci/pcie/aspm.c | |
45e829ea | 4 | * Enabling PCIe link L0s/L1 state and Clock Power Management |
7d715a6c SL |
5 | * |
6 | * Copyright (C) 2007 Intel | |
7 | * Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com) | |
8 | * Copyright (C) Shaohua Li (shaohua.li@intel.com) | |
9 | */ | |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/moduleparam.h> | |
14 | #include <linux/pci.h> | |
15 | #include <linux/pci_regs.h> | |
16 | #include <linux/errno.h> | |
17 | #include <linux/pm.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/slab.h> | |
2a42d9db | 20 | #include <linux/jiffies.h> |
987a4c78 | 21 | #include <linux/delay.h> |
7d715a6c SL |
22 | #include <linux/pci-aspm.h> |
23 | #include "../pci.h" | |
24 | ||
25 | #ifdef MODULE_PARAM_PREFIX | |
26 | #undef MODULE_PARAM_PREFIX | |
27 | #endif | |
28 | #define MODULE_PARAM_PREFIX "pcie_aspm." | |
29 | ||
ac18018a KK |
30 | /* Note: those are not register definitions */ |
31 | #define ASPM_STATE_L0S_UP (1) /* Upstream direction L0s state */ | |
32 | #define ASPM_STATE_L0S_DW (2) /* Downstream direction L0s state */ | |
33 | #define ASPM_STATE_L1 (4) /* L1 state */ | |
b2103ccb RJ |
34 | #define ASPM_STATE_L1_1 (8) /* ASPM L1.1 state */ |
35 | #define ASPM_STATE_L1_2 (0x10) /* ASPM L1.2 state */ | |
36 | #define ASPM_STATE_L1_1_PCIPM (0x20) /* PCI PM L1.1 state */ | |
37 | #define ASPM_STATE_L1_2_PCIPM (0x40) /* PCI PM L1.2 state */ | |
38 | #define ASPM_STATE_L1_SS_PCIPM (ASPM_STATE_L1_1_PCIPM | ASPM_STATE_L1_2_PCIPM) | |
39 | #define ASPM_STATE_L1_2_MASK (ASPM_STATE_L1_2 | ASPM_STATE_L1_2_PCIPM) | |
40 | #define ASPM_STATE_L1SS (ASPM_STATE_L1_1 | ASPM_STATE_L1_1_PCIPM |\ | |
41 | ASPM_STATE_L1_2_MASK) | |
ac18018a | 42 | #define ASPM_STATE_L0S (ASPM_STATE_L0S_UP | ASPM_STATE_L0S_DW) |
b2103ccb RJ |
43 | #define ASPM_STATE_ALL (ASPM_STATE_L0S | ASPM_STATE_L1 | \ |
44 | ASPM_STATE_L1SS) | |
ac18018a | 45 | |
b6c2e54d KK |
46 | struct aspm_latency { |
47 | u32 l0s; /* L0s latency (nsec) */ | |
48 | u32 l1; /* L1 latency (nsec) */ | |
7d715a6c SL |
49 | }; |
50 | ||
51 | struct pcie_link_state { | |
5cde89d8 | 52 | struct pci_dev *pdev; /* Upstream component of the Link */ |
b5a0a9b5 | 53 | struct pci_dev *downstream; /* Downstream component, function 0 */ |
5c92ffb1 | 54 | struct pcie_link_state *root; /* pointer to the root port link */ |
5cde89d8 KK |
55 | struct pcie_link_state *parent; /* pointer to the parent Link state */ |
56 | struct list_head sibling; /* node in link_list */ | |
57 | struct list_head children; /* list of child link states */ | |
58 | struct list_head link; /* node in parent's children list */ | |
7d715a6c SL |
59 | |
60 | /* ASPM state */ | |
b2103ccb RJ |
61 | u32 aspm_support:7; /* Supported ASPM state */ |
62 | u32 aspm_enabled:7; /* Enabled ASPM state */ | |
63 | u32 aspm_capable:7; /* Capable ASPM state with latency */ | |
64 | u32 aspm_default:7; /* Default ASPM state by BIOS */ | |
65 | u32 aspm_disable:7; /* Disabled ASPM state */ | |
80bfdbe3 | 66 | |
4d246e45 KK |
67 | /* Clock PM state */ |
68 | u32 clkpm_capable:1; /* Clock PM capable? */ | |
69 | u32 clkpm_enabled:1; /* Current Clock PM state */ | |
70 | u32 clkpm_default:1; /* Default Clock PM state by BIOS */ | |
71 | ||
ac18018a KK |
72 | /* Exit latencies */ |
73 | struct aspm_latency latency_up; /* Upstream direction exit latency */ | |
74 | struct aspm_latency latency_dw; /* Downstream direction exit latency */ | |
7d715a6c | 75 | /* |
b6c2e54d KK |
76 | * Endpoint acceptable latencies. A pcie downstream port only |
77 | * has one slot under it, so at most there are 8 functions. | |
7d715a6c | 78 | */ |
b6c2e54d | 79 | struct aspm_latency acceptable[8]; |
f1f0366d RJ |
80 | |
81 | /* L1 PM Substate info */ | |
82 | struct { | |
83 | u32 up_cap_ptr; /* L1SS cap ptr in upstream dev */ | |
84 | u32 dw_cap_ptr; /* L1SS cap ptr in downstream dev */ | |
85 | u32 ctl1; /* value to be programmed in ctl1 */ | |
86 | u32 ctl2; /* value to be programmed in ctl2 */ | |
87 | } l1ss; | |
7d715a6c SL |
88 | }; |
89 | ||
3c076351 | 90 | static int aspm_disabled, aspm_force; |
8b8bae90 | 91 | static bool aspm_support_enabled = true; |
7d715a6c SL |
92 | static DEFINE_MUTEX(aspm_lock); |
93 | static LIST_HEAD(link_list); | |
94 | ||
95 | #define POLICY_DEFAULT 0 /* BIOS default setting */ | |
96 | #define POLICY_PERFORMANCE 1 /* high performance */ | |
97 | #define POLICY_POWERSAVE 2 /* high power saving */ | |
b2103ccb | 98 | #define POLICY_POWER_SUPERSAVE 3 /* possibly even more power saving */ |
ad71c962 MG |
99 | |
100 | #ifdef CONFIG_PCIEASPM_PERFORMANCE | |
101 | static int aspm_policy = POLICY_PERFORMANCE; | |
102 | #elif defined CONFIG_PCIEASPM_POWERSAVE | |
103 | static int aspm_policy = POLICY_POWERSAVE; | |
b2103ccb RJ |
104 | #elif defined CONFIG_PCIEASPM_POWER_SUPERSAVE |
105 | static int aspm_policy = POLICY_POWER_SUPERSAVE; | |
ad71c962 | 106 | #else |
7d715a6c | 107 | static int aspm_policy; |
ad71c962 MG |
108 | #endif |
109 | ||
7d715a6c SL |
110 | static const char *policy_str[] = { |
111 | [POLICY_DEFAULT] = "default", | |
112 | [POLICY_PERFORMANCE] = "performance", | |
b2103ccb RJ |
113 | [POLICY_POWERSAVE] = "powersave", |
114 | [POLICY_POWER_SUPERSAVE] = "powersupersave" | |
7d715a6c SL |
115 | }; |
116 | ||
987a4c78 AP |
117 | #define LINK_RETRAIN_TIMEOUT HZ |
118 | ||
5aa63583 | 119 | static int policy_to_aspm_state(struct pcie_link_state *link) |
7d715a6c | 120 | { |
7d715a6c SL |
121 | switch (aspm_policy) { |
122 | case POLICY_PERFORMANCE: | |
123 | /* Disable ASPM and Clock PM */ | |
124 | return 0; | |
125 | case POLICY_POWERSAVE: | |
126 | /* Enable ASPM L0s/L1 */ | |
b2103ccb RJ |
127 | return (ASPM_STATE_L0S | ASPM_STATE_L1); |
128 | case POLICY_POWER_SUPERSAVE: | |
129 | /* Enable Everything */ | |
ac18018a | 130 | return ASPM_STATE_ALL; |
7d715a6c | 131 | case POLICY_DEFAULT: |
5aa63583 | 132 | return link->aspm_default; |
7d715a6c SL |
133 | } |
134 | return 0; | |
135 | } | |
136 | ||
5aa63583 | 137 | static int policy_to_clkpm_state(struct pcie_link_state *link) |
7d715a6c | 138 | { |
7d715a6c SL |
139 | switch (aspm_policy) { |
140 | case POLICY_PERFORMANCE: | |
141 | /* Disable ASPM and Clock PM */ | |
142 | return 0; | |
143 | case POLICY_POWERSAVE: | |
b2103ccb RJ |
144 | case POLICY_POWER_SUPERSAVE: |
145 | /* Enable Clock PM */ | |
7d715a6c SL |
146 | return 1; |
147 | case POLICY_DEFAULT: | |
5aa63583 | 148 | return link->clkpm_default; |
7d715a6c SL |
149 | } |
150 | return 0; | |
151 | } | |
152 | ||
430842e2 | 153 | static void pcie_set_clkpm_nocheck(struct pcie_link_state *link, int enable) |
7d715a6c | 154 | { |
5aa63583 KK |
155 | struct pci_dev *child; |
156 | struct pci_bus *linkbus = link->pdev->subordinate; | |
0c0cbb6c | 157 | u32 val = enable ? PCI_EXP_LNKCTL_CLKREQ_EN : 0; |
7d715a6c | 158 | |
0c0cbb6c BH |
159 | list_for_each_entry(child, &linkbus->devices, bus_list) |
160 | pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL, | |
161 | PCI_EXP_LNKCTL_CLKREQ_EN, | |
162 | val); | |
5aa63583 | 163 | link->clkpm_enabled = !!enable; |
7d715a6c SL |
164 | } |
165 | ||
430842e2 KK |
166 | static void pcie_set_clkpm(struct pcie_link_state *link, int enable) |
167 | { | |
168 | /* Don't enable Clock PM if the link is not Clock PM capable */ | |
a6c1c6f3 | 169 | if (!link->clkpm_capable) |
2f671e2d | 170 | enable = 0; |
430842e2 KK |
171 | /* Need nothing if the specified equals to current state */ |
172 | if (link->clkpm_enabled == enable) | |
173 | return; | |
174 | pcie_set_clkpm_nocheck(link, enable); | |
175 | } | |
176 | ||
8d349ace | 177 | static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist) |
7d715a6c | 178 | { |
f12eb72a | 179 | int capable = 1, enabled = 1; |
7d715a6c SL |
180 | u32 reg32; |
181 | u16 reg16; | |
5aa63583 KK |
182 | struct pci_dev *child; |
183 | struct pci_bus *linkbus = link->pdev->subordinate; | |
7d715a6c SL |
184 | |
185 | /* All functions should have the same cap and state, take the worst */ | |
5aa63583 | 186 | list_for_each_entry(child, &linkbus->devices, bus_list) { |
f12eb72a | 187 | pcie_capability_read_dword(child, PCI_EXP_LNKCAP, ®32); |
7d715a6c SL |
188 | if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) { |
189 | capable = 0; | |
190 | enabled = 0; | |
191 | break; | |
192 | } | |
f12eb72a | 193 | pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16); |
7d715a6c SL |
194 | if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN)) |
195 | enabled = 0; | |
196 | } | |
5aa63583 KK |
197 | link->clkpm_enabled = enabled; |
198 | link->clkpm_default = enabled; | |
8d349ace | 199 | link->clkpm_capable = (blacklist) ? 0 : capable; |
46bbdfa4 SL |
200 | } |
201 | ||
7d715a6c SL |
202 | /* |
203 | * pcie_aspm_configure_common_clock: check if the 2 ends of a link | |
204 | * could use common clock. If they are, configure them to use the | |
205 | * common clock. That will reduce the ASPM state exit latency. | |
206 | */ | |
5aa63583 | 207 | static void pcie_aspm_configure_common_clock(struct pcie_link_state *link) |
7d715a6c | 208 | { |
f12eb72a | 209 | int same_clock = 1; |
5aa63583 | 210 | u16 reg16, parent_reg, child_reg[8]; |
2a42d9db | 211 | unsigned long start_jiffies; |
5aa63583 KK |
212 | struct pci_dev *child, *parent = link->pdev; |
213 | struct pci_bus *linkbus = parent->subordinate; | |
7d715a6c | 214 | /* |
5aa63583 | 215 | * All functions of a slot should have the same Slot Clock |
7d715a6c | 216 | * Configuration, so just check one function |
5aa63583 KK |
217 | */ |
218 | child = list_entry(linkbus->devices.next, struct pci_dev, bus_list); | |
8b06477d | 219 | BUG_ON(!pci_is_pcie(child)); |
7d715a6c SL |
220 | |
221 | /* Check downstream component if bit Slot Clock Configuration is 1 */ | |
f12eb72a | 222 | pcie_capability_read_word(child, PCI_EXP_LNKSTA, ®16); |
7d715a6c SL |
223 | if (!(reg16 & PCI_EXP_LNKSTA_SLC)) |
224 | same_clock = 0; | |
225 | ||
226 | /* Check upstream component if bit Slot Clock Configuration is 1 */ | |
f12eb72a | 227 | pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16); |
7d715a6c SL |
228 | if (!(reg16 & PCI_EXP_LNKSTA_SLC)) |
229 | same_clock = 0; | |
230 | ||
231 | /* Configure downstream component, all functions */ | |
5aa63583 | 232 | list_for_each_entry(child, &linkbus->devices, bus_list) { |
f12eb72a | 233 | pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16); |
5aa63583 | 234 | child_reg[PCI_FUNC(child->devfn)] = reg16; |
7d715a6c SL |
235 | if (same_clock) |
236 | reg16 |= PCI_EXP_LNKCTL_CCC; | |
237 | else | |
238 | reg16 &= ~PCI_EXP_LNKCTL_CCC; | |
f12eb72a | 239 | pcie_capability_write_word(child, PCI_EXP_LNKCTL, reg16); |
7d715a6c SL |
240 | } |
241 | ||
242 | /* Configure upstream component */ | |
f12eb72a | 243 | pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16); |
2a42d9db | 244 | parent_reg = reg16; |
7d715a6c SL |
245 | if (same_clock) |
246 | reg16 |= PCI_EXP_LNKCTL_CCC; | |
247 | else | |
248 | reg16 &= ~PCI_EXP_LNKCTL_CCC; | |
f12eb72a | 249 | pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16); |
7d715a6c | 250 | |
5aa63583 | 251 | /* Retrain link */ |
7d715a6c | 252 | reg16 |= PCI_EXP_LNKCTL_RL; |
f12eb72a | 253 | pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16); |
7d715a6c | 254 | |
5aa63583 | 255 | /* Wait for link training end. Break out after waiting for timeout */ |
2a42d9db | 256 | start_jiffies = jiffies; |
987a4c78 | 257 | for (;;) { |
f12eb72a | 258 | pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16); |
7d715a6c SL |
259 | if (!(reg16 & PCI_EXP_LNKSTA_LT)) |
260 | break; | |
987a4c78 AP |
261 | if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) |
262 | break; | |
263 | msleep(1); | |
7d715a6c | 264 | } |
5aa63583 KK |
265 | if (!(reg16 & PCI_EXP_LNKSTA_LT)) |
266 | return; | |
267 | ||
268 | /* Training failed. Restore common clock configurations */ | |
438be3c6 | 269 | dev_err(&parent->dev, "ASPM: Could not configure common clock\n"); |
f12eb72a JL |
270 | list_for_each_entry(child, &linkbus->devices, bus_list) |
271 | pcie_capability_write_word(child, PCI_EXP_LNKCTL, | |
272 | child_reg[PCI_FUNC(child->devfn)]); | |
273 | pcie_capability_write_word(parent, PCI_EXP_LNKCTL, parent_reg); | |
7d715a6c SL |
274 | } |
275 | ||
5e0eaa7d KK |
276 | /* Convert L0s latency encoding to ns */ |
277 | static u32 calc_l0s_latency(u32 encoding) | |
7d715a6c | 278 | { |
5e0eaa7d KK |
279 | if (encoding == 0x7) |
280 | return (5 * 1000); /* > 4us */ | |
281 | return (64 << encoding); | |
282 | } | |
7d715a6c | 283 | |
5e0eaa7d KK |
284 | /* Convert L0s acceptable latency encoding to ns */ |
285 | static u32 calc_l0s_acceptable(u32 encoding) | |
286 | { | |
287 | if (encoding == 0x7) | |
288 | return -1U; | |
289 | return (64 << encoding); | |
7d715a6c SL |
290 | } |
291 | ||
5e0eaa7d KK |
292 | /* Convert L1 latency encoding to ns */ |
293 | static u32 calc_l1_latency(u32 encoding) | |
7d715a6c | 294 | { |
5e0eaa7d KK |
295 | if (encoding == 0x7) |
296 | return (65 * 1000); /* > 64us */ | |
297 | return (1000 << encoding); | |
298 | } | |
7d715a6c | 299 | |
5e0eaa7d KK |
300 | /* Convert L1 acceptable latency encoding to ns */ |
301 | static u32 calc_l1_acceptable(u32 encoding) | |
302 | { | |
303 | if (encoding == 0x7) | |
304 | return -1U; | |
305 | return (1000 << encoding); | |
7d715a6c SL |
306 | } |
307 | ||
f1f0366d RJ |
308 | /* Convert L1SS T_pwr encoding to usec */ |
309 | static u32 calc_l1ss_pwron(struct pci_dev *pdev, u32 scale, u32 val) | |
310 | { | |
311 | switch (scale) { | |
312 | case 0: | |
313 | return val * 2; | |
314 | case 1: | |
315 | return val * 10; | |
316 | case 2: | |
317 | return val * 100; | |
318 | } | |
319 | dev_err(&pdev->dev, "%s: Invalid T_PwrOn scale: %u\n", | |
320 | __func__, scale); | |
321 | return 0; | |
322 | } | |
323 | ||
c1eb5963 BH |
324 | static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value) |
325 | { | |
326 | u64 threshold_ns = threshold_us * 1000; | |
327 | ||
328 | /* See PCIe r3.1, sec 7.33.3 and sec 6.18 */ | |
329 | if (threshold_ns < 32) { | |
330 | *scale = 0; | |
331 | *value = threshold_ns; | |
332 | } else if (threshold_ns < 1024) { | |
333 | *scale = 1; | |
334 | *value = threshold_ns >> 5; | |
335 | } else if (threshold_ns < 32768) { | |
336 | *scale = 2; | |
337 | *value = threshold_ns >> 10; | |
338 | } else if (threshold_ns < 1048576) { | |
339 | *scale = 3; | |
340 | *value = threshold_ns >> 15; | |
341 | } else if (threshold_ns < 33554432) { | |
342 | *scale = 4; | |
343 | *value = threshold_ns >> 20; | |
344 | } else { | |
345 | *scale = 5; | |
346 | *value = threshold_ns >> 25; | |
347 | } | |
348 | } | |
349 | ||
ac18018a KK |
350 | struct aspm_register_info { |
351 | u32 support:2; | |
352 | u32 enabled:2; | |
353 | u32 latency_encoding_l0s; | |
354 | u32 latency_encoding_l1; | |
b5a0a9b5 RJ |
355 | |
356 | /* L1 substates */ | |
357 | u32 l1ss_cap_ptr; | |
358 | u32 l1ss_cap; | |
359 | u32 l1ss_ctl1; | |
360 | u32 l1ss_ctl2; | |
ac18018a KK |
361 | }; |
362 | ||
363 | static void pcie_get_aspm_reg(struct pci_dev *pdev, | |
364 | struct aspm_register_info *info) | |
7d715a6c | 365 | { |
7d715a6c | 366 | u16 reg16; |
ac18018a | 367 | u32 reg32; |
7d715a6c | 368 | |
f12eb72a | 369 | pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, ®32); |
ac18018a | 370 | info->support = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10; |
ac18018a KK |
371 | info->latency_encoding_l0s = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12; |
372 | info->latency_encoding_l1 = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15; | |
f12eb72a | 373 | pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, ®16); |
ac18018a | 374 | info->enabled = reg16 & PCI_EXP_LNKCTL_ASPMC; |
b5a0a9b5 RJ |
375 | |
376 | /* Read L1 PM substate capabilities */ | |
377 | info->l1ss_cap = info->l1ss_ctl1 = info->l1ss_ctl2 = 0; | |
378 | info->l1ss_cap_ptr = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); | |
379 | if (!info->l1ss_cap_ptr) | |
380 | return; | |
381 | pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CAP, | |
382 | &info->l1ss_cap); | |
383 | if (!(info->l1ss_cap & PCI_L1SS_CAP_L1_PM_SS)) { | |
384 | info->l1ss_cap = 0; | |
385 | return; | |
386 | } | |
89cd06b7 BH |
387 | |
388 | /* | |
389 | * If we don't have LTR for the entire path from the Root Complex | |
390 | * to this device, we can't use ASPM L1.2 because it relies on the | |
391 | * LTR_L1.2_THRESHOLD. See PCIe r4.0, secs 5.5.4, 6.18. | |
392 | */ | |
393 | if (!pdev->ltr_path) | |
394 | info->l1ss_cap &= ~PCI_L1SS_CAP_ASPM_L1_2; | |
395 | ||
b5a0a9b5 RJ |
396 | pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CTL1, |
397 | &info->l1ss_ctl1); | |
398 | pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CTL2, | |
399 | &info->l1ss_ctl2); | |
7d715a6c SL |
400 | } |
401 | ||
07d92760 KK |
402 | static void pcie_aspm_check_latency(struct pci_dev *endpoint) |
403 | { | |
ac18018a | 404 | u32 latency, l1_switch_latency = 0; |
07d92760 KK |
405 | struct aspm_latency *acceptable; |
406 | struct pcie_link_state *link; | |
407 | ||
408 | /* Device not in D0 doesn't need latency check */ | |
409 | if ((endpoint->current_state != PCI_D0) && | |
410 | (endpoint->current_state != PCI_UNKNOWN)) | |
411 | return; | |
412 | ||
413 | link = endpoint->bus->self->link_state; | |
414 | acceptable = &link->acceptable[PCI_FUNC(endpoint->devfn)]; | |
415 | ||
416 | while (link) { | |
ac18018a KK |
417 | /* Check upstream direction L0s latency */ |
418 | if ((link->aspm_capable & ASPM_STATE_L0S_UP) && | |
419 | (link->latency_up.l0s > acceptable->l0s)) | |
420 | link->aspm_capable &= ~ASPM_STATE_L0S_UP; | |
421 | ||
422 | /* Check downstream direction L0s latency */ | |
423 | if ((link->aspm_capable & ASPM_STATE_L0S_DW) && | |
424 | (link->latency_dw.l0s > acceptable->l0s)) | |
425 | link->aspm_capable &= ~ASPM_STATE_L0S_DW; | |
07d92760 KK |
426 | /* |
427 | * Check L1 latency. | |
428 | * Every switch on the path to root complex need 1 | |
429 | * more microsecond for L1. Spec doesn't mention L0s. | |
a142f4d3 RJ |
430 | * |
431 | * The exit latencies for L1 substates are not advertised | |
432 | * by a device. Since the spec also doesn't mention a way | |
433 | * to determine max latencies introduced by enabling L1 | |
434 | * substates on the components, it is not clear how to do | |
435 | * a L1 substate exit latency check. We assume that the | |
436 | * L1 exit latencies advertised by a device include L1 | |
437 | * substate latencies (and hence do not do any check). | |
07d92760 | 438 | */ |
ac18018a KK |
439 | latency = max_t(u32, link->latency_up.l1, link->latency_dw.l1); |
440 | if ((link->aspm_capable & ASPM_STATE_L1) && | |
441 | (latency + l1_switch_latency > acceptable->l1)) | |
442 | link->aspm_capable &= ~ASPM_STATE_L1; | |
07d92760 KK |
443 | l1_switch_latency += 1000; |
444 | ||
445 | link = link->parent; | |
446 | } | |
447 | } | |
448 | ||
b5a0a9b5 RJ |
449 | /* |
450 | * The L1 PM substate capability is only implemented in function 0 in a | |
451 | * multi function device. | |
452 | */ | |
453 | static struct pci_dev *pci_function_0(struct pci_bus *linkbus) | |
454 | { | |
455 | struct pci_dev *child; | |
456 | ||
457 | list_for_each_entry(child, &linkbus->devices, bus_list) | |
458 | if (PCI_FUNC(child->devfn) == 0) | |
459 | return child; | |
460 | return NULL; | |
461 | } | |
462 | ||
f1f0366d RJ |
463 | /* Calculate L1.2 PM substate timing parameters */ |
464 | static void aspm_calc_l1ss_info(struct pcie_link_state *link, | |
465 | struct aspm_register_info *upreg, | |
466 | struct aspm_register_info *dwreg) | |
467 | { | |
468 | u32 val1, val2, scale1, scale2; | |
c1eb5963 | 469 | u32 t_common_mode, t_power_on, l1_2_threshold, scale, value; |
f1f0366d RJ |
470 | |
471 | link->l1ss.up_cap_ptr = upreg->l1ss_cap_ptr; | |
472 | link->l1ss.dw_cap_ptr = dwreg->l1ss_cap_ptr; | |
473 | link->l1ss.ctl1 = link->l1ss.ctl2 = 0; | |
474 | ||
475 | if (!(link->aspm_support & ASPM_STATE_L1_2_MASK)) | |
476 | return; | |
477 | ||
a48f3d5b BH |
478 | /* Choose the greater of the two Port Common_Mode_Restore_Times */ |
479 | val1 = (upreg->l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8; | |
480 | val2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8; | |
c1eb5963 | 481 | t_common_mode = max(val1, val2); |
f1f0366d | 482 | |
a48f3d5b BH |
483 | /* Choose the greater of the two Port T_POWER_ON times */ |
484 | val1 = (upreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19; | |
485 | scale1 = (upreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16; | |
486 | val2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19; | |
487 | scale2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16; | |
f1f0366d RJ |
488 | |
489 | if (calc_l1ss_pwron(link->pdev, scale1, val1) > | |
c1eb5963 | 490 | calc_l1ss_pwron(link->downstream, scale2, val2)) { |
f1f0366d | 491 | link->l1ss.ctl2 |= scale1 | (val1 << 3); |
c1eb5963 BH |
492 | t_power_on = calc_l1ss_pwron(link->pdev, scale1, val1); |
493 | } else { | |
f1f0366d | 494 | link->l1ss.ctl2 |= scale2 | (val2 << 3); |
c1eb5963 BH |
495 | t_power_on = calc_l1ss_pwron(link->downstream, scale2, val2); |
496 | } | |
497 | ||
498 | /* | |
499 | * Set LTR_L1.2_THRESHOLD to the time required to transition the | |
500 | * Link from L0 to L1.2 and back to L0 so we enter L1.2 only if | |
501 | * downstream devices report (via LTR) that they can tolerate at | |
502 | * least that much latency. | |
503 | * | |
504 | * Based on PCIe r3.1, sec 5.5.3.3.1, Figures 5-16 and 5-17, and | |
505 | * Table 5-11. T(POWER_OFF) is at most 2us and T(L1.2) is at | |
506 | * least 4us. | |
507 | */ | |
508 | l1_2_threshold = 2 + 4 + t_common_mode + t_power_on; | |
509 | encode_l12_threshold(l1_2_threshold, &scale, &value); | |
510 | link->l1ss.ctl1 |= t_common_mode << 8 | scale << 29 | value << 16; | |
f1f0366d RJ |
511 | } |
512 | ||
8d349ace | 513 | static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) |
7d715a6c | 514 | { |
3bd7db63 | 515 | struct pci_dev *child = link->downstream, *parent = link->pdev; |
5aa63583 | 516 | struct pci_bus *linkbus = parent->subordinate; |
ac18018a | 517 | struct aspm_register_info upreg, dwreg; |
7d715a6c | 518 | |
8d349ace | 519 | if (blacklist) { |
f1c0ca29 | 520 | /* Set enabled/disable so that we will disable ASPM later */ |
ac18018a KK |
521 | link->aspm_enabled = ASPM_STATE_ALL; |
522 | link->aspm_disable = ASPM_STATE_ALL; | |
8d349ace KK |
523 | return; |
524 | } | |
525 | ||
e53f9a28 DD |
526 | /* Get upstream/downstream components' register state */ |
527 | pcie_get_aspm_reg(parent, &upreg); | |
e53f9a28 DD |
528 | pcie_get_aspm_reg(child, &dwreg); |
529 | ||
530 | /* | |
531 | * If ASPM not supported, don't mess with the clocks and link, | |
532 | * bail out now. | |
533 | */ | |
534 | if (!(upreg.support & dwreg.support)) | |
535 | return; | |
536 | ||
8d349ace KK |
537 | /* Configure common clock before checking latencies */ |
538 | pcie_aspm_configure_common_clock(link); | |
539 | ||
e53f9a28 DD |
540 | /* |
541 | * Re-read upstream/downstream components' register state | |
542 | * after clock configuration | |
543 | */ | |
ac18018a | 544 | pcie_get_aspm_reg(parent, &upreg); |
ac18018a KK |
545 | pcie_get_aspm_reg(child, &dwreg); |
546 | ||
547 | /* | |
548 | * Setup L0s state | |
549 | * | |
550 | * Note that we must not enable L0s in either direction on a | |
551 | * given link unless components on both sides of the link each | |
552 | * support L0s. | |
553 | */ | |
554 | if (dwreg.support & upreg.support & PCIE_LINK_STATE_L0S) | |
555 | link->aspm_support |= ASPM_STATE_L0S; | |
556 | if (dwreg.enabled & PCIE_LINK_STATE_L0S) | |
557 | link->aspm_enabled |= ASPM_STATE_L0S_UP; | |
558 | if (upreg.enabled & PCIE_LINK_STATE_L0S) | |
559 | link->aspm_enabled |= ASPM_STATE_L0S_DW; | |
560 | link->latency_up.l0s = calc_l0s_latency(upreg.latency_encoding_l0s); | |
561 | link->latency_dw.l0s = calc_l0s_latency(dwreg.latency_encoding_l0s); | |
562 | ||
563 | /* Setup L1 state */ | |
564 | if (upreg.support & dwreg.support & PCIE_LINK_STATE_L1) | |
565 | link->aspm_support |= ASPM_STATE_L1; | |
566 | if (upreg.enabled & dwreg.enabled & PCIE_LINK_STATE_L1) | |
567 | link->aspm_enabled |= ASPM_STATE_L1; | |
568 | link->latency_up.l1 = calc_l1_latency(upreg.latency_encoding_l1); | |
569 | link->latency_dw.l1 = calc_l1_latency(dwreg.latency_encoding_l1); | |
5aa63583 | 570 | |
b5a0a9b5 RJ |
571 | /* Setup L1 substate */ |
572 | if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_ASPM_L1_1) | |
573 | link->aspm_support |= ASPM_STATE_L1_1; | |
574 | if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_ASPM_L1_2) | |
575 | link->aspm_support |= ASPM_STATE_L1_2; | |
576 | if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_1) | |
577 | link->aspm_support |= ASPM_STATE_L1_1_PCIPM; | |
578 | if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_2) | |
579 | link->aspm_support |= ASPM_STATE_L1_2_PCIPM; | |
580 | ||
581 | if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_1) | |
582 | link->aspm_enabled |= ASPM_STATE_L1_1; | |
583 | if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_2) | |
584 | link->aspm_enabled |= ASPM_STATE_L1_2; | |
585 | if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_1) | |
586 | link->aspm_enabled |= ASPM_STATE_L1_1_PCIPM; | |
587 | if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_2) | |
588 | link->aspm_enabled |= ASPM_STATE_L1_2_PCIPM; | |
589 | ||
f1f0366d RJ |
590 | if (link->aspm_support & ASPM_STATE_L1SS) |
591 | aspm_calc_l1ss_info(link, &upreg, &dwreg); | |
592 | ||
b127bd55 KK |
593 | /* Save default state */ |
594 | link->aspm_default = link->aspm_enabled; | |
07d92760 KK |
595 | |
596 | /* Setup initial capable state. Will be updated later */ | |
597 | link->aspm_capable = link->aspm_support; | |
f1c0ca29 KK |
598 | /* |
599 | * If the downstream component has pci bridge function, don't | |
600 | * do ASPM for now. | |
601 | */ | |
602 | list_for_each_entry(child, &linkbus->devices, bus_list) { | |
62f87c0e | 603 | if (pci_pcie_type(child) == PCI_EXP_TYPE_PCI_BRIDGE) { |
ac18018a | 604 | link->aspm_disable = ASPM_STATE_ALL; |
f1c0ca29 KK |
605 | break; |
606 | } | |
607 | } | |
b127bd55 | 608 | |
b7206cbf | 609 | /* Get and check endpoint acceptable latencies */ |
5aa63583 | 610 | list_for_each_entry(child, &linkbus->devices, bus_list) { |
5e0eaa7d | 611 | u32 reg32, encoding; |
b6c2e54d | 612 | struct aspm_latency *acceptable = |
5aa63583 | 613 | &link->acceptable[PCI_FUNC(child->devfn)]; |
7d715a6c | 614 | |
62f87c0e YW |
615 | if (pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT && |
616 | pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END) | |
7d715a6c SL |
617 | continue; |
618 | ||
f12eb72a | 619 | pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32); |
07d92760 | 620 | /* Calculate endpoint L0s acceptable latency */ |
5e0eaa7d KK |
621 | encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6; |
622 | acceptable->l0s = calc_l0s_acceptable(encoding); | |
07d92760 KK |
623 | /* Calculate endpoint L1 acceptable latency */ |
624 | encoding = (reg32 & PCI_EXP_DEVCAP_L1) >> 9; | |
625 | acceptable->l1 = calc_l1_acceptable(encoding); | |
626 | ||
627 | pcie_aspm_check_latency(child); | |
7d715a6c SL |
628 | } |
629 | } | |
630 | ||
aeda9ade RJ |
631 | static void pci_clear_and_set_dword(struct pci_dev *pdev, int pos, |
632 | u32 clear, u32 set) | |
633 | { | |
634 | u32 val; | |
635 | ||
636 | pci_read_config_dword(pdev, pos, &val); | |
637 | val &= ~clear; | |
638 | val |= set; | |
639 | pci_write_config_dword(pdev, pos, val); | |
640 | } | |
641 | ||
642 | /* Configure the ASPM L1 substates */ | |
643 | static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state) | |
644 | { | |
645 | u32 val, enable_req; | |
646 | struct pci_dev *child = link->downstream, *parent = link->pdev; | |
647 | u32 up_cap_ptr = link->l1ss.up_cap_ptr; | |
648 | u32 dw_cap_ptr = link->l1ss.dw_cap_ptr; | |
649 | ||
650 | enable_req = (link->aspm_enabled ^ state) & state; | |
651 | ||
652 | /* | |
653 | * Here are the rules specified in the PCIe spec for enabling L1SS: | |
654 | * - When enabling L1.x, enable bit at parent first, then at child | |
655 | * - When disabling L1.x, disable bit at child first, then at parent | |
656 | * - When enabling ASPM L1.x, need to disable L1 | |
657 | * (at child followed by parent). | |
658 | * - The ASPM/PCIPM L1.2 must be disabled while programming timing | |
659 | * parameters | |
660 | * | |
661 | * To keep it simple, disable all L1SS bits first, and later enable | |
662 | * what is needed. | |
663 | */ | |
664 | ||
665 | /* Disable all L1 substates */ | |
666 | pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1, | |
667 | PCI_L1SS_CTL1_L1SS_MASK, 0); | |
668 | pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1, | |
669 | PCI_L1SS_CTL1_L1SS_MASK, 0); | |
670 | /* | |
671 | * If needed, disable L1, and it gets enabled later | |
672 | * in pcie_config_aspm_link(). | |
673 | */ | |
674 | if (enable_req & (ASPM_STATE_L1_1 | ASPM_STATE_L1_2)) { | |
675 | pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL, | |
676 | PCI_EXP_LNKCTL_ASPM_L1, 0); | |
677 | pcie_capability_clear_and_set_word(parent, PCI_EXP_LNKCTL, | |
678 | PCI_EXP_LNKCTL_ASPM_L1, 0); | |
679 | } | |
680 | ||
681 | if (enable_req & ASPM_STATE_L1_2_MASK) { | |
682 | ||
a48f3d5b | 683 | /* Program T_POWER_ON times in both ports */ |
aeda9ade RJ |
684 | pci_write_config_dword(parent, up_cap_ptr + PCI_L1SS_CTL2, |
685 | link->l1ss.ctl2); | |
686 | pci_write_config_dword(child, dw_cap_ptr + PCI_L1SS_CTL2, | |
687 | link->l1ss.ctl2); | |
688 | ||
a48f3d5b | 689 | /* Program Common_Mode_Restore_Time in upstream device */ |
aeda9ade | 690 | pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1, |
a48f3d5b BH |
691 | PCI_L1SS_CTL1_CM_RESTORE_TIME, |
692 | link->l1ss.ctl1); | |
aeda9ade | 693 | |
a48f3d5b | 694 | /* Program LTR_L1.2_THRESHOLD time in both ports */ |
c00054f5 | 695 | pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1, |
a48f3d5b BH |
696 | PCI_L1SS_CTL1_LTR_L12_TH_VALUE | |
697 | PCI_L1SS_CTL1_LTR_L12_TH_SCALE, | |
698 | link->l1ss.ctl1); | |
aeda9ade | 699 | pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1, |
a48f3d5b BH |
700 | PCI_L1SS_CTL1_LTR_L12_TH_VALUE | |
701 | PCI_L1SS_CTL1_LTR_L12_TH_SCALE, | |
702 | link->l1ss.ctl1); | |
aeda9ade RJ |
703 | } |
704 | ||
705 | val = 0; | |
706 | if (state & ASPM_STATE_L1_1) | |
707 | val |= PCI_L1SS_CTL1_ASPM_L1_1; | |
708 | if (state & ASPM_STATE_L1_2) | |
709 | val |= PCI_L1SS_CTL1_ASPM_L1_2; | |
710 | if (state & ASPM_STATE_L1_1_PCIPM) | |
711 | val |= PCI_L1SS_CTL1_PCIPM_L1_1; | |
712 | if (state & ASPM_STATE_L1_2_PCIPM) | |
713 | val |= PCI_L1SS_CTL1_PCIPM_L1_2; | |
714 | ||
715 | /* Enable what we need to enable */ | |
716 | pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1, | |
717 | PCI_L1SS_CAP_L1_PM_SS, val); | |
718 | pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1, | |
719 | PCI_L1SS_CAP_L1_PM_SS, val); | |
720 | } | |
721 | ||
ac18018a | 722 | static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val) |
7d715a6c | 723 | { |
75083206 BH |
724 | pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL, |
725 | PCI_EXP_LNKCTL_ASPMC, val); | |
7d715a6c SL |
726 | } |
727 | ||
b7206cbf | 728 | static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state) |
7d715a6c | 729 | { |
ac18018a | 730 | u32 upstream = 0, dwstream = 0; |
aeda9ade | 731 | struct pci_dev *child = link->downstream, *parent = link->pdev; |
5aa63583 | 732 | struct pci_bus *linkbus = parent->subordinate; |
7d715a6c | 733 | |
aeda9ade | 734 | /* Enable only the states that were not explicitly disabled */ |
b7206cbf | 735 | state &= (link->aspm_capable & ~link->aspm_disable); |
aeda9ade RJ |
736 | |
737 | /* Can't enable any substates if L1 is not enabled */ | |
738 | if (!(state & ASPM_STATE_L1)) | |
739 | state &= ~ASPM_STATE_L1SS; | |
740 | ||
741 | /* Spec says both ports must be in D0 before enabling PCI PM substates*/ | |
742 | if (parent->current_state != PCI_D0 || child->current_state != PCI_D0) { | |
743 | state &= ~ASPM_STATE_L1_SS_PCIPM; | |
744 | state |= (link->aspm_enabled & ASPM_STATE_L1_SS_PCIPM); | |
745 | } | |
746 | ||
747 | /* Nothing to do if the link is already in the requested state */ | |
f1c0ca29 KK |
748 | if (link->aspm_enabled == state) |
749 | return; | |
ac18018a KK |
750 | /* Convert ASPM state to upstream/downstream ASPM register state */ |
751 | if (state & ASPM_STATE_L0S_UP) | |
75083206 | 752 | dwstream |= PCI_EXP_LNKCTL_ASPM_L0S; |
ac18018a | 753 | if (state & ASPM_STATE_L0S_DW) |
75083206 | 754 | upstream |= PCI_EXP_LNKCTL_ASPM_L0S; |
ac18018a | 755 | if (state & ASPM_STATE_L1) { |
75083206 BH |
756 | upstream |= PCI_EXP_LNKCTL_ASPM_L1; |
757 | dwstream |= PCI_EXP_LNKCTL_ASPM_L1; | |
ac18018a | 758 | } |
aeda9ade RJ |
759 | |
760 | if (link->aspm_capable & ASPM_STATE_L1SS) | |
761 | pcie_config_aspm_l1ss(link, state); | |
762 | ||
7d715a6c | 763 | /* |
5aa63583 KK |
764 | * Spec 2.0 suggests all functions should be configured the |
765 | * same setting for ASPM. Enabling ASPM L1 should be done in | |
766 | * upstream component first and then downstream, and vice | |
767 | * versa for disabling ASPM L1. Spec doesn't mention L0S. | |
7d715a6c | 768 | */ |
ac18018a KK |
769 | if (state & ASPM_STATE_L1) |
770 | pcie_config_aspm_dev(parent, upstream); | |
5aa63583 | 771 | list_for_each_entry(child, &linkbus->devices, bus_list) |
ac18018a KK |
772 | pcie_config_aspm_dev(child, dwstream); |
773 | if (!(state & ASPM_STATE_L1)) | |
774 | pcie_config_aspm_dev(parent, upstream); | |
7d715a6c | 775 | |
5aa63583 | 776 | link->aspm_enabled = state; |
7d715a6c SL |
777 | } |
778 | ||
b7206cbf | 779 | static void pcie_config_aspm_path(struct pcie_link_state *link) |
7d715a6c | 780 | { |
b7206cbf KK |
781 | while (link) { |
782 | pcie_config_aspm_link(link, policy_to_aspm_state(link)); | |
783 | link = link->parent; | |
46bbdfa4 | 784 | } |
7d715a6c SL |
785 | } |
786 | ||
5aa63583 | 787 | static void free_link_state(struct pcie_link_state *link) |
7d715a6c | 788 | { |
5aa63583 KK |
789 | link->pdev->link_state = NULL; |
790 | kfree(link); | |
7d715a6c SL |
791 | } |
792 | ||
ddc9753f SL |
793 | static int pcie_aspm_sanity_check(struct pci_dev *pdev) |
794 | { | |
3647584d | 795 | struct pci_dev *child; |
149e1637 | 796 | u32 reg32; |
2f671e2d | 797 | |
ddc9753f | 798 | /* |
45e829ea | 799 | * Some functions in a slot might not all be PCIe functions, |
3647584d | 800 | * very strange. Disable ASPM for the whole slot |
ddc9753f | 801 | */ |
3647584d | 802 | list_for_each_entry(child, &pdev->subordinate->devices, bus_list) { |
f12eb72a | 803 | if (!pci_is_pcie(child)) |
ddc9753f | 804 | return -EINVAL; |
c9651e70 MG |
805 | |
806 | /* | |
807 | * If ASPM is disabled then we're not going to change | |
808 | * the BIOS state. It's safe to continue even if it's a | |
809 | * pre-1.1 device | |
810 | */ | |
811 | ||
812 | if (aspm_disabled) | |
813 | continue; | |
814 | ||
149e1637 SL |
815 | /* |
816 | * Disable ASPM for pre-1.1 PCIe device, we follow MS to use | |
817 | * RBER bit to determine if a function is 1.1 version device | |
818 | */ | |
f12eb72a | 819 | pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32); |
e1f4f59d | 820 | if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) { |
438be3c6 | 821 | dev_info(&child->dev, "disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force'\n"); |
149e1637 SL |
822 | return -EINVAL; |
823 | } | |
ddc9753f SL |
824 | } |
825 | return 0; | |
826 | } | |
827 | ||
b7206cbf | 828 | static struct pcie_link_state *alloc_pcie_link_state(struct pci_dev *pdev) |
8d349ace KK |
829 | { |
830 | struct pcie_link_state *link; | |
8d349ace KK |
831 | |
832 | link = kzalloc(sizeof(*link), GFP_KERNEL); | |
833 | if (!link) | |
834 | return NULL; | |
030305d6 | 835 | |
8d349ace KK |
836 | INIT_LIST_HEAD(&link->sibling); |
837 | INIT_LIST_HEAD(&link->children); | |
838 | INIT_LIST_HEAD(&link->link); | |
839 | link->pdev = pdev; | |
3bd7db63 | 840 | link->downstream = pci_function_0(pdev->subordinate); |
030305d6 BH |
841 | |
842 | /* | |
843 | * Root Ports and PCI/PCI-X to PCIe Bridges are roots of PCIe | |
ee8bdfb6 AB |
844 | * hierarchies. Note that some PCIe host implementations omit |
845 | * the root ports entirely, in which case a downstream port on | |
846 | * a switch may become the root of the link state chain for all | |
847 | * its subordinate endpoints. | |
030305d6 BH |
848 | */ |
849 | if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT || | |
ee8bdfb6 AB |
850 | pci_pcie_type(pdev) == PCI_EXP_TYPE_PCIE_BRIDGE || |
851 | !pdev->bus->parent->self) { | |
030305d6 BH |
852 | link->root = link; |
853 | } else { | |
8d349ace | 854 | struct pcie_link_state *parent; |
030305d6 | 855 | |
8d349ace KK |
856 | parent = pdev->bus->parent->self->link_state; |
857 | if (!parent) { | |
858 | kfree(link); | |
859 | return NULL; | |
860 | } | |
030305d6 | 861 | |
8d349ace | 862 | link->parent = parent; |
030305d6 | 863 | link->root = link->parent->root; |
8d349ace KK |
864 | list_add(&link->link, &parent->children); |
865 | } | |
5c92ffb1 | 866 | |
8d349ace | 867 | list_add(&link->sibling, &link_list); |
8d349ace | 868 | pdev->link_state = link; |
8d349ace KK |
869 | return link; |
870 | } | |
871 | ||
7d715a6c SL |
872 | /* |
873 | * pcie_aspm_init_link_state: Initiate PCI express link state. | |
f7625980 | 874 | * It is called after the pcie and its children devices are scanned. |
7d715a6c SL |
875 | * @pdev: the root port or switch downstream port |
876 | */ | |
877 | void pcie_aspm_init_link_state(struct pci_dev *pdev) | |
878 | { | |
8d349ace | 879 | struct pcie_link_state *link; |
b7206cbf | 880 | int blacklist = !!pcie_aspm_sanity_check(pdev); |
7d715a6c | 881 | |
a26d5ecb JL |
882 | if (!aspm_support_enabled) |
883 | return; | |
884 | ||
c8fc9339 | 885 | if (pdev->link_state) |
7d715a6c | 886 | return; |
c8fc9339 YW |
887 | |
888 | /* | |
889 | * We allocate pcie_link_state for the component on the upstream | |
890 | * end of a Link, so there's nothing to do unless this device has a | |
891 | * Link on its secondary side. | |
892 | */ | |
893 | if (!pdev->has_secondary_link) | |
7d715a6c | 894 | return; |
8d349ace | 895 | |
8e822df7 | 896 | /* VIA has a strange chipset, root port is under a bridge */ |
62f87c0e | 897 | if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT && |
8d349ace | 898 | pdev->bus->self) |
8e822df7 | 899 | return; |
8d349ace | 900 | |
7d715a6c SL |
901 | down_read(&pci_bus_sem); |
902 | if (list_empty(&pdev->subordinate->devices)) | |
903 | goto out; | |
904 | ||
905 | mutex_lock(&aspm_lock); | |
b7206cbf | 906 | link = alloc_pcie_link_state(pdev); |
8d349ace KK |
907 | if (!link) |
908 | goto unlock; | |
909 | /* | |
b7206cbf KK |
910 | * Setup initial ASPM state. Note that we need to configure |
911 | * upstream links also because capable state of them can be | |
912 | * update through pcie_aspm_cap_init(). | |
8d349ace | 913 | */ |
b7206cbf | 914 | pcie_aspm_cap_init(link, blacklist); |
7d715a6c | 915 | |
8d349ace | 916 | /* Setup initial Clock PM state */ |
b7206cbf | 917 | pcie_clkpm_cap_init(link, blacklist); |
41cd766b MG |
918 | |
919 | /* | |
920 | * At this stage drivers haven't had an opportunity to change the | |
921 | * link policy setting. Enabling ASPM on broken hardware can cripple | |
922 | * it even before the driver has had a chance to disable ASPM, so | |
923 | * default to a safe level right now. If we're enabling ASPM beyond | |
924 | * the BIOS's expectation, we'll do so once pci_enable_device() is | |
925 | * called. | |
926 | */ | |
b2103ccb RJ |
927 | if (aspm_policy != POLICY_POWERSAVE && |
928 | aspm_policy != POLICY_POWER_SUPERSAVE) { | |
41cd766b MG |
929 | pcie_config_aspm_path(link); |
930 | pcie_set_clkpm(link, policy_to_clkpm_state(link)); | |
931 | } | |
932 | ||
8d349ace | 933 | unlock: |
7d715a6c SL |
934 | mutex_unlock(&aspm_lock); |
935 | out: | |
936 | up_read(&pci_bus_sem); | |
937 | } | |
938 | ||
07d92760 KK |
939 | /* Recheck latencies and update aspm_capable for links under the root */ |
940 | static void pcie_update_aspm_capable(struct pcie_link_state *root) | |
941 | { | |
942 | struct pcie_link_state *link; | |
943 | BUG_ON(root->parent); | |
944 | list_for_each_entry(link, &link_list, sibling) { | |
945 | if (link->root != root) | |
946 | continue; | |
947 | link->aspm_capable = link->aspm_support; | |
948 | } | |
949 | list_for_each_entry(link, &link_list, sibling) { | |
950 | struct pci_dev *child; | |
951 | struct pci_bus *linkbus = link->pdev->subordinate; | |
952 | if (link->root != root) | |
953 | continue; | |
954 | list_for_each_entry(child, &linkbus->devices, bus_list) { | |
62f87c0e YW |
955 | if ((pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT) && |
956 | (pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END)) | |
07d92760 KK |
957 | continue; |
958 | pcie_aspm_check_latency(child); | |
959 | } | |
960 | } | |
961 | } | |
962 | ||
7d715a6c SL |
963 | /* @pdev: the endpoint device */ |
964 | void pcie_aspm_exit_link_state(struct pci_dev *pdev) | |
965 | { | |
966 | struct pci_dev *parent = pdev->bus->self; | |
b7206cbf | 967 | struct pcie_link_state *link, *root, *parent_link; |
7d715a6c | 968 | |
84fb913c | 969 | if (!parent || !parent->link_state) |
7d715a6c | 970 | return; |
fc87e919 | 971 | |
7d715a6c SL |
972 | down_read(&pci_bus_sem); |
973 | mutex_lock(&aspm_lock); | |
7d715a6c SL |
974 | /* |
975 | * All PCIe functions are in one slot, remove one function will remove | |
3419c75e | 976 | * the whole slot, so just wait until we are the last function left. |
7d715a6c | 977 | */ |
9ee7f2c6 | 978 | if (!list_empty(&parent->subordinate->devices)) |
7d715a6c SL |
979 | goto out; |
980 | ||
fc87e919 | 981 | link = parent->link_state; |
07d92760 | 982 | root = link->root; |
b7206cbf | 983 | parent_link = link->parent; |
fc87e919 | 984 | |
7d715a6c | 985 | /* All functions are removed, so just disable ASPM for the link */ |
b7206cbf | 986 | pcie_config_aspm_link(link, 0); |
fc87e919 KK |
987 | list_del(&link->sibling); |
988 | list_del(&link->link); | |
7d715a6c | 989 | /* Clock PM is for endpoint device */ |
fc87e919 | 990 | free_link_state(link); |
07d92760 KK |
991 | |
992 | /* Recheck latencies and configure upstream links */ | |
b26a34aa KK |
993 | if (parent_link) { |
994 | pcie_update_aspm_capable(root); | |
995 | pcie_config_aspm_path(parent_link); | |
996 | } | |
7d715a6c SL |
997 | out: |
998 | mutex_unlock(&aspm_lock); | |
999 | up_read(&pci_bus_sem); | |
1000 | } | |
1001 | ||
1002 | /* @pdev: the root port or switch downstream port */ | |
1003 | void pcie_aspm_pm_state_change(struct pci_dev *pdev) | |
1004 | { | |
07d92760 | 1005 | struct pcie_link_state *link = pdev->link_state; |
7d715a6c | 1006 | |
f9b8cd7c | 1007 | if (aspm_disabled || !link) |
7d715a6c SL |
1008 | return; |
1009 | /* | |
07d92760 KK |
1010 | * Devices changed PM state, we should recheck if latency |
1011 | * meets all functions' requirement | |
7d715a6c | 1012 | */ |
07d92760 KK |
1013 | down_read(&pci_bus_sem); |
1014 | mutex_lock(&aspm_lock); | |
1015 | pcie_update_aspm_capable(link->root); | |
b7206cbf | 1016 | pcie_config_aspm_path(link); |
07d92760 KK |
1017 | mutex_unlock(&aspm_lock); |
1018 | up_read(&pci_bus_sem); | |
7d715a6c SL |
1019 | } |
1020 | ||
1a680b7c NC |
1021 | void pcie_aspm_powersave_config_link(struct pci_dev *pdev) |
1022 | { | |
1023 | struct pcie_link_state *link = pdev->link_state; | |
1024 | ||
f9b8cd7c | 1025 | if (aspm_disabled || !link) |
1a680b7c NC |
1026 | return; |
1027 | ||
b2103ccb RJ |
1028 | if (aspm_policy != POLICY_POWERSAVE && |
1029 | aspm_policy != POLICY_POWER_SUPERSAVE) | |
1a680b7c NC |
1030 | return; |
1031 | ||
1a680b7c NC |
1032 | down_read(&pci_bus_sem); |
1033 | mutex_lock(&aspm_lock); | |
1034 | pcie_config_aspm_path(link); | |
1035 | pcie_set_clkpm(link, policy_to_clkpm_state(link)); | |
1036 | mutex_unlock(&aspm_lock); | |
1037 | up_read(&pci_bus_sem); | |
1038 | } | |
1039 | ||
e127a04f | 1040 | static void __pci_disable_link_state(struct pci_dev *pdev, int state, bool sem) |
7d715a6c SL |
1041 | { |
1042 | struct pci_dev *parent = pdev->bus->self; | |
f1c0ca29 | 1043 | struct pcie_link_state *link; |
7d715a6c | 1044 | |
3c076351 | 1045 | if (!pci_is_pcie(pdev)) |
7d715a6c | 1046 | return; |
3c076351 | 1047 | |
c8fc9339 | 1048 | if (pdev->has_secondary_link) |
7d715a6c SL |
1049 | parent = pdev; |
1050 | if (!parent || !parent->link_state) | |
1051 | return; | |
1052 | ||
2add0ec1 BH |
1053 | /* |
1054 | * A driver requested that ASPM be disabled on this device, but | |
1055 | * if we don't have permission to manage ASPM (e.g., on ACPI | |
1056 | * systems we have to observe the FADT ACPI_FADT_NO_ASPM bit and | |
1057 | * the _OSC method), we can't honor that request. Windows has | |
1058 | * a similar mechanism using "PciASPMOptOut", which is also | |
1059 | * ignored in this situation. | |
1060 | */ | |
e127a04f | 1061 | if (aspm_disabled) { |
2add0ec1 BH |
1062 | dev_warn(&pdev->dev, "can't disable ASPM; OS doesn't have ASPM control\n"); |
1063 | return; | |
1064 | } | |
1065 | ||
9f728f53 YL |
1066 | if (sem) |
1067 | down_read(&pci_bus_sem); | |
7d715a6c | 1068 | mutex_lock(&aspm_lock); |
f1c0ca29 | 1069 | link = parent->link_state; |
ac18018a KK |
1070 | if (state & PCIE_LINK_STATE_L0S) |
1071 | link->aspm_disable |= ASPM_STATE_L0S; | |
1072 | if (state & PCIE_LINK_STATE_L1) | |
1073 | link->aspm_disable |= ASPM_STATE_L1; | |
b7206cbf KK |
1074 | pcie_config_aspm_link(link, policy_to_aspm_state(link)); |
1075 | ||
430842e2 | 1076 | if (state & PCIE_LINK_STATE_CLKPM) { |
f1c0ca29 KK |
1077 | link->clkpm_capable = 0; |
1078 | pcie_set_clkpm(link, 0); | |
430842e2 | 1079 | } |
7d715a6c | 1080 | mutex_unlock(&aspm_lock); |
9f728f53 YL |
1081 | if (sem) |
1082 | up_read(&pci_bus_sem); | |
1083 | } | |
1084 | ||
1085 | void pci_disable_link_state_locked(struct pci_dev *pdev, int state) | |
1086 | { | |
e127a04f | 1087 | __pci_disable_link_state(pdev, state, false); |
9f728f53 YL |
1088 | } |
1089 | EXPORT_SYMBOL(pci_disable_link_state_locked); | |
1090 | ||
2dfca877 YW |
1091 | /** |
1092 | * pci_disable_link_state - Disable device's link state, so the link will | |
1093 | * never enter specific states. Note that if the BIOS didn't grant ASPM | |
1094 | * control to the OS, this does nothing because we can't touch the LNKCTL | |
1095 | * register. | |
1096 | * | |
1097 | * @pdev: PCI device | |
1098 | * @state: ASPM link state to disable | |
1099 | */ | |
9f728f53 YL |
1100 | void pci_disable_link_state(struct pci_dev *pdev, int state) |
1101 | { | |
e127a04f | 1102 | __pci_disable_link_state(pdev, state, true); |
7d715a6c SL |
1103 | } |
1104 | EXPORT_SYMBOL(pci_disable_link_state); | |
1105 | ||
e4dca7b7 KC |
1106 | static int pcie_aspm_set_policy(const char *val, |
1107 | const struct kernel_param *kp) | |
7d715a6c SL |
1108 | { |
1109 | int i; | |
b7206cbf | 1110 | struct pcie_link_state *link; |
7d715a6c | 1111 | |
bbfa306a NC |
1112 | if (aspm_disabled) |
1113 | return -EPERM; | |
7d715a6c SL |
1114 | for (i = 0; i < ARRAY_SIZE(policy_str); i++) |
1115 | if (!strncmp(val, policy_str[i], strlen(policy_str[i]))) | |
1116 | break; | |
1117 | if (i >= ARRAY_SIZE(policy_str)) | |
1118 | return -EINVAL; | |
1119 | if (i == aspm_policy) | |
1120 | return 0; | |
1121 | ||
1122 | down_read(&pci_bus_sem); | |
1123 | mutex_lock(&aspm_lock); | |
1124 | aspm_policy = i; | |
b7206cbf KK |
1125 | list_for_each_entry(link, &link_list, sibling) { |
1126 | pcie_config_aspm_link(link, policy_to_aspm_state(link)); | |
1127 | pcie_set_clkpm(link, policy_to_clkpm_state(link)); | |
7d715a6c SL |
1128 | } |
1129 | mutex_unlock(&aspm_lock); | |
1130 | up_read(&pci_bus_sem); | |
1131 | return 0; | |
1132 | } | |
1133 | ||
e4dca7b7 | 1134 | static int pcie_aspm_get_policy(char *buffer, const struct kernel_param *kp) |
7d715a6c SL |
1135 | { |
1136 | int i, cnt = 0; | |
1137 | for (i = 0; i < ARRAY_SIZE(policy_str); i++) | |
1138 | if (i == aspm_policy) | |
1139 | cnt += sprintf(buffer + cnt, "[%s] ", policy_str[i]); | |
1140 | else | |
1141 | cnt += sprintf(buffer + cnt, "%s ", policy_str[i]); | |
1142 | return cnt; | |
1143 | } | |
1144 | ||
1145 | module_param_call(policy, pcie_aspm_set_policy, pcie_aspm_get_policy, | |
1146 | NULL, 0644); | |
1147 | ||
1148 | #ifdef CONFIG_PCIEASPM_DEBUG | |
1149 | static ssize_t link_state_show(struct device *dev, | |
1150 | struct device_attribute *attr, | |
1151 | char *buf) | |
1152 | { | |
1153 | struct pci_dev *pci_device = to_pci_dev(dev); | |
1154 | struct pcie_link_state *link_state = pci_device->link_state; | |
1155 | ||
80bfdbe3 | 1156 | return sprintf(buf, "%d\n", link_state->aspm_enabled); |
7d715a6c SL |
1157 | } |
1158 | ||
1159 | static ssize_t link_state_store(struct device *dev, | |
1160 | struct device_attribute *attr, | |
1161 | const char *buf, | |
1162 | size_t n) | |
1163 | { | |
5aa63583 | 1164 | struct pci_dev *pdev = to_pci_dev(dev); |
b7206cbf | 1165 | struct pcie_link_state *link, *root = pdev->link_state->root; |
57d86a04 | 1166 | u32 state; |
7d715a6c | 1167 | |
bbfa306a NC |
1168 | if (aspm_disabled) |
1169 | return -EPERM; | |
7d715a6c | 1170 | |
57d86a04 AL |
1171 | if (kstrtouint(buf, 10, &state)) |
1172 | return -EINVAL; | |
1173 | if ((state & ~ASPM_STATE_ALL) != 0) | |
1174 | return -EINVAL; | |
ac18018a | 1175 | |
b7206cbf KK |
1176 | down_read(&pci_bus_sem); |
1177 | mutex_lock(&aspm_lock); | |
1178 | list_for_each_entry(link, &link_list, sibling) { | |
1179 | if (link->root != root) | |
1180 | continue; | |
1181 | pcie_config_aspm_link(link, state); | |
1182 | } | |
1183 | mutex_unlock(&aspm_lock); | |
1184 | up_read(&pci_bus_sem); | |
1185 | return n; | |
7d715a6c SL |
1186 | } |
1187 | ||
1188 | static ssize_t clk_ctl_show(struct device *dev, | |
1189 | struct device_attribute *attr, | |
1190 | char *buf) | |
1191 | { | |
1192 | struct pci_dev *pci_device = to_pci_dev(dev); | |
1193 | struct pcie_link_state *link_state = pci_device->link_state; | |
1194 | ||
4d246e45 | 1195 | return sprintf(buf, "%d\n", link_state->clkpm_enabled); |
7d715a6c SL |
1196 | } |
1197 | ||
1198 | static ssize_t clk_ctl_store(struct device *dev, | |
1199 | struct device_attribute *attr, | |
1200 | const char *buf, | |
1201 | size_t n) | |
1202 | { | |
430842e2 | 1203 | struct pci_dev *pdev = to_pci_dev(dev); |
94a90312 | 1204 | bool state; |
7d715a6c | 1205 | |
94a90312 | 1206 | if (strtobool(buf, &state)) |
7d715a6c | 1207 | return -EINVAL; |
7d715a6c SL |
1208 | |
1209 | down_read(&pci_bus_sem); | |
1210 | mutex_lock(&aspm_lock); | |
94a90312 | 1211 | pcie_set_clkpm_nocheck(pdev->link_state, state); |
7d715a6c SL |
1212 | mutex_unlock(&aspm_lock); |
1213 | up_read(&pci_bus_sem); | |
1214 | ||
1215 | return n; | |
1216 | } | |
1217 | ||
fc4f57fa JL |
1218 | static DEVICE_ATTR_RW(link_state); |
1219 | static DEVICE_ATTR_RW(clk_ctl); | |
7d715a6c SL |
1220 | |
1221 | static char power_group[] = "power"; | |
1222 | void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev) | |
1223 | { | |
1224 | struct pcie_link_state *link_state = pdev->link_state; | |
1225 | ||
f9b8cd7c | 1226 | if (!link_state) |
7d715a6c SL |
1227 | return; |
1228 | ||
80bfdbe3 | 1229 | if (link_state->aspm_support) |
7d715a6c SL |
1230 | sysfs_add_file_to_group(&pdev->dev.kobj, |
1231 | &dev_attr_link_state.attr, power_group); | |
4d246e45 | 1232 | if (link_state->clkpm_capable) |
7d715a6c SL |
1233 | sysfs_add_file_to_group(&pdev->dev.kobj, |
1234 | &dev_attr_clk_ctl.attr, power_group); | |
1235 | } | |
1236 | ||
1237 | void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev) | |
1238 | { | |
1239 | struct pcie_link_state *link_state = pdev->link_state; | |
1240 | ||
f9b8cd7c | 1241 | if (!link_state) |
7d715a6c SL |
1242 | return; |
1243 | ||
80bfdbe3 | 1244 | if (link_state->aspm_support) |
7d715a6c SL |
1245 | sysfs_remove_file_from_group(&pdev->dev.kobj, |
1246 | &dev_attr_link_state.attr, power_group); | |
4d246e45 | 1247 | if (link_state->clkpm_capable) |
7d715a6c SL |
1248 | sysfs_remove_file_from_group(&pdev->dev.kobj, |
1249 | &dev_attr_clk_ctl.attr, power_group); | |
1250 | } | |
1251 | #endif | |
1252 | ||
1253 | static int __init pcie_aspm_disable(char *str) | |
1254 | { | |
d6d38574 | 1255 | if (!strcmp(str, "off")) { |
3c076351 | 1256 | aspm_policy = POLICY_DEFAULT; |
d6d38574 | 1257 | aspm_disabled = 1; |
8b8bae90 | 1258 | aspm_support_enabled = false; |
d6d38574 SL |
1259 | printk(KERN_INFO "PCIe ASPM is disabled\n"); |
1260 | } else if (!strcmp(str, "force")) { | |
1261 | aspm_force = 1; | |
8072ba1b | 1262 | printk(KERN_INFO "PCIe ASPM is forcibly enabled\n"); |
d6d38574 | 1263 | } |
7d715a6c SL |
1264 | return 1; |
1265 | } | |
1266 | ||
d6d38574 | 1267 | __setup("pcie_aspm=", pcie_aspm_disable); |
7d715a6c | 1268 | |
5fde244d SL |
1269 | void pcie_no_aspm(void) |
1270 | { | |
3c076351 MG |
1271 | /* |
1272 | * Disabling ASPM is intended to prevent the kernel from modifying | |
1273 | * existing hardware state, not to clear existing state. To that end: | |
1274 | * (a) set policy to POLICY_DEFAULT in order to avoid changing state | |
1275 | * (b) prevent userspace from changing policy | |
1276 | */ | |
1277 | if (!aspm_force) { | |
1278 | aspm_policy = POLICY_DEFAULT; | |
d6d38574 | 1279 | aspm_disabled = 1; |
3c076351 | 1280 | } |
5fde244d SL |
1281 | } |
1282 | ||
8b8bae90 RW |
1283 | bool pcie_aspm_support_enabled(void) |
1284 | { | |
1285 | return aspm_support_enabled; | |
1286 | } | |
1287 | EXPORT_SYMBOL(pcie_aspm_support_enabled); |