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Commit | Line | Data |
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7d715a6c SL |
1 | /* |
2 | * File: drivers/pci/pcie/aspm.c | |
45e829ea | 3 | * Enabling PCIe link L0s/L1 state and Clock Power Management |
7d715a6c SL |
4 | * |
5 | * Copyright (C) 2007 Intel | |
6 | * Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com) | |
7 | * Copyright (C) Shaohua Li (shaohua.li@intel.com) | |
8 | */ | |
9 | ||
10 | #include <linux/kernel.h> | |
11 | #include <linux/module.h> | |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/pci.h> | |
14 | #include <linux/pci_regs.h> | |
15 | #include <linux/errno.h> | |
16 | #include <linux/pm.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/slab.h> | |
2a42d9db | 19 | #include <linux/jiffies.h> |
987a4c78 | 20 | #include <linux/delay.h> |
7d715a6c SL |
21 | #include <linux/pci-aspm.h> |
22 | #include "../pci.h" | |
23 | ||
24 | #ifdef MODULE_PARAM_PREFIX | |
25 | #undef MODULE_PARAM_PREFIX | |
26 | #endif | |
27 | #define MODULE_PARAM_PREFIX "pcie_aspm." | |
28 | ||
ac18018a KK |
29 | /* Note: those are not register definitions */ |
30 | #define ASPM_STATE_L0S_UP (1) /* Upstream direction L0s state */ | |
31 | #define ASPM_STATE_L0S_DW (2) /* Downstream direction L0s state */ | |
32 | #define ASPM_STATE_L1 (4) /* L1 state */ | |
33 | #define ASPM_STATE_L0S (ASPM_STATE_L0S_UP | ASPM_STATE_L0S_DW) | |
34 | #define ASPM_STATE_ALL (ASPM_STATE_L0S | ASPM_STATE_L1) | |
35 | ||
b6c2e54d KK |
36 | struct aspm_latency { |
37 | u32 l0s; /* L0s latency (nsec) */ | |
38 | u32 l1; /* L1 latency (nsec) */ | |
7d715a6c SL |
39 | }; |
40 | ||
41 | struct pcie_link_state { | |
5cde89d8 | 42 | struct pci_dev *pdev; /* Upstream component of the Link */ |
5c92ffb1 | 43 | struct pcie_link_state *root; /* pointer to the root port link */ |
5cde89d8 KK |
44 | struct pcie_link_state *parent; /* pointer to the parent Link state */ |
45 | struct list_head sibling; /* node in link_list */ | |
46 | struct list_head children; /* list of child link states */ | |
47 | struct list_head link; /* node in parent's children list */ | |
7d715a6c SL |
48 | |
49 | /* ASPM state */ | |
ac18018a KK |
50 | u32 aspm_support:3; /* Supported ASPM state */ |
51 | u32 aspm_enabled:3; /* Enabled ASPM state */ | |
52 | u32 aspm_capable:3; /* Capable ASPM state with latency */ | |
53 | u32 aspm_default:3; /* Default ASPM state by BIOS */ | |
54 | u32 aspm_disable:3; /* Disabled ASPM state */ | |
80bfdbe3 | 55 | |
4d246e45 KK |
56 | /* Clock PM state */ |
57 | u32 clkpm_capable:1; /* Clock PM capable? */ | |
58 | u32 clkpm_enabled:1; /* Current Clock PM state */ | |
59 | u32 clkpm_default:1; /* Default Clock PM state by BIOS */ | |
60 | ||
ac18018a KK |
61 | /* Exit latencies */ |
62 | struct aspm_latency latency_up; /* Upstream direction exit latency */ | |
63 | struct aspm_latency latency_dw; /* Downstream direction exit latency */ | |
7d715a6c | 64 | /* |
b6c2e54d KK |
65 | * Endpoint acceptable latencies. A pcie downstream port only |
66 | * has one slot under it, so at most there are 8 functions. | |
7d715a6c | 67 | */ |
b6c2e54d | 68 | struct aspm_latency acceptable[8]; |
7d715a6c SL |
69 | }; |
70 | ||
2f671e2d | 71 | static int aspm_disabled, aspm_force, aspm_clear_state; |
8b8bae90 | 72 | static bool aspm_support_enabled = true; |
7d715a6c SL |
73 | static DEFINE_MUTEX(aspm_lock); |
74 | static LIST_HEAD(link_list); | |
75 | ||
76 | #define POLICY_DEFAULT 0 /* BIOS default setting */ | |
77 | #define POLICY_PERFORMANCE 1 /* high performance */ | |
78 | #define POLICY_POWERSAVE 2 /* high power saving */ | |
79 | static int aspm_policy; | |
80 | static const char *policy_str[] = { | |
81 | [POLICY_DEFAULT] = "default", | |
82 | [POLICY_PERFORMANCE] = "performance", | |
83 | [POLICY_POWERSAVE] = "powersave" | |
84 | }; | |
85 | ||
987a4c78 AP |
86 | #define LINK_RETRAIN_TIMEOUT HZ |
87 | ||
5aa63583 | 88 | static int policy_to_aspm_state(struct pcie_link_state *link) |
7d715a6c | 89 | { |
7d715a6c SL |
90 | switch (aspm_policy) { |
91 | case POLICY_PERFORMANCE: | |
92 | /* Disable ASPM and Clock PM */ | |
93 | return 0; | |
94 | case POLICY_POWERSAVE: | |
95 | /* Enable ASPM L0s/L1 */ | |
ac18018a | 96 | return ASPM_STATE_ALL; |
7d715a6c | 97 | case POLICY_DEFAULT: |
5aa63583 | 98 | return link->aspm_default; |
7d715a6c SL |
99 | } |
100 | return 0; | |
101 | } | |
102 | ||
5aa63583 | 103 | static int policy_to_clkpm_state(struct pcie_link_state *link) |
7d715a6c | 104 | { |
7d715a6c SL |
105 | switch (aspm_policy) { |
106 | case POLICY_PERFORMANCE: | |
107 | /* Disable ASPM and Clock PM */ | |
108 | return 0; | |
109 | case POLICY_POWERSAVE: | |
110 | /* Disable Clock PM */ | |
111 | return 1; | |
112 | case POLICY_DEFAULT: | |
5aa63583 | 113 | return link->clkpm_default; |
7d715a6c SL |
114 | } |
115 | return 0; | |
116 | } | |
117 | ||
430842e2 | 118 | static void pcie_set_clkpm_nocheck(struct pcie_link_state *link, int enable) |
7d715a6c | 119 | { |
7d715a6c SL |
120 | int pos; |
121 | u16 reg16; | |
5aa63583 KK |
122 | struct pci_dev *child; |
123 | struct pci_bus *linkbus = link->pdev->subordinate; | |
7d715a6c | 124 | |
5aa63583 | 125 | list_for_each_entry(child, &linkbus->devices, bus_list) { |
db9538a7 | 126 | pos = pci_pcie_cap(child); |
7d715a6c SL |
127 | if (!pos) |
128 | return; | |
5aa63583 | 129 | pci_read_config_word(child, pos + PCI_EXP_LNKCTL, ®16); |
7d715a6c SL |
130 | if (enable) |
131 | reg16 |= PCI_EXP_LNKCTL_CLKREQ_EN; | |
132 | else | |
133 | reg16 &= ~PCI_EXP_LNKCTL_CLKREQ_EN; | |
5aa63583 | 134 | pci_write_config_word(child, pos + PCI_EXP_LNKCTL, reg16); |
7d715a6c | 135 | } |
5aa63583 | 136 | link->clkpm_enabled = !!enable; |
7d715a6c SL |
137 | } |
138 | ||
430842e2 KK |
139 | static void pcie_set_clkpm(struct pcie_link_state *link, int enable) |
140 | { | |
141 | /* Don't enable Clock PM if the link is not Clock PM capable */ | |
142 | if (!link->clkpm_capable && enable) | |
2f671e2d | 143 | enable = 0; |
430842e2 KK |
144 | /* Need nothing if the specified equals to current state */ |
145 | if (link->clkpm_enabled == enable) | |
146 | return; | |
147 | pcie_set_clkpm_nocheck(link, enable); | |
148 | } | |
149 | ||
8d349ace | 150 | static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist) |
7d715a6c | 151 | { |
5aa63583 | 152 | int pos, capable = 1, enabled = 1; |
7d715a6c SL |
153 | u32 reg32; |
154 | u16 reg16; | |
5aa63583 KK |
155 | struct pci_dev *child; |
156 | struct pci_bus *linkbus = link->pdev->subordinate; | |
7d715a6c SL |
157 | |
158 | /* All functions should have the same cap and state, take the worst */ | |
5aa63583 | 159 | list_for_each_entry(child, &linkbus->devices, bus_list) { |
db9538a7 | 160 | pos = pci_pcie_cap(child); |
7d715a6c SL |
161 | if (!pos) |
162 | return; | |
5aa63583 | 163 | pci_read_config_dword(child, pos + PCI_EXP_LNKCAP, ®32); |
7d715a6c SL |
164 | if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) { |
165 | capable = 0; | |
166 | enabled = 0; | |
167 | break; | |
168 | } | |
5aa63583 | 169 | pci_read_config_word(child, pos + PCI_EXP_LNKCTL, ®16); |
7d715a6c SL |
170 | if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN)) |
171 | enabled = 0; | |
172 | } | |
5aa63583 KK |
173 | link->clkpm_enabled = enabled; |
174 | link->clkpm_default = enabled; | |
8d349ace | 175 | link->clkpm_capable = (blacklist) ? 0 : capable; |
46bbdfa4 SL |
176 | } |
177 | ||
7d715a6c SL |
178 | /* |
179 | * pcie_aspm_configure_common_clock: check if the 2 ends of a link | |
180 | * could use common clock. If they are, configure them to use the | |
181 | * common clock. That will reduce the ASPM state exit latency. | |
182 | */ | |
5aa63583 | 183 | static void pcie_aspm_configure_common_clock(struct pcie_link_state *link) |
7d715a6c | 184 | { |
5aa63583 KK |
185 | int ppos, cpos, same_clock = 1; |
186 | u16 reg16, parent_reg, child_reg[8]; | |
2a42d9db | 187 | unsigned long start_jiffies; |
5aa63583 KK |
188 | struct pci_dev *child, *parent = link->pdev; |
189 | struct pci_bus *linkbus = parent->subordinate; | |
7d715a6c | 190 | /* |
5aa63583 | 191 | * All functions of a slot should have the same Slot Clock |
7d715a6c | 192 | * Configuration, so just check one function |
5aa63583 KK |
193 | */ |
194 | child = list_entry(linkbus->devices.next, struct pci_dev, bus_list); | |
8b06477d | 195 | BUG_ON(!pci_is_pcie(child)); |
7d715a6c SL |
196 | |
197 | /* Check downstream component if bit Slot Clock Configuration is 1 */ | |
db9538a7 | 198 | cpos = pci_pcie_cap(child); |
5aa63583 | 199 | pci_read_config_word(child, cpos + PCI_EXP_LNKSTA, ®16); |
7d715a6c SL |
200 | if (!(reg16 & PCI_EXP_LNKSTA_SLC)) |
201 | same_clock = 0; | |
202 | ||
203 | /* Check upstream component if bit Slot Clock Configuration is 1 */ | |
db9538a7 | 204 | ppos = pci_pcie_cap(parent); |
5aa63583 | 205 | pci_read_config_word(parent, ppos + PCI_EXP_LNKSTA, ®16); |
7d715a6c SL |
206 | if (!(reg16 & PCI_EXP_LNKSTA_SLC)) |
207 | same_clock = 0; | |
208 | ||
209 | /* Configure downstream component, all functions */ | |
5aa63583 | 210 | list_for_each_entry(child, &linkbus->devices, bus_list) { |
db9538a7 | 211 | cpos = pci_pcie_cap(child); |
5aa63583 KK |
212 | pci_read_config_word(child, cpos + PCI_EXP_LNKCTL, ®16); |
213 | child_reg[PCI_FUNC(child->devfn)] = reg16; | |
7d715a6c SL |
214 | if (same_clock) |
215 | reg16 |= PCI_EXP_LNKCTL_CCC; | |
216 | else | |
217 | reg16 &= ~PCI_EXP_LNKCTL_CCC; | |
5aa63583 | 218 | pci_write_config_word(child, cpos + PCI_EXP_LNKCTL, reg16); |
7d715a6c SL |
219 | } |
220 | ||
221 | /* Configure upstream component */ | |
5aa63583 | 222 | pci_read_config_word(parent, ppos + PCI_EXP_LNKCTL, ®16); |
2a42d9db | 223 | parent_reg = reg16; |
7d715a6c SL |
224 | if (same_clock) |
225 | reg16 |= PCI_EXP_LNKCTL_CCC; | |
226 | else | |
227 | reg16 &= ~PCI_EXP_LNKCTL_CCC; | |
5aa63583 | 228 | pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, reg16); |
7d715a6c | 229 | |
5aa63583 | 230 | /* Retrain link */ |
7d715a6c | 231 | reg16 |= PCI_EXP_LNKCTL_RL; |
5aa63583 | 232 | pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, reg16); |
7d715a6c | 233 | |
5aa63583 | 234 | /* Wait for link training end. Break out after waiting for timeout */ |
2a42d9db | 235 | start_jiffies = jiffies; |
987a4c78 | 236 | for (;;) { |
5aa63583 | 237 | pci_read_config_word(parent, ppos + PCI_EXP_LNKSTA, ®16); |
7d715a6c SL |
238 | if (!(reg16 & PCI_EXP_LNKSTA_LT)) |
239 | break; | |
987a4c78 AP |
240 | if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) |
241 | break; | |
242 | msleep(1); | |
7d715a6c | 243 | } |
5aa63583 KK |
244 | if (!(reg16 & PCI_EXP_LNKSTA_LT)) |
245 | return; | |
246 | ||
247 | /* Training failed. Restore common clock configurations */ | |
248 | dev_printk(KERN_ERR, &parent->dev, | |
249 | "ASPM: Could not configure common clock\n"); | |
250 | list_for_each_entry(child, &linkbus->devices, bus_list) { | |
db9538a7 | 251 | cpos = pci_pcie_cap(child); |
5aa63583 KK |
252 | pci_write_config_word(child, cpos + PCI_EXP_LNKCTL, |
253 | child_reg[PCI_FUNC(child->devfn)]); | |
2a42d9db | 254 | } |
5aa63583 | 255 | pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, parent_reg); |
7d715a6c SL |
256 | } |
257 | ||
5e0eaa7d KK |
258 | /* Convert L0s latency encoding to ns */ |
259 | static u32 calc_l0s_latency(u32 encoding) | |
7d715a6c | 260 | { |
5e0eaa7d KK |
261 | if (encoding == 0x7) |
262 | return (5 * 1000); /* > 4us */ | |
263 | return (64 << encoding); | |
264 | } | |
7d715a6c | 265 | |
5e0eaa7d KK |
266 | /* Convert L0s acceptable latency encoding to ns */ |
267 | static u32 calc_l0s_acceptable(u32 encoding) | |
268 | { | |
269 | if (encoding == 0x7) | |
270 | return -1U; | |
271 | return (64 << encoding); | |
7d715a6c SL |
272 | } |
273 | ||
5e0eaa7d KK |
274 | /* Convert L1 latency encoding to ns */ |
275 | static u32 calc_l1_latency(u32 encoding) | |
7d715a6c | 276 | { |
5e0eaa7d KK |
277 | if (encoding == 0x7) |
278 | return (65 * 1000); /* > 64us */ | |
279 | return (1000 << encoding); | |
280 | } | |
7d715a6c | 281 | |
5e0eaa7d KK |
282 | /* Convert L1 acceptable latency encoding to ns */ |
283 | static u32 calc_l1_acceptable(u32 encoding) | |
284 | { | |
285 | if (encoding == 0x7) | |
286 | return -1U; | |
287 | return (1000 << encoding); | |
7d715a6c SL |
288 | } |
289 | ||
ac18018a KK |
290 | struct aspm_register_info { |
291 | u32 support:2; | |
292 | u32 enabled:2; | |
293 | u32 latency_encoding_l0s; | |
294 | u32 latency_encoding_l1; | |
295 | }; | |
296 | ||
297 | static void pcie_get_aspm_reg(struct pci_dev *pdev, | |
298 | struct aspm_register_info *info) | |
7d715a6c SL |
299 | { |
300 | int pos; | |
301 | u16 reg16; | |
ac18018a | 302 | u32 reg32; |
7d715a6c | 303 | |
db9538a7 | 304 | pos = pci_pcie_cap(pdev); |
7d715a6c | 305 | pci_read_config_dword(pdev, pos + PCI_EXP_LNKCAP, ®32); |
ac18018a | 306 | info->support = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10; |
ac18018a KK |
307 | info->latency_encoding_l0s = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12; |
308 | info->latency_encoding_l1 = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15; | |
7d715a6c | 309 | pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, ®16); |
ac18018a | 310 | info->enabled = reg16 & PCI_EXP_LNKCTL_ASPMC; |
7d715a6c SL |
311 | } |
312 | ||
07d92760 KK |
313 | static void pcie_aspm_check_latency(struct pci_dev *endpoint) |
314 | { | |
ac18018a | 315 | u32 latency, l1_switch_latency = 0; |
07d92760 KK |
316 | struct aspm_latency *acceptable; |
317 | struct pcie_link_state *link; | |
318 | ||
319 | /* Device not in D0 doesn't need latency check */ | |
320 | if ((endpoint->current_state != PCI_D0) && | |
321 | (endpoint->current_state != PCI_UNKNOWN)) | |
322 | return; | |
323 | ||
324 | link = endpoint->bus->self->link_state; | |
325 | acceptable = &link->acceptable[PCI_FUNC(endpoint->devfn)]; | |
326 | ||
327 | while (link) { | |
ac18018a KK |
328 | /* Check upstream direction L0s latency */ |
329 | if ((link->aspm_capable & ASPM_STATE_L0S_UP) && | |
330 | (link->latency_up.l0s > acceptable->l0s)) | |
331 | link->aspm_capable &= ~ASPM_STATE_L0S_UP; | |
332 | ||
333 | /* Check downstream direction L0s latency */ | |
334 | if ((link->aspm_capable & ASPM_STATE_L0S_DW) && | |
335 | (link->latency_dw.l0s > acceptable->l0s)) | |
336 | link->aspm_capable &= ~ASPM_STATE_L0S_DW; | |
07d92760 KK |
337 | /* |
338 | * Check L1 latency. | |
339 | * Every switch on the path to root complex need 1 | |
340 | * more microsecond for L1. Spec doesn't mention L0s. | |
341 | */ | |
ac18018a KK |
342 | latency = max_t(u32, link->latency_up.l1, link->latency_dw.l1); |
343 | if ((link->aspm_capable & ASPM_STATE_L1) && | |
344 | (latency + l1_switch_latency > acceptable->l1)) | |
345 | link->aspm_capable &= ~ASPM_STATE_L1; | |
07d92760 KK |
346 | l1_switch_latency += 1000; |
347 | ||
348 | link = link->parent; | |
349 | } | |
350 | } | |
351 | ||
8d349ace | 352 | static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) |
7d715a6c | 353 | { |
5aa63583 KK |
354 | struct pci_dev *child, *parent = link->pdev; |
355 | struct pci_bus *linkbus = parent->subordinate; | |
ac18018a | 356 | struct aspm_register_info upreg, dwreg; |
7d715a6c | 357 | |
8d349ace | 358 | if (blacklist) { |
f1c0ca29 | 359 | /* Set enabled/disable so that we will disable ASPM later */ |
ac18018a KK |
360 | link->aspm_enabled = ASPM_STATE_ALL; |
361 | link->aspm_disable = ASPM_STATE_ALL; | |
8d349ace KK |
362 | return; |
363 | } | |
364 | ||
365 | /* Configure common clock before checking latencies */ | |
366 | pcie_aspm_configure_common_clock(link); | |
367 | ||
ac18018a KK |
368 | /* Get upstream/downstream components' register state */ |
369 | pcie_get_aspm_reg(parent, &upreg); | |
5aa63583 | 370 | child = list_entry(linkbus->devices.next, struct pci_dev, bus_list); |
ac18018a KK |
371 | pcie_get_aspm_reg(child, &dwreg); |
372 | ||
373 | /* | |
374 | * Setup L0s state | |
375 | * | |
376 | * Note that we must not enable L0s in either direction on a | |
377 | * given link unless components on both sides of the link each | |
378 | * support L0s. | |
379 | */ | |
380 | if (dwreg.support & upreg.support & PCIE_LINK_STATE_L0S) | |
381 | link->aspm_support |= ASPM_STATE_L0S; | |
382 | if (dwreg.enabled & PCIE_LINK_STATE_L0S) | |
383 | link->aspm_enabled |= ASPM_STATE_L0S_UP; | |
384 | if (upreg.enabled & PCIE_LINK_STATE_L0S) | |
385 | link->aspm_enabled |= ASPM_STATE_L0S_DW; | |
386 | link->latency_up.l0s = calc_l0s_latency(upreg.latency_encoding_l0s); | |
387 | link->latency_dw.l0s = calc_l0s_latency(dwreg.latency_encoding_l0s); | |
388 | ||
389 | /* Setup L1 state */ | |
390 | if (upreg.support & dwreg.support & PCIE_LINK_STATE_L1) | |
391 | link->aspm_support |= ASPM_STATE_L1; | |
392 | if (upreg.enabled & dwreg.enabled & PCIE_LINK_STATE_L1) | |
393 | link->aspm_enabled |= ASPM_STATE_L1; | |
394 | link->latency_up.l1 = calc_l1_latency(upreg.latency_encoding_l1); | |
395 | link->latency_dw.l1 = calc_l1_latency(dwreg.latency_encoding_l1); | |
5aa63583 | 396 | |
b127bd55 KK |
397 | /* Save default state */ |
398 | link->aspm_default = link->aspm_enabled; | |
07d92760 KK |
399 | |
400 | /* Setup initial capable state. Will be updated later */ | |
401 | link->aspm_capable = link->aspm_support; | |
f1c0ca29 KK |
402 | /* |
403 | * If the downstream component has pci bridge function, don't | |
404 | * do ASPM for now. | |
405 | */ | |
406 | list_for_each_entry(child, &linkbus->devices, bus_list) { | |
407 | if (child->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE) { | |
ac18018a | 408 | link->aspm_disable = ASPM_STATE_ALL; |
f1c0ca29 KK |
409 | break; |
410 | } | |
411 | } | |
b127bd55 | 412 | |
b7206cbf | 413 | /* Get and check endpoint acceptable latencies */ |
5aa63583 | 414 | list_for_each_entry(child, &linkbus->devices, bus_list) { |
7d715a6c | 415 | int pos; |
5e0eaa7d | 416 | u32 reg32, encoding; |
b6c2e54d | 417 | struct aspm_latency *acceptable = |
5aa63583 | 418 | &link->acceptable[PCI_FUNC(child->devfn)]; |
7d715a6c | 419 | |
5aa63583 KK |
420 | if (child->pcie_type != PCI_EXP_TYPE_ENDPOINT && |
421 | child->pcie_type != PCI_EXP_TYPE_LEG_END) | |
7d715a6c SL |
422 | continue; |
423 | ||
db9538a7 | 424 | pos = pci_pcie_cap(child); |
5aa63583 | 425 | pci_read_config_dword(child, pos + PCI_EXP_DEVCAP, ®32); |
07d92760 | 426 | /* Calculate endpoint L0s acceptable latency */ |
5e0eaa7d KK |
427 | encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6; |
428 | acceptable->l0s = calc_l0s_acceptable(encoding); | |
07d92760 KK |
429 | /* Calculate endpoint L1 acceptable latency */ |
430 | encoding = (reg32 & PCI_EXP_DEVCAP_L1) >> 9; | |
431 | acceptable->l1 = calc_l1_acceptable(encoding); | |
432 | ||
433 | pcie_aspm_check_latency(child); | |
7d715a6c SL |
434 | } |
435 | } | |
436 | ||
ac18018a | 437 | static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val) |
7d715a6c SL |
438 | { |
439 | u16 reg16; | |
db9538a7 | 440 | int pos = pci_pcie_cap(pdev); |
7d715a6c SL |
441 | |
442 | pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, ®16); | |
443 | reg16 &= ~0x3; | |
ac18018a | 444 | reg16 |= val; |
7d715a6c SL |
445 | pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16); |
446 | } | |
447 | ||
b7206cbf | 448 | static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state) |
7d715a6c | 449 | { |
ac18018a | 450 | u32 upstream = 0, dwstream = 0; |
5aa63583 KK |
451 | struct pci_dev *child, *parent = link->pdev; |
452 | struct pci_bus *linkbus = parent->subordinate; | |
7d715a6c | 453 | |
f1c0ca29 | 454 | /* Nothing to do if the link is already in the requested state */ |
b7206cbf | 455 | state &= (link->aspm_capable & ~link->aspm_disable); |
f1c0ca29 KK |
456 | if (link->aspm_enabled == state) |
457 | return; | |
ac18018a KK |
458 | /* Convert ASPM state to upstream/downstream ASPM register state */ |
459 | if (state & ASPM_STATE_L0S_UP) | |
460 | dwstream |= PCIE_LINK_STATE_L0S; | |
461 | if (state & ASPM_STATE_L0S_DW) | |
462 | upstream |= PCIE_LINK_STATE_L0S; | |
463 | if (state & ASPM_STATE_L1) { | |
464 | upstream |= PCIE_LINK_STATE_L1; | |
465 | dwstream |= PCIE_LINK_STATE_L1; | |
466 | } | |
7d715a6c | 467 | /* |
5aa63583 KK |
468 | * Spec 2.0 suggests all functions should be configured the |
469 | * same setting for ASPM. Enabling ASPM L1 should be done in | |
470 | * upstream component first and then downstream, and vice | |
471 | * versa for disabling ASPM L1. Spec doesn't mention L0S. | |
7d715a6c | 472 | */ |
ac18018a KK |
473 | if (state & ASPM_STATE_L1) |
474 | pcie_config_aspm_dev(parent, upstream); | |
5aa63583 | 475 | list_for_each_entry(child, &linkbus->devices, bus_list) |
ac18018a KK |
476 | pcie_config_aspm_dev(child, dwstream); |
477 | if (!(state & ASPM_STATE_L1)) | |
478 | pcie_config_aspm_dev(parent, upstream); | |
7d715a6c | 479 | |
5aa63583 | 480 | link->aspm_enabled = state; |
7d715a6c SL |
481 | } |
482 | ||
b7206cbf | 483 | static void pcie_config_aspm_path(struct pcie_link_state *link) |
7d715a6c | 484 | { |
b7206cbf KK |
485 | while (link) { |
486 | pcie_config_aspm_link(link, policy_to_aspm_state(link)); | |
487 | link = link->parent; | |
46bbdfa4 | 488 | } |
7d715a6c SL |
489 | } |
490 | ||
5aa63583 | 491 | static void free_link_state(struct pcie_link_state *link) |
7d715a6c | 492 | { |
5aa63583 KK |
493 | link->pdev->link_state = NULL; |
494 | kfree(link); | |
7d715a6c SL |
495 | } |
496 | ||
ddc9753f SL |
497 | static int pcie_aspm_sanity_check(struct pci_dev *pdev) |
498 | { | |
3647584d KK |
499 | struct pci_dev *child; |
500 | int pos; | |
149e1637 | 501 | u32 reg32; |
2f671e2d MG |
502 | |
503 | if (aspm_clear_state) | |
504 | return -EINVAL; | |
505 | ||
ddc9753f | 506 | /* |
45e829ea | 507 | * Some functions in a slot might not all be PCIe functions, |
3647584d | 508 | * very strange. Disable ASPM for the whole slot |
ddc9753f | 509 | */ |
3647584d | 510 | list_for_each_entry(child, &pdev->subordinate->devices, bus_list) { |
db9538a7 | 511 | pos = pci_pcie_cap(child); |
3647584d | 512 | if (!pos) |
ddc9753f | 513 | return -EINVAL; |
149e1637 SL |
514 | /* |
515 | * Disable ASPM for pre-1.1 PCIe device, we follow MS to use | |
516 | * RBER bit to determine if a function is 1.1 version device | |
517 | */ | |
3647584d | 518 | pci_read_config_dword(child, pos + PCI_EXP_DEVCAP, ®32); |
e1f4f59d | 519 | if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) { |
3647584d | 520 | dev_printk(KERN_INFO, &child->dev, "disabling ASPM" |
f393d9b1 VL |
521 | " on pre-1.1 PCIe device. You can enable it" |
522 | " with 'pcie_aspm=force'\n"); | |
149e1637 SL |
523 | return -EINVAL; |
524 | } | |
ddc9753f SL |
525 | } |
526 | return 0; | |
527 | } | |
528 | ||
b7206cbf | 529 | static struct pcie_link_state *alloc_pcie_link_state(struct pci_dev *pdev) |
8d349ace KK |
530 | { |
531 | struct pcie_link_state *link; | |
8d349ace KK |
532 | |
533 | link = kzalloc(sizeof(*link), GFP_KERNEL); | |
534 | if (!link) | |
535 | return NULL; | |
536 | INIT_LIST_HEAD(&link->sibling); | |
537 | INIT_LIST_HEAD(&link->children); | |
538 | INIT_LIST_HEAD(&link->link); | |
539 | link->pdev = pdev; | |
8d349ace KK |
540 | if (pdev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM) { |
541 | struct pcie_link_state *parent; | |
542 | parent = pdev->bus->parent->self->link_state; | |
543 | if (!parent) { | |
544 | kfree(link); | |
545 | return NULL; | |
546 | } | |
547 | link->parent = parent; | |
548 | list_add(&link->link, &parent->children); | |
549 | } | |
5c92ffb1 KK |
550 | /* Setup a pointer to the root port link */ |
551 | if (!link->parent) | |
552 | link->root = link; | |
553 | else | |
554 | link->root = link->parent->root; | |
555 | ||
8d349ace | 556 | list_add(&link->sibling, &link_list); |
8d349ace | 557 | pdev->link_state = link; |
8d349ace KK |
558 | return link; |
559 | } | |
560 | ||
7d715a6c SL |
561 | /* |
562 | * pcie_aspm_init_link_state: Initiate PCI express link state. | |
563 | * It is called after the pcie and its children devices are scaned. | |
564 | * @pdev: the root port or switch downstream port | |
565 | */ | |
566 | void pcie_aspm_init_link_state(struct pci_dev *pdev) | |
567 | { | |
8d349ace | 568 | struct pcie_link_state *link; |
b7206cbf | 569 | int blacklist = !!pcie_aspm_sanity_check(pdev); |
7d715a6c | 570 | |
2f671e2d | 571 | if (!pci_is_pcie(pdev) || pdev->link_state) |
7d715a6c SL |
572 | return; |
573 | if (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && | |
8d349ace | 574 | pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) |
7d715a6c | 575 | return; |
8d349ace | 576 | |
2f671e2d MG |
577 | if (aspm_disabled && !aspm_clear_state) |
578 | return; | |
579 | ||
8e822df7 SL |
580 | /* VIA has a strange chipset, root port is under a bridge */ |
581 | if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT && | |
8d349ace | 582 | pdev->bus->self) |
8e822df7 | 583 | return; |
8d349ace | 584 | |
7d715a6c SL |
585 | down_read(&pci_bus_sem); |
586 | if (list_empty(&pdev->subordinate->devices)) | |
587 | goto out; | |
588 | ||
589 | mutex_lock(&aspm_lock); | |
b7206cbf | 590 | link = alloc_pcie_link_state(pdev); |
8d349ace KK |
591 | if (!link) |
592 | goto unlock; | |
593 | /* | |
b7206cbf KK |
594 | * Setup initial ASPM state. Note that we need to configure |
595 | * upstream links also because capable state of them can be | |
596 | * update through pcie_aspm_cap_init(). | |
8d349ace | 597 | */ |
b7206cbf | 598 | pcie_aspm_cap_init(link, blacklist); |
7d715a6c | 599 | |
8d349ace | 600 | /* Setup initial Clock PM state */ |
b7206cbf | 601 | pcie_clkpm_cap_init(link, blacklist); |
41cd766b MG |
602 | |
603 | /* | |
604 | * At this stage drivers haven't had an opportunity to change the | |
605 | * link policy setting. Enabling ASPM on broken hardware can cripple | |
606 | * it even before the driver has had a chance to disable ASPM, so | |
607 | * default to a safe level right now. If we're enabling ASPM beyond | |
608 | * the BIOS's expectation, we'll do so once pci_enable_device() is | |
609 | * called. | |
610 | */ | |
3504e47f | 611 | if (aspm_policy != POLICY_POWERSAVE || aspm_clear_state) { |
41cd766b MG |
612 | pcie_config_aspm_path(link); |
613 | pcie_set_clkpm(link, policy_to_clkpm_state(link)); | |
614 | } | |
615 | ||
8d349ace | 616 | unlock: |
7d715a6c SL |
617 | mutex_unlock(&aspm_lock); |
618 | out: | |
619 | up_read(&pci_bus_sem); | |
620 | } | |
621 | ||
07d92760 KK |
622 | /* Recheck latencies and update aspm_capable for links under the root */ |
623 | static void pcie_update_aspm_capable(struct pcie_link_state *root) | |
624 | { | |
625 | struct pcie_link_state *link; | |
626 | BUG_ON(root->parent); | |
627 | list_for_each_entry(link, &link_list, sibling) { | |
628 | if (link->root != root) | |
629 | continue; | |
630 | link->aspm_capable = link->aspm_support; | |
631 | } | |
632 | list_for_each_entry(link, &link_list, sibling) { | |
633 | struct pci_dev *child; | |
634 | struct pci_bus *linkbus = link->pdev->subordinate; | |
635 | if (link->root != root) | |
636 | continue; | |
637 | list_for_each_entry(child, &linkbus->devices, bus_list) { | |
638 | if ((child->pcie_type != PCI_EXP_TYPE_ENDPOINT) && | |
639 | (child->pcie_type != PCI_EXP_TYPE_LEG_END)) | |
640 | continue; | |
641 | pcie_aspm_check_latency(child); | |
642 | } | |
643 | } | |
644 | } | |
645 | ||
7d715a6c SL |
646 | /* @pdev: the endpoint device */ |
647 | void pcie_aspm_exit_link_state(struct pci_dev *pdev) | |
648 | { | |
649 | struct pci_dev *parent = pdev->bus->self; | |
b7206cbf | 650 | struct pcie_link_state *link, *root, *parent_link; |
7d715a6c | 651 | |
2f671e2d | 652 | if ((aspm_disabled && !aspm_clear_state) || !pci_is_pcie(pdev) || |
8b06477d | 653 | !parent || !parent->link_state) |
7d715a6c | 654 | return; |
b7206cbf KK |
655 | if ((parent->pcie_type != PCI_EXP_TYPE_ROOT_PORT) && |
656 | (parent->pcie_type != PCI_EXP_TYPE_DOWNSTREAM)) | |
7d715a6c | 657 | return; |
fc87e919 | 658 | |
7d715a6c SL |
659 | down_read(&pci_bus_sem); |
660 | mutex_lock(&aspm_lock); | |
7d715a6c SL |
661 | /* |
662 | * All PCIe functions are in one slot, remove one function will remove | |
3419c75e | 663 | * the whole slot, so just wait until we are the last function left. |
7d715a6c | 664 | */ |
3419c75e | 665 | if (!list_is_last(&pdev->bus_list, &parent->subordinate->devices)) |
7d715a6c SL |
666 | goto out; |
667 | ||
fc87e919 | 668 | link = parent->link_state; |
07d92760 | 669 | root = link->root; |
b7206cbf | 670 | parent_link = link->parent; |
fc87e919 | 671 | |
7d715a6c | 672 | /* All functions are removed, so just disable ASPM for the link */ |
b7206cbf | 673 | pcie_config_aspm_link(link, 0); |
fc87e919 KK |
674 | list_del(&link->sibling); |
675 | list_del(&link->link); | |
7d715a6c | 676 | /* Clock PM is for endpoint device */ |
fc87e919 | 677 | free_link_state(link); |
07d92760 KK |
678 | |
679 | /* Recheck latencies and configure upstream links */ | |
b26a34aa KK |
680 | if (parent_link) { |
681 | pcie_update_aspm_capable(root); | |
682 | pcie_config_aspm_path(parent_link); | |
683 | } | |
7d715a6c SL |
684 | out: |
685 | mutex_unlock(&aspm_lock); | |
686 | up_read(&pci_bus_sem); | |
687 | } | |
688 | ||
689 | /* @pdev: the root port or switch downstream port */ | |
690 | void pcie_aspm_pm_state_change(struct pci_dev *pdev) | |
691 | { | |
07d92760 | 692 | struct pcie_link_state *link = pdev->link_state; |
7d715a6c | 693 | |
8b06477d | 694 | if (aspm_disabled || !pci_is_pcie(pdev) || !link) |
7d715a6c | 695 | return; |
07d92760 KK |
696 | if ((pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT) && |
697 | (pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM)) | |
7d715a6c SL |
698 | return; |
699 | /* | |
07d92760 KK |
700 | * Devices changed PM state, we should recheck if latency |
701 | * meets all functions' requirement | |
7d715a6c | 702 | */ |
07d92760 KK |
703 | down_read(&pci_bus_sem); |
704 | mutex_lock(&aspm_lock); | |
705 | pcie_update_aspm_capable(link->root); | |
b7206cbf | 706 | pcie_config_aspm_path(link); |
07d92760 KK |
707 | mutex_unlock(&aspm_lock); |
708 | up_read(&pci_bus_sem); | |
7d715a6c SL |
709 | } |
710 | ||
1a680b7c NC |
711 | void pcie_aspm_powersave_config_link(struct pci_dev *pdev) |
712 | { | |
713 | struct pcie_link_state *link = pdev->link_state; | |
714 | ||
715 | if (aspm_disabled || !pci_is_pcie(pdev) || !link) | |
716 | return; | |
717 | ||
718 | if (aspm_policy != POLICY_POWERSAVE) | |
719 | return; | |
720 | ||
721 | if ((pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT) && | |
722 | (pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM)) | |
723 | return; | |
724 | ||
725 | down_read(&pci_bus_sem); | |
726 | mutex_lock(&aspm_lock); | |
727 | pcie_config_aspm_path(link); | |
728 | pcie_set_clkpm(link, policy_to_clkpm_state(link)); | |
729 | mutex_unlock(&aspm_lock); | |
730 | up_read(&pci_bus_sem); | |
731 | } | |
732 | ||
7d715a6c SL |
733 | /* |
734 | * pci_disable_link_state - disable pci device's link state, so the link will | |
735 | * never enter specific states | |
736 | */ | |
737 | void pci_disable_link_state(struct pci_dev *pdev, int state) | |
738 | { | |
739 | struct pci_dev *parent = pdev->bus->self; | |
f1c0ca29 | 740 | struct pcie_link_state *link; |
7d715a6c | 741 | |
8b06477d | 742 | if (aspm_disabled || !pci_is_pcie(pdev)) |
7d715a6c SL |
743 | return; |
744 | if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT || | |
745 | pdev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM) | |
746 | parent = pdev; | |
747 | if (!parent || !parent->link_state) | |
748 | return; | |
749 | ||
750 | down_read(&pci_bus_sem); | |
751 | mutex_lock(&aspm_lock); | |
f1c0ca29 | 752 | link = parent->link_state; |
ac18018a KK |
753 | if (state & PCIE_LINK_STATE_L0S) |
754 | link->aspm_disable |= ASPM_STATE_L0S; | |
755 | if (state & PCIE_LINK_STATE_L1) | |
756 | link->aspm_disable |= ASPM_STATE_L1; | |
b7206cbf KK |
757 | pcie_config_aspm_link(link, policy_to_aspm_state(link)); |
758 | ||
430842e2 | 759 | if (state & PCIE_LINK_STATE_CLKPM) { |
f1c0ca29 KK |
760 | link->clkpm_capable = 0; |
761 | pcie_set_clkpm(link, 0); | |
430842e2 | 762 | } |
7d715a6c SL |
763 | mutex_unlock(&aspm_lock); |
764 | up_read(&pci_bus_sem); | |
765 | } | |
766 | EXPORT_SYMBOL(pci_disable_link_state); | |
767 | ||
768 | static int pcie_aspm_set_policy(const char *val, struct kernel_param *kp) | |
769 | { | |
770 | int i; | |
b7206cbf | 771 | struct pcie_link_state *link; |
7d715a6c | 772 | |
bbfa306a NC |
773 | if (aspm_disabled) |
774 | return -EPERM; | |
7d715a6c SL |
775 | for (i = 0; i < ARRAY_SIZE(policy_str); i++) |
776 | if (!strncmp(val, policy_str[i], strlen(policy_str[i]))) | |
777 | break; | |
778 | if (i >= ARRAY_SIZE(policy_str)) | |
779 | return -EINVAL; | |
780 | if (i == aspm_policy) | |
781 | return 0; | |
782 | ||
783 | down_read(&pci_bus_sem); | |
784 | mutex_lock(&aspm_lock); | |
785 | aspm_policy = i; | |
b7206cbf KK |
786 | list_for_each_entry(link, &link_list, sibling) { |
787 | pcie_config_aspm_link(link, policy_to_aspm_state(link)); | |
788 | pcie_set_clkpm(link, policy_to_clkpm_state(link)); | |
7d715a6c SL |
789 | } |
790 | mutex_unlock(&aspm_lock); | |
791 | up_read(&pci_bus_sem); | |
792 | return 0; | |
793 | } | |
794 | ||
795 | static int pcie_aspm_get_policy(char *buffer, struct kernel_param *kp) | |
796 | { | |
797 | int i, cnt = 0; | |
798 | for (i = 0; i < ARRAY_SIZE(policy_str); i++) | |
799 | if (i == aspm_policy) | |
800 | cnt += sprintf(buffer + cnt, "[%s] ", policy_str[i]); | |
801 | else | |
802 | cnt += sprintf(buffer + cnt, "%s ", policy_str[i]); | |
803 | return cnt; | |
804 | } | |
805 | ||
806 | module_param_call(policy, pcie_aspm_set_policy, pcie_aspm_get_policy, | |
807 | NULL, 0644); | |
808 | ||
809 | #ifdef CONFIG_PCIEASPM_DEBUG | |
810 | static ssize_t link_state_show(struct device *dev, | |
811 | struct device_attribute *attr, | |
812 | char *buf) | |
813 | { | |
814 | struct pci_dev *pci_device = to_pci_dev(dev); | |
815 | struct pcie_link_state *link_state = pci_device->link_state; | |
816 | ||
80bfdbe3 | 817 | return sprintf(buf, "%d\n", link_state->aspm_enabled); |
7d715a6c SL |
818 | } |
819 | ||
820 | static ssize_t link_state_store(struct device *dev, | |
821 | struct device_attribute *attr, | |
822 | const char *buf, | |
823 | size_t n) | |
824 | { | |
5aa63583 | 825 | struct pci_dev *pdev = to_pci_dev(dev); |
b7206cbf | 826 | struct pcie_link_state *link, *root = pdev->link_state->root; |
ac18018a | 827 | u32 val = buf[0] - '0', state = 0; |
7d715a6c | 828 | |
bbfa306a NC |
829 | if (aspm_disabled) |
830 | return -EPERM; | |
ac18018a | 831 | if (n < 1 || val > 3) |
7d715a6c | 832 | return -EINVAL; |
7d715a6c | 833 | |
ac18018a KK |
834 | /* Convert requested state to ASPM state */ |
835 | if (val & PCIE_LINK_STATE_L0S) | |
836 | state |= ASPM_STATE_L0S; | |
837 | if (val & PCIE_LINK_STATE_L1) | |
838 | state |= ASPM_STATE_L1; | |
839 | ||
b7206cbf KK |
840 | down_read(&pci_bus_sem); |
841 | mutex_lock(&aspm_lock); | |
842 | list_for_each_entry(link, &link_list, sibling) { | |
843 | if (link->root != root) | |
844 | continue; | |
845 | pcie_config_aspm_link(link, state); | |
846 | } | |
847 | mutex_unlock(&aspm_lock); | |
848 | up_read(&pci_bus_sem); | |
849 | return n; | |
7d715a6c SL |
850 | } |
851 | ||
852 | static ssize_t clk_ctl_show(struct device *dev, | |
853 | struct device_attribute *attr, | |
854 | char *buf) | |
855 | { | |
856 | struct pci_dev *pci_device = to_pci_dev(dev); | |
857 | struct pcie_link_state *link_state = pci_device->link_state; | |
858 | ||
4d246e45 | 859 | return sprintf(buf, "%d\n", link_state->clkpm_enabled); |
7d715a6c SL |
860 | } |
861 | ||
862 | static ssize_t clk_ctl_store(struct device *dev, | |
863 | struct device_attribute *attr, | |
864 | const char *buf, | |
865 | size_t n) | |
866 | { | |
430842e2 | 867 | struct pci_dev *pdev = to_pci_dev(dev); |
7d715a6c SL |
868 | int state; |
869 | ||
870 | if (n < 1) | |
871 | return -EINVAL; | |
872 | state = buf[0]-'0'; | |
873 | ||
874 | down_read(&pci_bus_sem); | |
875 | mutex_lock(&aspm_lock); | |
430842e2 | 876 | pcie_set_clkpm_nocheck(pdev->link_state, !!state); |
7d715a6c SL |
877 | mutex_unlock(&aspm_lock); |
878 | up_read(&pci_bus_sem); | |
879 | ||
880 | return n; | |
881 | } | |
882 | ||
883 | static DEVICE_ATTR(link_state, 0644, link_state_show, link_state_store); | |
884 | static DEVICE_ATTR(clk_ctl, 0644, clk_ctl_show, clk_ctl_store); | |
885 | ||
886 | static char power_group[] = "power"; | |
887 | void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev) | |
888 | { | |
889 | struct pcie_link_state *link_state = pdev->link_state; | |
890 | ||
8b06477d KK |
891 | if (!pci_is_pcie(pdev) || |
892 | (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && | |
893 | pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) || !link_state) | |
7d715a6c SL |
894 | return; |
895 | ||
80bfdbe3 | 896 | if (link_state->aspm_support) |
7d715a6c SL |
897 | sysfs_add_file_to_group(&pdev->dev.kobj, |
898 | &dev_attr_link_state.attr, power_group); | |
4d246e45 | 899 | if (link_state->clkpm_capable) |
7d715a6c SL |
900 | sysfs_add_file_to_group(&pdev->dev.kobj, |
901 | &dev_attr_clk_ctl.attr, power_group); | |
902 | } | |
903 | ||
904 | void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev) | |
905 | { | |
906 | struct pcie_link_state *link_state = pdev->link_state; | |
907 | ||
8b06477d KK |
908 | if (!pci_is_pcie(pdev) || |
909 | (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && | |
910 | pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) || !link_state) | |
7d715a6c SL |
911 | return; |
912 | ||
80bfdbe3 | 913 | if (link_state->aspm_support) |
7d715a6c SL |
914 | sysfs_remove_file_from_group(&pdev->dev.kobj, |
915 | &dev_attr_link_state.attr, power_group); | |
4d246e45 | 916 | if (link_state->clkpm_capable) |
7d715a6c SL |
917 | sysfs_remove_file_from_group(&pdev->dev.kobj, |
918 | &dev_attr_clk_ctl.attr, power_group); | |
919 | } | |
920 | #endif | |
921 | ||
922 | static int __init pcie_aspm_disable(char *str) | |
923 | { | |
d6d38574 SL |
924 | if (!strcmp(str, "off")) { |
925 | aspm_disabled = 1; | |
8b8bae90 | 926 | aspm_support_enabled = false; |
d6d38574 SL |
927 | printk(KERN_INFO "PCIe ASPM is disabled\n"); |
928 | } else if (!strcmp(str, "force")) { | |
929 | aspm_force = 1; | |
930 | printk(KERN_INFO "PCIe ASPM is forcedly enabled\n"); | |
931 | } | |
7d715a6c SL |
932 | return 1; |
933 | } | |
934 | ||
d6d38574 | 935 | __setup("pcie_aspm=", pcie_aspm_disable); |
7d715a6c | 936 | |
2f671e2d MG |
937 | void pcie_clear_aspm(void) |
938 | { | |
939 | if (!aspm_force) | |
940 | aspm_clear_state = 1; | |
941 | } | |
942 | ||
5fde244d SL |
943 | void pcie_no_aspm(void) |
944 | { | |
d6d38574 SL |
945 | if (!aspm_force) |
946 | aspm_disabled = 1; | |
5fde244d SL |
947 | } |
948 | ||
3e1b1600 AP |
949 | /** |
950 | * pcie_aspm_enabled - is PCIe ASPM enabled? | |
951 | * | |
952 | * Returns true if ASPM has not been disabled by the command-line option | |
953 | * pcie_aspm=off. | |
954 | **/ | |
955 | int pcie_aspm_enabled(void) | |
7d715a6c | 956 | { |
3e1b1600 | 957 | return !aspm_disabled; |
7d715a6c | 958 | } |
3e1b1600 | 959 | EXPORT_SYMBOL(pcie_aspm_enabled); |
7d715a6c | 960 | |
8b8bae90 RW |
961 | bool pcie_aspm_support_enabled(void) |
962 | { | |
963 | return aspm_support_enabled; | |
964 | } | |
965 | EXPORT_SYMBOL(pcie_aspm_support_enabled); |