]>
Commit | Line | Data |
---|---|---|
7d715a6c SL |
1 | /* |
2 | * File: drivers/pci/pcie/aspm.c | |
45e829ea | 3 | * Enabling PCIe link L0s/L1 state and Clock Power Management |
7d715a6c SL |
4 | * |
5 | * Copyright (C) 2007 Intel | |
6 | * Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com) | |
7 | * Copyright (C) Shaohua Li (shaohua.li@intel.com) | |
8 | */ | |
9 | ||
10 | #include <linux/kernel.h> | |
11 | #include <linux/module.h> | |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/pci.h> | |
14 | #include <linux/pci_regs.h> | |
15 | #include <linux/errno.h> | |
16 | #include <linux/pm.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/slab.h> | |
2a42d9db | 19 | #include <linux/jiffies.h> |
987a4c78 | 20 | #include <linux/delay.h> |
7d715a6c SL |
21 | #include <linux/pci-aspm.h> |
22 | #include "../pci.h" | |
23 | ||
24 | #ifdef MODULE_PARAM_PREFIX | |
25 | #undef MODULE_PARAM_PREFIX | |
26 | #endif | |
27 | #define MODULE_PARAM_PREFIX "pcie_aspm." | |
28 | ||
ac18018a KK |
29 | /* Note: those are not register definitions */ |
30 | #define ASPM_STATE_L0S_UP (1) /* Upstream direction L0s state */ | |
31 | #define ASPM_STATE_L0S_DW (2) /* Downstream direction L0s state */ | |
32 | #define ASPM_STATE_L1 (4) /* L1 state */ | |
33 | #define ASPM_STATE_L0S (ASPM_STATE_L0S_UP | ASPM_STATE_L0S_DW) | |
34 | #define ASPM_STATE_ALL (ASPM_STATE_L0S | ASPM_STATE_L1) | |
35 | ||
b6c2e54d KK |
36 | struct aspm_latency { |
37 | u32 l0s; /* L0s latency (nsec) */ | |
38 | u32 l1; /* L1 latency (nsec) */ | |
7d715a6c SL |
39 | }; |
40 | ||
41 | struct pcie_link_state { | |
5cde89d8 | 42 | struct pci_dev *pdev; /* Upstream component of the Link */ |
5c92ffb1 | 43 | struct pcie_link_state *root; /* pointer to the root port link */ |
5cde89d8 KK |
44 | struct pcie_link_state *parent; /* pointer to the parent Link state */ |
45 | struct list_head sibling; /* node in link_list */ | |
46 | struct list_head children; /* list of child link states */ | |
47 | struct list_head link; /* node in parent's children list */ | |
7d715a6c SL |
48 | |
49 | /* ASPM state */ | |
ac18018a KK |
50 | u32 aspm_support:3; /* Supported ASPM state */ |
51 | u32 aspm_enabled:3; /* Enabled ASPM state */ | |
52 | u32 aspm_capable:3; /* Capable ASPM state with latency */ | |
53 | u32 aspm_default:3; /* Default ASPM state by BIOS */ | |
54 | u32 aspm_disable:3; /* Disabled ASPM state */ | |
80bfdbe3 | 55 | |
4d246e45 KK |
56 | /* Clock PM state */ |
57 | u32 clkpm_capable:1; /* Clock PM capable? */ | |
58 | u32 clkpm_enabled:1; /* Current Clock PM state */ | |
59 | u32 clkpm_default:1; /* Default Clock PM state by BIOS */ | |
60 | ||
ac18018a KK |
61 | /* Exit latencies */ |
62 | struct aspm_latency latency_up; /* Upstream direction exit latency */ | |
63 | struct aspm_latency latency_dw; /* Downstream direction exit latency */ | |
7d715a6c | 64 | /* |
b6c2e54d KK |
65 | * Endpoint acceptable latencies. A pcie downstream port only |
66 | * has one slot under it, so at most there are 8 functions. | |
7d715a6c | 67 | */ |
b6c2e54d | 68 | struct aspm_latency acceptable[8]; |
7d715a6c SL |
69 | }; |
70 | ||
3c076351 | 71 | static int aspm_disabled, aspm_force; |
8b8bae90 | 72 | static bool aspm_support_enabled = true; |
7d715a6c SL |
73 | static DEFINE_MUTEX(aspm_lock); |
74 | static LIST_HEAD(link_list); | |
75 | ||
76 | #define POLICY_DEFAULT 0 /* BIOS default setting */ | |
77 | #define POLICY_PERFORMANCE 1 /* high performance */ | |
78 | #define POLICY_POWERSAVE 2 /* high power saving */ | |
ad71c962 MG |
79 | |
80 | #ifdef CONFIG_PCIEASPM_PERFORMANCE | |
81 | static int aspm_policy = POLICY_PERFORMANCE; | |
82 | #elif defined CONFIG_PCIEASPM_POWERSAVE | |
83 | static int aspm_policy = POLICY_POWERSAVE; | |
84 | #else | |
7d715a6c | 85 | static int aspm_policy; |
ad71c962 MG |
86 | #endif |
87 | ||
7d715a6c SL |
88 | static const char *policy_str[] = { |
89 | [POLICY_DEFAULT] = "default", | |
90 | [POLICY_PERFORMANCE] = "performance", | |
91 | [POLICY_POWERSAVE] = "powersave" | |
92 | }; | |
93 | ||
987a4c78 AP |
94 | #define LINK_RETRAIN_TIMEOUT HZ |
95 | ||
5aa63583 | 96 | static int policy_to_aspm_state(struct pcie_link_state *link) |
7d715a6c | 97 | { |
7d715a6c SL |
98 | switch (aspm_policy) { |
99 | case POLICY_PERFORMANCE: | |
100 | /* Disable ASPM and Clock PM */ | |
101 | return 0; | |
102 | case POLICY_POWERSAVE: | |
103 | /* Enable ASPM L0s/L1 */ | |
ac18018a | 104 | return ASPM_STATE_ALL; |
7d715a6c | 105 | case POLICY_DEFAULT: |
5aa63583 | 106 | return link->aspm_default; |
7d715a6c SL |
107 | } |
108 | return 0; | |
109 | } | |
110 | ||
5aa63583 | 111 | static int policy_to_clkpm_state(struct pcie_link_state *link) |
7d715a6c | 112 | { |
7d715a6c SL |
113 | switch (aspm_policy) { |
114 | case POLICY_PERFORMANCE: | |
115 | /* Disable ASPM and Clock PM */ | |
116 | return 0; | |
117 | case POLICY_POWERSAVE: | |
118 | /* Disable Clock PM */ | |
119 | return 1; | |
120 | case POLICY_DEFAULT: | |
5aa63583 | 121 | return link->clkpm_default; |
7d715a6c SL |
122 | } |
123 | return 0; | |
124 | } | |
125 | ||
430842e2 | 126 | static void pcie_set_clkpm_nocheck(struct pcie_link_state *link, int enable) |
7d715a6c | 127 | { |
5aa63583 KK |
128 | struct pci_dev *child; |
129 | struct pci_bus *linkbus = link->pdev->subordinate; | |
0c0cbb6c | 130 | u32 val = enable ? PCI_EXP_LNKCTL_CLKREQ_EN : 0; |
7d715a6c | 131 | |
0c0cbb6c BH |
132 | list_for_each_entry(child, &linkbus->devices, bus_list) |
133 | pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL, | |
134 | PCI_EXP_LNKCTL_CLKREQ_EN, | |
135 | val); | |
5aa63583 | 136 | link->clkpm_enabled = !!enable; |
7d715a6c SL |
137 | } |
138 | ||
430842e2 KK |
139 | static void pcie_set_clkpm(struct pcie_link_state *link, int enable) |
140 | { | |
141 | /* Don't enable Clock PM if the link is not Clock PM capable */ | |
a6c1c6f3 | 142 | if (!link->clkpm_capable) |
2f671e2d | 143 | enable = 0; |
430842e2 KK |
144 | /* Need nothing if the specified equals to current state */ |
145 | if (link->clkpm_enabled == enable) | |
146 | return; | |
147 | pcie_set_clkpm_nocheck(link, enable); | |
148 | } | |
149 | ||
8d349ace | 150 | static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist) |
7d715a6c | 151 | { |
f12eb72a | 152 | int capable = 1, enabled = 1; |
7d715a6c SL |
153 | u32 reg32; |
154 | u16 reg16; | |
5aa63583 KK |
155 | struct pci_dev *child; |
156 | struct pci_bus *linkbus = link->pdev->subordinate; | |
7d715a6c SL |
157 | |
158 | /* All functions should have the same cap and state, take the worst */ | |
5aa63583 | 159 | list_for_each_entry(child, &linkbus->devices, bus_list) { |
f12eb72a | 160 | pcie_capability_read_dword(child, PCI_EXP_LNKCAP, ®32); |
7d715a6c SL |
161 | if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) { |
162 | capable = 0; | |
163 | enabled = 0; | |
164 | break; | |
165 | } | |
f12eb72a | 166 | pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16); |
7d715a6c SL |
167 | if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN)) |
168 | enabled = 0; | |
169 | } | |
5aa63583 KK |
170 | link->clkpm_enabled = enabled; |
171 | link->clkpm_default = enabled; | |
8d349ace | 172 | link->clkpm_capable = (blacklist) ? 0 : capable; |
46bbdfa4 SL |
173 | } |
174 | ||
7d715a6c SL |
175 | /* |
176 | * pcie_aspm_configure_common_clock: check if the 2 ends of a link | |
177 | * could use common clock. If they are, configure them to use the | |
178 | * common clock. That will reduce the ASPM state exit latency. | |
179 | */ | |
5aa63583 | 180 | static void pcie_aspm_configure_common_clock(struct pcie_link_state *link) |
7d715a6c | 181 | { |
f12eb72a | 182 | int same_clock = 1; |
5aa63583 | 183 | u16 reg16, parent_reg, child_reg[8]; |
2a42d9db | 184 | unsigned long start_jiffies; |
5aa63583 KK |
185 | struct pci_dev *child, *parent = link->pdev; |
186 | struct pci_bus *linkbus = parent->subordinate; | |
7d715a6c | 187 | /* |
5aa63583 | 188 | * All functions of a slot should have the same Slot Clock |
7d715a6c | 189 | * Configuration, so just check one function |
5aa63583 KK |
190 | */ |
191 | child = list_entry(linkbus->devices.next, struct pci_dev, bus_list); | |
8b06477d | 192 | BUG_ON(!pci_is_pcie(child)); |
7d715a6c SL |
193 | |
194 | /* Check downstream component if bit Slot Clock Configuration is 1 */ | |
f12eb72a | 195 | pcie_capability_read_word(child, PCI_EXP_LNKSTA, ®16); |
7d715a6c SL |
196 | if (!(reg16 & PCI_EXP_LNKSTA_SLC)) |
197 | same_clock = 0; | |
198 | ||
199 | /* Check upstream component if bit Slot Clock Configuration is 1 */ | |
f12eb72a | 200 | pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16); |
7d715a6c SL |
201 | if (!(reg16 & PCI_EXP_LNKSTA_SLC)) |
202 | same_clock = 0; | |
203 | ||
204 | /* Configure downstream component, all functions */ | |
5aa63583 | 205 | list_for_each_entry(child, &linkbus->devices, bus_list) { |
f12eb72a | 206 | pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16); |
5aa63583 | 207 | child_reg[PCI_FUNC(child->devfn)] = reg16; |
7d715a6c SL |
208 | if (same_clock) |
209 | reg16 |= PCI_EXP_LNKCTL_CCC; | |
210 | else | |
211 | reg16 &= ~PCI_EXP_LNKCTL_CCC; | |
f12eb72a | 212 | pcie_capability_write_word(child, PCI_EXP_LNKCTL, reg16); |
7d715a6c SL |
213 | } |
214 | ||
215 | /* Configure upstream component */ | |
f12eb72a | 216 | pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16); |
2a42d9db | 217 | parent_reg = reg16; |
7d715a6c SL |
218 | if (same_clock) |
219 | reg16 |= PCI_EXP_LNKCTL_CCC; | |
220 | else | |
221 | reg16 &= ~PCI_EXP_LNKCTL_CCC; | |
f12eb72a | 222 | pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16); |
7d715a6c | 223 | |
5aa63583 | 224 | /* Retrain link */ |
7d715a6c | 225 | reg16 |= PCI_EXP_LNKCTL_RL; |
f12eb72a | 226 | pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16); |
7d715a6c | 227 | |
5aa63583 | 228 | /* Wait for link training end. Break out after waiting for timeout */ |
2a42d9db | 229 | start_jiffies = jiffies; |
987a4c78 | 230 | for (;;) { |
f12eb72a | 231 | pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16); |
7d715a6c SL |
232 | if (!(reg16 & PCI_EXP_LNKSTA_LT)) |
233 | break; | |
987a4c78 AP |
234 | if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) |
235 | break; | |
236 | msleep(1); | |
7d715a6c | 237 | } |
5aa63583 KK |
238 | if (!(reg16 & PCI_EXP_LNKSTA_LT)) |
239 | return; | |
240 | ||
241 | /* Training failed. Restore common clock configurations */ | |
438be3c6 | 242 | dev_err(&parent->dev, "ASPM: Could not configure common clock\n"); |
f12eb72a JL |
243 | list_for_each_entry(child, &linkbus->devices, bus_list) |
244 | pcie_capability_write_word(child, PCI_EXP_LNKCTL, | |
245 | child_reg[PCI_FUNC(child->devfn)]); | |
246 | pcie_capability_write_word(parent, PCI_EXP_LNKCTL, parent_reg); | |
7d715a6c SL |
247 | } |
248 | ||
5e0eaa7d KK |
249 | /* Convert L0s latency encoding to ns */ |
250 | static u32 calc_l0s_latency(u32 encoding) | |
7d715a6c | 251 | { |
5e0eaa7d KK |
252 | if (encoding == 0x7) |
253 | return (5 * 1000); /* > 4us */ | |
254 | return (64 << encoding); | |
255 | } | |
7d715a6c | 256 | |
5e0eaa7d KK |
257 | /* Convert L0s acceptable latency encoding to ns */ |
258 | static u32 calc_l0s_acceptable(u32 encoding) | |
259 | { | |
260 | if (encoding == 0x7) | |
261 | return -1U; | |
262 | return (64 << encoding); | |
7d715a6c SL |
263 | } |
264 | ||
5e0eaa7d KK |
265 | /* Convert L1 latency encoding to ns */ |
266 | static u32 calc_l1_latency(u32 encoding) | |
7d715a6c | 267 | { |
5e0eaa7d KK |
268 | if (encoding == 0x7) |
269 | return (65 * 1000); /* > 64us */ | |
270 | return (1000 << encoding); | |
271 | } | |
7d715a6c | 272 | |
5e0eaa7d KK |
273 | /* Convert L1 acceptable latency encoding to ns */ |
274 | static u32 calc_l1_acceptable(u32 encoding) | |
275 | { | |
276 | if (encoding == 0x7) | |
277 | return -1U; | |
278 | return (1000 << encoding); | |
7d715a6c SL |
279 | } |
280 | ||
ac18018a KK |
281 | struct aspm_register_info { |
282 | u32 support:2; | |
283 | u32 enabled:2; | |
284 | u32 latency_encoding_l0s; | |
285 | u32 latency_encoding_l1; | |
286 | }; | |
287 | ||
288 | static void pcie_get_aspm_reg(struct pci_dev *pdev, | |
289 | struct aspm_register_info *info) | |
7d715a6c | 290 | { |
7d715a6c | 291 | u16 reg16; |
ac18018a | 292 | u32 reg32; |
7d715a6c | 293 | |
f12eb72a | 294 | pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, ®32); |
ac18018a | 295 | info->support = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10; |
ac18018a KK |
296 | info->latency_encoding_l0s = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12; |
297 | info->latency_encoding_l1 = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15; | |
f12eb72a | 298 | pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, ®16); |
ac18018a | 299 | info->enabled = reg16 & PCI_EXP_LNKCTL_ASPMC; |
7d715a6c SL |
300 | } |
301 | ||
07d92760 KK |
302 | static void pcie_aspm_check_latency(struct pci_dev *endpoint) |
303 | { | |
ac18018a | 304 | u32 latency, l1_switch_latency = 0; |
07d92760 KK |
305 | struct aspm_latency *acceptable; |
306 | struct pcie_link_state *link; | |
307 | ||
308 | /* Device not in D0 doesn't need latency check */ | |
309 | if ((endpoint->current_state != PCI_D0) && | |
310 | (endpoint->current_state != PCI_UNKNOWN)) | |
311 | return; | |
312 | ||
313 | link = endpoint->bus->self->link_state; | |
314 | acceptable = &link->acceptable[PCI_FUNC(endpoint->devfn)]; | |
315 | ||
316 | while (link) { | |
ac18018a KK |
317 | /* Check upstream direction L0s latency */ |
318 | if ((link->aspm_capable & ASPM_STATE_L0S_UP) && | |
319 | (link->latency_up.l0s > acceptable->l0s)) | |
320 | link->aspm_capable &= ~ASPM_STATE_L0S_UP; | |
321 | ||
322 | /* Check downstream direction L0s latency */ | |
323 | if ((link->aspm_capable & ASPM_STATE_L0S_DW) && | |
324 | (link->latency_dw.l0s > acceptable->l0s)) | |
325 | link->aspm_capable &= ~ASPM_STATE_L0S_DW; | |
07d92760 KK |
326 | /* |
327 | * Check L1 latency. | |
328 | * Every switch on the path to root complex need 1 | |
329 | * more microsecond for L1. Spec doesn't mention L0s. | |
330 | */ | |
ac18018a KK |
331 | latency = max_t(u32, link->latency_up.l1, link->latency_dw.l1); |
332 | if ((link->aspm_capable & ASPM_STATE_L1) && | |
333 | (latency + l1_switch_latency > acceptable->l1)) | |
334 | link->aspm_capable &= ~ASPM_STATE_L1; | |
07d92760 KK |
335 | l1_switch_latency += 1000; |
336 | ||
337 | link = link->parent; | |
338 | } | |
339 | } | |
340 | ||
8d349ace | 341 | static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) |
7d715a6c | 342 | { |
5aa63583 KK |
343 | struct pci_dev *child, *parent = link->pdev; |
344 | struct pci_bus *linkbus = parent->subordinate; | |
ac18018a | 345 | struct aspm_register_info upreg, dwreg; |
7d715a6c | 346 | |
8d349ace | 347 | if (blacklist) { |
f1c0ca29 | 348 | /* Set enabled/disable so that we will disable ASPM later */ |
ac18018a KK |
349 | link->aspm_enabled = ASPM_STATE_ALL; |
350 | link->aspm_disable = ASPM_STATE_ALL; | |
8d349ace KK |
351 | return; |
352 | } | |
353 | ||
e53f9a28 DD |
354 | /* Get upstream/downstream components' register state */ |
355 | pcie_get_aspm_reg(parent, &upreg); | |
356 | child = list_entry(linkbus->devices.next, struct pci_dev, bus_list); | |
357 | pcie_get_aspm_reg(child, &dwreg); | |
358 | ||
359 | /* | |
360 | * If ASPM not supported, don't mess with the clocks and link, | |
361 | * bail out now. | |
362 | */ | |
363 | if (!(upreg.support & dwreg.support)) | |
364 | return; | |
365 | ||
8d349ace KK |
366 | /* Configure common clock before checking latencies */ |
367 | pcie_aspm_configure_common_clock(link); | |
368 | ||
e53f9a28 DD |
369 | /* |
370 | * Re-read upstream/downstream components' register state | |
371 | * after clock configuration | |
372 | */ | |
ac18018a | 373 | pcie_get_aspm_reg(parent, &upreg); |
ac18018a KK |
374 | pcie_get_aspm_reg(child, &dwreg); |
375 | ||
376 | /* | |
377 | * Setup L0s state | |
378 | * | |
379 | * Note that we must not enable L0s in either direction on a | |
380 | * given link unless components on both sides of the link each | |
381 | * support L0s. | |
382 | */ | |
383 | if (dwreg.support & upreg.support & PCIE_LINK_STATE_L0S) | |
384 | link->aspm_support |= ASPM_STATE_L0S; | |
385 | if (dwreg.enabled & PCIE_LINK_STATE_L0S) | |
386 | link->aspm_enabled |= ASPM_STATE_L0S_UP; | |
387 | if (upreg.enabled & PCIE_LINK_STATE_L0S) | |
388 | link->aspm_enabled |= ASPM_STATE_L0S_DW; | |
389 | link->latency_up.l0s = calc_l0s_latency(upreg.latency_encoding_l0s); | |
390 | link->latency_dw.l0s = calc_l0s_latency(dwreg.latency_encoding_l0s); | |
391 | ||
392 | /* Setup L1 state */ | |
393 | if (upreg.support & dwreg.support & PCIE_LINK_STATE_L1) | |
394 | link->aspm_support |= ASPM_STATE_L1; | |
395 | if (upreg.enabled & dwreg.enabled & PCIE_LINK_STATE_L1) | |
396 | link->aspm_enabled |= ASPM_STATE_L1; | |
397 | link->latency_up.l1 = calc_l1_latency(upreg.latency_encoding_l1); | |
398 | link->latency_dw.l1 = calc_l1_latency(dwreg.latency_encoding_l1); | |
5aa63583 | 399 | |
b127bd55 KK |
400 | /* Save default state */ |
401 | link->aspm_default = link->aspm_enabled; | |
07d92760 KK |
402 | |
403 | /* Setup initial capable state. Will be updated later */ | |
404 | link->aspm_capable = link->aspm_support; | |
f1c0ca29 KK |
405 | /* |
406 | * If the downstream component has pci bridge function, don't | |
407 | * do ASPM for now. | |
408 | */ | |
409 | list_for_each_entry(child, &linkbus->devices, bus_list) { | |
62f87c0e | 410 | if (pci_pcie_type(child) == PCI_EXP_TYPE_PCI_BRIDGE) { |
ac18018a | 411 | link->aspm_disable = ASPM_STATE_ALL; |
f1c0ca29 KK |
412 | break; |
413 | } | |
414 | } | |
b127bd55 | 415 | |
b7206cbf | 416 | /* Get and check endpoint acceptable latencies */ |
5aa63583 | 417 | list_for_each_entry(child, &linkbus->devices, bus_list) { |
5e0eaa7d | 418 | u32 reg32, encoding; |
b6c2e54d | 419 | struct aspm_latency *acceptable = |
5aa63583 | 420 | &link->acceptable[PCI_FUNC(child->devfn)]; |
7d715a6c | 421 | |
62f87c0e YW |
422 | if (pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT && |
423 | pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END) | |
7d715a6c SL |
424 | continue; |
425 | ||
f12eb72a | 426 | pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32); |
07d92760 | 427 | /* Calculate endpoint L0s acceptable latency */ |
5e0eaa7d KK |
428 | encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6; |
429 | acceptable->l0s = calc_l0s_acceptable(encoding); | |
07d92760 KK |
430 | /* Calculate endpoint L1 acceptable latency */ |
431 | encoding = (reg32 & PCI_EXP_DEVCAP_L1) >> 9; | |
432 | acceptable->l1 = calc_l1_acceptable(encoding); | |
433 | ||
434 | pcie_aspm_check_latency(child); | |
7d715a6c SL |
435 | } |
436 | } | |
437 | ||
ac18018a | 438 | static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val) |
7d715a6c | 439 | { |
75083206 BH |
440 | pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL, |
441 | PCI_EXP_LNKCTL_ASPMC, val); | |
7d715a6c SL |
442 | } |
443 | ||
b7206cbf | 444 | static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state) |
7d715a6c | 445 | { |
ac18018a | 446 | u32 upstream = 0, dwstream = 0; |
5aa63583 KK |
447 | struct pci_dev *child, *parent = link->pdev; |
448 | struct pci_bus *linkbus = parent->subordinate; | |
7d715a6c | 449 | |
f1c0ca29 | 450 | /* Nothing to do if the link is already in the requested state */ |
b7206cbf | 451 | state &= (link->aspm_capable & ~link->aspm_disable); |
f1c0ca29 KK |
452 | if (link->aspm_enabled == state) |
453 | return; | |
ac18018a KK |
454 | /* Convert ASPM state to upstream/downstream ASPM register state */ |
455 | if (state & ASPM_STATE_L0S_UP) | |
75083206 | 456 | dwstream |= PCI_EXP_LNKCTL_ASPM_L0S; |
ac18018a | 457 | if (state & ASPM_STATE_L0S_DW) |
75083206 | 458 | upstream |= PCI_EXP_LNKCTL_ASPM_L0S; |
ac18018a | 459 | if (state & ASPM_STATE_L1) { |
75083206 BH |
460 | upstream |= PCI_EXP_LNKCTL_ASPM_L1; |
461 | dwstream |= PCI_EXP_LNKCTL_ASPM_L1; | |
ac18018a | 462 | } |
7d715a6c | 463 | /* |
5aa63583 KK |
464 | * Spec 2.0 suggests all functions should be configured the |
465 | * same setting for ASPM. Enabling ASPM L1 should be done in | |
466 | * upstream component first and then downstream, and vice | |
467 | * versa for disabling ASPM L1. Spec doesn't mention L0S. | |
7d715a6c | 468 | */ |
ac18018a KK |
469 | if (state & ASPM_STATE_L1) |
470 | pcie_config_aspm_dev(parent, upstream); | |
5aa63583 | 471 | list_for_each_entry(child, &linkbus->devices, bus_list) |
ac18018a KK |
472 | pcie_config_aspm_dev(child, dwstream); |
473 | if (!(state & ASPM_STATE_L1)) | |
474 | pcie_config_aspm_dev(parent, upstream); | |
7d715a6c | 475 | |
5aa63583 | 476 | link->aspm_enabled = state; |
7d715a6c SL |
477 | } |
478 | ||
b7206cbf | 479 | static void pcie_config_aspm_path(struct pcie_link_state *link) |
7d715a6c | 480 | { |
b7206cbf KK |
481 | while (link) { |
482 | pcie_config_aspm_link(link, policy_to_aspm_state(link)); | |
483 | link = link->parent; | |
46bbdfa4 | 484 | } |
7d715a6c SL |
485 | } |
486 | ||
5aa63583 | 487 | static void free_link_state(struct pcie_link_state *link) |
7d715a6c | 488 | { |
5aa63583 KK |
489 | link->pdev->link_state = NULL; |
490 | kfree(link); | |
7d715a6c SL |
491 | } |
492 | ||
ddc9753f SL |
493 | static int pcie_aspm_sanity_check(struct pci_dev *pdev) |
494 | { | |
3647584d | 495 | struct pci_dev *child; |
149e1637 | 496 | u32 reg32; |
2f671e2d | 497 | |
ddc9753f | 498 | /* |
45e829ea | 499 | * Some functions in a slot might not all be PCIe functions, |
3647584d | 500 | * very strange. Disable ASPM for the whole slot |
ddc9753f | 501 | */ |
3647584d | 502 | list_for_each_entry(child, &pdev->subordinate->devices, bus_list) { |
f12eb72a | 503 | if (!pci_is_pcie(child)) |
ddc9753f | 504 | return -EINVAL; |
c9651e70 MG |
505 | |
506 | /* | |
507 | * If ASPM is disabled then we're not going to change | |
508 | * the BIOS state. It's safe to continue even if it's a | |
509 | * pre-1.1 device | |
510 | */ | |
511 | ||
512 | if (aspm_disabled) | |
513 | continue; | |
514 | ||
149e1637 SL |
515 | /* |
516 | * Disable ASPM for pre-1.1 PCIe device, we follow MS to use | |
517 | * RBER bit to determine if a function is 1.1 version device | |
518 | */ | |
f12eb72a | 519 | pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32); |
e1f4f59d | 520 | if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) { |
438be3c6 | 521 | dev_info(&child->dev, "disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force'\n"); |
149e1637 SL |
522 | return -EINVAL; |
523 | } | |
ddc9753f SL |
524 | } |
525 | return 0; | |
526 | } | |
527 | ||
b7206cbf | 528 | static struct pcie_link_state *alloc_pcie_link_state(struct pci_dev *pdev) |
8d349ace KK |
529 | { |
530 | struct pcie_link_state *link; | |
8d349ace KK |
531 | |
532 | link = kzalloc(sizeof(*link), GFP_KERNEL); | |
533 | if (!link) | |
534 | return NULL; | |
030305d6 | 535 | |
8d349ace KK |
536 | INIT_LIST_HEAD(&link->sibling); |
537 | INIT_LIST_HEAD(&link->children); | |
538 | INIT_LIST_HEAD(&link->link); | |
539 | link->pdev = pdev; | |
030305d6 BH |
540 | |
541 | /* | |
542 | * Root Ports and PCI/PCI-X to PCIe Bridges are roots of PCIe | |
543 | * hierarchies. | |
544 | */ | |
545 | if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT || | |
546 | pci_pcie_type(pdev) == PCI_EXP_TYPE_PCIE_BRIDGE) { | |
547 | link->root = link; | |
548 | } else { | |
8d349ace | 549 | struct pcie_link_state *parent; |
030305d6 | 550 | |
8d349ace KK |
551 | parent = pdev->bus->parent->self->link_state; |
552 | if (!parent) { | |
553 | kfree(link); | |
554 | return NULL; | |
555 | } | |
030305d6 | 556 | |
8d349ace | 557 | link->parent = parent; |
030305d6 | 558 | link->root = link->parent->root; |
8d349ace KK |
559 | list_add(&link->link, &parent->children); |
560 | } | |
5c92ffb1 | 561 | |
8d349ace | 562 | list_add(&link->sibling, &link_list); |
8d349ace | 563 | pdev->link_state = link; |
8d349ace KK |
564 | return link; |
565 | } | |
566 | ||
7d715a6c SL |
567 | /* |
568 | * pcie_aspm_init_link_state: Initiate PCI express link state. | |
f7625980 | 569 | * It is called after the pcie and its children devices are scanned. |
7d715a6c SL |
570 | * @pdev: the root port or switch downstream port |
571 | */ | |
572 | void pcie_aspm_init_link_state(struct pci_dev *pdev) | |
573 | { | |
8d349ace | 574 | struct pcie_link_state *link; |
b7206cbf | 575 | int blacklist = !!pcie_aspm_sanity_check(pdev); |
7d715a6c | 576 | |
a26d5ecb JL |
577 | if (!aspm_support_enabled) |
578 | return; | |
579 | ||
c8fc9339 | 580 | if (pdev->link_state) |
7d715a6c | 581 | return; |
c8fc9339 YW |
582 | |
583 | /* | |
584 | * We allocate pcie_link_state for the component on the upstream | |
585 | * end of a Link, so there's nothing to do unless this device has a | |
586 | * Link on its secondary side. | |
587 | */ | |
588 | if (!pdev->has_secondary_link) | |
7d715a6c | 589 | return; |
8d349ace | 590 | |
8e822df7 | 591 | /* VIA has a strange chipset, root port is under a bridge */ |
62f87c0e | 592 | if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT && |
8d349ace | 593 | pdev->bus->self) |
8e822df7 | 594 | return; |
8d349ace | 595 | |
7d715a6c SL |
596 | down_read(&pci_bus_sem); |
597 | if (list_empty(&pdev->subordinate->devices)) | |
598 | goto out; | |
599 | ||
600 | mutex_lock(&aspm_lock); | |
b7206cbf | 601 | link = alloc_pcie_link_state(pdev); |
8d349ace KK |
602 | if (!link) |
603 | goto unlock; | |
604 | /* | |
b7206cbf KK |
605 | * Setup initial ASPM state. Note that we need to configure |
606 | * upstream links also because capable state of them can be | |
607 | * update through pcie_aspm_cap_init(). | |
8d349ace | 608 | */ |
b7206cbf | 609 | pcie_aspm_cap_init(link, blacklist); |
7d715a6c | 610 | |
8d349ace | 611 | /* Setup initial Clock PM state */ |
b7206cbf | 612 | pcie_clkpm_cap_init(link, blacklist); |
41cd766b MG |
613 | |
614 | /* | |
615 | * At this stage drivers haven't had an opportunity to change the | |
616 | * link policy setting. Enabling ASPM on broken hardware can cripple | |
617 | * it even before the driver has had a chance to disable ASPM, so | |
618 | * default to a safe level right now. If we're enabling ASPM beyond | |
619 | * the BIOS's expectation, we'll do so once pci_enable_device() is | |
620 | * called. | |
621 | */ | |
3c076351 | 622 | if (aspm_policy != POLICY_POWERSAVE) { |
41cd766b MG |
623 | pcie_config_aspm_path(link); |
624 | pcie_set_clkpm(link, policy_to_clkpm_state(link)); | |
625 | } | |
626 | ||
8d349ace | 627 | unlock: |
7d715a6c SL |
628 | mutex_unlock(&aspm_lock); |
629 | out: | |
630 | up_read(&pci_bus_sem); | |
631 | } | |
632 | ||
07d92760 KK |
633 | /* Recheck latencies and update aspm_capable for links under the root */ |
634 | static void pcie_update_aspm_capable(struct pcie_link_state *root) | |
635 | { | |
636 | struct pcie_link_state *link; | |
637 | BUG_ON(root->parent); | |
638 | list_for_each_entry(link, &link_list, sibling) { | |
639 | if (link->root != root) | |
640 | continue; | |
641 | link->aspm_capable = link->aspm_support; | |
642 | } | |
643 | list_for_each_entry(link, &link_list, sibling) { | |
644 | struct pci_dev *child; | |
645 | struct pci_bus *linkbus = link->pdev->subordinate; | |
646 | if (link->root != root) | |
647 | continue; | |
648 | list_for_each_entry(child, &linkbus->devices, bus_list) { | |
62f87c0e YW |
649 | if ((pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT) && |
650 | (pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END)) | |
07d92760 KK |
651 | continue; |
652 | pcie_aspm_check_latency(child); | |
653 | } | |
654 | } | |
655 | } | |
656 | ||
7d715a6c SL |
657 | /* @pdev: the endpoint device */ |
658 | void pcie_aspm_exit_link_state(struct pci_dev *pdev) | |
659 | { | |
660 | struct pci_dev *parent = pdev->bus->self; | |
b7206cbf | 661 | struct pcie_link_state *link, *root, *parent_link; |
7d715a6c | 662 | |
84fb913c | 663 | if (!parent || !parent->link_state) |
7d715a6c | 664 | return; |
fc87e919 | 665 | |
7d715a6c SL |
666 | down_read(&pci_bus_sem); |
667 | mutex_lock(&aspm_lock); | |
7d715a6c SL |
668 | /* |
669 | * All PCIe functions are in one slot, remove one function will remove | |
3419c75e | 670 | * the whole slot, so just wait until we are the last function left. |
7d715a6c | 671 | */ |
3419c75e | 672 | if (!list_is_last(&pdev->bus_list, &parent->subordinate->devices)) |
7d715a6c SL |
673 | goto out; |
674 | ||
fc87e919 | 675 | link = parent->link_state; |
07d92760 | 676 | root = link->root; |
b7206cbf | 677 | parent_link = link->parent; |
fc87e919 | 678 | |
7d715a6c | 679 | /* All functions are removed, so just disable ASPM for the link */ |
b7206cbf | 680 | pcie_config_aspm_link(link, 0); |
fc87e919 KK |
681 | list_del(&link->sibling); |
682 | list_del(&link->link); | |
7d715a6c | 683 | /* Clock PM is for endpoint device */ |
fc87e919 | 684 | free_link_state(link); |
07d92760 KK |
685 | |
686 | /* Recheck latencies and configure upstream links */ | |
b26a34aa KK |
687 | if (parent_link) { |
688 | pcie_update_aspm_capable(root); | |
689 | pcie_config_aspm_path(parent_link); | |
690 | } | |
7d715a6c SL |
691 | out: |
692 | mutex_unlock(&aspm_lock); | |
693 | up_read(&pci_bus_sem); | |
694 | } | |
695 | ||
696 | /* @pdev: the root port or switch downstream port */ | |
697 | void pcie_aspm_pm_state_change(struct pci_dev *pdev) | |
698 | { | |
07d92760 | 699 | struct pcie_link_state *link = pdev->link_state; |
7d715a6c | 700 | |
f9b8cd7c | 701 | if (aspm_disabled || !link) |
7d715a6c SL |
702 | return; |
703 | /* | |
07d92760 KK |
704 | * Devices changed PM state, we should recheck if latency |
705 | * meets all functions' requirement | |
7d715a6c | 706 | */ |
07d92760 KK |
707 | down_read(&pci_bus_sem); |
708 | mutex_lock(&aspm_lock); | |
709 | pcie_update_aspm_capable(link->root); | |
b7206cbf | 710 | pcie_config_aspm_path(link); |
07d92760 KK |
711 | mutex_unlock(&aspm_lock); |
712 | up_read(&pci_bus_sem); | |
7d715a6c SL |
713 | } |
714 | ||
1a680b7c NC |
715 | void pcie_aspm_powersave_config_link(struct pci_dev *pdev) |
716 | { | |
717 | struct pcie_link_state *link = pdev->link_state; | |
718 | ||
f9b8cd7c | 719 | if (aspm_disabled || !link) |
1a680b7c NC |
720 | return; |
721 | ||
722 | if (aspm_policy != POLICY_POWERSAVE) | |
723 | return; | |
724 | ||
1a680b7c NC |
725 | down_read(&pci_bus_sem); |
726 | mutex_lock(&aspm_lock); | |
727 | pcie_config_aspm_path(link); | |
728 | pcie_set_clkpm(link, policy_to_clkpm_state(link)); | |
729 | mutex_unlock(&aspm_lock); | |
730 | up_read(&pci_bus_sem); | |
731 | } | |
732 | ||
e127a04f | 733 | static void __pci_disable_link_state(struct pci_dev *pdev, int state, bool sem) |
7d715a6c SL |
734 | { |
735 | struct pci_dev *parent = pdev->bus->self; | |
f1c0ca29 | 736 | struct pcie_link_state *link; |
7d715a6c | 737 | |
3c076351 | 738 | if (!pci_is_pcie(pdev)) |
7d715a6c | 739 | return; |
3c076351 | 740 | |
c8fc9339 | 741 | if (pdev->has_secondary_link) |
7d715a6c SL |
742 | parent = pdev; |
743 | if (!parent || !parent->link_state) | |
744 | return; | |
745 | ||
2add0ec1 BH |
746 | /* |
747 | * A driver requested that ASPM be disabled on this device, but | |
748 | * if we don't have permission to manage ASPM (e.g., on ACPI | |
749 | * systems we have to observe the FADT ACPI_FADT_NO_ASPM bit and | |
750 | * the _OSC method), we can't honor that request. Windows has | |
751 | * a similar mechanism using "PciASPMOptOut", which is also | |
752 | * ignored in this situation. | |
753 | */ | |
e127a04f | 754 | if (aspm_disabled) { |
2add0ec1 BH |
755 | dev_warn(&pdev->dev, "can't disable ASPM; OS doesn't have ASPM control\n"); |
756 | return; | |
757 | } | |
758 | ||
9f728f53 YL |
759 | if (sem) |
760 | down_read(&pci_bus_sem); | |
7d715a6c | 761 | mutex_lock(&aspm_lock); |
f1c0ca29 | 762 | link = parent->link_state; |
ac18018a KK |
763 | if (state & PCIE_LINK_STATE_L0S) |
764 | link->aspm_disable |= ASPM_STATE_L0S; | |
765 | if (state & PCIE_LINK_STATE_L1) | |
766 | link->aspm_disable |= ASPM_STATE_L1; | |
b7206cbf KK |
767 | pcie_config_aspm_link(link, policy_to_aspm_state(link)); |
768 | ||
430842e2 | 769 | if (state & PCIE_LINK_STATE_CLKPM) { |
f1c0ca29 KK |
770 | link->clkpm_capable = 0; |
771 | pcie_set_clkpm(link, 0); | |
430842e2 | 772 | } |
7d715a6c | 773 | mutex_unlock(&aspm_lock); |
9f728f53 YL |
774 | if (sem) |
775 | up_read(&pci_bus_sem); | |
776 | } | |
777 | ||
778 | void pci_disable_link_state_locked(struct pci_dev *pdev, int state) | |
779 | { | |
e127a04f | 780 | __pci_disable_link_state(pdev, state, false); |
9f728f53 YL |
781 | } |
782 | EXPORT_SYMBOL(pci_disable_link_state_locked); | |
783 | ||
2dfca877 YW |
784 | /** |
785 | * pci_disable_link_state - Disable device's link state, so the link will | |
786 | * never enter specific states. Note that if the BIOS didn't grant ASPM | |
787 | * control to the OS, this does nothing because we can't touch the LNKCTL | |
788 | * register. | |
789 | * | |
790 | * @pdev: PCI device | |
791 | * @state: ASPM link state to disable | |
792 | */ | |
9f728f53 YL |
793 | void pci_disable_link_state(struct pci_dev *pdev, int state) |
794 | { | |
e127a04f | 795 | __pci_disable_link_state(pdev, state, true); |
7d715a6c SL |
796 | } |
797 | EXPORT_SYMBOL(pci_disable_link_state); | |
798 | ||
799 | static int pcie_aspm_set_policy(const char *val, struct kernel_param *kp) | |
800 | { | |
801 | int i; | |
b7206cbf | 802 | struct pcie_link_state *link; |
7d715a6c | 803 | |
bbfa306a NC |
804 | if (aspm_disabled) |
805 | return -EPERM; | |
7d715a6c SL |
806 | for (i = 0; i < ARRAY_SIZE(policy_str); i++) |
807 | if (!strncmp(val, policy_str[i], strlen(policy_str[i]))) | |
808 | break; | |
809 | if (i >= ARRAY_SIZE(policy_str)) | |
810 | return -EINVAL; | |
811 | if (i == aspm_policy) | |
812 | return 0; | |
813 | ||
814 | down_read(&pci_bus_sem); | |
815 | mutex_lock(&aspm_lock); | |
816 | aspm_policy = i; | |
b7206cbf KK |
817 | list_for_each_entry(link, &link_list, sibling) { |
818 | pcie_config_aspm_link(link, policy_to_aspm_state(link)); | |
819 | pcie_set_clkpm(link, policy_to_clkpm_state(link)); | |
7d715a6c SL |
820 | } |
821 | mutex_unlock(&aspm_lock); | |
822 | up_read(&pci_bus_sem); | |
823 | return 0; | |
824 | } | |
825 | ||
826 | static int pcie_aspm_get_policy(char *buffer, struct kernel_param *kp) | |
827 | { | |
828 | int i, cnt = 0; | |
829 | for (i = 0; i < ARRAY_SIZE(policy_str); i++) | |
830 | if (i == aspm_policy) | |
831 | cnt += sprintf(buffer + cnt, "[%s] ", policy_str[i]); | |
832 | else | |
833 | cnt += sprintf(buffer + cnt, "%s ", policy_str[i]); | |
834 | return cnt; | |
835 | } | |
836 | ||
837 | module_param_call(policy, pcie_aspm_set_policy, pcie_aspm_get_policy, | |
838 | NULL, 0644); | |
839 | ||
840 | #ifdef CONFIG_PCIEASPM_DEBUG | |
841 | static ssize_t link_state_show(struct device *dev, | |
842 | struct device_attribute *attr, | |
843 | char *buf) | |
844 | { | |
845 | struct pci_dev *pci_device = to_pci_dev(dev); | |
846 | struct pcie_link_state *link_state = pci_device->link_state; | |
847 | ||
80bfdbe3 | 848 | return sprintf(buf, "%d\n", link_state->aspm_enabled); |
7d715a6c SL |
849 | } |
850 | ||
851 | static ssize_t link_state_store(struct device *dev, | |
852 | struct device_attribute *attr, | |
853 | const char *buf, | |
854 | size_t n) | |
855 | { | |
5aa63583 | 856 | struct pci_dev *pdev = to_pci_dev(dev); |
b7206cbf | 857 | struct pcie_link_state *link, *root = pdev->link_state->root; |
57d86a04 | 858 | u32 state; |
7d715a6c | 859 | |
bbfa306a NC |
860 | if (aspm_disabled) |
861 | return -EPERM; | |
7d715a6c | 862 | |
57d86a04 AL |
863 | if (kstrtouint(buf, 10, &state)) |
864 | return -EINVAL; | |
865 | if ((state & ~ASPM_STATE_ALL) != 0) | |
866 | return -EINVAL; | |
ac18018a | 867 | |
b7206cbf KK |
868 | down_read(&pci_bus_sem); |
869 | mutex_lock(&aspm_lock); | |
870 | list_for_each_entry(link, &link_list, sibling) { | |
871 | if (link->root != root) | |
872 | continue; | |
873 | pcie_config_aspm_link(link, state); | |
874 | } | |
875 | mutex_unlock(&aspm_lock); | |
876 | up_read(&pci_bus_sem); | |
877 | return n; | |
7d715a6c SL |
878 | } |
879 | ||
880 | static ssize_t clk_ctl_show(struct device *dev, | |
881 | struct device_attribute *attr, | |
882 | char *buf) | |
883 | { | |
884 | struct pci_dev *pci_device = to_pci_dev(dev); | |
885 | struct pcie_link_state *link_state = pci_device->link_state; | |
886 | ||
4d246e45 | 887 | return sprintf(buf, "%d\n", link_state->clkpm_enabled); |
7d715a6c SL |
888 | } |
889 | ||
890 | static ssize_t clk_ctl_store(struct device *dev, | |
891 | struct device_attribute *attr, | |
892 | const char *buf, | |
893 | size_t n) | |
894 | { | |
430842e2 | 895 | struct pci_dev *pdev = to_pci_dev(dev); |
94a90312 | 896 | bool state; |
7d715a6c | 897 | |
94a90312 | 898 | if (strtobool(buf, &state)) |
7d715a6c | 899 | return -EINVAL; |
7d715a6c SL |
900 | |
901 | down_read(&pci_bus_sem); | |
902 | mutex_lock(&aspm_lock); | |
94a90312 | 903 | pcie_set_clkpm_nocheck(pdev->link_state, state); |
7d715a6c SL |
904 | mutex_unlock(&aspm_lock); |
905 | up_read(&pci_bus_sem); | |
906 | ||
907 | return n; | |
908 | } | |
909 | ||
fc4f57fa JL |
910 | static DEVICE_ATTR_RW(link_state); |
911 | static DEVICE_ATTR_RW(clk_ctl); | |
7d715a6c SL |
912 | |
913 | static char power_group[] = "power"; | |
914 | void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev) | |
915 | { | |
916 | struct pcie_link_state *link_state = pdev->link_state; | |
917 | ||
f9b8cd7c | 918 | if (!link_state) |
7d715a6c SL |
919 | return; |
920 | ||
80bfdbe3 | 921 | if (link_state->aspm_support) |
7d715a6c SL |
922 | sysfs_add_file_to_group(&pdev->dev.kobj, |
923 | &dev_attr_link_state.attr, power_group); | |
4d246e45 | 924 | if (link_state->clkpm_capable) |
7d715a6c SL |
925 | sysfs_add_file_to_group(&pdev->dev.kobj, |
926 | &dev_attr_clk_ctl.attr, power_group); | |
927 | } | |
928 | ||
929 | void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev) | |
930 | { | |
931 | struct pcie_link_state *link_state = pdev->link_state; | |
932 | ||
f9b8cd7c | 933 | if (!link_state) |
7d715a6c SL |
934 | return; |
935 | ||
80bfdbe3 | 936 | if (link_state->aspm_support) |
7d715a6c SL |
937 | sysfs_remove_file_from_group(&pdev->dev.kobj, |
938 | &dev_attr_link_state.attr, power_group); | |
4d246e45 | 939 | if (link_state->clkpm_capable) |
7d715a6c SL |
940 | sysfs_remove_file_from_group(&pdev->dev.kobj, |
941 | &dev_attr_clk_ctl.attr, power_group); | |
942 | } | |
943 | #endif | |
944 | ||
945 | static int __init pcie_aspm_disable(char *str) | |
946 | { | |
d6d38574 | 947 | if (!strcmp(str, "off")) { |
3c076351 | 948 | aspm_policy = POLICY_DEFAULT; |
d6d38574 | 949 | aspm_disabled = 1; |
8b8bae90 | 950 | aspm_support_enabled = false; |
d6d38574 SL |
951 | printk(KERN_INFO "PCIe ASPM is disabled\n"); |
952 | } else if (!strcmp(str, "force")) { | |
953 | aspm_force = 1; | |
8072ba1b | 954 | printk(KERN_INFO "PCIe ASPM is forcibly enabled\n"); |
d6d38574 | 955 | } |
7d715a6c SL |
956 | return 1; |
957 | } | |
958 | ||
d6d38574 | 959 | __setup("pcie_aspm=", pcie_aspm_disable); |
7d715a6c | 960 | |
5fde244d SL |
961 | void pcie_no_aspm(void) |
962 | { | |
3c076351 MG |
963 | /* |
964 | * Disabling ASPM is intended to prevent the kernel from modifying | |
965 | * existing hardware state, not to clear existing state. To that end: | |
966 | * (a) set policy to POLICY_DEFAULT in order to avoid changing state | |
967 | * (b) prevent userspace from changing policy | |
968 | */ | |
969 | if (!aspm_force) { | |
970 | aspm_policy = POLICY_DEFAULT; | |
d6d38574 | 971 | aspm_disabled = 1; |
3c076351 | 972 | } |
5fde244d SL |
973 | } |
974 | ||
8b8bae90 RW |
975 | bool pcie_aspm_support_enabled(void) |
976 | { | |
977 | return aspm_support_enabled; | |
978 | } | |
979 | EXPORT_SYMBOL(pcie_aspm_support_enabled); |