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Commit | Line | Data |
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7328c8f4 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1da177e4 | 2 | /* |
df62ab5e | 3 | * PCI detection and setup code |
1da177e4 LT |
4 | */ |
5 | ||
6 | #include <linux/kernel.h> | |
7 | #include <linux/delay.h> | |
8 | #include <linux/init.h> | |
9 | #include <linux/pci.h> | |
bbd8810d | 10 | #include <linux/msi.h> |
50230713 | 11 | #include <linux/of_device.h> |
de335bb4 | 12 | #include <linux/of_pci.h> |
589fcc23 | 13 | #include <linux/pci_hotplug.h> |
1da177e4 LT |
14 | #include <linux/slab.h> |
15 | #include <linux/module.h> | |
16 | #include <linux/cpumask.h> | |
b07461a8 | 17 | #include <linux/aer.h> |
29dbe1f0 | 18 | #include <linux/acpi.h> |
690f4304 | 19 | #include <linux/hypervisor.h> |
788858eb | 20 | #include <linux/irqdomain.h> |
d963f651 | 21 | #include <linux/pm_runtime.h> |
69139244 | 22 | #include <linux/bitfield.h> |
1e19e335 | 23 | #include <linux/list_sort.h> |
bc56b9e0 | 24 | #include "pci.h" |
1da177e4 LT |
25 | |
26 | #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ | |
27 | #define CARDBUS_RESERVE_BUSNR 3 | |
1da177e4 | 28 | |
0b950f0f | 29 | static struct resource busn_resource = { |
67cdc827 YL |
30 | .name = "PCI busn", |
31 | .start = 0, | |
32 | .end = 255, | |
33 | .flags = IORESOURCE_BUS, | |
34 | }; | |
35 | ||
1da177e4 LT |
36 | /* Ugh. Need to stop exporting this to modules. */ |
37 | LIST_HEAD(pci_root_buses); | |
38 | EXPORT_SYMBOL(pci_root_buses); | |
39 | ||
5cc62c20 YL |
40 | static LIST_HEAD(pci_domain_busn_res_list); |
41 | ||
42 | struct pci_domain_busn_res { | |
43 | struct list_head list; | |
44 | struct resource res; | |
45 | int domain_nr; | |
46 | }; | |
47 | ||
48 | static struct resource *get_pci_domain_busn_res(int domain_nr) | |
49 | { | |
50 | struct pci_domain_busn_res *r; | |
51 | ||
52 | list_for_each_entry(r, &pci_domain_busn_res_list, list) | |
53 | if (r->domain_nr == domain_nr) | |
54 | return &r->res; | |
55 | ||
56 | r = kzalloc(sizeof(*r), GFP_KERNEL); | |
57 | if (!r) | |
58 | return NULL; | |
59 | ||
60 | r->domain_nr = domain_nr; | |
61 | r->res.start = 0; | |
62 | r->res.end = 0xff; | |
63 | r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED; | |
64 | ||
65 | list_add_tail(&r->list, &pci_domain_busn_res_list); | |
66 | ||
67 | return &r->res; | |
68 | } | |
69 | ||
ed4aaadb | 70 | /* |
3e466e2d BH |
71 | * Some device drivers need know if PCI is initiated. |
72 | * Basically, we think PCI is not initiated when there | |
70308923 | 73 | * is no device to be found on the pci_bus_type. |
ed4aaadb ZY |
74 | */ |
75 | int no_pci_devices(void) | |
76 | { | |
70308923 GKH |
77 | struct device *dev; |
78 | int no_devices; | |
ed4aaadb | 79 | |
6bf85ba9 | 80 | dev = bus_find_next_device(&pci_bus_type, NULL); |
70308923 GKH |
81 | no_devices = (dev == NULL); |
82 | put_device(dev); | |
83 | return no_devices; | |
84 | } | |
ed4aaadb ZY |
85 | EXPORT_SYMBOL(no_pci_devices); |
86 | ||
1da177e4 LT |
87 | /* |
88 | * PCI Bus Class | |
89 | */ | |
fd7d1ced | 90 | static void release_pcibus_dev(struct device *dev) |
1da177e4 | 91 | { |
fd7d1ced | 92 | struct pci_bus *pci_bus = to_pci_bus(dev); |
1da177e4 | 93 | |
ff0387c3 | 94 | put_device(pci_bus->bridge); |
2fe2abf8 | 95 | pci_bus_remove_resources(pci_bus); |
98d9f30c | 96 | pci_release_bus_of_node(pci_bus); |
1da177e4 LT |
97 | kfree(pci_bus); |
98 | } | |
99 | ||
100 | static struct class pcibus_class = { | |
101 | .name = "pci_bus", | |
fd7d1ced | 102 | .dev_release = &release_pcibus_dev, |
56039e65 | 103 | .dev_groups = pcibus_groups, |
1da177e4 LT |
104 | }; |
105 | ||
106 | static int __init pcibus_class_init(void) | |
107 | { | |
108 | return class_register(&pcibus_class); | |
109 | } | |
110 | postcore_initcall(pcibus_class_init); | |
111 | ||
6ac665c6 | 112 | static u64 pci_size(u64 base, u64 maxbase, u64 mask) |
1da177e4 | 113 | { |
6ac665c6 | 114 | u64 size = mask & maxbase; /* Find the significant bits */ |
1da177e4 LT |
115 | if (!size) |
116 | return 0; | |
117 | ||
3e466e2d BH |
118 | /* |
119 | * Get the lowest of them to find the decode size, and from that | |
120 | * the extent. | |
121 | */ | |
01b37f85 | 122 | size = size & ~(size-1); |
1da177e4 | 123 | |
3e466e2d BH |
124 | /* |
125 | * base == maxbase can be valid only if the BAR has already been | |
126 | * programmed with all 1s. | |
127 | */ | |
01b37f85 | 128 | if (base == maxbase && ((base | (size - 1)) & mask) != mask) |
1da177e4 LT |
129 | return 0; |
130 | ||
131 | return size; | |
132 | } | |
133 | ||
28c6821a | 134 | static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar) |
6ac665c6 | 135 | { |
8d6a6a47 | 136 | u32 mem_type; |
28c6821a | 137 | unsigned long flags; |
8d6a6a47 | 138 | |
6ac665c6 | 139 | if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { |
28c6821a BH |
140 | flags = bar & ~PCI_BASE_ADDRESS_IO_MASK; |
141 | flags |= IORESOURCE_IO; | |
142 | return flags; | |
6ac665c6 | 143 | } |
07eddf3d | 144 | |
28c6821a BH |
145 | flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK; |
146 | flags |= IORESOURCE_MEM; | |
147 | if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) | |
148 | flags |= IORESOURCE_PREFETCH; | |
07eddf3d | 149 | |
8d6a6a47 BH |
150 | mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK; |
151 | switch (mem_type) { | |
152 | case PCI_BASE_ADDRESS_MEM_TYPE_32: | |
153 | break; | |
154 | case PCI_BASE_ADDRESS_MEM_TYPE_1M: | |
0ff9514b | 155 | /* 1M mem BAR treated as 32-bit BAR */ |
8d6a6a47 BH |
156 | break; |
157 | case PCI_BASE_ADDRESS_MEM_TYPE_64: | |
28c6821a BH |
158 | flags |= IORESOURCE_MEM_64; |
159 | break; | |
8d6a6a47 | 160 | default: |
0ff9514b | 161 | /* mem unknown type treated as 32-bit BAR */ |
8d6a6a47 BH |
162 | break; |
163 | } | |
28c6821a | 164 | return flags; |
07eddf3d YL |
165 | } |
166 | ||
808e34e2 ZK |
167 | #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO) |
168 | ||
0b400c7e | 169 | /** |
2f0cd59c | 170 | * __pci_read_base - Read a PCI BAR |
0b400c7e YZ |
171 | * @dev: the PCI device |
172 | * @type: type of the BAR | |
173 | * @res: resource buffer to be filled in | |
174 | * @pos: BAR position in the config space | |
175 | * | |
176 | * Returns 1 if the BAR is 64-bit, or 0 if 32-bit. | |
6ac665c6 | 177 | */ |
0b400c7e | 178 | int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, |
3c78bc61 | 179 | struct resource *res, unsigned int pos) |
07eddf3d | 180 | { |
dc5205ef | 181 | u32 l = 0, sz = 0, mask; |
23b13bc7 | 182 | u64 l64, sz64, mask64; |
253d2e54 | 183 | u16 orig_cmd; |
cf4d1cf5 | 184 | struct pci_bus_region region, inverted_region; |
6ac665c6 | 185 | |
1ed67439 | 186 | mask = type ? PCI_ROM_ADDRESS_MASK : ~0; |
6ac665c6 | 187 | |
0ff9514b | 188 | /* No printks while decoding is disabled! */ |
253d2e54 JP |
189 | if (!dev->mmio_always_on) { |
190 | pci_read_config_word(dev, PCI_COMMAND, &orig_cmd); | |
808e34e2 ZK |
191 | if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) { |
192 | pci_write_config_word(dev, PCI_COMMAND, | |
193 | orig_cmd & ~PCI_COMMAND_DECODE_ENABLE); | |
194 | } | |
253d2e54 JP |
195 | } |
196 | ||
6ac665c6 MW |
197 | res->name = pci_name(dev); |
198 | ||
199 | pci_read_config_dword(dev, pos, &l); | |
1ed67439 | 200 | pci_write_config_dword(dev, pos, l | mask); |
6ac665c6 MW |
201 | pci_read_config_dword(dev, pos, &sz); |
202 | pci_write_config_dword(dev, pos, l); | |
203 | ||
204 | /* | |
205 | * All bits set in sz means the device isn't working properly. | |
45aa23b4 BH |
206 | * If the BAR isn't implemented, all bits must be 0. If it's a |
207 | * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit | |
208 | * 1 must be clear. | |
6ac665c6 | 209 | */ |
f795d86a MS |
210 | if (sz == 0xffffffff) |
211 | sz = 0; | |
6ac665c6 MW |
212 | |
213 | /* | |
214 | * I don't know how l can have all bits set. Copied from old code. | |
215 | * Maybe it fixes a bug on some ancient platform. | |
216 | */ | |
217 | if (l == 0xffffffff) | |
218 | l = 0; | |
219 | ||
220 | if (type == pci_bar_unknown) { | |
28c6821a BH |
221 | res->flags = decode_bar(dev, l); |
222 | res->flags |= IORESOURCE_SIZEALIGN; | |
223 | if (res->flags & IORESOURCE_IO) { | |
f795d86a MS |
224 | l64 = l & PCI_BASE_ADDRESS_IO_MASK; |
225 | sz64 = sz & PCI_BASE_ADDRESS_IO_MASK; | |
226 | mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT; | |
6ac665c6 | 227 | } else { |
f795d86a MS |
228 | l64 = l & PCI_BASE_ADDRESS_MEM_MASK; |
229 | sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK; | |
230 | mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK; | |
6ac665c6 MW |
231 | } |
232 | } else { | |
7a6d312b BH |
233 | if (l & PCI_ROM_ADDRESS_ENABLE) |
234 | res->flags |= IORESOURCE_ROM_ENABLE; | |
f795d86a MS |
235 | l64 = l & PCI_ROM_ADDRESS_MASK; |
236 | sz64 = sz & PCI_ROM_ADDRESS_MASK; | |
76dc5268 | 237 | mask64 = PCI_ROM_ADDRESS_MASK; |
6ac665c6 MW |
238 | } |
239 | ||
28c6821a | 240 | if (res->flags & IORESOURCE_MEM_64) { |
6ac665c6 MW |
241 | pci_read_config_dword(dev, pos + 4, &l); |
242 | pci_write_config_dword(dev, pos + 4, ~0); | |
243 | pci_read_config_dword(dev, pos + 4, &sz); | |
244 | pci_write_config_dword(dev, pos + 4, l); | |
245 | ||
246 | l64 |= ((u64)l << 32); | |
247 | sz64 |= ((u64)sz << 32); | |
f795d86a MS |
248 | mask64 |= ((u64)~0 << 32); |
249 | } | |
6ac665c6 | 250 | |
f795d86a MS |
251 | if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE)) |
252 | pci_write_config_word(dev, PCI_COMMAND, orig_cmd); | |
6ac665c6 | 253 | |
f795d86a MS |
254 | if (!sz64) |
255 | goto fail; | |
6ac665c6 | 256 | |
f795d86a | 257 | sz64 = pci_size(l64, sz64, mask64); |
7e79c5f8 | 258 | if (!sz64) { |
7506dc79 | 259 | pci_info(dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n", |
7e79c5f8 | 260 | pos); |
f795d86a | 261 | goto fail; |
7e79c5f8 | 262 | } |
f795d86a MS |
263 | |
264 | if (res->flags & IORESOURCE_MEM_64) { | |
3a9ad0b4 YL |
265 | if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8) |
266 | && sz64 > 0x100000000ULL) { | |
23b13bc7 BH |
267 | res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED; |
268 | res->start = 0; | |
269 | res->end = 0; | |
7506dc79 | 270 | pci_err(dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n", |
f795d86a | 271 | pos, (unsigned long long)sz64); |
23b13bc7 | 272 | goto out; |
c7dabef8 BH |
273 | } |
274 | ||
3a9ad0b4 | 275 | if ((sizeof(pci_bus_addr_t) < 8) && l) { |
31e9dd25 | 276 | /* Above 32-bit boundary; try to reallocate */ |
c83bd900 | 277 | res->flags |= IORESOURCE_UNSET; |
72dc5601 | 278 | res->start = 0; |
01b37f85 | 279 | res->end = sz64 - 1; |
7506dc79 | 280 | pci_info(dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n", |
f795d86a | 281 | pos, (unsigned long long)l64); |
72dc5601 | 282 | goto out; |
6ac665c6 | 283 | } |
6ac665c6 MW |
284 | } |
285 | ||
f795d86a | 286 | region.start = l64; |
01b37f85 | 287 | region.end = l64 + sz64 - 1; |
f795d86a | 288 | |
fc279850 YL |
289 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
290 | pcibios_resource_to_bus(dev->bus, &inverted_region, res); | |
cf4d1cf5 KH |
291 | |
292 | /* | |
293 | * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is | |
294 | * the corresponding resource address (the physical address used by | |
295 | * the CPU. Converting that resource address back to a bus address | |
296 | * should yield the original BAR value: | |
297 | * | |
298 | * resource_to_bus(bus_to_resource(A)) == A | |
299 | * | |
300 | * If it doesn't, CPU accesses to "bus_to_resource(A)" will not | |
301 | * be claimed by the device. | |
302 | */ | |
303 | if (inverted_region.start != region.start) { | |
cf4d1cf5 | 304 | res->flags |= IORESOURCE_UNSET; |
cf4d1cf5 | 305 | res->start = 0; |
26370fc6 | 306 | res->end = region.end - region.start; |
7506dc79 | 307 | pci_info(dev, "reg 0x%x: initial BAR value %#010llx invalid\n", |
f795d86a | 308 | pos, (unsigned long long)region.start); |
cf4d1cf5 | 309 | } |
96ddef25 | 310 | |
0ff9514b BH |
311 | goto out; |
312 | ||
313 | ||
314 | fail: | |
315 | res->flags = 0; | |
316 | out: | |
31e9dd25 | 317 | if (res->flags) |
34c6b710 | 318 | pci_info(dev, "reg 0x%x: %pR\n", pos, res); |
0ff9514b | 319 | |
28c6821a | 320 | return (res->flags & IORESOURCE_MEM_64) ? 1 : 0; |
07eddf3d YL |
321 | } |
322 | ||
1da177e4 LT |
323 | static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) |
324 | { | |
6ac665c6 | 325 | unsigned int pos, reg; |
07eddf3d | 326 | |
ad67b437 PB |
327 | if (dev->non_compliant_bars) |
328 | return; | |
329 | ||
bf4447fd KA |
330 | /* Per PCIe r4.0, sec 9.3.4.1.11, the VF BARs are all RO Zero */ |
331 | if (dev->is_virtfn) | |
332 | return; | |
333 | ||
6ac665c6 MW |
334 | for (pos = 0; pos < howmany; pos++) { |
335 | struct resource *res = &dev->resource[pos]; | |
1da177e4 | 336 | reg = PCI_BASE_ADDRESS_0 + (pos << 2); |
6ac665c6 | 337 | pos += __pci_read_base(dev, pci_bar_unknown, res, reg); |
1da177e4 | 338 | } |
6ac665c6 | 339 | |
1da177e4 | 340 | if (rom) { |
6ac665c6 | 341 | struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; |
1da177e4 | 342 | dev->rom_base_reg = rom; |
6ac665c6 | 343 | res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | |
92b19ff5 | 344 | IORESOURCE_READONLY | IORESOURCE_SIZEALIGN; |
6ac665c6 | 345 | __pci_read_base(dev, pci_bar_mem32, res, rom); |
1da177e4 LT |
346 | } |
347 | } | |
348 | ||
51c48b31 BH |
349 | static void pci_read_bridge_windows(struct pci_dev *bridge) |
350 | { | |
351 | u16 io; | |
352 | u32 pmem, tmp; | |
353 | ||
354 | pci_read_config_word(bridge, PCI_IO_BASE, &io); | |
355 | if (!io) { | |
356 | pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0); | |
357 | pci_read_config_word(bridge, PCI_IO_BASE, &io); | |
358 | pci_write_config_word(bridge, PCI_IO_BASE, 0x0); | |
359 | } | |
360 | if (io) | |
361 | bridge->io_window = 1; | |
362 | ||
363 | /* | |
364 | * DECchip 21050 pass 2 errata: the bridge may miss an address | |
365 | * disconnect boundary by one PCI data phase. Workaround: do not | |
366 | * use prefetching on this device. | |
367 | */ | |
368 | if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) | |
369 | return; | |
370 | ||
371 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); | |
372 | if (!pmem) { | |
373 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, | |
374 | 0xffe0fff0); | |
375 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); | |
376 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); | |
377 | } | |
378 | if (!pmem) | |
379 | return; | |
380 | ||
381 | bridge->pref_window = 1; | |
382 | ||
383 | if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { | |
384 | ||
385 | /* | |
386 | * Bridge claims to have a 64-bit prefetchable memory | |
387 | * window; verify that the upper bits are actually | |
388 | * writable. | |
389 | */ | |
390 | pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &pmem); | |
391 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
392 | 0xffffffff); | |
393 | pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp); | |
394 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, pmem); | |
395 | if (tmp) | |
396 | bridge->pref_64_window = 1; | |
397 | } | |
398 | } | |
399 | ||
15856ad5 | 400 | static void pci_read_bridge_io(struct pci_bus *child) |
1da177e4 LT |
401 | { |
402 | struct pci_dev *dev = child->self; | |
403 | u8 io_base_lo, io_limit_lo; | |
2b28ae19 | 404 | unsigned long io_mask, io_granularity, base, limit; |
5bfa14ed | 405 | struct pci_bus_region region; |
2b28ae19 BH |
406 | struct resource *res; |
407 | ||
408 | io_mask = PCI_IO_RANGE_MASK; | |
409 | io_granularity = 0x1000; | |
410 | if (dev->io_window_1k) { | |
411 | /* Support 1K I/O space granularity */ | |
412 | io_mask = PCI_IO_1K_RANGE_MASK; | |
413 | io_granularity = 0x400; | |
414 | } | |
1da177e4 | 415 | |
1da177e4 LT |
416 | res = child->resource[0]; |
417 | pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); | |
418 | pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); | |
2b28ae19 BH |
419 | base = (io_base_lo & io_mask) << 8; |
420 | limit = (io_limit_lo & io_mask) << 8; | |
1da177e4 LT |
421 | |
422 | if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { | |
423 | u16 io_base_hi, io_limit_hi; | |
8f38eaca | 424 | |
1da177e4 LT |
425 | pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); |
426 | pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); | |
8f38eaca BH |
427 | base |= ((unsigned long) io_base_hi << 16); |
428 | limit |= ((unsigned long) io_limit_hi << 16); | |
1da177e4 LT |
429 | } |
430 | ||
5dde383e | 431 | if (base <= limit) { |
1da177e4 | 432 | res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; |
5bfa14ed | 433 | region.start = base; |
2b28ae19 | 434 | region.end = limit + io_granularity - 1; |
fc279850 | 435 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
34c6b710 | 436 | pci_info(dev, " bridge window %pR\n", res); |
1da177e4 | 437 | } |
fa27b2d1 BH |
438 | } |
439 | ||
15856ad5 | 440 | static void pci_read_bridge_mmio(struct pci_bus *child) |
fa27b2d1 BH |
441 | { |
442 | struct pci_dev *dev = child->self; | |
443 | u16 mem_base_lo, mem_limit_lo; | |
444 | unsigned long base, limit; | |
5bfa14ed | 445 | struct pci_bus_region region; |
fa27b2d1 | 446 | struct resource *res; |
1da177e4 LT |
447 | |
448 | res = child->resource[1]; | |
449 | pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); | |
450 | pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); | |
8f38eaca BH |
451 | base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; |
452 | limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; | |
5dde383e | 453 | if (base <= limit) { |
1da177e4 | 454 | res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; |
5bfa14ed BH |
455 | region.start = base; |
456 | region.end = limit + 0xfffff; | |
fc279850 | 457 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
34c6b710 | 458 | pci_info(dev, " bridge window %pR\n", res); |
1da177e4 | 459 | } |
fa27b2d1 BH |
460 | } |
461 | ||
15856ad5 | 462 | static void pci_read_bridge_mmio_pref(struct pci_bus *child) |
fa27b2d1 BH |
463 | { |
464 | struct pci_dev *dev = child->self; | |
465 | u16 mem_base_lo, mem_limit_lo; | |
7fc986d8 | 466 | u64 base64, limit64; |
3a9ad0b4 | 467 | pci_bus_addr_t base, limit; |
5bfa14ed | 468 | struct pci_bus_region region; |
fa27b2d1 | 469 | struct resource *res; |
1da177e4 LT |
470 | |
471 | res = child->resource[2]; | |
472 | pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); | |
473 | pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); | |
7fc986d8 YL |
474 | base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; |
475 | limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; | |
1da177e4 LT |
476 | |
477 | if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { | |
478 | u32 mem_base_hi, mem_limit_hi; | |
8f38eaca | 479 | |
1da177e4 LT |
480 | pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); |
481 | pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); | |
482 | ||
483 | /* | |
484 | * Some bridges set the base > limit by default, and some | |
485 | * (broken) BIOSes do not initialize them. If we find | |
486 | * this, just assume they are not being used. | |
487 | */ | |
488 | if (mem_base_hi <= mem_limit_hi) { | |
7fc986d8 YL |
489 | base64 |= (u64) mem_base_hi << 32; |
490 | limit64 |= (u64) mem_limit_hi << 32; | |
1da177e4 LT |
491 | } |
492 | } | |
7fc986d8 | 493 | |
3a9ad0b4 YL |
494 | base = (pci_bus_addr_t) base64; |
495 | limit = (pci_bus_addr_t) limit64; | |
7fc986d8 YL |
496 | |
497 | if (base != base64) { | |
7506dc79 | 498 | pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n", |
7fc986d8 YL |
499 | (unsigned long long) base64); |
500 | return; | |
501 | } | |
502 | ||
5dde383e | 503 | if (base <= limit) { |
1f82de10 YL |
504 | res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) | |
505 | IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
506 | if (res->flags & PCI_PREF_RANGE_TYPE_64) | |
507 | res->flags |= IORESOURCE_MEM_64; | |
5bfa14ed BH |
508 | region.start = base; |
509 | region.end = limit + 0xfffff; | |
fc279850 | 510 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
34c6b710 | 511 | pci_info(dev, " bridge window %pR\n", res); |
1da177e4 LT |
512 | } |
513 | } | |
514 | ||
15856ad5 | 515 | void pci_read_bridge_bases(struct pci_bus *child) |
fa27b2d1 BH |
516 | { |
517 | struct pci_dev *dev = child->self; | |
2fe2abf8 | 518 | struct resource *res; |
fa27b2d1 BH |
519 | int i; |
520 | ||
521 | if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */ | |
522 | return; | |
523 | ||
7506dc79 | 524 | pci_info(dev, "PCI bridge to %pR%s\n", |
b918c62e | 525 | &child->busn_res, |
fa27b2d1 BH |
526 | dev->transparent ? " (subtractive decode)" : ""); |
527 | ||
2fe2abf8 BH |
528 | pci_bus_remove_resources(child); |
529 | for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) | |
530 | child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; | |
531 | ||
fa27b2d1 BH |
532 | pci_read_bridge_io(child); |
533 | pci_read_bridge_mmio(child); | |
534 | pci_read_bridge_mmio_pref(child); | |
2adf7516 BH |
535 | |
536 | if (dev->transparent) { | |
2fe2abf8 | 537 | pci_bus_for_each_resource(child->parent, res, i) { |
d739a099 | 538 | if (res && res->flags) { |
2fe2abf8 BH |
539 | pci_bus_add_resource(child, res, |
540 | PCI_SUBTRACTIVE_DECODE); | |
34c6b710 | 541 | pci_info(dev, " bridge window %pR (subtractive decode)\n", |
2fe2abf8 BH |
542 | res); |
543 | } | |
2adf7516 BH |
544 | } |
545 | } | |
fa27b2d1 BH |
546 | } |
547 | ||
670ba0c8 | 548 | static struct pci_bus *pci_alloc_bus(struct pci_bus *parent) |
1da177e4 LT |
549 | { |
550 | struct pci_bus *b; | |
551 | ||
f5afe806 | 552 | b = kzalloc(sizeof(*b), GFP_KERNEL); |
05013486 BH |
553 | if (!b) |
554 | return NULL; | |
555 | ||
556 | INIT_LIST_HEAD(&b->node); | |
557 | INIT_LIST_HEAD(&b->children); | |
558 | INIT_LIST_HEAD(&b->devices); | |
559 | INIT_LIST_HEAD(&b->slots); | |
560 | INIT_LIST_HEAD(&b->resources); | |
561 | b->max_bus_speed = PCI_SPEED_UNKNOWN; | |
562 | b->cur_bus_speed = PCI_SPEED_UNKNOWN; | |
670ba0c8 CM |
563 | #ifdef CONFIG_PCI_DOMAINS_GENERIC |
564 | if (parent) | |
565 | b->domain_nr = parent->domain_nr; | |
566 | #endif | |
1da177e4 LT |
567 | return b; |
568 | } | |
569 | ||
9885440b | 570 | static void pci_release_host_bridge_dev(struct device *dev) |
70efde2a JL |
571 | { |
572 | struct pci_host_bridge *bridge = to_pci_host_bridge(dev); | |
573 | ||
574 | if (bridge->release_fn) | |
575 | bridge->release_fn(bridge); | |
3bbce531 JK |
576 | |
577 | pci_free_resource_list(&bridge->windows); | |
7608158d | 578 | pci_free_resource_list(&bridge->dma_ranges); |
9885440b | 579 | kfree(bridge); |
70efde2a JL |
580 | } |
581 | ||
6302bf3e | 582 | static void pci_init_host_bridge(struct pci_host_bridge *bridge) |
7b543663 | 583 | { |
05013486 | 584 | INIT_LIST_HEAD(&bridge->windows); |
e80a91ad | 585 | INIT_LIST_HEAD(&bridge->dma_ranges); |
37d6a0a6 | 586 | |
02bfeb48 BH |
587 | /* |
588 | * We assume we can manage these PCIe features. Some systems may | |
589 | * reserve these for use by the platform itself, e.g., an ACPI BIOS | |
590 | * may implement its own AER handling and use _OSC to prevent the | |
591 | * OS from interfering. | |
592 | */ | |
593 | bridge->native_aer = 1; | |
9310f0dc | 594 | bridge->native_pcie_hotplug = 1; |
1df81a6d | 595 | bridge->native_shpc_hotplug = 1; |
02bfeb48 | 596 | bridge->native_pme = 1; |
af8bb9f8 | 597 | bridge->native_ltr = 1; |
ac1c8e35 | 598 | bridge->native_dpc = 1; |
15d82ca2 | 599 | bridge->domain_nr = PCI_DOMAIN_NR_NOT_SET; |
9885440b RH |
600 | |
601 | device_initialize(&bridge->dev); | |
6302bf3e JPB |
602 | } |
603 | ||
604 | struct pci_host_bridge *pci_alloc_host_bridge(size_t priv) | |
605 | { | |
606 | struct pci_host_bridge *bridge; | |
607 | ||
608 | bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL); | |
609 | if (!bridge) | |
610 | return NULL; | |
611 | ||
612 | pci_init_host_bridge(bridge); | |
613 | bridge->dev.release = pci_release_host_bridge_dev; | |
02bfeb48 | 614 | |
7b543663 YL |
615 | return bridge; |
616 | } | |
a52d1443 | 617 | EXPORT_SYMBOL(pci_alloc_host_bridge); |
7b543663 | 618 | |
9885440b RH |
619 | static void devm_pci_alloc_host_bridge_release(void *data) |
620 | { | |
621 | pci_free_host_bridge(data); | |
622 | } | |
623 | ||
5c3f18cc LP |
624 | struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, |
625 | size_t priv) | |
626 | { | |
9885440b | 627 | int ret; |
5c3f18cc LP |
628 | struct pci_host_bridge *bridge; |
629 | ||
9885440b | 630 | bridge = pci_alloc_host_bridge(priv); |
5c3f18cc LP |
631 | if (!bridge) |
632 | return NULL; | |
633 | ||
6a589900 RH |
634 | bridge->dev.parent = dev; |
635 | ||
9885440b RH |
636 | ret = devm_add_action_or_reset(dev, devm_pci_alloc_host_bridge_release, |
637 | bridge); | |
638 | if (ret) | |
639 | return NULL; | |
5c3f18cc | 640 | |
669cbc70 RH |
641 | ret = devm_of_pci_bridge_init(dev, bridge); |
642 | if (ret) | |
643 | return NULL; | |
644 | ||
5c3f18cc LP |
645 | return bridge; |
646 | } | |
647 | EXPORT_SYMBOL(devm_pci_alloc_host_bridge); | |
648 | ||
dff79b91 LP |
649 | void pci_free_host_bridge(struct pci_host_bridge *bridge) |
650 | { | |
9885440b | 651 | put_device(&bridge->dev); |
dff79b91 LP |
652 | } |
653 | EXPORT_SYMBOL(pci_free_host_bridge); | |
654 | ||
e56faff5 | 655 | /* Indexed by PCI_X_SSTATUS_FREQ (secondary bus mode and frequency) */ |
0b950f0f | 656 | static const unsigned char pcix_bus_speed[] = { |
9be60ca0 MW |
657 | PCI_SPEED_UNKNOWN, /* 0 */ |
658 | PCI_SPEED_66MHz_PCIX, /* 1 */ | |
659 | PCI_SPEED_100MHz_PCIX, /* 2 */ | |
660 | PCI_SPEED_133MHz_PCIX, /* 3 */ | |
661 | PCI_SPEED_UNKNOWN, /* 4 */ | |
662 | PCI_SPEED_66MHz_PCIX_ECC, /* 5 */ | |
663 | PCI_SPEED_100MHz_PCIX_ECC, /* 6 */ | |
664 | PCI_SPEED_133MHz_PCIX_ECC, /* 7 */ | |
665 | PCI_SPEED_UNKNOWN, /* 8 */ | |
666 | PCI_SPEED_66MHz_PCIX_266, /* 9 */ | |
667 | PCI_SPEED_100MHz_PCIX_266, /* A */ | |
668 | PCI_SPEED_133MHz_PCIX_266, /* B */ | |
669 | PCI_SPEED_UNKNOWN, /* C */ | |
670 | PCI_SPEED_66MHz_PCIX_533, /* D */ | |
671 | PCI_SPEED_100MHz_PCIX_533, /* E */ | |
672 | PCI_SPEED_133MHz_PCIX_533 /* F */ | |
673 | }; | |
674 | ||
e56faff5 | 675 | /* Indexed by PCI_EXP_LNKCAP_SLS, PCI_EXP_LNKSTA_CLS */ |
343e51ae | 676 | const unsigned char pcie_link_speed[] = { |
3749c51a MW |
677 | PCI_SPEED_UNKNOWN, /* 0 */ |
678 | PCIE_SPEED_2_5GT, /* 1 */ | |
679 | PCIE_SPEED_5_0GT, /* 2 */ | |
9dfd97fe | 680 | PCIE_SPEED_8_0GT, /* 3 */ |
1acfb9b7 | 681 | PCIE_SPEED_16_0GT, /* 4 */ |
de76cda2 | 682 | PCIE_SPEED_32_0GT, /* 5 */ |
34191749 | 683 | PCIE_SPEED_64_0GT, /* 6 */ |
3749c51a MW |
684 | PCI_SPEED_UNKNOWN, /* 7 */ |
685 | PCI_SPEED_UNKNOWN, /* 8 */ | |
686 | PCI_SPEED_UNKNOWN, /* 9 */ | |
687 | PCI_SPEED_UNKNOWN, /* A */ | |
688 | PCI_SPEED_UNKNOWN, /* B */ | |
689 | PCI_SPEED_UNKNOWN, /* C */ | |
690 | PCI_SPEED_UNKNOWN, /* D */ | |
691 | PCI_SPEED_UNKNOWN, /* E */ | |
692 | PCI_SPEED_UNKNOWN /* F */ | |
693 | }; | |
e56faff5 BH |
694 | EXPORT_SYMBOL_GPL(pcie_link_speed); |
695 | ||
696 | const char *pci_speed_string(enum pci_bus_speed speed) | |
697 | { | |
698 | /* Indexed by the pci_bus_speed enum */ | |
699 | static const char *speed_strings[] = { | |
700 | "33 MHz PCI", /* 0x00 */ | |
701 | "66 MHz PCI", /* 0x01 */ | |
702 | "66 MHz PCI-X", /* 0x02 */ | |
703 | "100 MHz PCI-X", /* 0x03 */ | |
704 | "133 MHz PCI-X", /* 0x04 */ | |
705 | NULL, /* 0x05 */ | |
706 | NULL, /* 0x06 */ | |
707 | NULL, /* 0x07 */ | |
708 | NULL, /* 0x08 */ | |
709 | "66 MHz PCI-X 266", /* 0x09 */ | |
710 | "100 MHz PCI-X 266", /* 0x0a */ | |
711 | "133 MHz PCI-X 266", /* 0x0b */ | |
712 | "Unknown AGP", /* 0x0c */ | |
713 | "1x AGP", /* 0x0d */ | |
714 | "2x AGP", /* 0x0e */ | |
715 | "4x AGP", /* 0x0f */ | |
716 | "8x AGP", /* 0x10 */ | |
717 | "66 MHz PCI-X 533", /* 0x11 */ | |
718 | "100 MHz PCI-X 533", /* 0x12 */ | |
719 | "133 MHz PCI-X 533", /* 0x13 */ | |
720 | "2.5 GT/s PCIe", /* 0x14 */ | |
721 | "5.0 GT/s PCIe", /* 0x15 */ | |
722 | "8.0 GT/s PCIe", /* 0x16 */ | |
723 | "16.0 GT/s PCIe", /* 0x17 */ | |
724 | "32.0 GT/s PCIe", /* 0x18 */ | |
34191749 | 725 | "64.0 GT/s PCIe", /* 0x19 */ |
e56faff5 BH |
726 | }; |
727 | ||
728 | if (speed < ARRAY_SIZE(speed_strings)) | |
729 | return speed_strings[speed]; | |
730 | return "Unknown"; | |
731 | } | |
732 | EXPORT_SYMBOL_GPL(pci_speed_string); | |
3749c51a MW |
733 | |
734 | void pcie_update_link_speed(struct pci_bus *bus, u16 linksta) | |
735 | { | |
231afea1 | 736 | bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS]; |
3749c51a MW |
737 | } |
738 | EXPORT_SYMBOL_GPL(pcie_update_link_speed); | |
739 | ||
45b4cdd5 MW |
740 | static unsigned char agp_speeds[] = { |
741 | AGP_UNKNOWN, | |
742 | AGP_1X, | |
743 | AGP_2X, | |
744 | AGP_4X, | |
745 | AGP_8X | |
746 | }; | |
747 | ||
748 | static enum pci_bus_speed agp_speed(int agp3, int agpstat) | |
749 | { | |
750 | int index = 0; | |
751 | ||
752 | if (agpstat & 4) | |
753 | index = 3; | |
754 | else if (agpstat & 2) | |
755 | index = 2; | |
756 | else if (agpstat & 1) | |
757 | index = 1; | |
758 | else | |
759 | goto out; | |
f7625980 | 760 | |
45b4cdd5 MW |
761 | if (agp3) { |
762 | index += 2; | |
763 | if (index == 5) | |
764 | index = 0; | |
765 | } | |
766 | ||
767 | out: | |
768 | return agp_speeds[index]; | |
769 | } | |
770 | ||
9be60ca0 MW |
771 | static void pci_set_bus_speed(struct pci_bus *bus) |
772 | { | |
773 | struct pci_dev *bridge = bus->self; | |
774 | int pos; | |
775 | ||
45b4cdd5 MW |
776 | pos = pci_find_capability(bridge, PCI_CAP_ID_AGP); |
777 | if (!pos) | |
778 | pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3); | |
779 | if (pos) { | |
780 | u32 agpstat, agpcmd; | |
781 | ||
782 | pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat); | |
783 | bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7); | |
784 | ||
785 | pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd); | |
786 | bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7); | |
787 | } | |
788 | ||
9be60ca0 MW |
789 | pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); |
790 | if (pos) { | |
791 | u16 status; | |
792 | enum pci_bus_speed max; | |
9be60ca0 | 793 | |
7793eeab BH |
794 | pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS, |
795 | &status); | |
796 | ||
797 | if (status & PCI_X_SSTATUS_533MHZ) { | |
9be60ca0 | 798 | max = PCI_SPEED_133MHz_PCIX_533; |
7793eeab | 799 | } else if (status & PCI_X_SSTATUS_266MHZ) { |
9be60ca0 | 800 | max = PCI_SPEED_133MHz_PCIX_266; |
7793eeab | 801 | } else if (status & PCI_X_SSTATUS_133MHZ) { |
3c78bc61 | 802 | if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2) |
9be60ca0 | 803 | max = PCI_SPEED_133MHz_PCIX_ECC; |
3c78bc61 | 804 | else |
9be60ca0 | 805 | max = PCI_SPEED_133MHz_PCIX; |
9be60ca0 MW |
806 | } else { |
807 | max = PCI_SPEED_66MHz_PCIX; | |
808 | } | |
809 | ||
810 | bus->max_bus_speed = max; | |
7793eeab BH |
811 | bus->cur_bus_speed = pcix_bus_speed[ |
812 | (status & PCI_X_SSTATUS_FREQ) >> 6]; | |
9be60ca0 MW |
813 | |
814 | return; | |
815 | } | |
816 | ||
fdfe1511 | 817 | if (pci_is_pcie(bridge)) { |
9be60ca0 MW |
818 | u32 linkcap; |
819 | u16 linksta; | |
820 | ||
59875ae4 | 821 | pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap); |
231afea1 | 822 | bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS]; |
f0157160 | 823 | bridge->link_active_reporting = !!(linkcap & PCI_EXP_LNKCAP_DLLLARC); |
9be60ca0 | 824 | |
59875ae4 | 825 | pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta); |
9be60ca0 MW |
826 | pcie_update_link_speed(bus, linksta); |
827 | } | |
828 | } | |
829 | ||
44aa0c65 MZ |
830 | static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus) |
831 | { | |
b165e2b6 MZ |
832 | struct irq_domain *d; |
833 | ||
41dd40fd BF |
834 | /* If the host bridge driver sets a MSI domain of the bridge, use it */ |
835 | d = dev_get_msi_domain(bus->bridge); | |
836 | ||
44aa0c65 MZ |
837 | /* |
838 | * Any firmware interface that can resolve the msi_domain | |
839 | * should be called from here. | |
840 | */ | |
41dd40fd BF |
841 | if (!d) |
842 | d = pci_host_bridge_of_msi_domain(bus); | |
471036b2 SS |
843 | if (!d) |
844 | d = pci_host_bridge_acpi_msi_domain(bus); | |
44aa0c65 | 845 | |
788858eb JO |
846 | #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN |
847 | /* | |
848 | * If no IRQ domain was found via the OF tree, try looking it up | |
849 | * directly through the fwnode_handle. | |
850 | */ | |
851 | if (!d) { | |
852 | struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus); | |
853 | ||
854 | if (fwnode) | |
855 | d = irq_find_matching_fwnode(fwnode, | |
856 | DOMAIN_BUS_PCI_MSI); | |
857 | } | |
858 | #endif | |
859 | ||
b165e2b6 | 860 | return d; |
44aa0c65 MZ |
861 | } |
862 | ||
863 | static void pci_set_bus_msi_domain(struct pci_bus *bus) | |
864 | { | |
865 | struct irq_domain *d; | |
38ea72bd | 866 | struct pci_bus *b; |
44aa0c65 MZ |
867 | |
868 | /* | |
38ea72bd AW |
869 | * The bus can be a root bus, a subordinate bus, or a virtual bus |
870 | * created by an SR-IOV device. Walk up to the first bridge device | |
871 | * found or derive the domain from the host bridge. | |
44aa0c65 | 872 | */ |
38ea72bd AW |
873 | for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) { |
874 | if (b->self) | |
875 | d = dev_get_msi_domain(&b->self->dev); | |
876 | } | |
877 | ||
878 | if (!d) | |
879 | d = pci_host_bridge_msi_domain(b); | |
44aa0c65 MZ |
880 | |
881 | dev_set_msi_domain(&bus->dev, d); | |
882 | } | |
883 | ||
1e19e335 KHF |
884 | static int res_cmp(void *priv, const struct list_head *a, |
885 | const struct list_head *b) | |
886 | { | |
887 | struct resource_entry *entry1, *entry2; | |
888 | ||
889 | entry1 = container_of(a, struct resource_entry, node); | |
890 | entry2 = container_of(b, struct resource_entry, node); | |
891 | ||
892 | if (entry1->res->flags != entry2->res->flags) | |
893 | return entry1->res->flags > entry2->res->flags; | |
894 | ||
895 | if (entry1->offset != entry2->offset) | |
896 | return entry1->offset > entry2->offset; | |
897 | ||
898 | return entry1->res->start > entry2->res->start; | |
899 | } | |
900 | ||
cea9bc0b | 901 | static int pci_register_host_bridge(struct pci_host_bridge *bridge) |
37d6a0a6 AB |
902 | { |
903 | struct device *parent = bridge->dev.parent; | |
1e19e335 | 904 | struct resource_entry *window, *next, *n; |
37d6a0a6 | 905 | struct pci_bus *bus, *b; |
1e19e335 | 906 | resource_size_t offset, next_offset; |
37d6a0a6 | 907 | LIST_HEAD(resources); |
1e19e335 | 908 | struct resource *res, *next_res; |
37d6a0a6 AB |
909 | char addr[64], *fmt; |
910 | const char *name; | |
911 | int err; | |
912 | ||
913 | bus = pci_alloc_bus(NULL); | |
914 | if (!bus) | |
915 | return -ENOMEM; | |
916 | ||
917 | bridge->bus = bus; | |
918 | ||
3e466e2d | 919 | /* Temporarily move resources off the list */ |
37d6a0a6 AB |
920 | list_splice_init(&bridge->windows, &resources); |
921 | bus->sysdata = bridge->sysdata; | |
37d6a0a6 AB |
922 | bus->ops = bridge->ops; |
923 | bus->number = bus->busn_res.start = bridge->busnr; | |
924 | #ifdef CONFIG_PCI_DOMAINS_GENERIC | |
15d82ca2 BF |
925 | if (bridge->domain_nr == PCI_DOMAIN_NR_NOT_SET) |
926 | bus->domain_nr = pci_bus_find_domain_nr(bus, parent); | |
927 | else | |
928 | bus->domain_nr = bridge->domain_nr; | |
37d6a0a6 AB |
929 | #endif |
930 | ||
931 | b = pci_find_bus(pci_domain_nr(bus), bridge->busnr); | |
932 | if (b) { | |
3e466e2d | 933 | /* Ignore it if we already got here via a different bridge */ |
37d6a0a6 AB |
934 | dev_dbg(&b->dev, "bus already known\n"); |
935 | err = -EEXIST; | |
936 | goto free; | |
937 | } | |
938 | ||
939 | dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus), | |
940 | bridge->busnr); | |
941 | ||
942 | err = pcibios_root_bridge_prepare(bridge); | |
943 | if (err) | |
944 | goto free; | |
945 | ||
9885440b | 946 | err = device_add(&bridge->dev); |
1b54ae83 | 947 | if (err) { |
37d6a0a6 | 948 | put_device(&bridge->dev); |
1b54ae83 RH |
949 | goto free; |
950 | } | |
37d6a0a6 AB |
951 | bus->bridge = get_device(&bridge->dev); |
952 | device_enable_async_suspend(bus->bridge); | |
953 | pci_set_bus_of_node(bus); | |
954 | pci_set_bus_msi_domain(bus); | |
85aabbd7 JPB |
955 | if (bridge->msi_domain && !dev_get_msi_domain(&bus->dev) && |
956 | !pci_host_of_has_msi_map(parent)) | |
94e89b14 | 957 | bus->bus_flags |= PCI_BUS_FLAGS_NO_MSI; |
37d6a0a6 AB |
958 | |
959 | if (!parent) | |
960 | set_dev_node(bus->bridge, pcibus_to_node(bus)); | |
961 | ||
962 | bus->dev.class = &pcibus_class; | |
963 | bus->dev.parent = bus->bridge; | |
964 | ||
965 | dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number); | |
966 | name = dev_name(&bus->dev); | |
967 | ||
968 | err = device_register(&bus->dev); | |
969 | if (err) | |
970 | goto unregister; | |
971 | ||
972 | pcibios_add_bus(bus); | |
973 | ||
6e8e104d RH |
974 | if (bus->ops->add_bus) { |
975 | err = bus->ops->add_bus(bus); | |
976 | if (WARN_ON(err < 0)) | |
977 | dev_err(&bus->dev, "failed to add bus: %d\n", err); | |
978 | } | |
979 | ||
37d6a0a6 AB |
980 | /* Create legacy_io and legacy_mem files for this bus */ |
981 | pci_create_legacy_files(bus); | |
982 | ||
983 | if (parent) | |
984 | dev_info(parent, "PCI host bridge to bus %s\n", name); | |
985 | else | |
986 | pr_info("PCI host bridge to bus %s\n", name); | |
987 | ||
ad508610 YL |
988 | if (nr_node_ids > 1 && pcibus_to_node(bus) == NUMA_NO_NODE) |
989 | dev_warn(&bus->dev, "Unknown NUMA node; performance will be reduced\n"); | |
990 | ||
1e19e335 KHF |
991 | /* Sort and coalesce contiguous windows */ |
992 | list_sort(NULL, &resources, res_cmp); | |
993 | resource_list_for_each_entry_safe(window, n, &resources) { | |
994 | if (list_is_last(&window->node, &resources)) | |
995 | break; | |
996 | ||
997 | next = list_next_entry(window, node); | |
998 | offset = window->offset; | |
999 | res = window->res; | |
1000 | next_offset = next->offset; | |
1001 | next_res = next->res; | |
1002 | ||
1003 | if (res->flags != next_res->flags || offset != next_offset) | |
1004 | continue; | |
1005 | ||
1006 | if (res->end + 1 == next_res->start) { | |
1007 | next_res->start = res->start; | |
1008 | res->flags = res->start = res->end = 0; | |
1009 | } | |
1010 | } | |
1011 | ||
37d6a0a6 AB |
1012 | /* Add initial resources to the bus */ |
1013 | resource_list_for_each_entry_safe(window, n, &resources) { | |
37d6a0a6 AB |
1014 | offset = window->offset; |
1015 | res = window->res; | |
1e19e335 KHF |
1016 | if (!res->end) |
1017 | continue; | |
1018 | ||
1019 | list_move_tail(&window->node, &bridge->windows); | |
37d6a0a6 AB |
1020 | |
1021 | if (res->flags & IORESOURCE_BUS) | |
1022 | pci_bus_insert_busn_res(bus, bus->number, res->end); | |
1023 | else | |
1024 | pci_bus_add_resource(bus, res, 0); | |
1025 | ||
1026 | if (offset) { | |
1027 | if (resource_type(res) == IORESOURCE_IO) | |
1028 | fmt = " (bus address [%#06llx-%#06llx])"; | |
1029 | else | |
1030 | fmt = " (bus address [%#010llx-%#010llx])"; | |
1031 | ||
1032 | snprintf(addr, sizeof(addr), fmt, | |
1033 | (unsigned long long)(res->start - offset), | |
1034 | (unsigned long long)(res->end - offset)); | |
1035 | } else | |
1036 | addr[0] = '\0'; | |
1037 | ||
1038 | dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr); | |
1039 | } | |
1040 | ||
1041 | down_write(&pci_bus_sem); | |
1042 | list_add_tail(&bus->node, &pci_root_buses); | |
1043 | up_write(&pci_bus_sem); | |
1044 | ||
1045 | return 0; | |
1046 | ||
1047 | unregister: | |
1048 | put_device(&bridge->dev); | |
9885440b | 1049 | device_del(&bridge->dev); |
37d6a0a6 AB |
1050 | |
1051 | free: | |
1052 | kfree(bus); | |
1053 | return err; | |
1054 | } | |
1055 | ||
17e8f0d4 GB |
1056 | static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge) |
1057 | { | |
1058 | int pos; | |
1059 | u32 status; | |
1060 | ||
1061 | /* | |
1062 | * If extended config space isn't accessible on a bridge's primary | |
1063 | * bus, we certainly can't access it on the secondary bus. | |
1064 | */ | |
1065 | if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) | |
1066 | return false; | |
1067 | ||
1068 | /* | |
1069 | * PCIe Root Ports and switch ports are PCIe on both sides, so if | |
1070 | * extended config space is accessible on the primary, it's also | |
1071 | * accessible on the secondary. | |
1072 | */ | |
1073 | if (pci_is_pcie(bridge) && | |
1074 | (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT || | |
1075 | pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM || | |
1076 | pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM)) | |
1077 | return true; | |
1078 | ||
1079 | /* | |
1080 | * For the other bridge types: | |
1081 | * - PCI-to-PCI bridges | |
1082 | * - PCIe-to-PCI/PCI-X forward bridges | |
1083 | * - PCI/PCI-X-to-PCIe reverse bridges | |
1084 | * extended config space on the secondary side is only accessible | |
1085 | * if the bridge supports PCI-X Mode 2. | |
1086 | */ | |
1087 | pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); | |
1088 | if (!pos) | |
1089 | return false; | |
1090 | ||
1091 | pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status); | |
1092 | return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ); | |
1093 | } | |
1094 | ||
cbd4e055 AB |
1095 | static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, |
1096 | struct pci_dev *bridge, int busnr) | |
1da177e4 LT |
1097 | { |
1098 | struct pci_bus *child; | |
07e29295 | 1099 | struct pci_host_bridge *host; |
1da177e4 | 1100 | int i; |
4f535093 | 1101 | int ret; |
1da177e4 | 1102 | |
3e466e2d | 1103 | /* Allocate a new bus and inherit stuff from the parent */ |
670ba0c8 | 1104 | child = pci_alloc_bus(parent); |
1da177e4 LT |
1105 | if (!child) |
1106 | return NULL; | |
1107 | ||
1da177e4 | 1108 | child->parent = parent; |
1da177e4 | 1109 | child->sysdata = parent->sysdata; |
6e325a62 | 1110 | child->bus_flags = parent->bus_flags; |
1da177e4 | 1111 | |
07e29295 RH |
1112 | host = pci_find_host_bridge(parent); |
1113 | if (host->child_ops) | |
1114 | child->ops = host->child_ops; | |
1115 | else | |
1116 | child->ops = parent->ops; | |
1117 | ||
3e466e2d BH |
1118 | /* |
1119 | * Initialize some portions of the bus device, but don't register | |
1120 | * it now as the parent is not properly set up yet. | |
fd7d1ced GKH |
1121 | */ |
1122 | child->dev.class = &pcibus_class; | |
1a927133 | 1123 | dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr); |
1da177e4 | 1124 | |
3e466e2d | 1125 | /* Set up the primary, secondary and subordinate bus numbers */ |
b918c62e YL |
1126 | child->number = child->busn_res.start = busnr; |
1127 | child->primary = parent->busn_res.start; | |
1128 | child->busn_res.end = 0xff; | |
1da177e4 | 1129 | |
4f535093 YL |
1130 | if (!bridge) { |
1131 | child->dev.parent = parent->bridge; | |
1132 | goto add_dev; | |
1133 | } | |
3789fa8a YZ |
1134 | |
1135 | child->self = bridge; | |
1136 | child->bridge = get_device(&bridge->dev); | |
4f535093 | 1137 | child->dev.parent = child->bridge; |
98d9f30c | 1138 | pci_set_bus_of_node(child); |
9be60ca0 MW |
1139 | pci_set_bus_speed(child); |
1140 | ||
17e8f0d4 GB |
1141 | /* |
1142 | * Check whether extended config space is accessible on the child | |
1143 | * bus. Note that we currently assume it is always accessible on | |
1144 | * the root bus. | |
1145 | */ | |
1146 | if (!pci_bridge_child_ext_cfg_accessible(bridge)) { | |
1147 | child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG; | |
1148 | pci_info(child, "extended config space not accessible\n"); | |
1149 | } | |
1150 | ||
3e466e2d | 1151 | /* Set up default resource pointers and names */ |
fde09c6d | 1152 | for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { |
1da177e4 LT |
1153 | child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; |
1154 | child->resource[i]->name = child->name; | |
1155 | } | |
1156 | bridge->subordinate = child; | |
1157 | ||
4f535093 | 1158 | add_dev: |
44aa0c65 | 1159 | pci_set_bus_msi_domain(child); |
4f535093 YL |
1160 | ret = device_register(&child->dev); |
1161 | WARN_ON(ret < 0); | |
1162 | ||
10a95747 JL |
1163 | pcibios_add_bus(child); |
1164 | ||
057bd2e0 TR |
1165 | if (child->ops->add_bus) { |
1166 | ret = child->ops->add_bus(child); | |
1167 | if (WARN_ON(ret < 0)) | |
1168 | dev_err(&child->dev, "failed to add bus: %d\n", ret); | |
1169 | } | |
1170 | ||
4f535093 YL |
1171 | /* Create legacy_io and legacy_mem files for this bus */ |
1172 | pci_create_legacy_files(child); | |
1173 | ||
1da177e4 LT |
1174 | return child; |
1175 | } | |
1176 | ||
3c78bc61 RD |
1177 | struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, |
1178 | int busnr) | |
1da177e4 LT |
1179 | { |
1180 | struct pci_bus *child; | |
1181 | ||
1182 | child = pci_alloc_child_bus(parent, dev, busnr); | |
e4ea9bb7 | 1183 | if (child) { |
d71374da | 1184 | down_write(&pci_bus_sem); |
1da177e4 | 1185 | list_add_tail(&child->node, &parent->children); |
d71374da | 1186 | up_write(&pci_bus_sem); |
e4ea9bb7 | 1187 | } |
1da177e4 LT |
1188 | return child; |
1189 | } | |
b7fe9434 | 1190 | EXPORT_SYMBOL(pci_add_new_bus); |
1da177e4 | 1191 | |
f3dbd802 RJ |
1192 | static void pci_enable_crs(struct pci_dev *pdev) |
1193 | { | |
1194 | u16 root_cap = 0; | |
1195 | ||
1196 | /* Enable CRS Software Visibility if supported */ | |
1197 | pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap); | |
1198 | if (root_cap & PCI_EXP_RTCAP_CRSVIS) | |
1199 | pcie_capability_set_word(pdev, PCI_EXP_RTCTL, | |
1200 | PCI_EXP_RTCTL_CRSSVE); | |
1201 | } | |
1202 | ||
1c02ea81 MW |
1203 | static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus, |
1204 | unsigned int available_buses); | |
2dbce590 SS |
1205 | /** |
1206 | * pci_ea_fixed_busnrs() - Read fixed Secondary and Subordinate bus | |
1207 | * numbers from EA capability. | |
1208 | * @dev: Bridge | |
1209 | * @sec: updated with secondary bus number from EA | |
1210 | * @sub: updated with subordinate bus number from EA | |
1211 | * | |
73884a70 SS |
1212 | * If @dev is a bridge with EA capability that specifies valid secondary |
1213 | * and subordinate bus numbers, return true with the bus numbers in @sec | |
1214 | * and @sub. Otherwise return false. | |
2dbce590 SS |
1215 | */ |
1216 | static bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub) | |
1217 | { | |
1218 | int ea, offset; | |
1219 | u32 dw; | |
73884a70 | 1220 | u8 ea_sec, ea_sub; |
2dbce590 SS |
1221 | |
1222 | if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE) | |
1223 | return false; | |
1224 | ||
1225 | /* find PCI EA capability in list */ | |
1226 | ea = pci_find_capability(dev, PCI_CAP_ID_EA); | |
1227 | if (!ea) | |
1228 | return false; | |
1229 | ||
1230 | offset = ea + PCI_EA_FIRST_ENT; | |
1231 | pci_read_config_dword(dev, offset, &dw); | |
73884a70 SS |
1232 | ea_sec = dw & PCI_EA_SEC_BUS_MASK; |
1233 | ea_sub = (dw & PCI_EA_SUB_BUS_MASK) >> PCI_EA_SUB_BUS_SHIFT; | |
1234 | if (ea_sec == 0 || ea_sub < ea_sec) | |
1235 | return false; | |
1236 | ||
1237 | *sec = ea_sec; | |
1238 | *sub = ea_sub; | |
2dbce590 SS |
1239 | return true; |
1240 | } | |
1c02ea81 | 1241 | |
1da177e4 | 1242 | /* |
1c02ea81 MW |
1243 | * pci_scan_bridge_extend() - Scan buses behind a bridge |
1244 | * @bus: Parent bus the bridge is on | |
1245 | * @dev: Bridge itself | |
1246 | * @max: Starting subordinate number of buses behind this bridge | |
1247 | * @available_buses: Total number of buses available for this bridge and | |
1248 | * the devices below. After the minimal bus space has | |
1249 | * been allocated the remaining buses will be | |
1250 | * distributed equally between hotplug-capable bridges. | |
1251 | * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges | |
1252 | * that need to be reconfigured. | |
1253 | * | |
1da177e4 LT |
1254 | * If it's a bridge, configure it and scan the bus behind it. |
1255 | * For CardBus bridges, we don't scan behind as the devices will | |
1256 | * be handled by the bridge driver itself. | |
1257 | * | |
1258 | * We need to process bridges in two passes -- first we scan those | |
1259 | * already configured by the BIOS and after we are done with all of | |
1260 | * them, we proceed to assigning numbers to the remaining buses in | |
1261 | * order to avoid overlaps between old and new bus numbers. | |
70f7880d MW |
1262 | * |
1263 | * Return: New subordinate number covering all buses behind this bridge. | |
1da177e4 | 1264 | */ |
1c02ea81 MW |
1265 | static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev, |
1266 | int max, unsigned int available_buses, | |
1267 | int pass) | |
1da177e4 LT |
1268 | { |
1269 | struct pci_bus *child; | |
1270 | int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); | |
49887941 | 1271 | u32 buses, i, j = 0; |
1da177e4 | 1272 | u16 bctl; |
99ddd552 | 1273 | u8 primary, secondary, subordinate; |
a1c19894 | 1274 | int broken = 0; |
2dbce590 SS |
1275 | bool fixed_buses; |
1276 | u8 fixed_sec, fixed_sub; | |
1277 | int next_busnr; | |
1da177e4 | 1278 | |
d963f651 MW |
1279 | /* |
1280 | * Make sure the bridge is powered on to be able to access config | |
1281 | * space of devices below it. | |
1282 | */ | |
1283 | pm_runtime_get_sync(&dev->dev); | |
1284 | ||
1da177e4 | 1285 | pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); |
99ddd552 BH |
1286 | primary = buses & 0xFF; |
1287 | secondary = (buses >> 8) & 0xFF; | |
1288 | subordinate = (buses >> 16) & 0xFF; | |
1da177e4 | 1289 | |
7506dc79 | 1290 | pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n", |
99ddd552 | 1291 | secondary, subordinate, pass); |
1da177e4 | 1292 | |
71f6bd4a | 1293 | if (!primary && (primary != bus->number) && secondary && subordinate) { |
7506dc79 | 1294 | pci_warn(dev, "Primary bus is hard wired to 0\n"); |
71f6bd4a YL |
1295 | primary = bus->number; |
1296 | } | |
1297 | ||
a1c19894 BH |
1298 | /* Check if setup is sensible at all */ |
1299 | if (!pass && | |
1965f66e | 1300 | (primary != bus->number || secondary <= bus->number || |
12d87069 | 1301 | secondary > subordinate)) { |
7506dc79 | 1302 | pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n", |
1965f66e | 1303 | secondary, subordinate); |
a1c19894 BH |
1304 | broken = 1; |
1305 | } | |
1306 | ||
3e466e2d BH |
1307 | /* |
1308 | * Disable Master-Abort Mode during probing to avoid reporting of | |
1309 | * bus errors in some architectures. | |
1310 | */ | |
1da177e4 LT |
1311 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); |
1312 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, | |
1313 | bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); | |
1314 | ||
f3dbd802 RJ |
1315 | pci_enable_crs(dev); |
1316 | ||
99ddd552 BH |
1317 | if ((secondary || subordinate) && !pcibios_assign_all_busses() && |
1318 | !is_cardbus && !broken) { | |
1319 | unsigned int cmax; | |
3e466e2d | 1320 | |
1da177e4 | 1321 | /* |
3e466e2d BH |
1322 | * Bus already configured by firmware, process it in the |
1323 | * first pass and just note the configuration. | |
1da177e4 LT |
1324 | */ |
1325 | if (pass) | |
bbe8f9a3 | 1326 | goto out; |
1da177e4 LT |
1327 | |
1328 | /* | |
3e466e2d BH |
1329 | * The bus might already exist for two reasons: Either we |
1330 | * are rescanning the bus or the bus is reachable through | |
1331 | * more than one bridge. The second case can happen with | |
1332 | * the i450NX chipset. | |
1da177e4 | 1333 | */ |
99ddd552 | 1334 | child = pci_find_bus(pci_domain_nr(bus), secondary); |
74710ded | 1335 | if (!child) { |
99ddd552 | 1336 | child = pci_add_new_bus(bus, dev, secondary); |
74710ded AC |
1337 | if (!child) |
1338 | goto out; | |
99ddd552 | 1339 | child->primary = primary; |
bc76b731 | 1340 | pci_bus_insert_busn_res(child, secondary, subordinate); |
74710ded | 1341 | child->bridge_ctl = bctl; |
1da177e4 LT |
1342 | } |
1343 | ||
1da177e4 | 1344 | cmax = pci_scan_child_bus(child); |
c95b0bd6 | 1345 | if (cmax > subordinate) |
7506dc79 | 1346 | pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n", |
c95b0bd6 | 1347 | subordinate, cmax); |
3e466e2d BH |
1348 | |
1349 | /* Subordinate should equal child->busn_res.end */ | |
c95b0bd6 AN |
1350 | if (subordinate > max) |
1351 | max = subordinate; | |
1da177e4 | 1352 | } else { |
3e466e2d | 1353 | |
1da177e4 LT |
1354 | /* |
1355 | * We need to assign a number to this bus which we always | |
1356 | * do in the second pass. | |
1357 | */ | |
12f44f46 | 1358 | if (!pass) { |
619c8c31 | 1359 | if (pcibios_assign_all_busses() || broken || is_cardbus) |
3e466e2d BH |
1360 | |
1361 | /* | |
1362 | * Temporarily disable forwarding of the | |
1363 | * configuration cycles on all bridges in | |
1364 | * this bus segment to avoid possible | |
1365 | * conflicts in the second pass between two | |
1366 | * bridges programmed with overlapping bus | |
1367 | * ranges. | |
1368 | */ | |
12f44f46 IK |
1369 | pci_write_config_dword(dev, PCI_PRIMARY_BUS, |
1370 | buses & ~0xffffff); | |
bbe8f9a3 | 1371 | goto out; |
12f44f46 | 1372 | } |
1da177e4 LT |
1373 | |
1374 | /* Clear errors */ | |
1375 | pci_write_config_word(dev, PCI_STATUS, 0xffff); | |
1376 | ||
2dbce590 SS |
1377 | /* Read bus numbers from EA Capability (if present) */ |
1378 | fixed_buses = pci_ea_fixed_busnrs(dev, &fixed_sec, &fixed_sub); | |
1379 | if (fixed_buses) | |
1380 | next_busnr = fixed_sec; | |
1381 | else | |
1382 | next_busnr = max + 1; | |
1383 | ||
3e466e2d BH |
1384 | /* |
1385 | * Prevent assigning a bus number that already exists. | |
1386 | * This can happen when a bridge is hot-plugged, so in this | |
1387 | * case we only re-scan this bus. | |
1388 | */ | |
2dbce590 | 1389 | child = pci_find_bus(pci_domain_nr(bus), next_busnr); |
b1a98b69 | 1390 | if (!child) { |
2dbce590 | 1391 | child = pci_add_new_bus(bus, dev, next_busnr); |
b1a98b69 TC |
1392 | if (!child) |
1393 | goto out; | |
2dbce590 | 1394 | pci_bus_insert_busn_res(child, next_busnr, |
a20c7f36 | 1395 | bus->busn_res.end); |
b1a98b69 | 1396 | } |
9a4d7d87 | 1397 | max++; |
1c02ea81 MW |
1398 | if (available_buses) |
1399 | available_buses--; | |
1400 | ||
1da177e4 LT |
1401 | buses = (buses & 0xff000000) |
1402 | | ((unsigned int)(child->primary) << 0) | |
b918c62e YL |
1403 | | ((unsigned int)(child->busn_res.start) << 8) |
1404 | | ((unsigned int)(child->busn_res.end) << 16); | |
1da177e4 LT |
1405 | |
1406 | /* | |
1407 | * yenta.c forces a secondary latency timer of 176. | |
1408 | * Copy that behaviour here. | |
1409 | */ | |
1410 | if (is_cardbus) { | |
1411 | buses &= ~0xff000000; | |
1412 | buses |= CARDBUS_LATENCY_TIMER << 24; | |
1413 | } | |
7c867c88 | 1414 | |
3e466e2d | 1415 | /* We need to blast all three values with a single write */ |
1da177e4 LT |
1416 | pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); |
1417 | ||
1418 | if (!is_cardbus) { | |
11949255 | 1419 | child->bridge_ctl = bctl; |
1c02ea81 | 1420 | max = pci_scan_child_bus_extend(child, available_buses); |
1da177e4 | 1421 | } else { |
3e466e2d | 1422 | |
1da177e4 | 1423 | /* |
3e466e2d BH |
1424 | * For CardBus bridges, we leave 4 bus numbers as |
1425 | * cards with a PCI-to-PCI bridge can be inserted | |
1426 | * later. | |
1da177e4 | 1427 | */ |
3c78bc61 | 1428 | for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) { |
49887941 | 1429 | struct pci_bus *parent = bus; |
cc57450f RS |
1430 | if (pci_find_bus(pci_domain_nr(bus), |
1431 | max+i+1)) | |
1432 | break; | |
49887941 DB |
1433 | while (parent->parent) { |
1434 | if ((!pcibios_assign_all_busses()) && | |
b918c62e YL |
1435 | (parent->busn_res.end > max) && |
1436 | (parent->busn_res.end <= max+i)) { | |
49887941 DB |
1437 | j = 1; |
1438 | } | |
1439 | parent = parent->parent; | |
1440 | } | |
1441 | if (j) { | |
3e466e2d | 1442 | |
49887941 | 1443 | /* |
3e466e2d BH |
1444 | * Often, there are two CardBus |
1445 | * bridges -- try to leave one | |
1446 | * valid bus number for each one. | |
49887941 DB |
1447 | */ |
1448 | i /= 2; | |
1449 | break; | |
1450 | } | |
1451 | } | |
cc57450f | 1452 | max += i; |
1da177e4 | 1453 | } |
3e466e2d | 1454 | |
2dbce590 SS |
1455 | /* |
1456 | * Set subordinate bus number to its real value. | |
1457 | * If fixed subordinate bus number exists from EA | |
1458 | * capability then use it. | |
1459 | */ | |
1460 | if (fixed_buses) | |
1461 | max = fixed_sub; | |
bc76b731 | 1462 | pci_bus_update_busn_res_end(child, max); |
1da177e4 LT |
1463 | pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); |
1464 | } | |
1465 | ||
cb3576fa GH |
1466 | sprintf(child->name, |
1467 | (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), | |
1468 | pci_domain_nr(bus), child->number); | |
1da177e4 | 1469 | |
e412d63d | 1470 | /* Check that all devices are accessible */ |
49887941 | 1471 | while (bus->parent) { |
b918c62e YL |
1472 | if ((child->busn_res.end > bus->busn_res.end) || |
1473 | (child->number > bus->busn_res.end) || | |
49887941 | 1474 | (child->number < bus->number) || |
b918c62e | 1475 | (child->busn_res.end < bus->number)) { |
e412d63d MW |
1476 | dev_info(&dev->dev, "devices behind bridge are unusable because %pR cannot be assigned for them\n", |
1477 | &child->busn_res); | |
1478 | break; | |
49887941 DB |
1479 | } |
1480 | bus = bus->parent; | |
1481 | } | |
1482 | ||
bbe8f9a3 RB |
1483 | out: |
1484 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl); | |
1485 | ||
d963f651 MW |
1486 | pm_runtime_put(&dev->dev); |
1487 | ||
1da177e4 LT |
1488 | return max; |
1489 | } | |
1c02ea81 MW |
1490 | |
1491 | /* | |
1492 | * pci_scan_bridge() - Scan buses behind a bridge | |
1493 | * @bus: Parent bus the bridge is on | |
1494 | * @dev: Bridge itself | |
1495 | * @max: Starting subordinate number of buses behind this bridge | |
1496 | * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges | |
1497 | * that need to be reconfigured. | |
1498 | * | |
1499 | * If it's a bridge, configure it and scan the bus behind it. | |
1500 | * For CardBus bridges, we don't scan behind as the devices will | |
1501 | * be handled by the bridge driver itself. | |
1502 | * | |
1503 | * We need to process bridges in two passes -- first we scan those | |
1504 | * already configured by the BIOS and after we are done with all of | |
1505 | * them, we proceed to assigning numbers to the remaining buses in | |
1506 | * order to avoid overlaps between old and new bus numbers. | |
70f7880d MW |
1507 | * |
1508 | * Return: New subordinate number covering all buses behind this bridge. | |
1c02ea81 MW |
1509 | */ |
1510 | int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) | |
1511 | { | |
1512 | return pci_scan_bridge_extend(bus, dev, max, 0, pass); | |
1513 | } | |
b7fe9434 | 1514 | EXPORT_SYMBOL(pci_scan_bridge); |
1da177e4 LT |
1515 | |
1516 | /* | |
1517 | * Read interrupt line and base address registers. | |
1518 | * The architecture-dependent code can tweak these, of course. | |
1519 | */ | |
1520 | static void pci_read_irq(struct pci_dev *dev) | |
1521 | { | |
1522 | unsigned char irq; | |
1523 | ||
be20f6b0 KA |
1524 | /* VFs are not allowed to use INTx, so skip the config reads */ |
1525 | if (dev->is_virtfn) { | |
1526 | dev->pin = 0; | |
1527 | dev->irq = 0; | |
1528 | return; | |
1529 | } | |
1530 | ||
1da177e4 | 1531 | pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); |
ffeff788 | 1532 | dev->pin = irq; |
1da177e4 LT |
1533 | if (irq) |
1534 | pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); | |
1535 | dev->irq = irq; | |
1536 | } | |
1537 | ||
bb209c82 | 1538 | void set_pcie_port_type(struct pci_dev *pdev) |
480b93b7 YZ |
1539 | { |
1540 | int pos; | |
1541 | u16 reg16; | |
d0751b98 YW |
1542 | int type; |
1543 | struct pci_dev *parent; | |
480b93b7 YZ |
1544 | |
1545 | pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); | |
1546 | if (!pos) | |
1547 | return; | |
51ebfc92 | 1548 | |
0efea000 | 1549 | pdev->pcie_cap = pos; |
480b93b7 | 1550 | pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); |
786e2288 | 1551 | pdev->pcie_flags_reg = reg16; |
69139244 AN |
1552 | pci_read_config_dword(pdev, pos + PCI_EXP_DEVCAP, &pdev->devcap); |
1553 | pdev->pcie_mpss = FIELD_GET(PCI_EXP_DEVCAP_PAYLOAD, pdev->devcap); | |
d0751b98 | 1554 | |
ca784104 MW |
1555 | parent = pci_upstream_bridge(pdev); |
1556 | if (!parent) | |
1557 | return; | |
1558 | ||
d0751b98 | 1559 | /* |
ca784104 MW |
1560 | * Some systems do not identify their upstream/downstream ports |
1561 | * correctly so detect impossible configurations here and correct | |
1562 | * the port type accordingly. | |
d0751b98 YW |
1563 | */ |
1564 | type = pci_pcie_type(pdev); | |
ca784104 | 1565 | if (type == PCI_EXP_TYPE_DOWNSTREAM) { |
b35b1df5 | 1566 | /* |
ca784104 MW |
1567 | * If pdev claims to be downstream port but the parent |
1568 | * device is also downstream port assume pdev is actually | |
1569 | * upstream port. | |
b35b1df5 | 1570 | */ |
ca784104 MW |
1571 | if (pcie_downstream_port(parent)) { |
1572 | pci_info(pdev, "claims to be downstream port but is acting as upstream port, correcting type\n"); | |
1573 | pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE; | |
1574 | pdev->pcie_flags_reg |= PCI_EXP_TYPE_UPSTREAM; | |
1575 | } | |
1576 | } else if (type == PCI_EXP_TYPE_UPSTREAM) { | |
1577 | /* | |
1578 | * If pdev claims to be upstream port but the parent | |
1579 | * device is also upstream port assume pdev is actually | |
1580 | * downstream port. | |
1581 | */ | |
1582 | if (pci_pcie_type(parent) == PCI_EXP_TYPE_UPSTREAM) { | |
1583 | pci_info(pdev, "claims to be upstream port but is acting as downstream port, correcting type\n"); | |
1584 | pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE; | |
1585 | pdev->pcie_flags_reg |= PCI_EXP_TYPE_DOWNSTREAM; | |
1586 | } | |
d0751b98 | 1587 | } |
480b93b7 YZ |
1588 | } |
1589 | ||
bb209c82 | 1590 | void set_pcie_hotplug_bridge(struct pci_dev *pdev) |
28760489 | 1591 | { |
28760489 EB |
1592 | u32 reg32; |
1593 | ||
59875ae4 | 1594 | pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32); |
28760489 EB |
1595 | if (reg32 & PCI_EXP_SLTCAP_HPC) |
1596 | pdev->is_hotplug_bridge = 1; | |
1597 | } | |
1598 | ||
8531e283 LW |
1599 | static void set_pcie_thunderbolt(struct pci_dev *dev) |
1600 | { | |
1601 | int vsec = 0; | |
1602 | u32 header; | |
1603 | ||
1604 | while ((vsec = pci_find_next_ext_capability(dev, vsec, | |
1605 | PCI_EXT_CAP_ID_VNDR))) { | |
1606 | pci_read_config_dword(dev, vsec + PCI_VNDR_HEADER, &header); | |
1607 | ||
1608 | /* Is the device part of a Thunderbolt controller? */ | |
1609 | if (dev->vendor == PCI_VENDOR_ID_INTEL && | |
1610 | PCI_VNDR_HEADER_ID(header) == PCI_VSEC_ID_INTEL_TBT) { | |
1611 | dev->is_thunderbolt = 1; | |
1612 | return; | |
1613 | } | |
1614 | } | |
1615 | } | |
1616 | ||
617654aa MW |
1617 | static void set_pcie_untrusted(struct pci_dev *dev) |
1618 | { | |
1619 | struct pci_dev *parent; | |
1620 | ||
1621 | /* | |
1622 | * If the upstream bridge is untrusted we treat this device | |
1623 | * untrusted as well. | |
1624 | */ | |
1625 | parent = pci_upstream_bridge(dev); | |
99b50be9 | 1626 | if (parent && (parent->untrusted || parent->external_facing)) |
617654aa MW |
1627 | dev->untrusted = true; |
1628 | } | |
1629 | ||
c037b6c8 RJ |
1630 | static void pci_set_removable(struct pci_dev *dev) |
1631 | { | |
1632 | struct pci_dev *parent = pci_upstream_bridge(dev); | |
1633 | ||
1634 | /* | |
1635 | * We (only) consider everything downstream from an external_facing | |
1636 | * device to be removable by the user. We're mainly concerned with | |
1637 | * consumer platforms with user accessible thunderbolt ports that are | |
1638 | * vulnerable to DMA attacks, and we expect those ports to be marked by | |
1639 | * the firmware as external_facing. Devices in traditional hotplug | |
1640 | * slots can technically be removed, but the expectation is that unless | |
1641 | * the port is marked with external_facing, such devices are less | |
1642 | * accessible to user / may not be removed by end user, and thus not | |
1643 | * exposed as "removable" to userspace. | |
1644 | */ | |
1645 | if (parent && | |
1646 | (parent->external_facing || dev_is_removable(&parent->dev))) | |
1647 | dev_set_removable(&dev->dev, DEVICE_REMOVABLE); | |
1648 | } | |
1649 | ||
78916b00 | 1650 | /** |
3e466e2d | 1651 | * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config? |
78916b00 AW |
1652 | * @dev: PCI device |
1653 | * | |
1654 | * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that | |
1655 | * when forwarding a type1 configuration request the bridge must check that | |
1656 | * the extended register address field is zero. The bridge is not permitted | |
1657 | * to forward the transactions and must handle it as an Unsupported Request. | |
1658 | * Some bridges do not follow this rule and simply drop the extended register | |
1659 | * bits, resulting in the standard config space being aliased, every 256 | |
1660 | * bytes across the entire configuration space. Test for this condition by | |
1661 | * comparing the first dword of each potential alias to the vendor/device ID. | |
1662 | * Known offenders: | |
1663 | * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03) | |
1664 | * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40) | |
1665 | */ | |
1666 | static bool pci_ext_cfg_is_aliased(struct pci_dev *dev) | |
1667 | { | |
1668 | #ifdef CONFIG_PCI_QUIRKS | |
1669 | int pos; | |
1670 | u32 header, tmp; | |
1671 | ||
1672 | pci_read_config_dword(dev, PCI_VENDOR_ID, &header); | |
1673 | ||
1674 | for (pos = PCI_CFG_SPACE_SIZE; | |
1675 | pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) { | |
1676 | if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL | |
1677 | || header != tmp) | |
1678 | return false; | |
1679 | } | |
1680 | ||
1681 | return true; | |
1682 | #else | |
1683 | return false; | |
1684 | #endif | |
1685 | } | |
1686 | ||
0b950f0f | 1687 | /** |
2f0cd59c | 1688 | * pci_cfg_space_size_ext - Get the configuration space size of the PCI device |
0b950f0f SH |
1689 | * @dev: PCI device |
1690 | * | |
1691 | * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices | |
1692 | * have 4096 bytes. Even if the device is capable, that doesn't mean we can | |
1693 | * access it. Maybe we don't have a way to generate extended config space | |
1694 | * accesses, or the device is behind a reverse Express bridge. So we try | |
1695 | * reading the dword at 0x100 which must either be 0 or a valid extended | |
1696 | * capability header. | |
1697 | */ | |
1698 | static int pci_cfg_space_size_ext(struct pci_dev *dev) | |
1699 | { | |
1700 | u32 status; | |
1701 | int pos = PCI_CFG_SPACE_SIZE; | |
1702 | ||
1703 | if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL) | |
8e5a395a | 1704 | return PCI_CFG_SPACE_SIZE; |
78916b00 | 1705 | if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev)) |
8e5a395a | 1706 | return PCI_CFG_SPACE_SIZE; |
0b950f0f SH |
1707 | |
1708 | return PCI_CFG_SPACE_EXP_SIZE; | |
0b950f0f SH |
1709 | } |
1710 | ||
1711 | int pci_cfg_space_size(struct pci_dev *dev) | |
1712 | { | |
1713 | int pos; | |
1714 | u32 status; | |
1715 | u16 class; | |
1716 | ||
975bb8b4 | 1717 | #ifdef CONFIG_PCI_IOV |
06013b64 AW |
1718 | /* |
1719 | * Per the SR-IOV specification (rev 1.1, sec 3.5), VFs are required to | |
1720 | * implement a PCIe capability and therefore must implement extended | |
1721 | * config space. We can skip the NO_EXTCFG test below and the | |
1722 | * reachability/aliasing test in pci_cfg_space_size_ext() by virtue of | |
1723 | * the fact that the SR-IOV capability on the PF resides in extended | |
1724 | * config space and must be accessible and non-aliased to have enabled | |
1725 | * support for this VF. This is a micro performance optimization for | |
1726 | * systems supporting many VFs. | |
1727 | */ | |
1728 | if (dev->is_virtfn) | |
1729 | return PCI_CFG_SPACE_EXP_SIZE; | |
975bb8b4 KA |
1730 | #endif |
1731 | ||
17e8f0d4 GB |
1732 | if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) |
1733 | return PCI_CFG_SPACE_SIZE; | |
1734 | ||
0b950f0f SH |
1735 | class = dev->class >> 8; |
1736 | if (class == PCI_CLASS_BRIDGE_HOST) | |
1737 | return pci_cfg_space_size_ext(dev); | |
1738 | ||
8e5a395a BH |
1739 | if (pci_is_pcie(dev)) |
1740 | return pci_cfg_space_size_ext(dev); | |
0b950f0f | 1741 | |
8e5a395a BH |
1742 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); |
1743 | if (!pos) | |
1744 | return PCI_CFG_SPACE_SIZE; | |
0b950f0f | 1745 | |
8e5a395a BH |
1746 | pci_read_config_dword(dev, pos + PCI_X_STATUS, &status); |
1747 | if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)) | |
1748 | return pci_cfg_space_size_ext(dev); | |
0b950f0f | 1749 | |
0b950f0f SH |
1750 | return PCI_CFG_SPACE_SIZE; |
1751 | } | |
1752 | ||
cf0921be KA |
1753 | static u32 pci_class(struct pci_dev *dev) |
1754 | { | |
1755 | u32 class; | |
1756 | ||
1757 | #ifdef CONFIG_PCI_IOV | |
1758 | if (dev->is_virtfn) | |
1759 | return dev->physfn->sriov->class; | |
1760 | #endif | |
1761 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); | |
1762 | return class; | |
1763 | } | |
1764 | ||
1765 | static void pci_subsystem_ids(struct pci_dev *dev, u16 *vendor, u16 *device) | |
1766 | { | |
1767 | #ifdef CONFIG_PCI_IOV | |
1768 | if (dev->is_virtfn) { | |
1769 | *vendor = dev->physfn->sriov->subsystem_vendor; | |
1770 | *device = dev->physfn->sriov->subsystem_device; | |
1771 | return; | |
1772 | } | |
1773 | #endif | |
1774 | pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, vendor); | |
1775 | pci_read_config_word(dev, PCI_SUBSYSTEM_ID, device); | |
1776 | } | |
1777 | ||
1778 | static u8 pci_hdr_type(struct pci_dev *dev) | |
1779 | { | |
1780 | u8 hdr_type; | |
1781 | ||
1782 | #ifdef CONFIG_PCI_IOV | |
1783 | if (dev->is_virtfn) | |
1784 | return dev->physfn->sriov->hdr_type; | |
1785 | #endif | |
1786 | pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type); | |
1787 | return hdr_type; | |
1788 | } | |
1789 | ||
01abc2aa | 1790 | #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) |
76e6a1d6 | 1791 | |
99b3c58f | 1792 | /** |
3e466e2d | 1793 | * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability |
99b3c58f PG |
1794 | * @dev: PCI device |
1795 | * | |
1796 | * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this | |
1797 | * at enumeration-time to avoid modifying PCI_COMMAND at run-time. | |
1798 | */ | |
1799 | static int pci_intx_mask_broken(struct pci_dev *dev) | |
1800 | { | |
1801 | u16 orig, toggle, new; | |
1802 | ||
1803 | pci_read_config_word(dev, PCI_COMMAND, &orig); | |
1804 | toggle = orig ^ PCI_COMMAND_INTX_DISABLE; | |
1805 | pci_write_config_word(dev, PCI_COMMAND, toggle); | |
1806 | pci_read_config_word(dev, PCI_COMMAND, &new); | |
1807 | ||
1808 | pci_write_config_word(dev, PCI_COMMAND, orig); | |
1809 | ||
1810 | /* | |
1811 | * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI | |
1812 | * r2.3, so strictly speaking, a device is not *broken* if it's not | |
1813 | * writable. But we'll live with the misnomer for now. | |
1814 | */ | |
1815 | if (new != toggle) | |
1816 | return 1; | |
1817 | return 0; | |
1818 | } | |
1819 | ||
11eb0e0e SK |
1820 | static void early_dump_pci_device(struct pci_dev *pdev) |
1821 | { | |
1822 | u32 value[256 / 4]; | |
1823 | int i; | |
1824 | ||
1825 | pci_info(pdev, "config space:\n"); | |
1826 | ||
1827 | for (i = 0; i < 256; i += 4) | |
1828 | pci_read_config_dword(pdev, i, &value[i / 4]); | |
1829 | ||
1830 | print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1, | |
1831 | value, 256, false); | |
1832 | } | |
1833 | ||
1da177e4 | 1834 | /** |
3e466e2d | 1835 | * pci_setup_device - Fill in class and map information of a device |
1da177e4 LT |
1836 | * @dev: the device structure to fill |
1837 | * | |
f7625980 | 1838 | * Initialize the device structure with information about the device's |
3e466e2d | 1839 | * vendor,class,memory and IO-space addresses, IRQ lines etc. |
1da177e4 | 1840 | * Called at initialisation of the PCI subsystem and by CardBus services. |
480b93b7 YZ |
1841 | * Returns 0 on success and negative if unknown type of device (not normal, |
1842 | * bridge or CardBus). | |
1da177e4 | 1843 | */ |
480b93b7 | 1844 | int pci_setup_device(struct pci_dev *dev) |
1da177e4 LT |
1845 | { |
1846 | u32 class; | |
b84106b4 | 1847 | u16 cmd; |
480b93b7 | 1848 | u8 hdr_type; |
bc577d2b | 1849 | int pos = 0; |
5bfa14ed BH |
1850 | struct pci_bus_region region; |
1851 | struct resource *res; | |
480b93b7 | 1852 | |
cf0921be | 1853 | hdr_type = pci_hdr_type(dev); |
480b93b7 YZ |
1854 | |
1855 | dev->sysdata = dev->bus->sysdata; | |
1856 | dev->dev.parent = dev->bus->bridge; | |
1857 | dev->dev.bus = &pci_bus_type; | |
1858 | dev->hdr_type = hdr_type & 0x7f; | |
1859 | dev->multifunction = !!(hdr_type & 0x80); | |
480b93b7 YZ |
1860 | dev->error_state = pci_channel_io_normal; |
1861 | set_pcie_port_type(dev); | |
1862 | ||
375553a9 SD |
1863 | pci_set_of_node(dev); |
1864 | pci_set_acpi_fwnode(dev); | |
1865 | ||
017ffe64 | 1866 | pci_dev_assign_slot(dev); |
3e466e2d BH |
1867 | |
1868 | /* | |
1869 | * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) | |
1870 | * set this higher, assuming the system even supports it. | |
1871 | */ | |
480b93b7 | 1872 | dev->dma_mask = 0xffffffff; |
1da177e4 | 1873 | |
eebfcfb5 GKH |
1874 | dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), |
1875 | dev->bus->number, PCI_SLOT(dev->devfn), | |
1876 | PCI_FUNC(dev->devfn)); | |
1da177e4 | 1877 | |
cf0921be KA |
1878 | class = pci_class(dev); |
1879 | ||
b8a3a521 | 1880 | dev->revision = class & 0xff; |
2dd8ba92 | 1881 | dev->class = class >> 8; /* upper 3 bytes */ |
1da177e4 | 1882 | |
11eb0e0e SK |
1883 | if (pci_early_dump) |
1884 | early_dump_pci_device(dev); | |
1885 | ||
3e466e2d | 1886 | /* Need to have dev->class ready */ |
853346e4 YZ |
1887 | dev->cfg_size = pci_cfg_space_size(dev); |
1888 | ||
3e466e2d | 1889 | /* Need to have dev->cfg_size ready */ |
8531e283 LW |
1890 | set_pcie_thunderbolt(dev); |
1891 | ||
617654aa MW |
1892 | set_pcie_untrusted(dev); |
1893 | ||
1da177e4 | 1894 | /* "Unknown power state" */ |
3fe9d19f | 1895 | dev->current_state = PCI_UNKNOWN; |
1da177e4 LT |
1896 | |
1897 | /* Early fixups, before probing the BARs */ | |
1898 | pci_fixup_device(pci_fixup_early, dev); | |
3e466e2d | 1899 | |
c037b6c8 RJ |
1900 | pci_set_removable(dev); |
1901 | ||
b7360f60 TY |
1902 | pci_info(dev, "[%04x:%04x] type %02x class %#08x\n", |
1903 | dev->vendor, dev->device, dev->hdr_type, dev->class); | |
1904 | ||
3e466e2d | 1905 | /* Device class may be changed after fixup */ |
f79b1b14 | 1906 | class = dev->class >> 8; |
1da177e4 | 1907 | |
b6caa1d8 | 1908 | if (dev->non_compliant_bars && !dev->mmio_always_on) { |
b84106b4 BH |
1909 | pci_read_config_word(dev, PCI_COMMAND, &cmd); |
1910 | if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) { | |
7506dc79 | 1911 | pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n"); |
b84106b4 BH |
1912 | cmd &= ~PCI_COMMAND_IO; |
1913 | cmd &= ~PCI_COMMAND_MEMORY; | |
1914 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1915 | } | |
1916 | } | |
1917 | ||
99b3c58f PG |
1918 | dev->broken_intx_masking = pci_intx_mask_broken(dev); |
1919 | ||
1da177e4 LT |
1920 | switch (dev->hdr_type) { /* header type */ |
1921 | case PCI_HEADER_TYPE_NORMAL: /* standard header */ | |
1922 | if (class == PCI_CLASS_BRIDGE_PCI) | |
1923 | goto bad; | |
1924 | pci_read_irq(dev); | |
1925 | pci_read_bases(dev, 6, PCI_ROM_ADDRESS); | |
cf0921be KA |
1926 | |
1927 | pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device); | |
368c73d4 AC |
1928 | |
1929 | /* | |
075eb9e3 BH |
1930 | * Do the ugly legacy mode stuff here rather than broken chip |
1931 | * quirk code. Legacy mode ATA controllers have fixed | |
1932 | * addresses. These are not always echoed in BAR0-3, and | |
1933 | * BAR0-3 in a few cases contain junk! | |
368c73d4 AC |
1934 | */ |
1935 | if (class == PCI_CLASS_STORAGE_IDE) { | |
1936 | u8 progif; | |
1937 | pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); | |
1938 | if ((progif & 1) == 0) { | |
5bfa14ed BH |
1939 | region.start = 0x1F0; |
1940 | region.end = 0x1F7; | |
1941 | res = &dev->resource[0]; | |
1942 | res->flags = LEGACY_IO_RESOURCE; | |
fc279850 | 1943 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
7506dc79 | 1944 | pci_info(dev, "legacy IDE quirk: reg 0x10: %pR\n", |
075eb9e3 | 1945 | res); |
5bfa14ed BH |
1946 | region.start = 0x3F6; |
1947 | region.end = 0x3F6; | |
1948 | res = &dev->resource[1]; | |
1949 | res->flags = LEGACY_IO_RESOURCE; | |
fc279850 | 1950 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
7506dc79 | 1951 | pci_info(dev, "legacy IDE quirk: reg 0x14: %pR\n", |
075eb9e3 | 1952 | res); |
368c73d4 AC |
1953 | } |
1954 | if ((progif & 4) == 0) { | |
5bfa14ed BH |
1955 | region.start = 0x170; |
1956 | region.end = 0x177; | |
1957 | res = &dev->resource[2]; | |
1958 | res->flags = LEGACY_IO_RESOURCE; | |
fc279850 | 1959 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
7506dc79 | 1960 | pci_info(dev, "legacy IDE quirk: reg 0x18: %pR\n", |
075eb9e3 | 1961 | res); |
5bfa14ed BH |
1962 | region.start = 0x376; |
1963 | region.end = 0x376; | |
1964 | res = &dev->resource[3]; | |
1965 | res->flags = LEGACY_IO_RESOURCE; | |
fc279850 | 1966 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
7506dc79 | 1967 | pci_info(dev, "legacy IDE quirk: reg 0x1c: %pR\n", |
075eb9e3 | 1968 | res); |
368c73d4 AC |
1969 | } |
1970 | } | |
1da177e4 LT |
1971 | break; |
1972 | ||
1973 | case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ | |
3e466e2d BH |
1974 | /* |
1975 | * The PCI-to-PCI bridge spec requires that subtractive | |
1976 | * decoding (i.e. transparent) bridge must have programming | |
1977 | * interface code of 0x01. | |
1978 | */ | |
3efd273b | 1979 | pci_read_irq(dev); |
1da177e4 LT |
1980 | dev->transparent = ((dev->class & 0xff) == 1); |
1981 | pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); | |
51c48b31 | 1982 | pci_read_bridge_windows(dev); |
28760489 | 1983 | set_pcie_hotplug_bridge(dev); |
bc577d2b GB |
1984 | pos = pci_find_capability(dev, PCI_CAP_ID_SSVID); |
1985 | if (pos) { | |
1986 | pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor); | |
1987 | pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device); | |
1988 | } | |
1da177e4 LT |
1989 | break; |
1990 | ||
1991 | case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ | |
1992 | if (class != PCI_CLASS_BRIDGE_CARDBUS) | |
1993 | goto bad; | |
1994 | pci_read_irq(dev); | |
1995 | pci_read_bases(dev, 1, 0); | |
1996 | pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); | |
1997 | pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); | |
1998 | break; | |
1999 | ||
2000 | default: /* unknown header */ | |
7506dc79 | 2001 | pci_err(dev, "unknown header type %02x, ignoring device\n", |
227f0647 | 2002 | dev->hdr_type); |
375553a9 | 2003 | pci_release_of_node(dev); |
480b93b7 | 2004 | return -EIO; |
1da177e4 LT |
2005 | |
2006 | bad: | |
7506dc79 | 2007 | pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n", |
227f0647 | 2008 | dev->class, dev->hdr_type); |
2b4aed1d | 2009 | dev->class = PCI_CLASS_NOT_DEFINED << 8; |
1da177e4 LT |
2010 | } |
2011 | ||
2012 | /* We found a fine healthy device, go go go... */ | |
2013 | return 0; | |
2014 | } | |
2015 | ||
9dae3a97 BH |
2016 | static void pci_configure_mps(struct pci_dev *dev) |
2017 | { | |
2018 | struct pci_dev *bridge = pci_upstream_bridge(dev); | |
9f0e8935 | 2019 | int mps, mpss, p_mps, rc; |
9dae3a97 | 2020 | |
aa0ce96d | 2021 | if (!pci_is_pcie(dev)) |
9dae3a97 BH |
2022 | return; |
2023 | ||
3dbe97ef MS |
2024 | /* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */ |
2025 | if (dev->is_virtfn) | |
2026 | return; | |
2027 | ||
aa0ce96d AR |
2028 | /* |
2029 | * For Root Complex Integrated Endpoints, program the maximum | |
2030 | * supported value unless limited by the PCIE_BUS_PEER2PEER case. | |
2031 | */ | |
2032 | if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) { | |
2033 | if (pcie_bus_config == PCIE_BUS_PEER2PEER) | |
2034 | mps = 128; | |
2035 | else | |
2036 | mps = 128 << dev->pcie_mpss; | |
2037 | rc = pcie_set_mps(dev, mps); | |
2038 | if (rc) { | |
2039 | pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", | |
2040 | mps); | |
2041 | } | |
2042 | return; | |
2043 | } | |
2044 | ||
2045 | if (!bridge || !pci_is_pcie(bridge)) | |
2046 | return; | |
2047 | ||
9dae3a97 BH |
2048 | mps = pcie_get_mps(dev); |
2049 | p_mps = pcie_get_mps(bridge); | |
2050 | ||
2051 | if (mps == p_mps) | |
2052 | return; | |
2053 | ||
2054 | if (pcie_bus_config == PCIE_BUS_TUNE_OFF) { | |
7506dc79 | 2055 | pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", |
9dae3a97 BH |
2056 | mps, pci_name(bridge), p_mps); |
2057 | return; | |
2058 | } | |
27d868b5 KB |
2059 | |
2060 | /* | |
2061 | * Fancier MPS configuration is done later by | |
2062 | * pcie_bus_configure_settings() | |
2063 | */ | |
2064 | if (pcie_bus_config != PCIE_BUS_DEFAULT) | |
2065 | return; | |
2066 | ||
9f0e8935 MS |
2067 | mpss = 128 << dev->pcie_mpss; |
2068 | if (mpss < p_mps && pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) { | |
2069 | pcie_set_mps(bridge, mpss); | |
2070 | pci_info(dev, "Upstream bridge's Max Payload Size set to %d (was %d, max %d)\n", | |
2071 | mpss, p_mps, 128 << bridge->pcie_mpss); | |
2072 | p_mps = pcie_get_mps(bridge); | |
2073 | } | |
2074 | ||
27d868b5 KB |
2075 | rc = pcie_set_mps(dev, p_mps); |
2076 | if (rc) { | |
7506dc79 | 2077 | pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", |
27d868b5 KB |
2078 | p_mps); |
2079 | return; | |
2080 | } | |
2081 | ||
7506dc79 | 2082 | pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n", |
9f0e8935 | 2083 | p_mps, mps, mpss); |
9dae3a97 BH |
2084 | } |
2085 | ||
62ce94a7 | 2086 | int pci_configure_extended_tags(struct pci_dev *dev, void *ign) |
60db3a4d | 2087 | { |
62ce94a7 SK |
2088 | struct pci_host_bridge *host; |
2089 | u32 cap; | |
2090 | u16 ctl; | |
60db3a4d SK |
2091 | int ret; |
2092 | ||
2093 | if (!pci_is_pcie(dev)) | |
62ce94a7 | 2094 | return 0; |
60db3a4d | 2095 | |
62ce94a7 | 2096 | ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); |
60db3a4d | 2097 | if (ret) |
62ce94a7 SK |
2098 | return 0; |
2099 | ||
2100 | if (!(cap & PCI_EXP_DEVCAP_EXT_TAG)) | |
2101 | return 0; | |
60db3a4d | 2102 | |
62ce94a7 SK |
2103 | ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); |
2104 | if (ret) | |
2105 | return 0; | |
2106 | ||
2107 | host = pci_find_host_bridge(dev->bus); | |
2108 | if (!host) | |
2109 | return 0; | |
60db3a4d | 2110 | |
62ce94a7 SK |
2111 | /* |
2112 | * If some device in the hierarchy doesn't handle Extended Tags | |
2113 | * correctly, make sure they're disabled. | |
2114 | */ | |
2115 | if (host->no_ext_tags) { | |
2116 | if (ctl & PCI_EXP_DEVCTL_EXT_TAG) { | |
7506dc79 | 2117 | pci_info(dev, "disabling Extended Tags\n"); |
62ce94a7 SK |
2118 | pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, |
2119 | PCI_EXP_DEVCTL_EXT_TAG); | |
2120 | } | |
2121 | return 0; | |
2122 | } | |
2123 | ||
2124 | if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) { | |
7506dc79 | 2125 | pci_info(dev, "enabling Extended Tags\n"); |
60db3a4d SK |
2126 | pcie_capability_set_word(dev, PCI_EXP_DEVCTL, |
2127 | PCI_EXP_DEVCTL_EXT_TAG); | |
62ce94a7 SK |
2128 | } |
2129 | return 0; | |
60db3a4d SK |
2130 | } |
2131 | ||
a99b646a | 2132 | /** |
2133 | * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable | |
2134 | * @dev: PCI device to query | |
2135 | * | |
2136 | * Returns true if the device has enabled relaxed ordering attribute. | |
2137 | */ | |
2138 | bool pcie_relaxed_ordering_enabled(struct pci_dev *dev) | |
2139 | { | |
2140 | u16 v; | |
2141 | ||
2142 | pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v); | |
2143 | ||
2144 | return !!(v & PCI_EXP_DEVCTL_RELAX_EN); | |
2145 | } | |
2146 | EXPORT_SYMBOL(pcie_relaxed_ordering_enabled); | |
2147 | ||
2148 | static void pci_configure_relaxed_ordering(struct pci_dev *dev) | |
2149 | { | |
2150 | struct pci_dev *root; | |
2151 | ||
2152 | /* PCI_EXP_DEVICE_RELAX_EN is RsvdP in VFs */ | |
2153 | if (dev->is_virtfn) | |
2154 | return; | |
2155 | ||
2156 | if (!pcie_relaxed_ordering_enabled(dev)) | |
2157 | return; | |
2158 | ||
2159 | /* | |
2160 | * For now, we only deal with Relaxed Ordering issues with Root | |
2161 | * Ports. Peer-to-Peer DMA is another can of worms. | |
2162 | */ | |
6ae72bfa | 2163 | root = pcie_find_root_port(dev); |
a99b646a | 2164 | if (!root) |
2165 | return; | |
2166 | ||
2167 | if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) { | |
2168 | pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, | |
2169 | PCI_EXP_DEVCTL_RELAX_EN); | |
7506dc79 | 2170 | pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n"); |
a99b646a | 2171 | } |
2172 | } | |
2173 | ||
c46fd358 BH |
2174 | static void pci_configure_ltr(struct pci_dev *dev) |
2175 | { | |
2176 | #ifdef CONFIG_PCIEASPM | |
af8bb9f8 | 2177 | struct pci_host_bridge *host = pci_find_host_bridge(dev->bus); |
c46fd358 | 2178 | struct pci_dev *bridge; |
10ecc818 | 2179 | u32 cap, ctl; |
af8bb9f8 | 2180 | |
c46fd358 BH |
2181 | if (!pci_is_pcie(dev)) |
2182 | return; | |
2183 | ||
ecdf57b4 SB |
2184 | /* Read L1 PM substate capabilities */ |
2185 | dev->l1ss = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_L1SS); | |
2186 | ||
c46fd358 BH |
2187 | pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); |
2188 | if (!(cap & PCI_EXP_DEVCAP2_LTR)) | |
2189 | return; | |
2190 | ||
10ecc818 BH |
2191 | pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl); |
2192 | if (ctl & PCI_EXP_DEVCTL2_LTR_EN) { | |
2193 | if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) { | |
2194 | dev->ltr_path = 1; | |
2195 | return; | |
2196 | } | |
2197 | ||
c46fd358 BH |
2198 | bridge = pci_upstream_bridge(dev); |
2199 | if (bridge && bridge->ltr_path) | |
2200 | dev->ltr_path = 1; | |
10ecc818 BH |
2201 | |
2202 | return; | |
c46fd358 BH |
2203 | } |
2204 | ||
10ecc818 BH |
2205 | if (!host->native_ltr) |
2206 | return; | |
2207 | ||
2208 | /* | |
2209 | * Software must not enable LTR in an Endpoint unless the Root | |
2210 | * Complex and all intermediate Switches indicate support for LTR. | |
2211 | * PCIe r4.0, sec 6.18. | |
2212 | */ | |
2213 | if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT || | |
2214 | ((bridge = pci_upstream_bridge(dev)) && | |
2215 | bridge->ltr_path)) { | |
c46fd358 BH |
2216 | pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, |
2217 | PCI_EXP_DEVCTL2_LTR_EN); | |
10ecc818 BH |
2218 | dev->ltr_path = 1; |
2219 | } | |
c46fd358 BH |
2220 | #endif |
2221 | } | |
2222 | ||
7ce3f912 SK |
2223 | static void pci_configure_eetlp_prefix(struct pci_dev *dev) |
2224 | { | |
2225 | #ifdef CONFIG_PCI_PASID | |
2226 | struct pci_dev *bridge; | |
9d27e39d | 2227 | int pcie_type; |
7ce3f912 SK |
2228 | u32 cap; |
2229 | ||
2230 | if (!pci_is_pcie(dev)) | |
2231 | return; | |
2232 | ||
2233 | pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); | |
2234 | if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX)) | |
2235 | return; | |
2236 | ||
9d27e39d FK |
2237 | pcie_type = pci_pcie_type(dev); |
2238 | if (pcie_type == PCI_EXP_TYPE_ROOT_PORT || | |
2239 | pcie_type == PCI_EXP_TYPE_RC_END) | |
7ce3f912 SK |
2240 | dev->eetlp_prefix_path = 1; |
2241 | else { | |
2242 | bridge = pci_upstream_bridge(dev); | |
2243 | if (bridge && bridge->eetlp_prefix_path) | |
2244 | dev->eetlp_prefix_path = 1; | |
2245 | } | |
2246 | #endif | |
2247 | } | |
2248 | ||
b4f6dcb9 BKG |
2249 | static void pci_configure_serr(struct pci_dev *dev) |
2250 | { | |
2251 | u16 control; | |
2252 | ||
2253 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { | |
2254 | ||
2255 | /* | |
2256 | * A bridge will not forward ERR_ messages coming from an | |
2257 | * endpoint unless SERR# forwarding is enabled. | |
2258 | */ | |
2259 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &control); | |
2260 | if (!(control & PCI_BRIDGE_CTL_SERR)) { | |
2261 | control |= PCI_BRIDGE_CTL_SERR; | |
2262 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, control); | |
2263 | } | |
2264 | } | |
2265 | } | |
2266 | ||
6cd33649 BH |
2267 | static void pci_configure_device(struct pci_dev *dev) |
2268 | { | |
9dae3a97 | 2269 | pci_configure_mps(dev); |
62ce94a7 | 2270 | pci_configure_extended_tags(dev, NULL); |
a99b646a | 2271 | pci_configure_relaxed_ordering(dev); |
c46fd358 | 2272 | pci_configure_ltr(dev); |
7ce3f912 | 2273 | pci_configure_eetlp_prefix(dev); |
b4f6dcb9 | 2274 | pci_configure_serr(dev); |
9dae3a97 | 2275 | |
4a2dbedd | 2276 | pci_acpi_program_hp_params(dev); |
6cd33649 BH |
2277 | } |
2278 | ||
201de56e ZY |
2279 | static void pci_release_capabilities(struct pci_dev *dev) |
2280 | { | |
db89ccbe | 2281 | pci_aer_exit(dev); |
90655631 | 2282 | pci_rcec_exit(dev); |
d1b054da | 2283 | pci_iov_release(dev); |
f796841e | 2284 | pci_free_cap_save_buffers(dev); |
201de56e ZY |
2285 | } |
2286 | ||
1da177e4 | 2287 | /** |
3e466e2d BH |
2288 | * pci_release_dev - Free a PCI device structure when all users of it are |
2289 | * finished | |
1da177e4 LT |
2290 | * @dev: device that's been disconnected |
2291 | * | |
3e466e2d | 2292 | * Will be called only by the device core when all users of this PCI device are |
1da177e4 LT |
2293 | * done. |
2294 | */ | |
2295 | static void pci_release_dev(struct device *dev) | |
2296 | { | |
04480094 | 2297 | struct pci_dev *pci_dev; |
1da177e4 | 2298 | |
04480094 | 2299 | pci_dev = to_pci_dev(dev); |
201de56e | 2300 | pci_release_capabilities(pci_dev); |
98d9f30c | 2301 | pci_release_of_node(pci_dev); |
6ae32c53 | 2302 | pcibios_release_device(pci_dev); |
8b1fce04 | 2303 | pci_bus_put(pci_dev->bus); |
782a985d | 2304 | kfree(pci_dev->driver_override); |
c6635792 | 2305 | bitmap_free(pci_dev->dma_alias_mask); |
ea4aae05 | 2306 | dev_dbg(dev, "device released\n"); |
1da177e4 LT |
2307 | kfree(pci_dev); |
2308 | } | |
2309 | ||
3c6e6ae7 | 2310 | struct pci_dev *pci_alloc_dev(struct pci_bus *bus) |
65891215 ME |
2311 | { |
2312 | struct pci_dev *dev; | |
2313 | ||
2314 | dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); | |
2315 | if (!dev) | |
2316 | return NULL; | |
2317 | ||
65891215 | 2318 | INIT_LIST_HEAD(&dev->bus_list); |
88e7b167 | 2319 | dev->dev.type = &pci_dev_type; |
3c6e6ae7 | 2320 | dev->bus = pci_bus_get(bus); |
65891215 ME |
2321 | |
2322 | return dev; | |
2323 | } | |
3c6e6ae7 GZ |
2324 | EXPORT_SYMBOL(pci_alloc_dev); |
2325 | ||
62bc6a6f SK |
2326 | static bool pci_bus_crs_vendor_id(u32 l) |
2327 | { | |
2328 | return (l & 0xffff) == 0x0001; | |
2329 | } | |
2330 | ||
6a802ef0 SK |
2331 | static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l, |
2332 | int timeout) | |
1da177e4 | 2333 | { |
1da177e4 LT |
2334 | int delay = 1; |
2335 | ||
6a802ef0 SK |
2336 | if (!pci_bus_crs_vendor_id(*l)) |
2337 | return true; /* not a CRS completion */ | |
1da177e4 | 2338 | |
6a802ef0 SK |
2339 | if (!timeout) |
2340 | return false; /* CRS, but caller doesn't want to wait */ | |
1da177e4 | 2341 | |
89665a6a | 2342 | /* |
6a802ef0 SK |
2343 | * We got the reserved Vendor ID that indicates a completion with |
2344 | * Configuration Request Retry Status (CRS). Retry until we get a | |
2345 | * valid Vendor ID or we time out. | |
89665a6a | 2346 | */ |
62bc6a6f | 2347 | while (pci_bus_crs_vendor_id(*l)) { |
6a802ef0 | 2348 | if (delay > timeout) { |
e78e661f SK |
2349 | pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n", |
2350 | pci_domain_nr(bus), bus->number, | |
2351 | PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); | |
2352 | ||
efdc87da | 2353 | return false; |
1da177e4 | 2354 | } |
e78e661f SK |
2355 | if (delay >= 1000) |
2356 | pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n", | |
2357 | pci_domain_nr(bus), bus->number, | |
2358 | PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); | |
efdc87da | 2359 | |
1da177e4 LT |
2360 | msleep(delay); |
2361 | delay *= 2; | |
9f982756 | 2362 | |
efdc87da YL |
2363 | if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) |
2364 | return false; | |
1da177e4 LT |
2365 | } |
2366 | ||
e78e661f SK |
2367 | if (delay >= 1000) |
2368 | pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n", | |
2369 | pci_domain_nr(bus), bus->number, | |
2370 | PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); | |
2371 | ||
efdc87da YL |
2372 | return true; |
2373 | } | |
6a802ef0 | 2374 | |
aa667c64 JP |
2375 | bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, |
2376 | int timeout) | |
6a802ef0 SK |
2377 | { |
2378 | if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) | |
2379 | return false; | |
2380 | ||
3e466e2d | 2381 | /* Some broken boards return 0 or ~0 if a slot is empty: */ |
6a802ef0 SK |
2382 | if (*l == 0xffffffff || *l == 0x00000000 || |
2383 | *l == 0x0000ffff || *l == 0xffff0000) | |
2384 | return false; | |
2385 | ||
2386 | if (pci_bus_crs_vendor_id(*l)) | |
2387 | return pci_bus_wait_crs(bus, devfn, l, timeout); | |
2388 | ||
efdc87da YL |
2389 | return true; |
2390 | } | |
aa667c64 JP |
2391 | |
2392 | bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, | |
2393 | int timeout) | |
2394 | { | |
2395 | #ifdef CONFIG_PCI_QUIRKS | |
2396 | struct pci_dev *bridge = bus->self; | |
2397 | ||
2398 | /* | |
2399 | * Certain IDT switches have an issue where they improperly trigger | |
2400 | * ACS Source Validation errors on completions for config reads. | |
2401 | */ | |
2402 | if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT && | |
2403 | bridge->device == 0x80b5) | |
2404 | return pci_idt_bus_quirk(bus, devfn, l, timeout); | |
2405 | #endif | |
2406 | ||
2407 | return pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout); | |
2408 | } | |
efdc87da YL |
2409 | EXPORT_SYMBOL(pci_bus_read_dev_vendor_id); |
2410 | ||
2411 | /* | |
3e466e2d BH |
2412 | * Read the config data for a PCI device, sanity-check it, |
2413 | * and fill in the dev structure. | |
efdc87da YL |
2414 | */ |
2415 | static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) | |
2416 | { | |
2417 | struct pci_dev *dev; | |
2418 | u32 l; | |
2419 | ||
2420 | if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000)) | |
2421 | return NULL; | |
2422 | ||
8b1fce04 | 2423 | dev = pci_alloc_dev(bus); |
1da177e4 LT |
2424 | if (!dev) |
2425 | return NULL; | |
2426 | ||
1da177e4 | 2427 | dev->devfn = devfn; |
1da177e4 LT |
2428 | dev->vendor = l & 0xffff; |
2429 | dev->device = (l >> 16) & 0xffff; | |
cef354db | 2430 | |
480b93b7 | 2431 | if (pci_setup_device(dev)) { |
8b1fce04 | 2432 | pci_bus_put(dev->bus); |
1da177e4 LT |
2433 | kfree(dev); |
2434 | return NULL; | |
2435 | } | |
1da177e4 LT |
2436 | |
2437 | return dev; | |
2438 | } | |
2439 | ||
0fa635ae | 2440 | void pcie_report_downtraining(struct pci_dev *dev) |
2d1ce5ec AG |
2441 | { |
2442 | if (!pci_is_pcie(dev)) | |
2443 | return; | |
2444 | ||
2445 | /* Look from the device up to avoid downstream ports with no devices */ | |
2446 | if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ENDPOINT) && | |
2447 | (pci_pcie_type(dev) != PCI_EXP_TYPE_LEG_END) && | |
2448 | (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)) | |
2449 | return; | |
2450 | ||
2451 | /* Multi-function PCIe devices share the same link/status */ | |
2452 | if (PCI_FUNC(dev->devfn) != 0 || dev->is_virtfn) | |
2453 | return; | |
2454 | ||
2455 | /* Print link status only if the device is constrained by the fabric */ | |
2456 | __pcie_print_link_status(dev, false); | |
2457 | } | |
2458 | ||
201de56e ZY |
2459 | static void pci_init_capabilities(struct pci_dev *dev) |
2460 | { | |
9d8b738b | 2461 | pci_ea_init(dev); /* Enhanced Allocation */ |
cbc40d5c BH |
2462 | pci_msi_init(dev); /* Disable MSI */ |
2463 | pci_msix_init(dev); /* Disable MSI-X */ | |
201de56e | 2464 | |
63f4898a RW |
2465 | /* Buffers for saving PCIe and PCI-X capabilities */ |
2466 | pci_allocate_cap_save_buffers(dev); | |
2467 | ||
9d8b738b BH |
2468 | pci_pm_init(dev); /* Power Management */ |
2469 | pci_vpd_init(dev); /* Vital Product Data */ | |
2470 | pci_configure_ari(dev); /* Alternative Routing-ID Forwarding */ | |
2471 | pci_iov_init(dev); /* Single Root I/O Virtualization */ | |
2472 | pci_ats_init(dev); /* Address Translation Services */ | |
7e124c40 BH |
2473 | pci_pri_init(dev); /* Page Request Interface */ |
2474 | pci_pasid_init(dev); /* Process Address Space ID */ | |
52fbf5bd | 2475 | pci_acs_init(dev); /* Access Control Services */ |
9d8b738b BH |
2476 | pci_ptm_init(dev); /* Precision Time Measurement */ |
2477 | pci_aer_init(dev); /* Advanced Error Reporting */ | |
27005618 | 2478 | pci_dpc_init(dev); /* Downstream Port Containment */ |
90655631 | 2479 | pci_rcec_init(dev); /* Root Complex Event Collector */ |
5b0764ca | 2480 | |
2d1ce5ec | 2481 | pcie_report_downtraining(dev); |
e20afa06 | 2482 | pci_init_reset_methods(dev); |
201de56e ZY |
2483 | } |
2484 | ||
098259eb | 2485 | /* |
3e466e2d | 2486 | * This is the equivalent of pci_host_bridge_msi_domain() that acts on |
098259eb MZ |
2487 | * devices. Firmware interfaces that can select the MSI domain on a |
2488 | * per-device basis should be called from here. | |
2489 | */ | |
2490 | static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev) | |
2491 | { | |
2492 | struct irq_domain *d; | |
2493 | ||
2494 | /* | |
3e466e2d | 2495 | * If a domain has been set through the pcibios_add_device() |
098259eb MZ |
2496 | * callback, then this is the one (platform code knows best). |
2497 | */ | |
2498 | d = dev_get_msi_domain(&dev->dev); | |
2499 | if (d) | |
2500 | return d; | |
2501 | ||
54fa97ee MZ |
2502 | /* |
2503 | * Let's see if we have a firmware interface able to provide | |
2504 | * the domain. | |
2505 | */ | |
2506 | d = pci_msi_get_device_domain(dev); | |
2507 | if (d) | |
2508 | return d; | |
2509 | ||
098259eb MZ |
2510 | return NULL; |
2511 | } | |
2512 | ||
44aa0c65 MZ |
2513 | static void pci_set_msi_domain(struct pci_dev *dev) |
2514 | { | |
098259eb MZ |
2515 | struct irq_domain *d; |
2516 | ||
44aa0c65 | 2517 | /* |
098259eb MZ |
2518 | * If the platform or firmware interfaces cannot supply a |
2519 | * device-specific MSI domain, then inherit the default domain | |
2520 | * from the host bridge itself. | |
44aa0c65 | 2521 | */ |
098259eb MZ |
2522 | d = pci_dev_msi_domain(dev); |
2523 | if (!d) | |
2524 | d = dev_get_msi_domain(&dev->bus->dev); | |
2525 | ||
2526 | dev_set_msi_domain(&dev->dev, d); | |
44aa0c65 MZ |
2527 | } |
2528 | ||
96bde06a | 2529 | void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) |
1da177e4 | 2530 | { |
4f535093 YL |
2531 | int ret; |
2532 | ||
6cd33649 BH |
2533 | pci_configure_device(dev); |
2534 | ||
cdb9b9f7 PM |
2535 | device_initialize(&dev->dev); |
2536 | dev->dev.release = pci_release_dev; | |
1da177e4 | 2537 | |
7629d19a | 2538 | set_dev_node(&dev->dev, pcibus_to_node(bus)); |
cdb9b9f7 | 2539 | dev->dev.dma_mask = &dev->dma_mask; |
4d57cdfa | 2540 | dev->dev.dma_parms = &dev->dma_parms; |
cdb9b9f7 | 2541 | dev->dev.coherent_dma_mask = 0xffffffffull; |
1da177e4 | 2542 | |
b0da3498 | 2543 | dma_set_max_seg_size(&dev->dev, 65536); |
a6f44cf9 | 2544 | dma_set_seg_boundary(&dev->dev, 0xffffffff); |
4d57cdfa | 2545 | |
1da177e4 LT |
2546 | /* Fix up broken headers */ |
2547 | pci_fixup_device(pci_fixup_header, dev); | |
2548 | ||
2069ecfb YL |
2549 | pci_reassigndev_resource_alignment(dev); |
2550 | ||
4b77b0a2 RW |
2551 | dev->state_saved = false; |
2552 | ||
201de56e | 2553 | pci_init_capabilities(dev); |
eb9d0fe4 | 2554 | |
1da177e4 LT |
2555 | /* |
2556 | * Add the device to our list of discovered devices | |
2557 | * and the bus list for fixup functions, etc. | |
2558 | */ | |
d71374da | 2559 | down_write(&pci_bus_sem); |
1da177e4 | 2560 | list_add_tail(&dev->bus_list, &bus->devices); |
d71374da | 2561 | up_write(&pci_bus_sem); |
4f535093 | 2562 | |
4f535093 YL |
2563 | ret = pcibios_add_device(dev); |
2564 | WARN_ON(ret < 0); | |
2565 | ||
3e466e2d | 2566 | /* Set up MSI IRQ domain */ |
44aa0c65 MZ |
2567 | pci_set_msi_domain(dev); |
2568 | ||
4f535093 YL |
2569 | /* Notifier could use PCI capabilities */ |
2570 | dev->match_driver = false; | |
2571 | ret = device_add(&dev->dev); | |
2572 | WARN_ON(ret < 0); | |
cdb9b9f7 PM |
2573 | } |
2574 | ||
10874f5a | 2575 | struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn) |
cdb9b9f7 PM |
2576 | { |
2577 | struct pci_dev *dev; | |
2578 | ||
90bdb311 TP |
2579 | dev = pci_get_slot(bus, devfn); |
2580 | if (dev) { | |
2581 | pci_dev_put(dev); | |
2582 | return dev; | |
2583 | } | |
2584 | ||
cdb9b9f7 PM |
2585 | dev = pci_scan_device(bus, devfn); |
2586 | if (!dev) | |
2587 | return NULL; | |
2588 | ||
2589 | pci_device_add(dev, bus); | |
1da177e4 LT |
2590 | |
2591 | return dev; | |
2592 | } | |
b73e9687 | 2593 | EXPORT_SYMBOL(pci_scan_single_device); |
1da177e4 | 2594 | |
b1bd58e4 | 2595 | static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn) |
f07852d6 | 2596 | { |
b1bd58e4 YW |
2597 | int pos; |
2598 | u16 cap = 0; | |
2599 | unsigned next_fn; | |
4fb88c1a | 2600 | |
b1bd58e4 YW |
2601 | if (pci_ari_enabled(bus)) { |
2602 | if (!dev) | |
2603 | return 0; | |
2604 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI); | |
2605 | if (!pos) | |
2606 | return 0; | |
4fb88c1a | 2607 | |
b1bd58e4 YW |
2608 | pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap); |
2609 | next_fn = PCI_ARI_CAP_NFN(cap); | |
2610 | if (next_fn <= fn) | |
2611 | return 0; /* protect against malformed list */ | |
f07852d6 | 2612 | |
b1bd58e4 YW |
2613 | return next_fn; |
2614 | } | |
2615 | ||
2616 | /* dev may be NULL for non-contiguous multifunction devices */ | |
2617 | if (!dev || dev->multifunction) | |
2618 | return (fn + 1) % 8; | |
f07852d6 | 2619 | |
f07852d6 MW |
2620 | return 0; |
2621 | } | |
2622 | ||
2623 | static int only_one_child(struct pci_bus *bus) | |
2624 | { | |
d57f0b8c | 2625 | struct pci_dev *bridge = bus->self; |
284f5f9d | 2626 | |
d57f0b8c BH |
2627 | /* |
2628 | * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so | |
2629 | * we scan for all possible devices, not just Device 0. | |
2630 | */ | |
2631 | if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS)) | |
f07852d6 | 2632 | return 0; |
5bbe029f BH |
2633 | |
2634 | /* | |
d57f0b8c BH |
2635 | * A PCIe Downstream Port normally leads to a Link with only Device |
2636 | * 0 on it (PCIe spec r3.1, sec 7.3.1). As an optimization, scan | |
2637 | * only for Device 0 in that situation. | |
5bbe029f | 2638 | */ |
ca784104 | 2639 | if (bridge && pci_is_pcie(bridge) && pcie_downstream_port(bridge)) |
f07852d6 | 2640 | return 1; |
d57f0b8c | 2641 | |
f07852d6 MW |
2642 | return 0; |
2643 | } | |
2644 | ||
1da177e4 | 2645 | /** |
3e466e2d | 2646 | * pci_scan_slot - Scan a PCI slot on a bus for devices |
1da177e4 | 2647 | * @bus: PCI bus to scan |
3e466e2d | 2648 | * @devfn: slot number to scan (must have zero function) |
1da177e4 LT |
2649 | * |
2650 | * Scan a PCI slot on the specified PCI bus for devices, adding | |
2651 | * discovered devices to the @bus->devices list. New devices | |
8a1bc901 | 2652 | * will not have is_added set. |
1b69dfc6 TP |
2653 | * |
2654 | * Returns the number of new devices found. | |
1da177e4 | 2655 | */ |
96bde06a | 2656 | int pci_scan_slot(struct pci_bus *bus, int devfn) |
1da177e4 | 2657 | { |
f07852d6 | 2658 | unsigned fn, nr = 0; |
1b69dfc6 | 2659 | struct pci_dev *dev; |
f07852d6 MW |
2660 | |
2661 | if (only_one_child(bus) && (devfn > 0)) | |
2662 | return 0; /* Already scanned the entire slot */ | |
1da177e4 | 2663 | |
1b69dfc6 | 2664 | dev = pci_scan_single_device(bus, devfn); |
4fb88c1a MW |
2665 | if (!dev) |
2666 | return 0; | |
44bda4b7 | 2667 | if (!pci_dev_is_added(dev)) |
1b69dfc6 TP |
2668 | nr++; |
2669 | ||
b1bd58e4 | 2670 | for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) { |
f07852d6 MW |
2671 | dev = pci_scan_single_device(bus, devfn + fn); |
2672 | if (dev) { | |
44bda4b7 | 2673 | if (!pci_dev_is_added(dev)) |
f07852d6 MW |
2674 | nr++; |
2675 | dev->multifunction = 1; | |
1da177e4 LT |
2676 | } |
2677 | } | |
7d715a6c | 2678 | |
3e466e2d | 2679 | /* Only one slot has PCIe device */ |
149e1637 | 2680 | if (bus->self && nr) |
7d715a6c SL |
2681 | pcie_aspm_init_link_state(bus->self); |
2682 | ||
1da177e4 LT |
2683 | return nr; |
2684 | } | |
b7fe9434 | 2685 | EXPORT_SYMBOL(pci_scan_slot); |
1da177e4 | 2686 | |
b03e7495 JM |
2687 | static int pcie_find_smpss(struct pci_dev *dev, void *data) |
2688 | { | |
2689 | u8 *smpss = data; | |
2690 | ||
2691 | if (!pci_is_pcie(dev)) | |
2692 | return 0; | |
2693 | ||
d4aa68f6 YW |
2694 | /* |
2695 | * We don't have a way to change MPS settings on devices that have | |
2696 | * drivers attached. A hot-added device might support only the minimum | |
2697 | * MPS setting (MPS=128). Therefore, if the fabric contains a bridge | |
2698 | * where devices may be hot-added, we limit the fabric MPS to 128 so | |
2699 | * hot-added devices will work correctly. | |
2700 | * | |
2701 | * However, if we hot-add a device to a slot directly below a Root | |
2702 | * Port, it's impossible for there to be other existing devices below | |
2703 | * the port. We don't limit the MPS in this case because we can | |
2704 | * reconfigure MPS on both the Root Port and the hot-added device, | |
2705 | * and there are no other devices involved. | |
2706 | * | |
2707 | * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA. | |
b03e7495 | 2708 | */ |
d4aa68f6 YW |
2709 | if (dev->is_hotplug_bridge && |
2710 | pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) | |
b03e7495 JM |
2711 | *smpss = 0; |
2712 | ||
2713 | if (*smpss > dev->pcie_mpss) | |
2714 | *smpss = dev->pcie_mpss; | |
2715 | ||
2716 | return 0; | |
2717 | } | |
2718 | ||
2719 | static void pcie_write_mps(struct pci_dev *dev, int mps) | |
2720 | { | |
62f392ea | 2721 | int rc; |
b03e7495 JM |
2722 | |
2723 | if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { | |
62f392ea | 2724 | mps = 128 << dev->pcie_mpss; |
b03e7495 | 2725 | |
62f87c0e YW |
2726 | if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT && |
2727 | dev->bus->self) | |
3e466e2d BH |
2728 | |
2729 | /* | |
2730 | * For "Performance", the assumption is made that | |
b03e7495 JM |
2731 | * downstream communication will never be larger than |
2732 | * the MRRS. So, the MPS only needs to be configured | |
2733 | * for the upstream communication. This being the case, | |
2734 | * walk from the top down and set the MPS of the child | |
2735 | * to that of the parent bus. | |
62f392ea JM |
2736 | * |
2737 | * Configure the device MPS with the smaller of the | |
2738 | * device MPSS or the bridge MPS (which is assumed to be | |
2739 | * properly configured at this point to the largest | |
2740 | * allowable MPS based on its parent bus). | |
b03e7495 | 2741 | */ |
62f392ea | 2742 | mps = min(mps, pcie_get_mps(dev->bus->self)); |
b03e7495 JM |
2743 | } |
2744 | ||
2745 | rc = pcie_set_mps(dev, mps); | |
2746 | if (rc) | |
7506dc79 | 2747 | pci_err(dev, "Failed attempting to set the MPS\n"); |
b03e7495 JM |
2748 | } |
2749 | ||
62f392ea | 2750 | static void pcie_write_mrrs(struct pci_dev *dev) |
b03e7495 | 2751 | { |
62f392ea | 2752 | int rc, mrrs; |
b03e7495 | 2753 | |
3e466e2d BH |
2754 | /* |
2755 | * In the "safe" case, do not configure the MRRS. There appear to be | |
ed2888e9 JM |
2756 | * issues with setting MRRS to 0 on a number of devices. |
2757 | */ | |
ed2888e9 JM |
2758 | if (pcie_bus_config != PCIE_BUS_PERFORMANCE) |
2759 | return; | |
2760 | ||
3e466e2d BH |
2761 | /* |
2762 | * For max performance, the MRRS must be set to the largest supported | |
ed2888e9 | 2763 | * value. However, it cannot be configured larger than the MPS the |
62f392ea | 2764 | * device or the bus can support. This should already be properly |
3e466e2d | 2765 | * configured by a prior call to pcie_write_mps(). |
ed2888e9 | 2766 | */ |
62f392ea | 2767 | mrrs = pcie_get_mps(dev); |
b03e7495 | 2768 | |
3e466e2d BH |
2769 | /* |
2770 | * MRRS is a R/W register. Invalid values can be written, but a | |
ed2888e9 | 2771 | * subsequent read will verify if the value is acceptable or not. |
b03e7495 JM |
2772 | * If the MRRS value provided is not acceptable (e.g., too large), |
2773 | * shrink the value until it is acceptable to the HW. | |
f7625980 | 2774 | */ |
b03e7495 JM |
2775 | while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) { |
2776 | rc = pcie_set_readrq(dev, mrrs); | |
62f392ea JM |
2777 | if (!rc) |
2778 | break; | |
b03e7495 | 2779 | |
7506dc79 | 2780 | pci_warn(dev, "Failed attempting to set the MRRS\n"); |
b03e7495 JM |
2781 | mrrs /= 2; |
2782 | } | |
62f392ea JM |
2783 | |
2784 | if (mrrs < 128) | |
7506dc79 | 2785 | pci_err(dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n"); |
b03e7495 JM |
2786 | } |
2787 | ||
2788 | static int pcie_bus_configure_set(struct pci_dev *dev, void *data) | |
2789 | { | |
a513a99a | 2790 | int mps, orig_mps; |
b03e7495 JM |
2791 | |
2792 | if (!pci_is_pcie(dev)) | |
2793 | return 0; | |
2794 | ||
27d868b5 KB |
2795 | if (pcie_bus_config == PCIE_BUS_TUNE_OFF || |
2796 | pcie_bus_config == PCIE_BUS_DEFAULT) | |
5895af79 | 2797 | return 0; |
5895af79 | 2798 | |
a513a99a JM |
2799 | mps = 128 << *(u8 *)data; |
2800 | orig_mps = pcie_get_mps(dev); | |
b03e7495 JM |
2801 | |
2802 | pcie_write_mps(dev, mps); | |
62f392ea | 2803 | pcie_write_mrrs(dev); |
b03e7495 | 2804 | |
7506dc79 | 2805 | pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n", |
227f0647 | 2806 | pcie_get_mps(dev), 128 << dev->pcie_mpss, |
a513a99a | 2807 | orig_mps, pcie_get_readrq(dev)); |
b03e7495 JM |
2808 | |
2809 | return 0; | |
2810 | } | |
2811 | ||
3e466e2d BH |
2812 | /* |
2813 | * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down, | |
b03e7495 JM |
2814 | * parents then children fashion. If this changes, then this code will not |
2815 | * work as designed. | |
2816 | */ | |
a58674ff | 2817 | void pcie_bus_configure_settings(struct pci_bus *bus) |
b03e7495 | 2818 | { |
1e358f94 | 2819 | u8 smpss = 0; |
b03e7495 | 2820 | |
a58674ff | 2821 | if (!bus->self) |
b03e7495 JM |
2822 | return; |
2823 | ||
b03e7495 | 2824 | if (!pci_is_pcie(bus->self)) |
5f39e670 JM |
2825 | return; |
2826 | ||
3e466e2d BH |
2827 | /* |
2828 | * FIXME - Peer to peer DMA is possible, though the endpoint would need | |
3315472c | 2829 | * to be aware of the MPS of the destination. To work around this, |
5f39e670 JM |
2830 | * simply force the MPS of the entire system to the smallest possible. |
2831 | */ | |
2832 | if (pcie_bus_config == PCIE_BUS_PEER2PEER) | |
2833 | smpss = 0; | |
2834 | ||
b03e7495 | 2835 | if (pcie_bus_config == PCIE_BUS_SAFE) { |
a58674ff | 2836 | smpss = bus->self->pcie_mpss; |
5f39e670 | 2837 | |
b03e7495 JM |
2838 | pcie_find_smpss(bus->self, &smpss); |
2839 | pci_walk_bus(bus, pcie_find_smpss, &smpss); | |
2840 | } | |
2841 | ||
2842 | pcie_bus_configure_set(bus->self, &smpss); | |
2843 | pci_walk_bus(bus, pcie_bus_configure_set, &smpss); | |
2844 | } | |
debc3b77 | 2845 | EXPORT_SYMBOL_GPL(pcie_bus_configure_settings); |
b03e7495 | 2846 | |
bccf90d6 PD |
2847 | /* |
2848 | * Called after each bus is probed, but before its children are examined. This | |
2849 | * is marked as __weak because multiple architectures define it. | |
2850 | */ | |
2851 | void __weak pcibios_fixup_bus(struct pci_bus *bus) | |
2852 | { | |
2853 | /* nothing to do, expected to be removed in the future */ | |
2854 | } | |
2855 | ||
1c02ea81 MW |
2856 | /** |
2857 | * pci_scan_child_bus_extend() - Scan devices below a bus | |
2858 | * @bus: Bus to scan for devices | |
2859 | * @available_buses: Total number of buses available (%0 does not try to | |
2860 | * extend beyond the minimal) | |
2861 | * | |
2862 | * Scans devices below @bus including subordinate buses. Returns new | |
2863 | * subordinate number including all the found devices. Passing | |
2864 | * @available_buses causes the remaining bus space to be distributed | |
2865 | * equally between hotplug-capable bridges to allow future extension of the | |
2866 | * hierarchy. | |
2867 | */ | |
2868 | static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus, | |
2869 | unsigned int available_buses) | |
1da177e4 | 2870 | { |
1c02ea81 MW |
2871 | unsigned int used_buses, normal_bridges = 0, hotplug_bridges = 0; |
2872 | unsigned int start = bus->busn_res.start; | |
690f4304 | 2873 | unsigned int devfn, fn, cmax, max = start; |
1da177e4 | 2874 | struct pci_dev *dev; |
690f4304 | 2875 | int nr_devs; |
1da177e4 | 2876 | |
0207c356 | 2877 | dev_dbg(&bus->dev, "scanning bus\n"); |
1da177e4 LT |
2878 | |
2879 | /* Go find them, Rover! */ | |
690f4304 JK |
2880 | for (devfn = 0; devfn < 256; devfn += 8) { |
2881 | nr_devs = pci_scan_slot(bus, devfn); | |
2882 | ||
2883 | /* | |
2884 | * The Jailhouse hypervisor may pass individual functions of a | |
2885 | * multi-function device to a guest without passing function 0. | |
2886 | * Look for them as well. | |
2887 | */ | |
2888 | if (jailhouse_paravirt() && nr_devs == 0) { | |
2889 | for (fn = 1; fn < 8; fn++) { | |
2890 | dev = pci_scan_single_device(bus, devfn + fn); | |
2891 | if (dev) | |
2892 | dev->multifunction = 1; | |
2893 | } | |
2894 | } | |
2895 | } | |
1da177e4 | 2896 | |
3e466e2d | 2897 | /* Reserve buses for SR-IOV capability */ |
1c02ea81 MW |
2898 | used_buses = pci_iov_bus_range(bus); |
2899 | max += used_buses; | |
a28724b0 | 2900 | |
1da177e4 LT |
2901 | /* |
2902 | * After performing arch-dependent fixup of the bus, look behind | |
2903 | * all PCI-to-PCI bridges on this bus. | |
2904 | */ | |
74710ded | 2905 | if (!bus->is_added) { |
0207c356 | 2906 | dev_dbg(&bus->dev, "fixups for bus\n"); |
74710ded | 2907 | pcibios_fixup_bus(bus); |
981cf9ea | 2908 | bus->is_added = 1; |
74710ded AC |
2909 | } |
2910 | ||
1c02ea81 MW |
2911 | /* |
2912 | * Calculate how many hotplug bridges and normal bridges there | |
2913 | * are on this bus. We will distribute the additional available | |
2914 | * buses between hotplug bridges. | |
2915 | */ | |
2916 | for_each_pci_bridge(dev, bus) { | |
2917 | if (dev->is_hotplug_bridge) | |
2918 | hotplug_bridges++; | |
2919 | else | |
2920 | normal_bridges++; | |
2921 | } | |
2922 | ||
4147c2fd MW |
2923 | /* |
2924 | * Scan bridges that are already configured. We don't touch them | |
2925 | * unless they are misconfigured (which will be done in the second | |
2926 | * scan below). | |
2927 | */ | |
1c02ea81 MW |
2928 | for_each_pci_bridge(dev, bus) { |
2929 | cmax = max; | |
2930 | max = pci_scan_bridge_extend(bus, dev, max, 0, 0); | |
3374c545 MW |
2931 | |
2932 | /* | |
2933 | * Reserve one bus for each bridge now to avoid extending | |
2934 | * hotplug bridges too much during the second scan below. | |
2935 | */ | |
2936 | used_buses++; | |
2937 | if (cmax - max > 1) | |
2938 | used_buses += cmax - max - 1; | |
1c02ea81 | 2939 | } |
4147c2fd MW |
2940 | |
2941 | /* Scan bridges that need to be reconfigured */ | |
1c02ea81 MW |
2942 | for_each_pci_bridge(dev, bus) { |
2943 | unsigned int buses = 0; | |
2944 | ||
2945 | if (!hotplug_bridges && normal_bridges == 1) { | |
3e466e2d | 2946 | |
1c02ea81 MW |
2947 | /* |
2948 | * There is only one bridge on the bus (upstream | |
2949 | * port) so it gets all available buses which it | |
2950 | * can then distribute to the possible hotplug | |
2951 | * bridges below. | |
2952 | */ | |
2953 | buses = available_buses; | |
2954 | } else if (dev->is_hotplug_bridge) { | |
3e466e2d | 2955 | |
1c02ea81 MW |
2956 | /* |
2957 | * Distribute the extra buses between hotplug | |
2958 | * bridges if any. | |
2959 | */ | |
2960 | buses = available_buses / hotplug_bridges; | |
3374c545 | 2961 | buses = min(buses, available_buses - used_buses + 1); |
1c02ea81 MW |
2962 | } |
2963 | ||
2964 | cmax = max; | |
2965 | max = pci_scan_bridge_extend(bus, dev, cmax, buses, 1); | |
3374c545 MW |
2966 | /* One bus is already accounted so don't add it again */ |
2967 | if (max - cmax > 1) | |
2968 | used_buses += max - cmax - 1; | |
1c02ea81 | 2969 | } |
1da177e4 | 2970 | |
e16b4660 KB |
2971 | /* |
2972 | * Make sure a hotplug bridge has at least the minimum requested | |
1c02ea81 MW |
2973 | * number of buses but allow it to grow up to the maximum available |
2974 | * bus number of there is room. | |
e16b4660 | 2975 | */ |
1c02ea81 MW |
2976 | if (bus->self && bus->self->is_hotplug_bridge) { |
2977 | used_buses = max_t(unsigned int, available_buses, | |
2978 | pci_hotplug_bus_size - 1); | |
2979 | if (max - start < used_buses) { | |
2980 | max = start + used_buses; | |
2981 | ||
2982 | /* Do not allocate more buses than we have room left */ | |
2983 | if (max > bus->busn_res.end) | |
2984 | max = bus->busn_res.end; | |
2985 | ||
2986 | dev_dbg(&bus->dev, "%pR extended by %#02x\n", | |
2987 | &bus->busn_res, max - start); | |
2988 | } | |
e16b4660 KB |
2989 | } |
2990 | ||
1da177e4 LT |
2991 | /* |
2992 | * We've scanned the bus and so we know all about what's on | |
2993 | * the other side of any bridges that may be on this bus plus | |
2994 | * any devices. | |
2995 | * | |
2996 | * Return how far we've got finding sub-buses. | |
2997 | */ | |
0207c356 | 2998 | dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max); |
1da177e4 LT |
2999 | return max; |
3000 | } | |
1c02ea81 MW |
3001 | |
3002 | /** | |
3003 | * pci_scan_child_bus() - Scan devices below a bus | |
3004 | * @bus: Bus to scan for devices | |
3005 | * | |
3006 | * Scans devices below @bus including subordinate buses. Returns new | |
3007 | * subordinate number including all the found devices. | |
3008 | */ | |
3009 | unsigned int pci_scan_child_bus(struct pci_bus *bus) | |
3010 | { | |
3011 | return pci_scan_child_bus_extend(bus, 0); | |
3012 | } | |
b7fe9434 | 3013 | EXPORT_SYMBOL_GPL(pci_scan_child_bus); |
1da177e4 | 3014 | |
6c0cc950 | 3015 | /** |
3e466e2d BH |
3016 | * pcibios_root_bridge_prepare - Platform-specific host bridge setup |
3017 | * @bridge: Host bridge to set up | |
6c0cc950 RW |
3018 | * |
3019 | * Default empty implementation. Replace with an architecture-specific setup | |
3020 | * routine, if necessary. | |
3021 | */ | |
3022 | int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) | |
3023 | { | |
3024 | return 0; | |
3025 | } | |
3026 | ||
10a95747 JL |
3027 | void __weak pcibios_add_bus(struct pci_bus *bus) |
3028 | { | |
3029 | } | |
3030 | ||
3031 | void __weak pcibios_remove_bus(struct pci_bus *bus) | |
3032 | { | |
3033 | } | |
3034 | ||
9ee8a1c4 LP |
3035 | struct pci_bus *pci_create_root_bus(struct device *parent, int bus, |
3036 | struct pci_ops *ops, void *sysdata, struct list_head *resources) | |
1da177e4 | 3037 | { |
0efd5aab | 3038 | int error; |
5a21d70d | 3039 | struct pci_host_bridge *bridge; |
1da177e4 | 3040 | |
59094065 | 3041 | bridge = pci_alloc_host_bridge(0); |
7b543663 | 3042 | if (!bridge) |
37d6a0a6 | 3043 | return NULL; |
7b543663 YL |
3044 | |
3045 | bridge->dev.parent = parent; | |
a9d9f527 | 3046 | |
37d6a0a6 AB |
3047 | list_splice_init(resources, &bridge->windows); |
3048 | bridge->sysdata = sysdata; | |
3049 | bridge->busnr = bus; | |
3050 | bridge->ops = ops; | |
a9d9f527 | 3051 | |
37d6a0a6 AB |
3052 | error = pci_register_host_bridge(bridge); |
3053 | if (error < 0) | |
3054 | goto err_out; | |
a5390aa6 | 3055 | |
37d6a0a6 | 3056 | return bridge->bus; |
1da177e4 | 3057 | |
1da177e4 | 3058 | err_out: |
9885440b | 3059 | put_device(&bridge->dev); |
1da177e4 LT |
3060 | return NULL; |
3061 | } | |
e6b29dea | 3062 | EXPORT_SYMBOL_GPL(pci_create_root_bus); |
cdb9b9f7 | 3063 | |
49b8e3f3 CP |
3064 | int pci_host_probe(struct pci_host_bridge *bridge) |
3065 | { | |
3066 | struct pci_bus *bus, *child; | |
3067 | int ret; | |
3068 | ||
3069 | ret = pci_scan_root_bus_bridge(bridge); | |
3070 | if (ret < 0) { | |
3071 | dev_err(bridge->dev.parent, "Scanning root bridge failed"); | |
3072 | return ret; | |
3073 | } | |
3074 | ||
3075 | bus = bridge->bus; | |
3076 | ||
3077 | /* | |
3078 | * We insert PCI resources into the iomem_resource and | |
3079 | * ioport_resource trees in either pci_bus_claim_resources() | |
3080 | * or pci_bus_assign_resources(). | |
3081 | */ | |
3082 | if (pci_has_flag(PCI_PROBE_ONLY)) { | |
3083 | pci_bus_claim_resources(bus); | |
3084 | } else { | |
3085 | pci_bus_size_bridges(bus); | |
3086 | pci_bus_assign_resources(bus); | |
3087 | ||
3088 | list_for_each_entry(child, &bus->children, node) | |
3089 | pcie_bus_configure_settings(child); | |
3090 | } | |
3091 | ||
3092 | pci_bus_add_devices(bus); | |
3093 | return 0; | |
3094 | } | |
3095 | EXPORT_SYMBOL_GPL(pci_host_probe); | |
3096 | ||
98a35831 YL |
3097 | int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max) |
3098 | { | |
3099 | struct resource *res = &b->busn_res; | |
3100 | struct resource *parent_res, *conflict; | |
3101 | ||
3102 | res->start = bus; | |
3103 | res->end = bus_max; | |
3104 | res->flags = IORESOURCE_BUS; | |
3105 | ||
3106 | if (!pci_is_root_bus(b)) | |
3107 | parent_res = &b->parent->busn_res; | |
3108 | else { | |
3109 | parent_res = get_pci_domain_busn_res(pci_domain_nr(b)); | |
3110 | res->flags |= IORESOURCE_PCI_FIXED; | |
3111 | } | |
3112 | ||
ced04d15 | 3113 | conflict = request_resource_conflict(parent_res, res); |
98a35831 YL |
3114 | |
3115 | if (conflict) | |
34c6b710 | 3116 | dev_info(&b->dev, |
98a35831 YL |
3117 | "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n", |
3118 | res, pci_is_root_bus(b) ? "domain " : "", | |
3119 | parent_res, conflict->name, conflict); | |
98a35831 YL |
3120 | |
3121 | return conflict == NULL; | |
3122 | } | |
3123 | ||
3124 | int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max) | |
3125 | { | |
3126 | struct resource *res = &b->busn_res; | |
3127 | struct resource old_res = *res; | |
3128 | resource_size_t size; | |
3129 | int ret; | |
3130 | ||
3131 | if (res->start > bus_max) | |
3132 | return -EINVAL; | |
3133 | ||
3134 | size = bus_max - res->start + 1; | |
3135 | ret = adjust_resource(res, res->start, size); | |
34c6b710 | 3136 | dev_info(&b->dev, "busn_res: %pR end %s updated to %02x\n", |
98a35831 YL |
3137 | &old_res, ret ? "can not be" : "is", bus_max); |
3138 | ||
3139 | if (!ret && !res->parent) | |
3140 | pci_bus_insert_busn_res(b, res->start, res->end); | |
3141 | ||
3142 | return ret; | |
3143 | } | |
3144 | ||
3145 | void pci_bus_release_busn_res(struct pci_bus *b) | |
3146 | { | |
3147 | struct resource *res = &b->busn_res; | |
3148 | int ret; | |
3149 | ||
3150 | if (!res->flags || !res->parent) | |
3151 | return; | |
3152 | ||
3153 | ret = release_resource(res); | |
34c6b710 | 3154 | dev_info(&b->dev, "busn_res: %pR %s released\n", |
98a35831 YL |
3155 | res, ret ? "can not be" : "is"); |
3156 | } | |
3157 | ||
1228c4b6 | 3158 | int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge) |
a2ebb827 | 3159 | { |
14d76b68 | 3160 | struct resource_entry *window; |
4d99f524 | 3161 | bool found = false; |
a2ebb827 | 3162 | struct pci_bus *b; |
1228c4b6 | 3163 | int max, bus, ret; |
4d99f524 | 3164 | |
1228c4b6 LP |
3165 | if (!bridge) |
3166 | return -EINVAL; | |
3167 | ||
3168 | resource_list_for_each_entry(window, &bridge->windows) | |
4d99f524 | 3169 | if (window->res->flags & IORESOURCE_BUS) { |
4f5c883d | 3170 | bridge->busnr = window->res->start; |
4d99f524 YL |
3171 | found = true; |
3172 | break; | |
3173 | } | |
a2ebb827 | 3174 | |
1228c4b6 LP |
3175 | ret = pci_register_host_bridge(bridge); |
3176 | if (ret < 0) | |
3177 | return ret; | |
3178 | ||
3179 | b = bridge->bus; | |
3180 | bus = bridge->busnr; | |
a2ebb827 | 3181 | |
4d99f524 YL |
3182 | if (!found) { |
3183 | dev_info(&b->dev, | |
3184 | "No busn resource found for root bus, will use [bus %02x-ff]\n", | |
3185 | bus); | |
3186 | pci_bus_insert_busn_res(b, bus, 255); | |
3187 | } | |
3188 | ||
3189 | max = pci_scan_child_bus(b); | |
3190 | ||
3191 | if (!found) | |
3192 | pci_bus_update_busn_res_end(b, max); | |
3193 | ||
1228c4b6 | 3194 | return 0; |
a2ebb827 | 3195 | } |
1228c4b6 | 3196 | EXPORT_SYMBOL(pci_scan_root_bus_bridge); |
d2a7926d LP |
3197 | |
3198 | struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, | |
3199 | struct pci_ops *ops, void *sysdata, struct list_head *resources) | |
3200 | { | |
14d76b68 | 3201 | struct resource_entry *window; |
4d99f524 | 3202 | bool found = false; |
a2ebb827 | 3203 | struct pci_bus *b; |
4d99f524 YL |
3204 | int max; |
3205 | ||
14d76b68 | 3206 | resource_list_for_each_entry(window, resources) |
4d99f524 YL |
3207 | if (window->res->flags & IORESOURCE_BUS) { |
3208 | found = true; | |
3209 | break; | |
3210 | } | |
a2ebb827 | 3211 | |
9ee8a1c4 | 3212 | b = pci_create_root_bus(parent, bus, ops, sysdata, resources); |
a2ebb827 BH |
3213 | if (!b) |
3214 | return NULL; | |
3215 | ||
4d99f524 YL |
3216 | if (!found) { |
3217 | dev_info(&b->dev, | |
3218 | "No busn resource found for root bus, will use [bus %02x-ff]\n", | |
3219 | bus); | |
3220 | pci_bus_insert_busn_res(b, bus, 255); | |
3221 | } | |
3222 | ||
3223 | max = pci_scan_child_bus(b); | |
3224 | ||
3225 | if (!found) | |
3226 | pci_bus_update_busn_res_end(b, max); | |
3227 | ||
a2ebb827 | 3228 | return b; |
d2a7926d | 3229 | } |
a2ebb827 BH |
3230 | EXPORT_SYMBOL(pci_scan_root_bus); |
3231 | ||
15856ad5 | 3232 | struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, |
de4b2f76 BH |
3233 | void *sysdata) |
3234 | { | |
3235 | LIST_HEAD(resources); | |
3236 | struct pci_bus *b; | |
3237 | ||
3238 | pci_add_resource(&resources, &ioport_resource); | |
3239 | pci_add_resource(&resources, &iomem_resource); | |
857c3b66 | 3240 | pci_add_resource(&resources, &busn_resource); |
de4b2f76 BH |
3241 | b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources); |
3242 | if (b) { | |
857c3b66 | 3243 | pci_scan_child_bus(b); |
de4b2f76 BH |
3244 | } else { |
3245 | pci_free_resource_list(&resources); | |
3246 | } | |
3247 | return b; | |
3248 | } | |
3249 | EXPORT_SYMBOL(pci_scan_bus); | |
3250 | ||
2f320521 | 3251 | /** |
3e466e2d | 3252 | * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices |
2f320521 YL |
3253 | * @bridge: PCI bridge for the bus to scan |
3254 | * | |
3255 | * Scan a PCI bus and child buses for new devices, add them, | |
3256 | * and enable them, resizing bridge mmio/io resource if necessary | |
3257 | * and possible. The caller must ensure the child devices are already | |
3258 | * removed for resizing to occur. | |
3259 | * | |
3260 | * Returns the max number of subordinate bus discovered. | |
3261 | */ | |
10874f5a | 3262 | unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge) |
2f320521 YL |
3263 | { |
3264 | unsigned int max; | |
3265 | struct pci_bus *bus = bridge->subordinate; | |
3266 | ||
3267 | max = pci_scan_child_bus(bus); | |
3268 | ||
3269 | pci_assign_unassigned_bridge_resources(bridge); | |
3270 | ||
3271 | pci_bus_add_devices(bus); | |
3272 | ||
3273 | return max; | |
3274 | } | |
3275 | ||
a5213a31 | 3276 | /** |
3e466e2d | 3277 | * pci_rescan_bus - Scan a PCI bus for devices |
a5213a31 YL |
3278 | * @bus: PCI bus to scan |
3279 | * | |
3e466e2d BH |
3280 | * Scan a PCI bus and child buses for new devices, add them, |
3281 | * and enable them. | |
a5213a31 YL |
3282 | * |
3283 | * Returns the max number of subordinate bus discovered. | |
3284 | */ | |
10874f5a | 3285 | unsigned int pci_rescan_bus(struct pci_bus *bus) |
a5213a31 YL |
3286 | { |
3287 | unsigned int max; | |
3288 | ||
3289 | max = pci_scan_child_bus(bus); | |
3290 | pci_assign_unassigned_bus_resources(bus); | |
3291 | pci_bus_add_devices(bus); | |
3292 | ||
3293 | return max; | |
3294 | } | |
3295 | EXPORT_SYMBOL_GPL(pci_rescan_bus); | |
3296 | ||
9d16947b RW |
3297 | /* |
3298 | * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal | |
3299 | * routines should always be executed under this mutex. | |
3300 | */ | |
3301 | static DEFINE_MUTEX(pci_rescan_remove_lock); | |
3302 | ||
3303 | void pci_lock_rescan_remove(void) | |
3304 | { | |
3305 | mutex_lock(&pci_rescan_remove_lock); | |
3306 | } | |
3307 | EXPORT_SYMBOL_GPL(pci_lock_rescan_remove); | |
3308 | ||
3309 | void pci_unlock_rescan_remove(void) | |
3310 | { | |
3311 | mutex_unlock(&pci_rescan_remove_lock); | |
3312 | } | |
3313 | EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove); | |
3314 | ||
3c78bc61 RD |
3315 | static int __init pci_sort_bf_cmp(const struct device *d_a, |
3316 | const struct device *d_b) | |
6b4b78fe | 3317 | { |
99178b03 GKH |
3318 | const struct pci_dev *a = to_pci_dev(d_a); |
3319 | const struct pci_dev *b = to_pci_dev(d_b); | |
3320 | ||
6b4b78fe MD |
3321 | if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1; |
3322 | else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1; | |
3323 | ||
3324 | if (a->bus->number < b->bus->number) return -1; | |
3325 | else if (a->bus->number > b->bus->number) return 1; | |
3326 | ||
3327 | if (a->devfn < b->devfn) return -1; | |
3328 | else if (a->devfn > b->devfn) return 1; | |
3329 | ||
3330 | return 0; | |
3331 | } | |
3332 | ||
5ff580c1 | 3333 | void __init pci_sort_breadthfirst(void) |
6b4b78fe | 3334 | { |
99178b03 | 3335 | bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp); |
6b4b78fe | 3336 | } |
95e3ba97 MW |
3337 | |
3338 | int pci_hp_add_bridge(struct pci_dev *dev) | |
3339 | { | |
3340 | struct pci_bus *parent = dev->bus; | |
4147c2fd | 3341 | int busnr, start = parent->busn_res.start; |
1c02ea81 | 3342 | unsigned int available_buses = 0; |
95e3ba97 MW |
3343 | int end = parent->busn_res.end; |
3344 | ||
3345 | for (busnr = start; busnr <= end; busnr++) { | |
3346 | if (!pci_find_bus(pci_domain_nr(parent), busnr)) | |
3347 | break; | |
3348 | } | |
3349 | if (busnr-- > end) { | |
7506dc79 | 3350 | pci_err(dev, "No bus number available for hot-added bridge\n"); |
95e3ba97 MW |
3351 | return -1; |
3352 | } | |
4147c2fd MW |
3353 | |
3354 | /* Scan bridges that are already configured */ | |
3355 | busnr = pci_scan_bridge(parent, dev, busnr, 0); | |
3356 | ||
1c02ea81 MW |
3357 | /* |
3358 | * Distribute the available bus numbers between hotplug-capable | |
3359 | * bridges to make extending the chain later possible. | |
3360 | */ | |
3361 | available_buses = end - busnr; | |
3362 | ||
4147c2fd | 3363 | /* Scan bridges that need to be reconfigured */ |
1c02ea81 | 3364 | pci_scan_bridge_extend(parent, dev, busnr, available_buses, 1); |
4147c2fd | 3365 | |
95e3ba97 MW |
3366 | if (!dev->subordinate) |
3367 | return -1; | |
3368 | ||
3369 | return 0; | |
3370 | } | |
3371 | EXPORT_SYMBOL_GPL(pci_hp_add_bridge); |