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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * probe.c - PCI detection and setup code | |
3 | */ | |
4 | ||
5 | #include <linux/kernel.h> | |
6 | #include <linux/delay.h> | |
7 | #include <linux/init.h> | |
8 | #include <linux/pci.h> | |
9 | #include <linux/slab.h> | |
10 | #include <linux/module.h> | |
11 | #include <linux/cpumask.h> | |
7d715a6c | 12 | #include <linux/pci-aspm.h> |
bc56b9e0 | 13 | #include "pci.h" |
1da177e4 LT |
14 | |
15 | #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ | |
16 | #define CARDBUS_RESERVE_BUSNR 3 | |
17 | #define PCI_CFG_SPACE_SIZE 256 | |
18 | #define PCI_CFG_SPACE_EXP_SIZE 4096 | |
19 | ||
20 | /* Ugh. Need to stop exporting this to modules. */ | |
21 | LIST_HEAD(pci_root_buses); | |
22 | EXPORT_SYMBOL(pci_root_buses); | |
23 | ||
70308923 GKH |
24 | |
25 | static int find_anything(struct device *dev, void *data) | |
26 | { | |
27 | return 1; | |
28 | } | |
29 | ||
ed4aaadb ZY |
30 | /* |
31 | * Some device drivers need know if pci is initiated. | |
32 | * Basically, we think pci is not initiated when there | |
70308923 | 33 | * is no device to be found on the pci_bus_type. |
ed4aaadb ZY |
34 | */ |
35 | int no_pci_devices(void) | |
36 | { | |
70308923 GKH |
37 | struct device *dev; |
38 | int no_devices; | |
ed4aaadb | 39 | |
70308923 GKH |
40 | dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything); |
41 | no_devices = (dev == NULL); | |
42 | put_device(dev); | |
43 | return no_devices; | |
44 | } | |
ed4aaadb ZY |
45 | EXPORT_SYMBOL(no_pci_devices); |
46 | ||
1da177e4 LT |
47 | #ifdef HAVE_PCI_LEGACY |
48 | /** | |
49 | * pci_create_legacy_files - create legacy I/O port and memory files | |
50 | * @b: bus to create files under | |
51 | * | |
52 | * Some platforms allow access to legacy I/O port and ISA memory space on | |
53 | * a per-bus basis. This routine creates the files and ties them into | |
54 | * their associated read, write and mmap files from pci-sysfs.c | |
55 | */ | |
56 | static void pci_create_legacy_files(struct pci_bus *b) | |
57 | { | |
f5afe806 | 58 | b->legacy_io = kzalloc(sizeof(struct bin_attribute) * 2, |
1da177e4 LT |
59 | GFP_ATOMIC); |
60 | if (b->legacy_io) { | |
1da177e4 LT |
61 | b->legacy_io->attr.name = "legacy_io"; |
62 | b->legacy_io->size = 0xffff; | |
63 | b->legacy_io->attr.mode = S_IRUSR | S_IWUSR; | |
1da177e4 LT |
64 | b->legacy_io->read = pci_read_legacy_io; |
65 | b->legacy_io->write = pci_write_legacy_io; | |
fd7d1ced | 66 | device_create_bin_file(&b->dev, b->legacy_io); |
1da177e4 LT |
67 | |
68 | /* Allocated above after the legacy_io struct */ | |
69 | b->legacy_mem = b->legacy_io + 1; | |
70 | b->legacy_mem->attr.name = "legacy_mem"; | |
71 | b->legacy_mem->size = 1024*1024; | |
72 | b->legacy_mem->attr.mode = S_IRUSR | S_IWUSR; | |
1da177e4 | 73 | b->legacy_mem->mmap = pci_mmap_legacy_mem; |
fd7d1ced | 74 | device_create_bin_file(&b->dev, b->legacy_mem); |
1da177e4 LT |
75 | } |
76 | } | |
77 | ||
78 | void pci_remove_legacy_files(struct pci_bus *b) | |
79 | { | |
80 | if (b->legacy_io) { | |
fd7d1ced GKH |
81 | device_remove_bin_file(&b->dev, b->legacy_io); |
82 | device_remove_bin_file(&b->dev, b->legacy_mem); | |
1da177e4 LT |
83 | kfree(b->legacy_io); /* both are allocated here */ |
84 | } | |
85 | } | |
86 | #else /* !HAVE_PCI_LEGACY */ | |
87 | static inline void pci_create_legacy_files(struct pci_bus *bus) { return; } | |
88 | void pci_remove_legacy_files(struct pci_bus *bus) { return; } | |
89 | #endif /* HAVE_PCI_LEGACY */ | |
90 | ||
91 | /* | |
92 | * PCI Bus Class Devices | |
93 | */ | |
fd7d1ced GKH |
94 | static ssize_t pci_bus_show_cpuaffinity(struct device *dev, |
95 | struct device_attribute *attr, | |
4327edf6 | 96 | char *buf) |
1da177e4 | 97 | { |
1da177e4 | 98 | int ret; |
4327edf6 | 99 | cpumask_t cpumask; |
1da177e4 | 100 | |
fd7d1ced | 101 | cpumask = pcibus_to_cpumask(to_pci_bus(dev)); |
1da177e4 LT |
102 | ret = cpumask_scnprintf(buf, PAGE_SIZE, cpumask); |
103 | if (ret < PAGE_SIZE) | |
104 | buf[ret++] = '\n'; | |
105 | return ret; | |
106 | } | |
fd7d1ced | 107 | DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpuaffinity, NULL); |
1da177e4 LT |
108 | |
109 | /* | |
110 | * PCI Bus Class | |
111 | */ | |
fd7d1ced | 112 | static void release_pcibus_dev(struct device *dev) |
1da177e4 | 113 | { |
fd7d1ced | 114 | struct pci_bus *pci_bus = to_pci_bus(dev); |
1da177e4 LT |
115 | |
116 | if (pci_bus->bridge) | |
117 | put_device(pci_bus->bridge); | |
118 | kfree(pci_bus); | |
119 | } | |
120 | ||
121 | static struct class pcibus_class = { | |
122 | .name = "pci_bus", | |
fd7d1ced | 123 | .dev_release = &release_pcibus_dev, |
1da177e4 LT |
124 | }; |
125 | ||
126 | static int __init pcibus_class_init(void) | |
127 | { | |
128 | return class_register(&pcibus_class); | |
129 | } | |
130 | postcore_initcall(pcibus_class_init); | |
131 | ||
132 | /* | |
133 | * Translate the low bits of the PCI base | |
134 | * to the resource type | |
135 | */ | |
136 | static inline unsigned int pci_calc_resource_flags(unsigned int flags) | |
137 | { | |
138 | if (flags & PCI_BASE_ADDRESS_SPACE_IO) | |
139 | return IORESOURCE_IO; | |
140 | ||
141 | if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) | |
142 | return IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
143 | ||
144 | return IORESOURCE_MEM; | |
145 | } | |
146 | ||
147 | /* | |
148 | * Find the extent of a PCI decode.. | |
149 | */ | |
f797f9cc | 150 | static u32 pci_size(u32 base, u32 maxbase, u32 mask) |
1da177e4 LT |
151 | { |
152 | u32 size = mask & maxbase; /* Find the significant bits */ | |
153 | if (!size) | |
154 | return 0; | |
155 | ||
156 | /* Get the lowest of them to find the decode size, and | |
157 | from that the extent. */ | |
158 | size = (size & ~(size-1)) - 1; | |
159 | ||
160 | /* base == maxbase can be valid only if the BAR has | |
161 | already been programmed with all 1s. */ | |
162 | if (base == maxbase && ((base | size) & mask) != mask) | |
163 | return 0; | |
164 | ||
165 | return size; | |
166 | } | |
167 | ||
07eddf3d YL |
168 | static u64 pci_size64(u64 base, u64 maxbase, u64 mask) |
169 | { | |
170 | u64 size = mask & maxbase; /* Find the significant bits */ | |
171 | if (!size) | |
172 | return 0; | |
173 | ||
174 | /* Get the lowest of them to find the decode size, and | |
175 | from that the extent. */ | |
176 | size = (size & ~(size-1)) - 1; | |
177 | ||
178 | /* base == maxbase can be valid only if the BAR has | |
179 | already been programmed with all 1s. */ | |
180 | if (base == maxbase && ((base | size) & mask) != mask) | |
181 | return 0; | |
182 | ||
183 | return size; | |
184 | } | |
185 | ||
186 | static inline int is_64bit_memory(u32 mask) | |
187 | { | |
188 | if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) == | |
189 | (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64)) | |
190 | return 1; | |
191 | return 0; | |
192 | } | |
193 | ||
1da177e4 LT |
194 | static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) |
195 | { | |
196 | unsigned int pos, reg, next; | |
197 | u32 l, sz; | |
198 | struct resource *res; | |
199 | ||
200 | for(pos=0; pos<howmany; pos = next) { | |
07eddf3d YL |
201 | u64 l64; |
202 | u64 sz64; | |
203 | u32 raw_sz; | |
204 | ||
1da177e4 LT |
205 | next = pos+1; |
206 | res = &dev->resource[pos]; | |
207 | res->name = pci_name(dev); | |
208 | reg = PCI_BASE_ADDRESS_0 + (pos << 2); | |
209 | pci_read_config_dword(dev, reg, &l); | |
210 | pci_write_config_dword(dev, reg, ~0); | |
211 | pci_read_config_dword(dev, reg, &sz); | |
212 | pci_write_config_dword(dev, reg, l); | |
213 | if (!sz || sz == 0xffffffff) | |
214 | continue; | |
215 | if (l == 0xffffffff) | |
216 | l = 0; | |
07eddf3d YL |
217 | raw_sz = sz; |
218 | if ((l & PCI_BASE_ADDRESS_SPACE) == | |
219 | PCI_BASE_ADDRESS_SPACE_MEMORY) { | |
3c6de929 | 220 | sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK); |
07eddf3d YL |
221 | /* |
222 | * For 64bit prefetchable memory sz could be 0, if the | |
223 | * real size is bigger than 4G, so we need to check | |
224 | * szhi for that. | |
225 | */ | |
226 | if (!is_64bit_memory(l) && !sz) | |
1da177e4 LT |
227 | continue; |
228 | res->start = l & PCI_BASE_ADDRESS_MEM_MASK; | |
229 | res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK; | |
230 | } else { | |
231 | sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff); | |
232 | if (!sz) | |
233 | continue; | |
234 | res->start = l & PCI_BASE_ADDRESS_IO_MASK; | |
235 | res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK; | |
236 | } | |
237 | res->end = res->start + (unsigned long) sz; | |
238 | res->flags |= pci_calc_resource_flags(l); | |
07eddf3d | 239 | if (is_64bit_memory(l)) { |
17d6dc8f | 240 | u32 szhi, lhi; |
07eddf3d | 241 | |
17d6dc8f PA |
242 | pci_read_config_dword(dev, reg+4, &lhi); |
243 | pci_write_config_dword(dev, reg+4, ~0); | |
244 | pci_read_config_dword(dev, reg+4, &szhi); | |
245 | pci_write_config_dword(dev, reg+4, lhi); | |
07eddf3d YL |
246 | sz64 = ((u64)szhi << 32) | raw_sz; |
247 | l64 = ((u64)lhi << 32) | l; | |
248 | sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK); | |
1da177e4 LT |
249 | next++; |
250 | #if BITS_PER_LONG == 64 | |
07eddf3d YL |
251 | if (!sz64) { |
252 | res->start = 0; | |
253 | res->end = 0; | |
254 | res->flags = 0; | |
255 | continue; | |
1da177e4 | 256 | } |
07eddf3d YL |
257 | res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK; |
258 | res->end = res->start + sz64; | |
1da177e4 | 259 | #else |
07eddf3d YL |
260 | if (sz64 > 0x100000000ULL) { |
261 | printk(KERN_ERR "PCI: Unable to handle 64-bit " | |
262 | "BAR for device %s\n", pci_name(dev)); | |
1da177e4 LT |
263 | res->start = 0; |
264 | res->flags = 0; | |
ea28502d | 265 | } else if (lhi) { |
17d6dc8f | 266 | /* 64-bit wide address, treat as disabled */ |
07eddf3d YL |
267 | pci_write_config_dword(dev, reg, |
268 | l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK); | |
17d6dc8f PA |
269 | pci_write_config_dword(dev, reg+4, 0); |
270 | res->start = 0; | |
271 | res->end = sz; | |
1da177e4 LT |
272 | } |
273 | #endif | |
274 | } | |
275 | } | |
276 | if (rom) { | |
277 | dev->rom_base_reg = rom; | |
278 | res = &dev->resource[PCI_ROM_RESOURCE]; | |
279 | res->name = pci_name(dev); | |
280 | pci_read_config_dword(dev, rom, &l); | |
281 | pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE); | |
282 | pci_read_config_dword(dev, rom, &sz); | |
283 | pci_write_config_dword(dev, rom, l); | |
284 | if (l == 0xffffffff) | |
285 | l = 0; | |
286 | if (sz && sz != 0xffffffff) { | |
3c6de929 | 287 | sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK); |
1da177e4 LT |
288 | if (sz) { |
289 | res->flags = (l & IORESOURCE_ROM_ENABLE) | | |
bb446093 GH |
290 | IORESOURCE_MEM | IORESOURCE_PREFETCH | |
291 | IORESOURCE_READONLY | IORESOURCE_CACHEABLE; | |
1da177e4 LT |
292 | res->start = l & PCI_ROM_ADDRESS_MASK; |
293 | res->end = res->start + (unsigned long) sz; | |
294 | } | |
295 | } | |
296 | } | |
297 | } | |
298 | ||
0ab2b57f | 299 | void __devinit pci_read_bridge_bases(struct pci_bus *child) |
1da177e4 LT |
300 | { |
301 | struct pci_dev *dev = child->self; | |
302 | u8 io_base_lo, io_limit_lo; | |
303 | u16 mem_base_lo, mem_limit_lo; | |
304 | unsigned long base, limit; | |
305 | struct resource *res; | |
306 | int i; | |
307 | ||
308 | if (!dev) /* It's a host bus, nothing to read */ | |
309 | return; | |
310 | ||
311 | if (dev->transparent) { | |
312 | printk(KERN_INFO "PCI: Transparent bridge - %s\n", pci_name(dev)); | |
90b54929 IK |
313 | for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++) |
314 | child->resource[i] = child->parent->resource[i - 3]; | |
1da177e4 LT |
315 | } |
316 | ||
317 | for(i=0; i<3; i++) | |
318 | child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; | |
319 | ||
320 | res = child->resource[0]; | |
321 | pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); | |
322 | pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); | |
323 | base = (io_base_lo & PCI_IO_RANGE_MASK) << 8; | |
324 | limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8; | |
325 | ||
326 | if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { | |
327 | u16 io_base_hi, io_limit_hi; | |
328 | pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); | |
329 | pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); | |
330 | base |= (io_base_hi << 16); | |
331 | limit |= (io_limit_hi << 16); | |
332 | } | |
333 | ||
334 | if (base <= limit) { | |
335 | res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; | |
9d265124 DY |
336 | if (!res->start) |
337 | res->start = base; | |
338 | if (!res->end) | |
339 | res->end = limit + 0xfff; | |
1da177e4 LT |
340 | } |
341 | ||
342 | res = child->resource[1]; | |
343 | pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); | |
344 | pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); | |
345 | base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; | |
346 | limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; | |
347 | if (base <= limit) { | |
348 | res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; | |
349 | res->start = base; | |
350 | res->end = limit + 0xfffff; | |
351 | } | |
352 | ||
353 | res = child->resource[2]; | |
354 | pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); | |
355 | pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); | |
356 | base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; | |
357 | limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; | |
358 | ||
359 | if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { | |
360 | u32 mem_base_hi, mem_limit_hi; | |
361 | pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); | |
362 | pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); | |
363 | ||
364 | /* | |
365 | * Some bridges set the base > limit by default, and some | |
366 | * (broken) BIOSes do not initialize them. If we find | |
367 | * this, just assume they are not being used. | |
368 | */ | |
369 | if (mem_base_hi <= mem_limit_hi) { | |
370 | #if BITS_PER_LONG == 64 | |
371 | base |= ((long) mem_base_hi) << 32; | |
372 | limit |= ((long) mem_limit_hi) << 32; | |
373 | #else | |
374 | if (mem_base_hi || mem_limit_hi) { | |
375 | printk(KERN_ERR "PCI: Unable to handle 64-bit address space for bridge %s\n", pci_name(dev)); | |
376 | return; | |
377 | } | |
378 | #endif | |
379 | } | |
380 | } | |
381 | if (base <= limit) { | |
382 | res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
383 | res->start = base; | |
384 | res->end = limit + 0xfffff; | |
385 | } | |
386 | } | |
387 | ||
96bde06a | 388 | static struct pci_bus * pci_alloc_bus(void) |
1da177e4 LT |
389 | { |
390 | struct pci_bus *b; | |
391 | ||
f5afe806 | 392 | b = kzalloc(sizeof(*b), GFP_KERNEL); |
1da177e4 | 393 | if (b) { |
1da177e4 LT |
394 | INIT_LIST_HEAD(&b->node); |
395 | INIT_LIST_HEAD(&b->children); | |
396 | INIT_LIST_HEAD(&b->devices); | |
397 | } | |
398 | return b; | |
399 | } | |
400 | ||
401 | static struct pci_bus * __devinit | |
402 | pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr) | |
403 | { | |
404 | struct pci_bus *child; | |
405 | int i; | |
406 | ||
407 | /* | |
408 | * Allocate a new bus, and inherit stuff from the parent.. | |
409 | */ | |
410 | child = pci_alloc_bus(); | |
411 | if (!child) | |
412 | return NULL; | |
413 | ||
414 | child->self = bridge; | |
415 | child->parent = parent; | |
416 | child->ops = parent->ops; | |
417 | child->sysdata = parent->sysdata; | |
6e325a62 | 418 | child->bus_flags = parent->bus_flags; |
1da177e4 LT |
419 | child->bridge = get_device(&bridge->dev); |
420 | ||
fd7d1ced GKH |
421 | /* initialize some portions of the bus device, but don't register it |
422 | * now as the parent is not properly set up yet. This device will get | |
423 | * registered later in pci_bus_add_devices() | |
424 | */ | |
425 | child->dev.class = &pcibus_class; | |
426 | sprintf(child->dev.bus_id, "%04x:%02x", pci_domain_nr(child), busnr); | |
1da177e4 LT |
427 | |
428 | /* | |
429 | * Set up the primary, secondary and subordinate | |
430 | * bus numbers. | |
431 | */ | |
432 | child->number = child->secondary = busnr; | |
433 | child->primary = parent->secondary; | |
434 | child->subordinate = 0xff; | |
435 | ||
436 | /* Set up default resource pointers and names.. */ | |
437 | for (i = 0; i < 4; i++) { | |
438 | child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; | |
439 | child->resource[i]->name = child->name; | |
440 | } | |
441 | bridge->subordinate = child; | |
442 | ||
443 | return child; | |
444 | } | |
445 | ||
451124a7 | 446 | struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr) |
1da177e4 LT |
447 | { |
448 | struct pci_bus *child; | |
449 | ||
450 | child = pci_alloc_child_bus(parent, dev, busnr); | |
e4ea9bb7 | 451 | if (child) { |
d71374da | 452 | down_write(&pci_bus_sem); |
1da177e4 | 453 | list_add_tail(&child->node, &parent->children); |
d71374da | 454 | up_write(&pci_bus_sem); |
e4ea9bb7 | 455 | } |
1da177e4 LT |
456 | return child; |
457 | } | |
458 | ||
96bde06a | 459 | static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max) |
26f674ae GKH |
460 | { |
461 | struct pci_bus *parent = child->parent; | |
12f44f46 IK |
462 | |
463 | /* Attempts to fix that up are really dangerous unless | |
464 | we're going to re-assign all bus numbers. */ | |
465 | if (!pcibios_assign_all_busses()) | |
466 | return; | |
467 | ||
26f674ae GKH |
468 | while (parent->parent && parent->subordinate < max) { |
469 | parent->subordinate = max; | |
470 | pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max); | |
471 | parent = parent->parent; | |
472 | } | |
473 | } | |
474 | ||
1da177e4 LT |
475 | /* |
476 | * If it's a bridge, configure it and scan the bus behind it. | |
477 | * For CardBus bridges, we don't scan behind as the devices will | |
478 | * be handled by the bridge driver itself. | |
479 | * | |
480 | * We need to process bridges in two passes -- first we scan those | |
481 | * already configured by the BIOS and after we are done with all of | |
482 | * them, we proceed to assigning numbers to the remaining buses in | |
483 | * order to avoid overlaps between old and new bus numbers. | |
484 | */ | |
0ab2b57f | 485 | int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) |
1da177e4 LT |
486 | { |
487 | struct pci_bus *child; | |
488 | int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); | |
49887941 | 489 | u32 buses, i, j = 0; |
1da177e4 LT |
490 | u16 bctl; |
491 | ||
492 | pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); | |
493 | ||
494 | pr_debug("PCI: Scanning behind PCI bridge %s, config %06x, pass %d\n", | |
495 | pci_name(dev), buses & 0xffffff, pass); | |
496 | ||
497 | /* Disable MasterAbortMode during probing to avoid reporting | |
498 | of bus errors (in some architectures) */ | |
499 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); | |
500 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, | |
501 | bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); | |
502 | ||
1da177e4 LT |
503 | if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) { |
504 | unsigned int cmax, busnr; | |
505 | /* | |
506 | * Bus already configured by firmware, process it in the first | |
507 | * pass and just note the configuration. | |
508 | */ | |
509 | if (pass) | |
bbe8f9a3 | 510 | goto out; |
1da177e4 LT |
511 | busnr = (buses >> 8) & 0xFF; |
512 | ||
513 | /* | |
514 | * If we already got to this bus through a different bridge, | |
515 | * ignore it. This can happen with the i450NX chipset. | |
516 | */ | |
517 | if (pci_find_bus(pci_domain_nr(bus), busnr)) { | |
518 | printk(KERN_INFO "PCI: Bus %04x:%02x already known\n", | |
519 | pci_domain_nr(bus), busnr); | |
bbe8f9a3 | 520 | goto out; |
1da177e4 LT |
521 | } |
522 | ||
6ef6f0e3 | 523 | child = pci_add_new_bus(bus, dev, busnr); |
1da177e4 | 524 | if (!child) |
bbe8f9a3 | 525 | goto out; |
1da177e4 LT |
526 | child->primary = buses & 0xFF; |
527 | child->subordinate = (buses >> 16) & 0xFF; | |
11949255 | 528 | child->bridge_ctl = bctl; |
1da177e4 LT |
529 | |
530 | cmax = pci_scan_child_bus(child); | |
531 | if (cmax > max) | |
532 | max = cmax; | |
533 | if (child->subordinate > max) | |
534 | max = child->subordinate; | |
535 | } else { | |
536 | /* | |
537 | * We need to assign a number to this bus which we always | |
538 | * do in the second pass. | |
539 | */ | |
12f44f46 IK |
540 | if (!pass) { |
541 | if (pcibios_assign_all_busses()) | |
542 | /* Temporarily disable forwarding of the | |
543 | configuration cycles on all bridges in | |
544 | this bus segment to avoid possible | |
545 | conflicts in the second pass between two | |
546 | bridges programmed with overlapping | |
547 | bus ranges. */ | |
548 | pci_write_config_dword(dev, PCI_PRIMARY_BUS, | |
549 | buses & ~0xffffff); | |
bbe8f9a3 | 550 | goto out; |
12f44f46 | 551 | } |
1da177e4 LT |
552 | |
553 | /* Clear errors */ | |
554 | pci_write_config_word(dev, PCI_STATUS, 0xffff); | |
555 | ||
cc57450f RS |
556 | /* Prevent assigning a bus number that already exists. |
557 | * This can happen when a bridge is hot-plugged */ | |
558 | if (pci_find_bus(pci_domain_nr(bus), max+1)) | |
bbe8f9a3 | 559 | goto out; |
6ef6f0e3 | 560 | child = pci_add_new_bus(bus, dev, ++max); |
1da177e4 LT |
561 | buses = (buses & 0xff000000) |
562 | | ((unsigned int)(child->primary) << 0) | |
563 | | ((unsigned int)(child->secondary) << 8) | |
564 | | ((unsigned int)(child->subordinate) << 16); | |
565 | ||
566 | /* | |
567 | * yenta.c forces a secondary latency timer of 176. | |
568 | * Copy that behaviour here. | |
569 | */ | |
570 | if (is_cardbus) { | |
571 | buses &= ~0xff000000; | |
572 | buses |= CARDBUS_LATENCY_TIMER << 24; | |
573 | } | |
574 | ||
575 | /* | |
576 | * We need to blast all three values with a single write. | |
577 | */ | |
578 | pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); | |
579 | ||
580 | if (!is_cardbus) { | |
11949255 | 581 | child->bridge_ctl = bctl; |
26f674ae GKH |
582 | /* |
583 | * Adjust subordinate busnr in parent buses. | |
584 | * We do this before scanning for children because | |
585 | * some devices may not be detected if the bios | |
586 | * was lazy. | |
587 | */ | |
588 | pci_fixup_parent_subordinate_busnr(child, max); | |
1da177e4 LT |
589 | /* Now we can scan all subordinate buses... */ |
590 | max = pci_scan_child_bus(child); | |
e3ac86d8 KA |
591 | /* |
592 | * now fix it up again since we have found | |
593 | * the real value of max. | |
594 | */ | |
595 | pci_fixup_parent_subordinate_busnr(child, max); | |
1da177e4 LT |
596 | } else { |
597 | /* | |
598 | * For CardBus bridges, we leave 4 bus numbers | |
599 | * as cards with a PCI-to-PCI bridge can be | |
600 | * inserted later. | |
601 | */ | |
49887941 DB |
602 | for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) { |
603 | struct pci_bus *parent = bus; | |
cc57450f RS |
604 | if (pci_find_bus(pci_domain_nr(bus), |
605 | max+i+1)) | |
606 | break; | |
49887941 DB |
607 | while (parent->parent) { |
608 | if ((!pcibios_assign_all_busses()) && | |
609 | (parent->subordinate > max) && | |
610 | (parent->subordinate <= max+i)) { | |
611 | j = 1; | |
612 | } | |
613 | parent = parent->parent; | |
614 | } | |
615 | if (j) { | |
616 | /* | |
617 | * Often, there are two cardbus bridges | |
618 | * -- try to leave one valid bus number | |
619 | * for each one. | |
620 | */ | |
621 | i /= 2; | |
622 | break; | |
623 | } | |
624 | } | |
cc57450f | 625 | max += i; |
26f674ae | 626 | pci_fixup_parent_subordinate_busnr(child, max); |
1da177e4 LT |
627 | } |
628 | /* | |
629 | * Set the subordinate bus number to its real value. | |
630 | */ | |
631 | child->subordinate = max; | |
632 | pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); | |
633 | } | |
634 | ||
cb3576fa GH |
635 | sprintf(child->name, |
636 | (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), | |
637 | pci_domain_nr(bus), child->number); | |
1da177e4 | 638 | |
d55bef51 | 639 | /* Has only triggered on CardBus, fixup is in yenta_socket */ |
49887941 DB |
640 | while (bus->parent) { |
641 | if ((child->subordinate > bus->subordinate) || | |
642 | (child->number > bus->subordinate) || | |
643 | (child->number < bus->number) || | |
644 | (child->subordinate < bus->number)) { | |
a6f29a98 | 645 | pr_debug("PCI: Bus #%02x (-#%02x) is %s " |
d55bef51 BK |
646 | "hidden behind%s bridge #%02x (-#%02x)\n", |
647 | child->number, child->subordinate, | |
648 | (bus->number > child->subordinate && | |
649 | bus->subordinate < child->number) ? | |
a6f29a98 JP |
650 | "wholly" : "partially", |
651 | bus->self->transparent ? " transparent" : "", | |
d55bef51 | 652 | bus->number, bus->subordinate); |
49887941 DB |
653 | } |
654 | bus = bus->parent; | |
655 | } | |
656 | ||
bbe8f9a3 RB |
657 | out: |
658 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl); | |
659 | ||
1da177e4 LT |
660 | return max; |
661 | } | |
662 | ||
663 | /* | |
664 | * Read interrupt line and base address registers. | |
665 | * The architecture-dependent code can tweak these, of course. | |
666 | */ | |
667 | static void pci_read_irq(struct pci_dev *dev) | |
668 | { | |
669 | unsigned char irq; | |
670 | ||
671 | pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); | |
ffeff788 | 672 | dev->pin = irq; |
1da177e4 LT |
673 | if (irq) |
674 | pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); | |
675 | dev->irq = irq; | |
676 | } | |
677 | ||
01abc2aa | 678 | #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) |
76e6a1d6 | 679 | |
1da177e4 LT |
680 | /** |
681 | * pci_setup_device - fill in class and map information of a device | |
682 | * @dev: the device structure to fill | |
683 | * | |
684 | * Initialize the device structure with information about the device's | |
685 | * vendor,class,memory and IO-space addresses,IRQ lines etc. | |
686 | * Called at initialisation of the PCI subsystem and by CardBus services. | |
687 | * Returns 0 on success and -1 if unknown type of device (not normal, bridge | |
688 | * or CardBus). | |
689 | */ | |
690 | static int pci_setup_device(struct pci_dev * dev) | |
691 | { | |
692 | u32 class; | |
693 | ||
694 | sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), | |
695 | dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); | |
696 | ||
697 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); | |
b8a3a521 | 698 | dev->revision = class & 0xff; |
1da177e4 LT |
699 | class >>= 8; /* upper 3 bytes */ |
700 | dev->class = class; | |
701 | class >>= 8; | |
702 | ||
703 | pr_debug("PCI: Found %s [%04x/%04x] %06x %02x\n", pci_name(dev), | |
704 | dev->vendor, dev->device, class, dev->hdr_type); | |
705 | ||
706 | /* "Unknown power state" */ | |
3fe9d19f | 707 | dev->current_state = PCI_UNKNOWN; |
1da177e4 LT |
708 | |
709 | /* Early fixups, before probing the BARs */ | |
710 | pci_fixup_device(pci_fixup_early, dev); | |
711 | class = dev->class >> 8; | |
712 | ||
713 | switch (dev->hdr_type) { /* header type */ | |
714 | case PCI_HEADER_TYPE_NORMAL: /* standard header */ | |
715 | if (class == PCI_CLASS_BRIDGE_PCI) | |
716 | goto bad; | |
717 | pci_read_irq(dev); | |
718 | pci_read_bases(dev, 6, PCI_ROM_ADDRESS); | |
719 | pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); | |
720 | pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device); | |
368c73d4 AC |
721 | |
722 | /* | |
723 | * Do the ugly legacy mode stuff here rather than broken chip | |
724 | * quirk code. Legacy mode ATA controllers have fixed | |
725 | * addresses. These are not always echoed in BAR0-3, and | |
726 | * BAR0-3 in a few cases contain junk! | |
727 | */ | |
728 | if (class == PCI_CLASS_STORAGE_IDE) { | |
729 | u8 progif; | |
730 | pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); | |
731 | if ((progif & 1) == 0) { | |
af1bff4f LT |
732 | dev->resource[0].start = 0x1F0; |
733 | dev->resource[0].end = 0x1F7; | |
734 | dev->resource[0].flags = LEGACY_IO_RESOURCE; | |
735 | dev->resource[1].start = 0x3F6; | |
736 | dev->resource[1].end = 0x3F6; | |
737 | dev->resource[1].flags = LEGACY_IO_RESOURCE; | |
368c73d4 AC |
738 | } |
739 | if ((progif & 4) == 0) { | |
af1bff4f LT |
740 | dev->resource[2].start = 0x170; |
741 | dev->resource[2].end = 0x177; | |
742 | dev->resource[2].flags = LEGACY_IO_RESOURCE; | |
743 | dev->resource[3].start = 0x376; | |
744 | dev->resource[3].end = 0x376; | |
745 | dev->resource[3].flags = LEGACY_IO_RESOURCE; | |
368c73d4 AC |
746 | } |
747 | } | |
1da177e4 LT |
748 | break; |
749 | ||
750 | case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ | |
751 | if (class != PCI_CLASS_BRIDGE_PCI) | |
752 | goto bad; | |
753 | /* The PCI-to-PCI bridge spec requires that subtractive | |
754 | decoding (i.e. transparent) bridge must have programming | |
755 | interface code of 0x01. */ | |
3efd273b | 756 | pci_read_irq(dev); |
1da177e4 LT |
757 | dev->transparent = ((dev->class & 0xff) == 1); |
758 | pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); | |
759 | break; | |
760 | ||
761 | case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ | |
762 | if (class != PCI_CLASS_BRIDGE_CARDBUS) | |
763 | goto bad; | |
764 | pci_read_irq(dev); | |
765 | pci_read_bases(dev, 1, 0); | |
766 | pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); | |
767 | pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); | |
768 | break; | |
769 | ||
770 | default: /* unknown header */ | |
771 | printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n", | |
772 | pci_name(dev), dev->hdr_type); | |
773 | return -1; | |
774 | ||
775 | bad: | |
776 | printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n", | |
777 | pci_name(dev), class, dev->hdr_type); | |
778 | dev->class = PCI_CLASS_NOT_DEFINED; | |
779 | } | |
780 | ||
781 | /* We found a fine healthy device, go go go... */ | |
782 | return 0; | |
783 | } | |
784 | ||
785 | /** | |
786 | * pci_release_dev - free a pci device structure when all users of it are finished. | |
787 | * @dev: device that's been disconnected | |
788 | * | |
789 | * Will be called only by the device core when all users of this pci device are | |
790 | * done. | |
791 | */ | |
792 | static void pci_release_dev(struct device *dev) | |
793 | { | |
794 | struct pci_dev *pci_dev; | |
795 | ||
796 | pci_dev = to_pci_dev(dev); | |
797 | kfree(pci_dev); | |
798 | } | |
799 | ||
994a65e2 KA |
800 | static void set_pcie_port_type(struct pci_dev *pdev) |
801 | { | |
802 | int pos; | |
803 | u16 reg16; | |
804 | ||
805 | pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); | |
806 | if (!pos) | |
807 | return; | |
808 | pdev->is_pcie = 1; | |
809 | pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); | |
810 | pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4; | |
811 | } | |
812 | ||
1da177e4 LT |
813 | /** |
814 | * pci_cfg_space_size - get the configuration space size of the PCI device. | |
8f7020d3 | 815 | * @dev: PCI device |
1da177e4 LT |
816 | * |
817 | * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices | |
818 | * have 4096 bytes. Even if the device is capable, that doesn't mean we can | |
819 | * access it. Maybe we don't have a way to generate extended config space | |
820 | * accesses, or the device is behind a reverse Express bridge. So we try | |
821 | * reading the dword at 0x100 which must either be 0 or a valid extended | |
822 | * capability header. | |
823 | */ | |
ac7dc65a | 824 | int pci_cfg_space_size(struct pci_dev *dev) |
1da177e4 LT |
825 | { |
826 | int pos; | |
827 | u32 status; | |
828 | ||
829 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
830 | if (!pos) { | |
831 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
832 | if (!pos) | |
833 | goto fail; | |
834 | ||
835 | pci_read_config_dword(dev, pos + PCI_X_STATUS, &status); | |
836 | if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))) | |
837 | goto fail; | |
838 | } | |
839 | ||
840 | if (pci_read_config_dword(dev, 256, &status) != PCIBIOS_SUCCESSFUL) | |
841 | goto fail; | |
842 | if (status == 0xffffffff) | |
843 | goto fail; | |
844 | ||
845 | return PCI_CFG_SPACE_EXP_SIZE; | |
846 | ||
847 | fail: | |
848 | return PCI_CFG_SPACE_SIZE; | |
849 | } | |
850 | ||
851 | static void pci_release_bus_bridge_dev(struct device *dev) | |
852 | { | |
853 | kfree(dev); | |
854 | } | |
855 | ||
65891215 ME |
856 | struct pci_dev *alloc_pci_dev(void) |
857 | { | |
858 | struct pci_dev *dev; | |
859 | ||
860 | dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); | |
861 | if (!dev) | |
862 | return NULL; | |
863 | ||
65891215 ME |
864 | INIT_LIST_HEAD(&dev->bus_list); |
865 | ||
4aa9bc95 ME |
866 | pci_msi_init_pci_dev(dev); |
867 | ||
65891215 ME |
868 | return dev; |
869 | } | |
870 | EXPORT_SYMBOL(alloc_pci_dev); | |
871 | ||
1da177e4 LT |
872 | /* |
873 | * Read the config data for a PCI device, sanity-check it | |
874 | * and fill in the dev structure... | |
875 | */ | |
876 | static struct pci_dev * __devinit | |
877 | pci_scan_device(struct pci_bus *bus, int devfn) | |
878 | { | |
879 | struct pci_dev *dev; | |
880 | u32 l; | |
881 | u8 hdr_type; | |
882 | int delay = 1; | |
883 | ||
884 | if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l)) | |
885 | return NULL; | |
886 | ||
887 | /* some broken boards return 0 or ~0 if a slot is empty: */ | |
888 | if (l == 0xffffffff || l == 0x00000000 || | |
889 | l == 0x0000ffff || l == 0xffff0000) | |
890 | return NULL; | |
891 | ||
892 | /* Configuration request Retry Status */ | |
893 | while (l == 0xffff0001) { | |
894 | msleep(delay); | |
895 | delay *= 2; | |
896 | if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l)) | |
897 | return NULL; | |
898 | /* Card hasn't responded in 60 seconds? Must be stuck. */ | |
899 | if (delay > 60 * 1000) { | |
900 | printk(KERN_WARNING "Device %04x:%02x:%02x.%d not " | |
901 | "responding\n", pci_domain_nr(bus), | |
902 | bus->number, PCI_SLOT(devfn), | |
903 | PCI_FUNC(devfn)); | |
904 | return NULL; | |
905 | } | |
906 | } | |
907 | ||
908 | if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type)) | |
909 | return NULL; | |
910 | ||
bab41e9b | 911 | dev = alloc_pci_dev(); |
1da177e4 LT |
912 | if (!dev) |
913 | return NULL; | |
914 | ||
1da177e4 LT |
915 | dev->bus = bus; |
916 | dev->sysdata = bus->sysdata; | |
917 | dev->dev.parent = bus->bridge; | |
918 | dev->dev.bus = &pci_bus_type; | |
919 | dev->devfn = devfn; | |
920 | dev->hdr_type = hdr_type & 0x7f; | |
921 | dev->multifunction = !!(hdr_type & 0x80); | |
922 | dev->vendor = l & 0xffff; | |
923 | dev->device = (l >> 16) & 0xffff; | |
924 | dev->cfg_size = pci_cfg_space_size(dev); | |
82081797 | 925 | dev->error_state = pci_channel_io_normal; |
994a65e2 | 926 | set_pcie_port_type(dev); |
1da177e4 LT |
927 | |
928 | /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) | |
929 | set this higher, assuming the system even supports it. */ | |
930 | dev->dma_mask = 0xffffffff; | |
931 | if (pci_setup_device(dev) < 0) { | |
932 | kfree(dev); | |
933 | return NULL; | |
934 | } | |
1da177e4 LT |
935 | |
936 | return dev; | |
937 | } | |
938 | ||
96bde06a | 939 | void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) |
1da177e4 | 940 | { |
cdb9b9f7 PM |
941 | device_initialize(&dev->dev); |
942 | dev->dev.release = pci_release_dev; | |
943 | pci_dev_get(dev); | |
1da177e4 | 944 | |
87348136 | 945 | set_dev_node(&dev->dev, pcibus_to_node(bus)); |
cdb9b9f7 | 946 | dev->dev.dma_mask = &dev->dma_mask; |
4d57cdfa | 947 | dev->dev.dma_parms = &dev->dma_parms; |
cdb9b9f7 | 948 | dev->dev.coherent_dma_mask = 0xffffffffull; |
1da177e4 | 949 | |
4d57cdfa | 950 | pci_set_dma_max_seg_size(dev, 65536); |
59fc67de | 951 | pci_set_dma_seg_boundary(dev, 0xffffffff); |
4d57cdfa | 952 | |
1da177e4 LT |
953 | /* Fix up broken headers */ |
954 | pci_fixup_device(pci_fixup_header, dev); | |
955 | ||
956 | /* | |
957 | * Add the device to our list of discovered devices | |
958 | * and the bus list for fixup functions, etc. | |
959 | */ | |
d71374da | 960 | down_write(&pci_bus_sem); |
1da177e4 | 961 | list_add_tail(&dev->bus_list, &bus->devices); |
d71374da | 962 | up_write(&pci_bus_sem); |
cdb9b9f7 PM |
963 | } |
964 | ||
451124a7 | 965 | struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn) |
cdb9b9f7 PM |
966 | { |
967 | struct pci_dev *dev; | |
968 | ||
969 | dev = pci_scan_device(bus, devfn); | |
970 | if (!dev) | |
971 | return NULL; | |
972 | ||
973 | pci_device_add(dev, bus); | |
1da177e4 LT |
974 | |
975 | return dev; | |
976 | } | |
b73e9687 | 977 | EXPORT_SYMBOL(pci_scan_single_device); |
1da177e4 LT |
978 | |
979 | /** | |
980 | * pci_scan_slot - scan a PCI slot on a bus for devices. | |
981 | * @bus: PCI bus to scan | |
982 | * @devfn: slot number to scan (must have zero function.) | |
983 | * | |
984 | * Scan a PCI slot on the specified PCI bus for devices, adding | |
985 | * discovered devices to the @bus->devices list. New devices | |
8a1bc901 | 986 | * will not have is_added set. |
1da177e4 | 987 | */ |
96bde06a | 988 | int pci_scan_slot(struct pci_bus *bus, int devfn) |
1da177e4 LT |
989 | { |
990 | int func, nr = 0; | |
991 | int scan_all_fns; | |
992 | ||
993 | scan_all_fns = pcibios_scan_all_fns(bus, devfn); | |
994 | ||
995 | for (func = 0; func < 8; func++, devfn++) { | |
996 | struct pci_dev *dev; | |
997 | ||
998 | dev = pci_scan_single_device(bus, devfn); | |
999 | if (dev) { | |
1000 | nr++; | |
1001 | ||
1002 | /* | |
1003 | * If this is a single function device, | |
1004 | * don't scan past the first function. | |
1005 | */ | |
1006 | if (!dev->multifunction) { | |
1007 | if (func > 0) { | |
1008 | dev->multifunction = 1; | |
1009 | } else { | |
1010 | break; | |
1011 | } | |
1012 | } | |
1013 | } else { | |
1014 | if (func == 0 && !scan_all_fns) | |
1015 | break; | |
1016 | } | |
1017 | } | |
7d715a6c SL |
1018 | |
1019 | if (bus->self) | |
1020 | pcie_aspm_init_link_state(bus->self); | |
1021 | ||
1da177e4 LT |
1022 | return nr; |
1023 | } | |
1024 | ||
0ab2b57f | 1025 | unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus) |
1da177e4 LT |
1026 | { |
1027 | unsigned int devfn, pass, max = bus->secondary; | |
1028 | struct pci_dev *dev; | |
1029 | ||
1030 | pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number); | |
1031 | ||
1032 | /* Go find them, Rover! */ | |
1033 | for (devfn = 0; devfn < 0x100; devfn += 8) | |
1034 | pci_scan_slot(bus, devfn); | |
1035 | ||
1036 | /* | |
1037 | * After performing arch-dependent fixup of the bus, look behind | |
1038 | * all PCI-to-PCI bridges on this bus. | |
1039 | */ | |
1040 | pr_debug("PCI: Fixups for bus %04x:%02x\n", pci_domain_nr(bus), bus->number); | |
1041 | pcibios_fixup_bus(bus); | |
1042 | for (pass=0; pass < 2; pass++) | |
1043 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1044 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || | |
1045 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) | |
1046 | max = pci_scan_bridge(bus, dev, max, pass); | |
1047 | } | |
1048 | ||
1049 | /* | |
1050 | * We've scanned the bus and so we know all about what's on | |
1051 | * the other side of any bridges that may be on this bus plus | |
1052 | * any devices. | |
1053 | * | |
1054 | * Return how far we've got finding sub-buses. | |
1055 | */ | |
1056 | pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n", | |
1057 | pci_domain_nr(bus), bus->number, max); | |
1058 | return max; | |
1059 | } | |
1060 | ||
96bde06a | 1061 | struct pci_bus * pci_create_bus(struct device *parent, |
cdb9b9f7 | 1062 | int bus, struct pci_ops *ops, void *sysdata) |
1da177e4 LT |
1063 | { |
1064 | int error; | |
1065 | struct pci_bus *b; | |
1066 | struct device *dev; | |
1067 | ||
1068 | b = pci_alloc_bus(); | |
1069 | if (!b) | |
1070 | return NULL; | |
1071 | ||
1072 | dev = kmalloc(sizeof(*dev), GFP_KERNEL); | |
1073 | if (!dev){ | |
1074 | kfree(b); | |
1075 | return NULL; | |
1076 | } | |
1077 | ||
1078 | b->sysdata = sysdata; | |
1079 | b->ops = ops; | |
1080 | ||
1081 | if (pci_find_bus(pci_domain_nr(b), bus)) { | |
1082 | /* If we already got to this bus through a different bridge, ignore it */ | |
1083 | pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus); | |
1084 | goto err_out; | |
1085 | } | |
d71374da ZY |
1086 | |
1087 | down_write(&pci_bus_sem); | |
1da177e4 | 1088 | list_add_tail(&b->node, &pci_root_buses); |
d71374da | 1089 | up_write(&pci_bus_sem); |
1da177e4 LT |
1090 | |
1091 | memset(dev, 0, sizeof(*dev)); | |
1092 | dev->parent = parent; | |
1093 | dev->release = pci_release_bus_bridge_dev; | |
1094 | sprintf(dev->bus_id, "pci%04x:%02x", pci_domain_nr(b), bus); | |
1095 | error = device_register(dev); | |
1096 | if (error) | |
1097 | goto dev_reg_err; | |
1098 | b->bridge = get_device(dev); | |
1099 | ||
fd7d1ced GKH |
1100 | b->dev.class = &pcibus_class; |
1101 | b->dev.parent = b->bridge; | |
1102 | sprintf(b->dev.bus_id, "%04x:%02x", pci_domain_nr(b), bus); | |
1103 | error = device_register(&b->dev); | |
1da177e4 LT |
1104 | if (error) |
1105 | goto class_dev_reg_err; | |
fd7d1ced | 1106 | error = device_create_file(&b->dev, &dev_attr_cpuaffinity); |
1da177e4 | 1107 | if (error) |
fd7d1ced | 1108 | goto dev_create_file_err; |
1da177e4 LT |
1109 | |
1110 | /* Create legacy_io and legacy_mem files for this bus */ | |
1111 | pci_create_legacy_files(b); | |
1112 | ||
1da177e4 LT |
1113 | b->number = b->secondary = bus; |
1114 | b->resource[0] = &ioport_resource; | |
1115 | b->resource[1] = &iomem_resource; | |
1116 | ||
1da177e4 LT |
1117 | return b; |
1118 | ||
fd7d1ced GKH |
1119 | dev_create_file_err: |
1120 | device_unregister(&b->dev); | |
1da177e4 LT |
1121 | class_dev_reg_err: |
1122 | device_unregister(dev); | |
1123 | dev_reg_err: | |
d71374da | 1124 | down_write(&pci_bus_sem); |
1da177e4 | 1125 | list_del(&b->node); |
d71374da | 1126 | up_write(&pci_bus_sem); |
1da177e4 LT |
1127 | err_out: |
1128 | kfree(dev); | |
1129 | kfree(b); | |
1130 | return NULL; | |
1131 | } | |
cdb9b9f7 | 1132 | |
0ab2b57f | 1133 | struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent, |
cdb9b9f7 PM |
1134 | int bus, struct pci_ops *ops, void *sysdata) |
1135 | { | |
1136 | struct pci_bus *b; | |
1137 | ||
1138 | b = pci_create_bus(parent, bus, ops, sysdata); | |
1139 | if (b) | |
1140 | b->subordinate = pci_scan_child_bus(b); | |
1141 | return b; | |
1142 | } | |
1da177e4 LT |
1143 | EXPORT_SYMBOL(pci_scan_bus_parented); |
1144 | ||
1145 | #ifdef CONFIG_HOTPLUG | |
1146 | EXPORT_SYMBOL(pci_add_new_bus); | |
1da177e4 LT |
1147 | EXPORT_SYMBOL(pci_scan_slot); |
1148 | EXPORT_SYMBOL(pci_scan_bridge); | |
1da177e4 LT |
1149 | EXPORT_SYMBOL_GPL(pci_scan_child_bus); |
1150 | #endif | |
6b4b78fe MD |
1151 | |
1152 | static int __init pci_sort_bf_cmp(const struct pci_dev *a, const struct pci_dev *b) | |
1153 | { | |
1154 | if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1; | |
1155 | else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1; | |
1156 | ||
1157 | if (a->bus->number < b->bus->number) return -1; | |
1158 | else if (a->bus->number > b->bus->number) return 1; | |
1159 | ||
1160 | if (a->devfn < b->devfn) return -1; | |
1161 | else if (a->devfn > b->devfn) return 1; | |
1162 | ||
1163 | return 0; | |
1164 | } | |
1165 | ||
1166 | /* | |
1167 | * Yes, this forcably breaks the klist abstraction temporarily. It | |
1168 | * just wants to sort the klist, not change reference counts and | |
1169 | * take/drop locks rapidly in the process. It does all this while | |
1170 | * holding the lock for the list, so objects can't otherwise be | |
1171 | * added/removed while we're swizzling. | |
1172 | */ | |
1173 | static void __init pci_insertion_sort_klist(struct pci_dev *a, struct list_head *list) | |
1174 | { | |
1175 | struct list_head *pos; | |
1176 | struct klist_node *n; | |
1177 | struct device *dev; | |
1178 | struct pci_dev *b; | |
1179 | ||
1180 | list_for_each(pos, list) { | |
1181 | n = container_of(pos, struct klist_node, n_node); | |
1182 | dev = container_of(n, struct device, knode_bus); | |
1183 | b = to_pci_dev(dev); | |
1184 | if (pci_sort_bf_cmp(a, b) <= 0) { | |
1185 | list_move_tail(&a->dev.knode_bus.n_node, &b->dev.knode_bus.n_node); | |
1186 | return; | |
1187 | } | |
1188 | } | |
1189 | list_move_tail(&a->dev.knode_bus.n_node, list); | |
1190 | } | |
1191 | ||
5ff580c1 | 1192 | void __init pci_sort_breadthfirst(void) |
6b4b78fe MD |
1193 | { |
1194 | LIST_HEAD(sorted_devices); | |
1195 | struct list_head *pos, *tmp; | |
1196 | struct klist_node *n; | |
1197 | struct device *dev; | |
1198 | struct pci_dev *pdev; | |
b249072e | 1199 | struct klist *device_klist; |
6b4b78fe | 1200 | |
b249072e GKH |
1201 | device_klist = bus_get_device_klist(&pci_bus_type); |
1202 | ||
1203 | spin_lock(&device_klist->k_lock); | |
1204 | list_for_each_safe(pos, tmp, &device_klist->k_list) { | |
6b4b78fe MD |
1205 | n = container_of(pos, struct klist_node, n_node); |
1206 | dev = container_of(n, struct device, knode_bus); | |
1207 | pdev = to_pci_dev(dev); | |
1208 | pci_insertion_sort_klist(pdev, &sorted_devices); | |
1209 | } | |
b249072e GKH |
1210 | list_splice(&sorted_devices, &device_klist->k_list); |
1211 | spin_unlock(&device_klist->k_lock); | |
6b4b78fe | 1212 | } |