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Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * probe.c - PCI detection and setup code | |
3 | */ | |
4 | ||
5 | #include <linux/kernel.h> | |
6 | #include <linux/delay.h> | |
7 | #include <linux/init.h> | |
8 | #include <linux/pci.h> | |
9 | #include <linux/slab.h> | |
10 | #include <linux/module.h> | |
11 | #include <linux/cpumask.h> | |
7d715a6c | 12 | #include <linux/pci-aspm.h> |
bc56b9e0 | 13 | #include "pci.h" |
1da177e4 LT |
14 | |
15 | #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ | |
16 | #define CARDBUS_RESERVE_BUSNR 3 | |
1da177e4 LT |
17 | |
18 | /* Ugh. Need to stop exporting this to modules. */ | |
19 | LIST_HEAD(pci_root_buses); | |
20 | EXPORT_SYMBOL(pci_root_buses); | |
21 | ||
70308923 GKH |
22 | |
23 | static int find_anything(struct device *dev, void *data) | |
24 | { | |
25 | return 1; | |
26 | } | |
1da177e4 | 27 | |
ed4aaadb ZY |
28 | /* |
29 | * Some device drivers need know if pci is initiated. | |
30 | * Basically, we think pci is not initiated when there | |
70308923 | 31 | * is no device to be found on the pci_bus_type. |
ed4aaadb ZY |
32 | */ |
33 | int no_pci_devices(void) | |
34 | { | |
70308923 GKH |
35 | struct device *dev; |
36 | int no_devices; | |
ed4aaadb | 37 | |
70308923 GKH |
38 | dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything); |
39 | no_devices = (dev == NULL); | |
40 | put_device(dev); | |
41 | return no_devices; | |
42 | } | |
ed4aaadb ZY |
43 | EXPORT_SYMBOL(no_pci_devices); |
44 | ||
1da177e4 LT |
45 | /* |
46 | * PCI Bus Class Devices | |
47 | */ | |
fd7d1ced | 48 | static ssize_t pci_bus_show_cpuaffinity(struct device *dev, |
39106dcf | 49 | int type, |
fd7d1ced | 50 | struct device_attribute *attr, |
4327edf6 | 51 | char *buf) |
1da177e4 | 52 | { |
1da177e4 | 53 | int ret; |
588235bb | 54 | const struct cpumask *cpumask; |
1da177e4 | 55 | |
588235bb | 56 | cpumask = cpumask_of_pcibus(to_pci_bus(dev)); |
39106dcf | 57 | ret = type? |
588235bb MT |
58 | cpulist_scnprintf(buf, PAGE_SIZE-2, cpumask) : |
59 | cpumask_scnprintf(buf, PAGE_SIZE-2, cpumask); | |
39106dcf MT |
60 | buf[ret++] = '\n'; |
61 | buf[ret] = '\0'; | |
1da177e4 LT |
62 | return ret; |
63 | } | |
39106dcf MT |
64 | |
65 | static ssize_t inline pci_bus_show_cpumaskaffinity(struct device *dev, | |
66 | struct device_attribute *attr, | |
67 | char *buf) | |
68 | { | |
69 | return pci_bus_show_cpuaffinity(dev, 0, attr, buf); | |
70 | } | |
71 | ||
72 | static ssize_t inline pci_bus_show_cpulistaffinity(struct device *dev, | |
73 | struct device_attribute *attr, | |
74 | char *buf) | |
75 | { | |
76 | return pci_bus_show_cpuaffinity(dev, 1, attr, buf); | |
77 | } | |
78 | ||
79 | DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpumaskaffinity, NULL); | |
80 | DEVICE_ATTR(cpulistaffinity, S_IRUGO, pci_bus_show_cpulistaffinity, NULL); | |
1da177e4 LT |
81 | |
82 | /* | |
83 | * PCI Bus Class | |
84 | */ | |
fd7d1ced | 85 | static void release_pcibus_dev(struct device *dev) |
1da177e4 | 86 | { |
fd7d1ced | 87 | struct pci_bus *pci_bus = to_pci_bus(dev); |
1da177e4 LT |
88 | |
89 | if (pci_bus->bridge) | |
90 | put_device(pci_bus->bridge); | |
91 | kfree(pci_bus); | |
92 | } | |
93 | ||
94 | static struct class pcibus_class = { | |
95 | .name = "pci_bus", | |
fd7d1ced | 96 | .dev_release = &release_pcibus_dev, |
1da177e4 LT |
97 | }; |
98 | ||
99 | static int __init pcibus_class_init(void) | |
100 | { | |
101 | return class_register(&pcibus_class); | |
102 | } | |
103 | postcore_initcall(pcibus_class_init); | |
104 | ||
105 | /* | |
106 | * Translate the low bits of the PCI base | |
107 | * to the resource type | |
108 | */ | |
109 | static inline unsigned int pci_calc_resource_flags(unsigned int flags) | |
110 | { | |
111 | if (flags & PCI_BASE_ADDRESS_SPACE_IO) | |
112 | return IORESOURCE_IO; | |
113 | ||
114 | if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) | |
115 | return IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
116 | ||
117 | return IORESOURCE_MEM; | |
118 | } | |
119 | ||
6ac665c6 | 120 | static u64 pci_size(u64 base, u64 maxbase, u64 mask) |
1da177e4 | 121 | { |
6ac665c6 | 122 | u64 size = mask & maxbase; /* Find the significant bits */ |
1da177e4 LT |
123 | if (!size) |
124 | return 0; | |
125 | ||
126 | /* Get the lowest of them to find the decode size, and | |
127 | from that the extent. */ | |
128 | size = (size & ~(size-1)) - 1; | |
129 | ||
130 | /* base == maxbase can be valid only if the BAR has | |
131 | already been programmed with all 1s. */ | |
132 | if (base == maxbase && ((base | size) & mask) != mask) | |
133 | return 0; | |
134 | ||
135 | return size; | |
136 | } | |
137 | ||
6ac665c6 MW |
138 | static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar) |
139 | { | |
140 | if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { | |
141 | res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK; | |
142 | return pci_bar_io; | |
143 | } | |
07eddf3d | 144 | |
6ac665c6 | 145 | res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK; |
07eddf3d | 146 | |
e354597c | 147 | if (res->flags & PCI_BASE_ADDRESS_MEM_TYPE_64) |
6ac665c6 MW |
148 | return pci_bar_mem64; |
149 | return pci_bar_mem32; | |
07eddf3d YL |
150 | } |
151 | ||
0b400c7e YZ |
152 | /** |
153 | * pci_read_base - read a PCI BAR | |
154 | * @dev: the PCI device | |
155 | * @type: type of the BAR | |
156 | * @res: resource buffer to be filled in | |
157 | * @pos: BAR position in the config space | |
158 | * | |
159 | * Returns 1 if the BAR is 64-bit, or 0 if 32-bit. | |
6ac665c6 | 160 | */ |
0b400c7e | 161 | int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, |
6ac665c6 | 162 | struct resource *res, unsigned int pos) |
07eddf3d | 163 | { |
6ac665c6 MW |
164 | u32 l, sz, mask; |
165 | ||
166 | mask = type ? ~PCI_ROM_ADDRESS_ENABLE : ~0; | |
167 | ||
168 | res->name = pci_name(dev); | |
169 | ||
170 | pci_read_config_dword(dev, pos, &l); | |
171 | pci_write_config_dword(dev, pos, mask); | |
172 | pci_read_config_dword(dev, pos, &sz); | |
173 | pci_write_config_dword(dev, pos, l); | |
174 | ||
175 | /* | |
176 | * All bits set in sz means the device isn't working properly. | |
177 | * If the BAR isn't implemented, all bits must be 0. If it's a | |
178 | * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit | |
179 | * 1 must be clear. | |
180 | */ | |
181 | if (!sz || sz == 0xffffffff) | |
182 | goto fail; | |
183 | ||
184 | /* | |
185 | * I don't know how l can have all bits set. Copied from old code. | |
186 | * Maybe it fixes a bug on some ancient platform. | |
187 | */ | |
188 | if (l == 0xffffffff) | |
189 | l = 0; | |
190 | ||
191 | if (type == pci_bar_unknown) { | |
192 | type = decode_bar(res, l); | |
193 | res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN; | |
194 | if (type == pci_bar_io) { | |
195 | l &= PCI_BASE_ADDRESS_IO_MASK; | |
1f82de10 | 196 | mask = PCI_BASE_ADDRESS_IO_MASK & IO_SPACE_LIMIT; |
6ac665c6 MW |
197 | } else { |
198 | l &= PCI_BASE_ADDRESS_MEM_MASK; | |
199 | mask = (u32)PCI_BASE_ADDRESS_MEM_MASK; | |
200 | } | |
201 | } else { | |
202 | res->flags |= (l & IORESOURCE_ROM_ENABLE); | |
203 | l &= PCI_ROM_ADDRESS_MASK; | |
204 | mask = (u32)PCI_ROM_ADDRESS_MASK; | |
205 | } | |
206 | ||
207 | if (type == pci_bar_mem64) { | |
208 | u64 l64 = l; | |
209 | u64 sz64 = sz; | |
210 | u64 mask64 = mask | (u64)~0 << 32; | |
211 | ||
212 | pci_read_config_dword(dev, pos + 4, &l); | |
213 | pci_write_config_dword(dev, pos + 4, ~0); | |
214 | pci_read_config_dword(dev, pos + 4, &sz); | |
215 | pci_write_config_dword(dev, pos + 4, l); | |
216 | ||
217 | l64 |= ((u64)l << 32); | |
218 | sz64 |= ((u64)sz << 32); | |
219 | ||
220 | sz64 = pci_size(l64, sz64, mask64); | |
221 | ||
222 | if (!sz64) | |
223 | goto fail; | |
224 | ||
cc5499c3 | 225 | if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) { |
6ac665c6 MW |
226 | dev_err(&dev->dev, "can't handle 64-bit BAR\n"); |
227 | goto fail; | |
cc5499c3 | 228 | } else if ((sizeof(resource_size_t) < 8) && l) { |
6ac665c6 MW |
229 | /* Address above 32-bit boundary; disable the BAR */ |
230 | pci_write_config_dword(dev, pos, 0); | |
231 | pci_write_config_dword(dev, pos + 4, 0); | |
232 | res->start = 0; | |
233 | res->end = sz64; | |
234 | } else { | |
235 | res->start = l64; | |
236 | res->end = l64 + sz64; | |
f393d9b1 VL |
237 | dev_printk(KERN_DEBUG, &dev->dev, |
238 | "reg %x 64bit mmio: %pR\n", pos, res); | |
6ac665c6 | 239 | } |
1f82de10 YL |
240 | |
241 | res->flags |= IORESOURCE_MEM_64; | |
6ac665c6 MW |
242 | } else { |
243 | sz = pci_size(l, sz, mask); | |
244 | ||
245 | if (!sz) | |
246 | goto fail; | |
247 | ||
248 | res->start = l; | |
249 | res->end = l + sz; | |
f393d9b1 VL |
250 | |
251 | dev_printk(KERN_DEBUG, &dev->dev, "reg %x %s: %pR\n", pos, | |
252 | (res->flags & IORESOURCE_IO) ? "io port" : "32bit mmio", | |
253 | res); | |
6ac665c6 MW |
254 | } |
255 | ||
256 | out: | |
257 | return (type == pci_bar_mem64) ? 1 : 0; | |
258 | fail: | |
259 | res->flags = 0; | |
260 | goto out; | |
07eddf3d YL |
261 | } |
262 | ||
1da177e4 LT |
263 | static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) |
264 | { | |
6ac665c6 | 265 | unsigned int pos, reg; |
07eddf3d | 266 | |
6ac665c6 MW |
267 | for (pos = 0; pos < howmany; pos++) { |
268 | struct resource *res = &dev->resource[pos]; | |
1da177e4 | 269 | reg = PCI_BASE_ADDRESS_0 + (pos << 2); |
6ac665c6 | 270 | pos += __pci_read_base(dev, pci_bar_unknown, res, reg); |
1da177e4 | 271 | } |
6ac665c6 | 272 | |
1da177e4 | 273 | if (rom) { |
6ac665c6 | 274 | struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; |
1da177e4 | 275 | dev->rom_base_reg = rom; |
6ac665c6 MW |
276 | res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | |
277 | IORESOURCE_READONLY | IORESOURCE_CACHEABLE | | |
278 | IORESOURCE_SIZEALIGN; | |
279 | __pci_read_base(dev, pci_bar_mem32, res, rom); | |
1da177e4 LT |
280 | } |
281 | } | |
282 | ||
0ab2b57f | 283 | void __devinit pci_read_bridge_bases(struct pci_bus *child) |
1da177e4 LT |
284 | { |
285 | struct pci_dev *dev = child->self; | |
286 | u8 io_base_lo, io_limit_lo; | |
287 | u16 mem_base_lo, mem_limit_lo; | |
288 | unsigned long base, limit; | |
289 | struct resource *res; | |
290 | int i; | |
291 | ||
f92d4e29 | 292 | if (!child->parent) /* It's a host bus, nothing to read */ |
1da177e4 LT |
293 | return; |
294 | ||
295 | if (dev->transparent) { | |
80ccba11 | 296 | dev_info(&dev->dev, "transparent bridge\n"); |
90b54929 IK |
297 | for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++) |
298 | child->resource[i] = child->parent->resource[i - 3]; | |
1da177e4 LT |
299 | } |
300 | ||
1da177e4 LT |
301 | res = child->resource[0]; |
302 | pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); | |
303 | pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); | |
304 | base = (io_base_lo & PCI_IO_RANGE_MASK) << 8; | |
305 | limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8; | |
306 | ||
307 | if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { | |
308 | u16 io_base_hi, io_limit_hi; | |
309 | pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); | |
310 | pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); | |
311 | base |= (io_base_hi << 16); | |
312 | limit |= (io_limit_hi << 16); | |
313 | } | |
314 | ||
315 | if (base <= limit) { | |
316 | res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; | |
9d265124 DY |
317 | if (!res->start) |
318 | res->start = base; | |
319 | if (!res->end) | |
320 | res->end = limit + 0xfff; | |
f393d9b1 | 321 | dev_printk(KERN_DEBUG, &dev->dev, "bridge io port: %pR\n", res); |
1da177e4 LT |
322 | } |
323 | ||
324 | res = child->resource[1]; | |
325 | pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); | |
326 | pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); | |
327 | base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; | |
328 | limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; | |
329 | if (base <= limit) { | |
330 | res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; | |
331 | res->start = base; | |
332 | res->end = limit + 0xfffff; | |
f393d9b1 VL |
333 | dev_printk(KERN_DEBUG, &dev->dev, "bridge 32bit mmio: %pR\n", |
334 | res); | |
1da177e4 LT |
335 | } |
336 | ||
337 | res = child->resource[2]; | |
338 | pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); | |
339 | pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); | |
340 | base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; | |
341 | limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; | |
342 | ||
343 | if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { | |
344 | u32 mem_base_hi, mem_limit_hi; | |
345 | pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); | |
346 | pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); | |
347 | ||
348 | /* | |
349 | * Some bridges set the base > limit by default, and some | |
350 | * (broken) BIOSes do not initialize them. If we find | |
351 | * this, just assume they are not being used. | |
352 | */ | |
353 | if (mem_base_hi <= mem_limit_hi) { | |
354 | #if BITS_PER_LONG == 64 | |
355 | base |= ((long) mem_base_hi) << 32; | |
356 | limit |= ((long) mem_limit_hi) << 32; | |
357 | #else | |
358 | if (mem_base_hi || mem_limit_hi) { | |
80ccba11 BH |
359 | dev_err(&dev->dev, "can't handle 64-bit " |
360 | "address space for bridge\n"); | |
1da177e4 LT |
361 | return; |
362 | } | |
363 | #endif | |
364 | } | |
365 | } | |
366 | if (base <= limit) { | |
1f82de10 YL |
367 | res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) | |
368 | IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
369 | if (res->flags & PCI_PREF_RANGE_TYPE_64) | |
370 | res->flags |= IORESOURCE_MEM_64; | |
1da177e4 LT |
371 | res->start = base; |
372 | res->end = limit + 0xfffff; | |
f393d9b1 VL |
373 | dev_printk(KERN_DEBUG, &dev->dev, "bridge %sbit mmio pref: %pR\n", |
374 | (res->flags & PCI_PREF_RANGE_TYPE_64) ? "64" : "32", | |
375 | res); | |
1da177e4 LT |
376 | } |
377 | } | |
378 | ||
96bde06a | 379 | static struct pci_bus * pci_alloc_bus(void) |
1da177e4 LT |
380 | { |
381 | struct pci_bus *b; | |
382 | ||
f5afe806 | 383 | b = kzalloc(sizeof(*b), GFP_KERNEL); |
1da177e4 | 384 | if (b) { |
1da177e4 LT |
385 | INIT_LIST_HEAD(&b->node); |
386 | INIT_LIST_HEAD(&b->children); | |
387 | INIT_LIST_HEAD(&b->devices); | |
f46753c5 | 388 | INIT_LIST_HEAD(&b->slots); |
1da177e4 LT |
389 | } |
390 | return b; | |
391 | } | |
392 | ||
cbd4e055 AB |
393 | static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, |
394 | struct pci_dev *bridge, int busnr) | |
1da177e4 LT |
395 | { |
396 | struct pci_bus *child; | |
397 | int i; | |
398 | ||
399 | /* | |
400 | * Allocate a new bus, and inherit stuff from the parent.. | |
401 | */ | |
402 | child = pci_alloc_bus(); | |
403 | if (!child) | |
404 | return NULL; | |
405 | ||
1da177e4 LT |
406 | child->parent = parent; |
407 | child->ops = parent->ops; | |
408 | child->sysdata = parent->sysdata; | |
6e325a62 | 409 | child->bus_flags = parent->bus_flags; |
1da177e4 | 410 | |
fd7d1ced GKH |
411 | /* initialize some portions of the bus device, but don't register it |
412 | * now as the parent is not properly set up yet. This device will get | |
413 | * registered later in pci_bus_add_devices() | |
414 | */ | |
415 | child->dev.class = &pcibus_class; | |
1a927133 | 416 | dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr); |
1da177e4 LT |
417 | |
418 | /* | |
419 | * Set up the primary, secondary and subordinate | |
420 | * bus numbers. | |
421 | */ | |
422 | child->number = child->secondary = busnr; | |
423 | child->primary = parent->secondary; | |
424 | child->subordinate = 0xff; | |
425 | ||
3789fa8a YZ |
426 | if (!bridge) |
427 | return child; | |
428 | ||
429 | child->self = bridge; | |
430 | child->bridge = get_device(&bridge->dev); | |
431 | ||
1da177e4 | 432 | /* Set up default resource pointers and names.. */ |
fde09c6d | 433 | for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { |
1da177e4 LT |
434 | child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; |
435 | child->resource[i]->name = child->name; | |
436 | } | |
437 | bridge->subordinate = child; | |
438 | ||
439 | return child; | |
440 | } | |
441 | ||
451124a7 | 442 | struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr) |
1da177e4 LT |
443 | { |
444 | struct pci_bus *child; | |
445 | ||
446 | child = pci_alloc_child_bus(parent, dev, busnr); | |
e4ea9bb7 | 447 | if (child) { |
d71374da | 448 | down_write(&pci_bus_sem); |
1da177e4 | 449 | list_add_tail(&child->node, &parent->children); |
d71374da | 450 | up_write(&pci_bus_sem); |
e4ea9bb7 | 451 | } |
1da177e4 LT |
452 | return child; |
453 | } | |
454 | ||
96bde06a | 455 | static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max) |
26f674ae GKH |
456 | { |
457 | struct pci_bus *parent = child->parent; | |
12f44f46 IK |
458 | |
459 | /* Attempts to fix that up are really dangerous unless | |
460 | we're going to re-assign all bus numbers. */ | |
461 | if (!pcibios_assign_all_busses()) | |
462 | return; | |
463 | ||
26f674ae GKH |
464 | while (parent->parent && parent->subordinate < max) { |
465 | parent->subordinate = max; | |
466 | pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max); | |
467 | parent = parent->parent; | |
468 | } | |
469 | } | |
470 | ||
1da177e4 LT |
471 | /* |
472 | * If it's a bridge, configure it and scan the bus behind it. | |
473 | * For CardBus bridges, we don't scan behind as the devices will | |
474 | * be handled by the bridge driver itself. | |
475 | * | |
476 | * We need to process bridges in two passes -- first we scan those | |
477 | * already configured by the BIOS and after we are done with all of | |
478 | * them, we proceed to assigning numbers to the remaining buses in | |
479 | * order to avoid overlaps between old and new bus numbers. | |
480 | */ | |
0ab2b57f | 481 | int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) |
1da177e4 LT |
482 | { |
483 | struct pci_bus *child; | |
484 | int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); | |
49887941 | 485 | u32 buses, i, j = 0; |
1da177e4 | 486 | u16 bctl; |
a1c19894 | 487 | int broken = 0; |
1da177e4 LT |
488 | |
489 | pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); | |
490 | ||
80ccba11 BH |
491 | dev_dbg(&dev->dev, "scanning behind bridge, config %06x, pass %d\n", |
492 | buses & 0xffffff, pass); | |
1da177e4 | 493 | |
a1c19894 BH |
494 | /* Check if setup is sensible at all */ |
495 | if (!pass && | |
496 | ((buses & 0xff) != bus->number || ((buses >> 8) & 0xff) <= bus->number)) { | |
497 | dev_dbg(&dev->dev, "bus configuration invalid, reconfiguring\n"); | |
498 | broken = 1; | |
499 | } | |
500 | ||
1da177e4 LT |
501 | /* Disable MasterAbortMode during probing to avoid reporting |
502 | of bus errors (in some architectures) */ | |
503 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); | |
504 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, | |
505 | bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); | |
506 | ||
a1c19894 | 507 | if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus && !broken) { |
1da177e4 LT |
508 | unsigned int cmax, busnr; |
509 | /* | |
510 | * Bus already configured by firmware, process it in the first | |
511 | * pass and just note the configuration. | |
512 | */ | |
513 | if (pass) | |
bbe8f9a3 | 514 | goto out; |
1da177e4 LT |
515 | busnr = (buses >> 8) & 0xFF; |
516 | ||
517 | /* | |
518 | * If we already got to this bus through a different bridge, | |
74710ded AC |
519 | * don't re-add it. This can happen with the i450NX chipset. |
520 | * | |
521 | * However, we continue to descend down the hierarchy and | |
522 | * scan remaining child buses. | |
1da177e4 | 523 | */ |
74710ded AC |
524 | child = pci_find_bus(pci_domain_nr(bus), busnr); |
525 | if (!child) { | |
526 | child = pci_add_new_bus(bus, dev, busnr); | |
527 | if (!child) | |
528 | goto out; | |
529 | child->primary = buses & 0xFF; | |
530 | child->subordinate = (buses >> 16) & 0xFF; | |
531 | child->bridge_ctl = bctl; | |
1da177e4 LT |
532 | } |
533 | ||
1da177e4 LT |
534 | cmax = pci_scan_child_bus(child); |
535 | if (cmax > max) | |
536 | max = cmax; | |
537 | if (child->subordinate > max) | |
538 | max = child->subordinate; | |
539 | } else { | |
540 | /* | |
541 | * We need to assign a number to this bus which we always | |
542 | * do in the second pass. | |
543 | */ | |
12f44f46 | 544 | if (!pass) { |
a1c19894 | 545 | if (pcibios_assign_all_busses() || broken) |
12f44f46 IK |
546 | /* Temporarily disable forwarding of the |
547 | configuration cycles on all bridges in | |
548 | this bus segment to avoid possible | |
549 | conflicts in the second pass between two | |
550 | bridges programmed with overlapping | |
551 | bus ranges. */ | |
552 | pci_write_config_dword(dev, PCI_PRIMARY_BUS, | |
553 | buses & ~0xffffff); | |
bbe8f9a3 | 554 | goto out; |
12f44f46 | 555 | } |
1da177e4 LT |
556 | |
557 | /* Clear errors */ | |
558 | pci_write_config_word(dev, PCI_STATUS, 0xffff); | |
559 | ||
cc57450f RS |
560 | /* Prevent assigning a bus number that already exists. |
561 | * This can happen when a bridge is hot-plugged */ | |
562 | if (pci_find_bus(pci_domain_nr(bus), max+1)) | |
bbe8f9a3 | 563 | goto out; |
6ef6f0e3 | 564 | child = pci_add_new_bus(bus, dev, ++max); |
1da177e4 LT |
565 | buses = (buses & 0xff000000) |
566 | | ((unsigned int)(child->primary) << 0) | |
567 | | ((unsigned int)(child->secondary) << 8) | |
568 | | ((unsigned int)(child->subordinate) << 16); | |
569 | ||
570 | /* | |
571 | * yenta.c forces a secondary latency timer of 176. | |
572 | * Copy that behaviour here. | |
573 | */ | |
574 | if (is_cardbus) { | |
575 | buses &= ~0xff000000; | |
576 | buses |= CARDBUS_LATENCY_TIMER << 24; | |
577 | } | |
578 | ||
579 | /* | |
580 | * We need to blast all three values with a single write. | |
581 | */ | |
582 | pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); | |
583 | ||
584 | if (!is_cardbus) { | |
11949255 | 585 | child->bridge_ctl = bctl; |
26f674ae GKH |
586 | /* |
587 | * Adjust subordinate busnr in parent buses. | |
588 | * We do this before scanning for children because | |
589 | * some devices may not be detected if the bios | |
590 | * was lazy. | |
591 | */ | |
592 | pci_fixup_parent_subordinate_busnr(child, max); | |
1da177e4 LT |
593 | /* Now we can scan all subordinate buses... */ |
594 | max = pci_scan_child_bus(child); | |
e3ac86d8 KA |
595 | /* |
596 | * now fix it up again since we have found | |
597 | * the real value of max. | |
598 | */ | |
599 | pci_fixup_parent_subordinate_busnr(child, max); | |
1da177e4 LT |
600 | } else { |
601 | /* | |
602 | * For CardBus bridges, we leave 4 bus numbers | |
603 | * as cards with a PCI-to-PCI bridge can be | |
604 | * inserted later. | |
605 | */ | |
49887941 DB |
606 | for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) { |
607 | struct pci_bus *parent = bus; | |
cc57450f RS |
608 | if (pci_find_bus(pci_domain_nr(bus), |
609 | max+i+1)) | |
610 | break; | |
49887941 DB |
611 | while (parent->parent) { |
612 | if ((!pcibios_assign_all_busses()) && | |
613 | (parent->subordinate > max) && | |
614 | (parent->subordinate <= max+i)) { | |
615 | j = 1; | |
616 | } | |
617 | parent = parent->parent; | |
618 | } | |
619 | if (j) { | |
620 | /* | |
621 | * Often, there are two cardbus bridges | |
622 | * -- try to leave one valid bus number | |
623 | * for each one. | |
624 | */ | |
625 | i /= 2; | |
626 | break; | |
627 | } | |
628 | } | |
cc57450f | 629 | max += i; |
26f674ae | 630 | pci_fixup_parent_subordinate_busnr(child, max); |
1da177e4 LT |
631 | } |
632 | /* | |
633 | * Set the subordinate bus number to its real value. | |
634 | */ | |
635 | child->subordinate = max; | |
636 | pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); | |
637 | } | |
638 | ||
cb3576fa GH |
639 | sprintf(child->name, |
640 | (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), | |
641 | pci_domain_nr(bus), child->number); | |
1da177e4 | 642 | |
d55bef51 | 643 | /* Has only triggered on CardBus, fixup is in yenta_socket */ |
49887941 DB |
644 | while (bus->parent) { |
645 | if ((child->subordinate > bus->subordinate) || | |
646 | (child->number > bus->subordinate) || | |
647 | (child->number < bus->number) || | |
648 | (child->subordinate < bus->number)) { | |
a6f29a98 | 649 | pr_debug("PCI: Bus #%02x (-#%02x) is %s " |
d55bef51 BK |
650 | "hidden behind%s bridge #%02x (-#%02x)\n", |
651 | child->number, child->subordinate, | |
652 | (bus->number > child->subordinate && | |
653 | bus->subordinate < child->number) ? | |
a6f29a98 JP |
654 | "wholly" : "partially", |
655 | bus->self->transparent ? " transparent" : "", | |
d55bef51 | 656 | bus->number, bus->subordinate); |
49887941 DB |
657 | } |
658 | bus = bus->parent; | |
659 | } | |
660 | ||
bbe8f9a3 RB |
661 | out: |
662 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl); | |
663 | ||
1da177e4 LT |
664 | return max; |
665 | } | |
666 | ||
667 | /* | |
668 | * Read interrupt line and base address registers. | |
669 | * The architecture-dependent code can tweak these, of course. | |
670 | */ | |
671 | static void pci_read_irq(struct pci_dev *dev) | |
672 | { | |
673 | unsigned char irq; | |
674 | ||
675 | pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); | |
ffeff788 | 676 | dev->pin = irq; |
1da177e4 LT |
677 | if (irq) |
678 | pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); | |
679 | dev->irq = irq; | |
680 | } | |
681 | ||
480b93b7 YZ |
682 | static void set_pcie_port_type(struct pci_dev *pdev) |
683 | { | |
684 | int pos; | |
685 | u16 reg16; | |
686 | ||
687 | pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); | |
688 | if (!pos) | |
689 | return; | |
690 | pdev->is_pcie = 1; | |
691 | pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); | |
692 | pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4; | |
693 | } | |
694 | ||
01abc2aa | 695 | #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) |
76e6a1d6 | 696 | |
1da177e4 LT |
697 | /** |
698 | * pci_setup_device - fill in class and map information of a device | |
699 | * @dev: the device structure to fill | |
700 | * | |
701 | * Initialize the device structure with information about the device's | |
702 | * vendor,class,memory and IO-space addresses,IRQ lines etc. | |
703 | * Called at initialisation of the PCI subsystem and by CardBus services. | |
480b93b7 YZ |
704 | * Returns 0 on success and negative if unknown type of device (not normal, |
705 | * bridge or CardBus). | |
1da177e4 | 706 | */ |
480b93b7 | 707 | int pci_setup_device(struct pci_dev *dev) |
1da177e4 LT |
708 | { |
709 | u32 class; | |
480b93b7 YZ |
710 | u8 hdr_type; |
711 | struct pci_slot *slot; | |
712 | ||
713 | if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type)) | |
714 | return -EIO; | |
715 | ||
716 | dev->sysdata = dev->bus->sysdata; | |
717 | dev->dev.parent = dev->bus->bridge; | |
718 | dev->dev.bus = &pci_bus_type; | |
719 | dev->hdr_type = hdr_type & 0x7f; | |
720 | dev->multifunction = !!(hdr_type & 0x80); | |
480b93b7 YZ |
721 | dev->error_state = pci_channel_io_normal; |
722 | set_pcie_port_type(dev); | |
723 | ||
724 | list_for_each_entry(slot, &dev->bus->slots, list) | |
725 | if (PCI_SLOT(dev->devfn) == slot->number) | |
726 | dev->slot = slot; | |
727 | ||
728 | /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) | |
729 | set this higher, assuming the system even supports it. */ | |
730 | dev->dma_mask = 0xffffffff; | |
1da177e4 | 731 | |
eebfcfb5 GKH |
732 | dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), |
733 | dev->bus->number, PCI_SLOT(dev->devfn), | |
734 | PCI_FUNC(dev->devfn)); | |
1da177e4 LT |
735 | |
736 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); | |
b8a3a521 | 737 | dev->revision = class & 0xff; |
1da177e4 LT |
738 | class >>= 8; /* upper 3 bytes */ |
739 | dev->class = class; | |
740 | class >>= 8; | |
741 | ||
34a2e15e | 742 | dev_dbg(&dev->dev, "found [%04x:%04x] class %06x header type %02x\n", |
1da177e4 LT |
743 | dev->vendor, dev->device, class, dev->hdr_type); |
744 | ||
853346e4 YZ |
745 | /* need to have dev->class ready */ |
746 | dev->cfg_size = pci_cfg_space_size(dev); | |
747 | ||
1da177e4 | 748 | /* "Unknown power state" */ |
3fe9d19f | 749 | dev->current_state = PCI_UNKNOWN; |
1da177e4 LT |
750 | |
751 | /* Early fixups, before probing the BARs */ | |
752 | pci_fixup_device(pci_fixup_early, dev); | |
f79b1b14 YZ |
753 | /* device class may be changed after fixup */ |
754 | class = dev->class >> 8; | |
1da177e4 LT |
755 | |
756 | switch (dev->hdr_type) { /* header type */ | |
757 | case PCI_HEADER_TYPE_NORMAL: /* standard header */ | |
758 | if (class == PCI_CLASS_BRIDGE_PCI) | |
759 | goto bad; | |
760 | pci_read_irq(dev); | |
761 | pci_read_bases(dev, 6, PCI_ROM_ADDRESS); | |
762 | pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); | |
763 | pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device); | |
368c73d4 AC |
764 | |
765 | /* | |
766 | * Do the ugly legacy mode stuff here rather than broken chip | |
767 | * quirk code. Legacy mode ATA controllers have fixed | |
768 | * addresses. These are not always echoed in BAR0-3, and | |
769 | * BAR0-3 in a few cases contain junk! | |
770 | */ | |
771 | if (class == PCI_CLASS_STORAGE_IDE) { | |
772 | u8 progif; | |
773 | pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); | |
774 | if ((progif & 1) == 0) { | |
af1bff4f LT |
775 | dev->resource[0].start = 0x1F0; |
776 | dev->resource[0].end = 0x1F7; | |
777 | dev->resource[0].flags = LEGACY_IO_RESOURCE; | |
778 | dev->resource[1].start = 0x3F6; | |
779 | dev->resource[1].end = 0x3F6; | |
780 | dev->resource[1].flags = LEGACY_IO_RESOURCE; | |
368c73d4 AC |
781 | } |
782 | if ((progif & 4) == 0) { | |
af1bff4f LT |
783 | dev->resource[2].start = 0x170; |
784 | dev->resource[2].end = 0x177; | |
785 | dev->resource[2].flags = LEGACY_IO_RESOURCE; | |
786 | dev->resource[3].start = 0x376; | |
787 | dev->resource[3].end = 0x376; | |
788 | dev->resource[3].flags = LEGACY_IO_RESOURCE; | |
368c73d4 AC |
789 | } |
790 | } | |
1da177e4 LT |
791 | break; |
792 | ||
793 | case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ | |
794 | if (class != PCI_CLASS_BRIDGE_PCI) | |
795 | goto bad; | |
796 | /* The PCI-to-PCI bridge spec requires that subtractive | |
797 | decoding (i.e. transparent) bridge must have programming | |
798 | interface code of 0x01. */ | |
3efd273b | 799 | pci_read_irq(dev); |
1da177e4 LT |
800 | dev->transparent = ((dev->class & 0xff) == 1); |
801 | pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); | |
802 | break; | |
803 | ||
804 | case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ | |
805 | if (class != PCI_CLASS_BRIDGE_CARDBUS) | |
806 | goto bad; | |
807 | pci_read_irq(dev); | |
808 | pci_read_bases(dev, 1, 0); | |
809 | pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); | |
810 | pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); | |
811 | break; | |
812 | ||
813 | default: /* unknown header */ | |
80ccba11 BH |
814 | dev_err(&dev->dev, "unknown header type %02x, " |
815 | "ignoring device\n", dev->hdr_type); | |
480b93b7 | 816 | return -EIO; |
1da177e4 LT |
817 | |
818 | bad: | |
80ccba11 BH |
819 | dev_err(&dev->dev, "ignoring class %02x (doesn't match header " |
820 | "type %02x)\n", class, dev->hdr_type); | |
1da177e4 LT |
821 | dev->class = PCI_CLASS_NOT_DEFINED; |
822 | } | |
823 | ||
824 | /* We found a fine healthy device, go go go... */ | |
825 | return 0; | |
826 | } | |
827 | ||
201de56e ZY |
828 | static void pci_release_capabilities(struct pci_dev *dev) |
829 | { | |
830 | pci_vpd_release(dev); | |
d1b054da | 831 | pci_iov_release(dev); |
201de56e ZY |
832 | } |
833 | ||
1da177e4 LT |
834 | /** |
835 | * pci_release_dev - free a pci device structure when all users of it are finished. | |
836 | * @dev: device that's been disconnected | |
837 | * | |
838 | * Will be called only by the device core when all users of this pci device are | |
839 | * done. | |
840 | */ | |
841 | static void pci_release_dev(struct device *dev) | |
842 | { | |
843 | struct pci_dev *pci_dev; | |
844 | ||
845 | pci_dev = to_pci_dev(dev); | |
201de56e | 846 | pci_release_capabilities(pci_dev); |
1da177e4 LT |
847 | kfree(pci_dev); |
848 | } | |
849 | ||
850 | /** | |
851 | * pci_cfg_space_size - get the configuration space size of the PCI device. | |
8f7020d3 | 852 | * @dev: PCI device |
1da177e4 LT |
853 | * |
854 | * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices | |
855 | * have 4096 bytes. Even if the device is capable, that doesn't mean we can | |
856 | * access it. Maybe we don't have a way to generate extended config space | |
857 | * accesses, or the device is behind a reverse Express bridge. So we try | |
858 | * reading the dword at 0x100 which must either be 0 or a valid extended | |
859 | * capability header. | |
860 | */ | |
70b9f7dc | 861 | int pci_cfg_space_size_ext(struct pci_dev *dev) |
1da177e4 | 862 | { |
1da177e4 | 863 | u32 status; |
557848c3 | 864 | int pos = PCI_CFG_SPACE_SIZE; |
1da177e4 | 865 | |
557848c3 | 866 | if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL) |
70b9f7dc YL |
867 | goto fail; |
868 | if (status == 0xffffffff) | |
869 | goto fail; | |
870 | ||
871 | return PCI_CFG_SPACE_EXP_SIZE; | |
872 | ||
873 | fail: | |
874 | return PCI_CFG_SPACE_SIZE; | |
875 | } | |
876 | ||
877 | int pci_cfg_space_size(struct pci_dev *dev) | |
878 | { | |
879 | int pos; | |
880 | u32 status; | |
dfadd9ed YL |
881 | u16 class; |
882 | ||
883 | class = dev->class >> 8; | |
884 | if (class == PCI_CLASS_BRIDGE_HOST) | |
885 | return pci_cfg_space_size_ext(dev); | |
57741a77 | 886 | |
1da177e4 LT |
887 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); |
888 | if (!pos) { | |
889 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
890 | if (!pos) | |
891 | goto fail; | |
892 | ||
893 | pci_read_config_dword(dev, pos + PCI_X_STATUS, &status); | |
894 | if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))) | |
895 | goto fail; | |
896 | } | |
897 | ||
70b9f7dc | 898 | return pci_cfg_space_size_ext(dev); |
1da177e4 LT |
899 | |
900 | fail: | |
901 | return PCI_CFG_SPACE_SIZE; | |
902 | } | |
903 | ||
904 | static void pci_release_bus_bridge_dev(struct device *dev) | |
905 | { | |
906 | kfree(dev); | |
907 | } | |
908 | ||
65891215 ME |
909 | struct pci_dev *alloc_pci_dev(void) |
910 | { | |
911 | struct pci_dev *dev; | |
912 | ||
913 | dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); | |
914 | if (!dev) | |
915 | return NULL; | |
916 | ||
65891215 ME |
917 | INIT_LIST_HEAD(&dev->bus_list); |
918 | ||
919 | return dev; | |
920 | } | |
921 | EXPORT_SYMBOL(alloc_pci_dev); | |
922 | ||
1da177e4 LT |
923 | /* |
924 | * Read the config data for a PCI device, sanity-check it | |
925 | * and fill in the dev structure... | |
926 | */ | |
7f7b5de2 | 927 | static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) |
1da177e4 LT |
928 | { |
929 | struct pci_dev *dev; | |
930 | u32 l; | |
1da177e4 LT |
931 | int delay = 1; |
932 | ||
933 | if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l)) | |
934 | return NULL; | |
935 | ||
936 | /* some broken boards return 0 or ~0 if a slot is empty: */ | |
937 | if (l == 0xffffffff || l == 0x00000000 || | |
938 | l == 0x0000ffff || l == 0xffff0000) | |
939 | return NULL; | |
940 | ||
941 | /* Configuration request Retry Status */ | |
942 | while (l == 0xffff0001) { | |
943 | msleep(delay); | |
944 | delay *= 2; | |
945 | if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l)) | |
946 | return NULL; | |
947 | /* Card hasn't responded in 60 seconds? Must be stuck. */ | |
948 | if (delay > 60 * 1000) { | |
80ccba11 | 949 | printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not " |
1da177e4 LT |
950 | "responding\n", pci_domain_nr(bus), |
951 | bus->number, PCI_SLOT(devfn), | |
952 | PCI_FUNC(devfn)); | |
953 | return NULL; | |
954 | } | |
955 | } | |
956 | ||
bab41e9b | 957 | dev = alloc_pci_dev(); |
1da177e4 LT |
958 | if (!dev) |
959 | return NULL; | |
960 | ||
1da177e4 | 961 | dev->bus = bus; |
1da177e4 | 962 | dev->devfn = devfn; |
1da177e4 LT |
963 | dev->vendor = l & 0xffff; |
964 | dev->device = (l >> 16) & 0xffff; | |
cef354db | 965 | |
480b93b7 | 966 | if (pci_setup_device(dev)) { |
1da177e4 LT |
967 | kfree(dev); |
968 | return NULL; | |
969 | } | |
1da177e4 LT |
970 | |
971 | return dev; | |
972 | } | |
973 | ||
201de56e ZY |
974 | static void pci_init_capabilities(struct pci_dev *dev) |
975 | { | |
976 | /* MSI/MSI-X list */ | |
977 | pci_msi_init_pci_dev(dev); | |
978 | ||
63f4898a RW |
979 | /* Buffers for saving PCIe and PCI-X capabilities */ |
980 | pci_allocate_cap_save_buffers(dev); | |
981 | ||
201de56e ZY |
982 | /* Power Management */ |
983 | pci_pm_init(dev); | |
eb9c39d0 | 984 | platform_pci_wakeup_init(dev); |
201de56e ZY |
985 | |
986 | /* Vital Product Data */ | |
987 | pci_vpd_pci22_init(dev); | |
58c3a727 YZ |
988 | |
989 | /* Alternative Routing-ID Forwarding */ | |
990 | pci_enable_ari(dev); | |
d1b054da YZ |
991 | |
992 | /* Single Root I/O Virtualization */ | |
993 | pci_iov_init(dev); | |
201de56e ZY |
994 | } |
995 | ||
96bde06a | 996 | void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) |
1da177e4 | 997 | { |
cdb9b9f7 PM |
998 | device_initialize(&dev->dev); |
999 | dev->dev.release = pci_release_dev; | |
1000 | pci_dev_get(dev); | |
1da177e4 | 1001 | |
cdb9b9f7 | 1002 | dev->dev.dma_mask = &dev->dma_mask; |
4d57cdfa | 1003 | dev->dev.dma_parms = &dev->dma_parms; |
cdb9b9f7 | 1004 | dev->dev.coherent_dma_mask = 0xffffffffull; |
1da177e4 | 1005 | |
4d57cdfa | 1006 | pci_set_dma_max_seg_size(dev, 65536); |
59fc67de | 1007 | pci_set_dma_seg_boundary(dev, 0xffffffff); |
4d57cdfa | 1008 | |
1da177e4 LT |
1009 | /* Fix up broken headers */ |
1010 | pci_fixup_device(pci_fixup_header, dev); | |
1011 | ||
201de56e ZY |
1012 | /* Initialize various capabilities */ |
1013 | pci_init_capabilities(dev); | |
eb9d0fe4 | 1014 | |
1da177e4 LT |
1015 | /* |
1016 | * Add the device to our list of discovered devices | |
1017 | * and the bus list for fixup functions, etc. | |
1018 | */ | |
d71374da | 1019 | down_write(&pci_bus_sem); |
1da177e4 | 1020 | list_add_tail(&dev->bus_list, &bus->devices); |
d71374da | 1021 | up_write(&pci_bus_sem); |
cdb9b9f7 PM |
1022 | } |
1023 | ||
451124a7 | 1024 | struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn) |
cdb9b9f7 PM |
1025 | { |
1026 | struct pci_dev *dev; | |
1027 | ||
90bdb311 TP |
1028 | dev = pci_get_slot(bus, devfn); |
1029 | if (dev) { | |
1030 | pci_dev_put(dev); | |
1031 | return dev; | |
1032 | } | |
1033 | ||
cdb9b9f7 PM |
1034 | dev = pci_scan_device(bus, devfn); |
1035 | if (!dev) | |
1036 | return NULL; | |
1037 | ||
1038 | pci_device_add(dev, bus); | |
1da177e4 LT |
1039 | |
1040 | return dev; | |
1041 | } | |
b73e9687 | 1042 | EXPORT_SYMBOL(pci_scan_single_device); |
1da177e4 LT |
1043 | |
1044 | /** | |
1045 | * pci_scan_slot - scan a PCI slot on a bus for devices. | |
1046 | * @bus: PCI bus to scan | |
1047 | * @devfn: slot number to scan (must have zero function.) | |
1048 | * | |
1049 | * Scan a PCI slot on the specified PCI bus for devices, adding | |
1050 | * discovered devices to the @bus->devices list. New devices | |
8a1bc901 | 1051 | * will not have is_added set. |
1b69dfc6 TP |
1052 | * |
1053 | * Returns the number of new devices found. | |
1da177e4 | 1054 | */ |
96bde06a | 1055 | int pci_scan_slot(struct pci_bus *bus, int devfn) |
1da177e4 | 1056 | { |
1b69dfc6 TP |
1057 | int fn, nr = 0; |
1058 | struct pci_dev *dev; | |
1da177e4 | 1059 | |
1b69dfc6 TP |
1060 | dev = pci_scan_single_device(bus, devfn); |
1061 | if (dev && !dev->is_added) /* new device? */ | |
1062 | nr++; | |
1063 | ||
1064 | if ((dev && dev->multifunction) || | |
1065 | (!dev && pcibios_scan_all_fns(bus, devfn))) { | |
1066 | for (fn = 1; fn < 8; fn++) { | |
1067 | dev = pci_scan_single_device(bus, devfn + fn); | |
1068 | if (dev) { | |
1069 | if (!dev->is_added) | |
1070 | nr++; | |
1071 | dev->multifunction = 1; | |
1da177e4 | 1072 | } |
1da177e4 LT |
1073 | } |
1074 | } | |
7d715a6c | 1075 | |
149e1637 SL |
1076 | /* only one slot has pcie device */ |
1077 | if (bus->self && nr) | |
7d715a6c SL |
1078 | pcie_aspm_init_link_state(bus->self); |
1079 | ||
1da177e4 LT |
1080 | return nr; |
1081 | } | |
1082 | ||
0ab2b57f | 1083 | unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus) |
1da177e4 LT |
1084 | { |
1085 | unsigned int devfn, pass, max = bus->secondary; | |
1086 | struct pci_dev *dev; | |
1087 | ||
1088 | pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number); | |
1089 | ||
1090 | /* Go find them, Rover! */ | |
1091 | for (devfn = 0; devfn < 0x100; devfn += 8) | |
1092 | pci_scan_slot(bus, devfn); | |
1093 | ||
a28724b0 YZ |
1094 | /* Reserve buses for SR-IOV capability. */ |
1095 | max += pci_iov_bus_range(bus); | |
1096 | ||
1da177e4 LT |
1097 | /* |
1098 | * After performing arch-dependent fixup of the bus, look behind | |
1099 | * all PCI-to-PCI bridges on this bus. | |
1100 | */ | |
74710ded AC |
1101 | if (!bus->is_added) { |
1102 | pr_debug("PCI: Fixups for bus %04x:%02x\n", | |
1103 | pci_domain_nr(bus), bus->number); | |
1104 | pcibios_fixup_bus(bus); | |
1105 | if (pci_is_root_bus(bus)) | |
1106 | bus->is_added = 1; | |
1107 | } | |
1108 | ||
1da177e4 LT |
1109 | for (pass=0; pass < 2; pass++) |
1110 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1111 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || | |
1112 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) | |
1113 | max = pci_scan_bridge(bus, dev, max, pass); | |
1114 | } | |
1115 | ||
1116 | /* | |
1117 | * We've scanned the bus and so we know all about what's on | |
1118 | * the other side of any bridges that may be on this bus plus | |
1119 | * any devices. | |
1120 | * | |
1121 | * Return how far we've got finding sub-buses. | |
1122 | */ | |
1123 | pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n", | |
1124 | pci_domain_nr(bus), bus->number, max); | |
1125 | return max; | |
1126 | } | |
1127 | ||
96bde06a | 1128 | struct pci_bus * pci_create_bus(struct device *parent, |
cdb9b9f7 | 1129 | int bus, struct pci_ops *ops, void *sysdata) |
1da177e4 LT |
1130 | { |
1131 | int error; | |
1132 | struct pci_bus *b; | |
1133 | struct device *dev; | |
1134 | ||
1135 | b = pci_alloc_bus(); | |
1136 | if (!b) | |
1137 | return NULL; | |
1138 | ||
6a3b3e26 | 1139 | dev = kzalloc(sizeof(*dev), GFP_KERNEL); |
1da177e4 LT |
1140 | if (!dev){ |
1141 | kfree(b); | |
1142 | return NULL; | |
1143 | } | |
1144 | ||
1145 | b->sysdata = sysdata; | |
1146 | b->ops = ops; | |
1147 | ||
1148 | if (pci_find_bus(pci_domain_nr(b), bus)) { | |
1149 | /* If we already got to this bus through a different bridge, ignore it */ | |
1150 | pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus); | |
1151 | goto err_out; | |
1152 | } | |
d71374da ZY |
1153 | |
1154 | down_write(&pci_bus_sem); | |
1da177e4 | 1155 | list_add_tail(&b->node, &pci_root_buses); |
d71374da | 1156 | up_write(&pci_bus_sem); |
1da177e4 | 1157 | |
1da177e4 LT |
1158 | dev->parent = parent; |
1159 | dev->release = pci_release_bus_bridge_dev; | |
1a927133 | 1160 | dev_set_name(dev, "pci%04x:%02x", pci_domain_nr(b), bus); |
1da177e4 LT |
1161 | error = device_register(dev); |
1162 | if (error) | |
1163 | goto dev_reg_err; | |
1164 | b->bridge = get_device(dev); | |
1165 | ||
0d358f22 YL |
1166 | if (!parent) |
1167 | set_dev_node(b->bridge, pcibus_to_node(b)); | |
1168 | ||
fd7d1ced GKH |
1169 | b->dev.class = &pcibus_class; |
1170 | b->dev.parent = b->bridge; | |
1a927133 | 1171 | dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus); |
fd7d1ced | 1172 | error = device_register(&b->dev); |
1da177e4 LT |
1173 | if (error) |
1174 | goto class_dev_reg_err; | |
fd7d1ced | 1175 | error = device_create_file(&b->dev, &dev_attr_cpuaffinity); |
1da177e4 | 1176 | if (error) |
fd7d1ced | 1177 | goto dev_create_file_err; |
1da177e4 LT |
1178 | |
1179 | /* Create legacy_io and legacy_mem files for this bus */ | |
1180 | pci_create_legacy_files(b); | |
1181 | ||
1da177e4 LT |
1182 | b->number = b->secondary = bus; |
1183 | b->resource[0] = &ioport_resource; | |
1184 | b->resource[1] = &iomem_resource; | |
1185 | ||
1da177e4 LT |
1186 | return b; |
1187 | ||
fd7d1ced GKH |
1188 | dev_create_file_err: |
1189 | device_unregister(&b->dev); | |
1da177e4 LT |
1190 | class_dev_reg_err: |
1191 | device_unregister(dev); | |
1192 | dev_reg_err: | |
d71374da | 1193 | down_write(&pci_bus_sem); |
1da177e4 | 1194 | list_del(&b->node); |
d71374da | 1195 | up_write(&pci_bus_sem); |
1da177e4 LT |
1196 | err_out: |
1197 | kfree(dev); | |
1198 | kfree(b); | |
1199 | return NULL; | |
1200 | } | |
cdb9b9f7 | 1201 | |
0ab2b57f | 1202 | struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent, |
cdb9b9f7 PM |
1203 | int bus, struct pci_ops *ops, void *sysdata) |
1204 | { | |
1205 | struct pci_bus *b; | |
1206 | ||
1207 | b = pci_create_bus(parent, bus, ops, sysdata); | |
1208 | if (b) | |
1209 | b->subordinate = pci_scan_child_bus(b); | |
1210 | return b; | |
1211 | } | |
1da177e4 LT |
1212 | EXPORT_SYMBOL(pci_scan_bus_parented); |
1213 | ||
1214 | #ifdef CONFIG_HOTPLUG | |
3ed4fd96 AC |
1215 | /** |
1216 | * pci_rescan_bus - scan a PCI bus for devices. | |
1217 | * @bus: PCI bus to scan | |
1218 | * | |
1219 | * Scan a PCI bus and child buses for new devices, adds them, | |
1220 | * and enables them. | |
1221 | * | |
1222 | * Returns the max number of subordinate bus discovered. | |
1223 | */ | |
5446a6bd | 1224 | unsigned int __ref pci_rescan_bus(struct pci_bus *bus) |
3ed4fd96 AC |
1225 | { |
1226 | unsigned int max; | |
1227 | struct pci_dev *dev; | |
1228 | ||
1229 | max = pci_scan_child_bus(bus); | |
1230 | ||
705b1aaa | 1231 | down_read(&pci_bus_sem); |
3ed4fd96 AC |
1232 | list_for_each_entry(dev, &bus->devices, bus_list) |
1233 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || | |
1234 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) | |
1235 | if (dev->subordinate) | |
1236 | pci_bus_size_bridges(dev->subordinate); | |
705b1aaa | 1237 | up_read(&pci_bus_sem); |
3ed4fd96 AC |
1238 | |
1239 | pci_bus_assign_resources(bus); | |
1240 | pci_enable_bridges(bus); | |
1241 | pci_bus_add_devices(bus); | |
1242 | ||
1243 | return max; | |
1244 | } | |
1245 | EXPORT_SYMBOL_GPL(pci_rescan_bus); | |
1246 | ||
1da177e4 | 1247 | EXPORT_SYMBOL(pci_add_new_bus); |
1da177e4 LT |
1248 | EXPORT_SYMBOL(pci_scan_slot); |
1249 | EXPORT_SYMBOL(pci_scan_bridge); | |
1da177e4 LT |
1250 | EXPORT_SYMBOL_GPL(pci_scan_child_bus); |
1251 | #endif | |
6b4b78fe | 1252 | |
99178b03 | 1253 | static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b) |
6b4b78fe | 1254 | { |
99178b03 GKH |
1255 | const struct pci_dev *a = to_pci_dev(d_a); |
1256 | const struct pci_dev *b = to_pci_dev(d_b); | |
1257 | ||
6b4b78fe MD |
1258 | if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1; |
1259 | else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1; | |
1260 | ||
1261 | if (a->bus->number < b->bus->number) return -1; | |
1262 | else if (a->bus->number > b->bus->number) return 1; | |
1263 | ||
1264 | if (a->devfn < b->devfn) return -1; | |
1265 | else if (a->devfn > b->devfn) return 1; | |
1266 | ||
1267 | return 0; | |
1268 | } | |
1269 | ||
5ff580c1 | 1270 | void __init pci_sort_breadthfirst(void) |
6b4b78fe | 1271 | { |
99178b03 | 1272 | bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp); |
6b4b78fe | 1273 | } |