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Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * probe.c - PCI detection and setup code | |
3 | */ | |
4 | ||
5 | #include <linux/kernel.h> | |
6 | #include <linux/delay.h> | |
7 | #include <linux/init.h> | |
8 | #include <linux/pci.h> | |
9 | #include <linux/slab.h> | |
10 | #include <linux/module.h> | |
11 | #include <linux/cpumask.h> | |
7d715a6c | 12 | #include <linux/pci-aspm.h> |
bc56b9e0 | 13 | #include "pci.h" |
1da177e4 LT |
14 | |
15 | #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ | |
16 | #define CARDBUS_RESERVE_BUSNR 3 | |
1da177e4 | 17 | |
5a21d70d BH |
18 | static LIST_HEAD(pci_host_bridges); |
19 | ||
1da177e4 LT |
20 | /* Ugh. Need to stop exporting this to modules. */ |
21 | LIST_HEAD(pci_root_buses); | |
22 | EXPORT_SYMBOL(pci_root_buses); | |
23 | ||
70308923 GKH |
24 | |
25 | static int find_anything(struct device *dev, void *data) | |
26 | { | |
27 | return 1; | |
28 | } | |
1da177e4 | 29 | |
ed4aaadb ZY |
30 | /* |
31 | * Some device drivers need know if pci is initiated. | |
32 | * Basically, we think pci is not initiated when there | |
70308923 | 33 | * is no device to be found on the pci_bus_type. |
ed4aaadb ZY |
34 | */ |
35 | int no_pci_devices(void) | |
36 | { | |
70308923 GKH |
37 | struct device *dev; |
38 | int no_devices; | |
ed4aaadb | 39 | |
70308923 GKH |
40 | dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything); |
41 | no_devices = (dev == NULL); | |
42 | put_device(dev); | |
43 | return no_devices; | |
44 | } | |
ed4aaadb ZY |
45 | EXPORT_SYMBOL(no_pci_devices); |
46 | ||
5a21d70d BH |
47 | static struct pci_host_bridge *pci_host_bridge(struct pci_dev *dev) |
48 | { | |
49 | struct pci_bus *bus; | |
50 | struct pci_host_bridge *bridge; | |
51 | ||
52 | bus = dev->bus; | |
53 | while (bus->parent) | |
54 | bus = bus->parent; | |
55 | ||
56 | list_for_each_entry(bridge, &pci_host_bridges, list) { | |
57 | if (bridge->bus == bus) | |
58 | return bridge; | |
59 | } | |
60 | ||
61 | return NULL; | |
62 | } | |
63 | ||
5bfa14ed BH |
64 | static bool resource_contains(struct resource *res1, struct resource *res2) |
65 | { | |
66 | return res1->start <= res2->start && res1->end >= res2->end; | |
67 | } | |
68 | ||
fb127cb9 BH |
69 | void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, |
70 | struct resource *res) | |
5bfa14ed BH |
71 | { |
72 | struct pci_host_bridge *bridge = pci_host_bridge(dev); | |
73 | struct pci_host_bridge_window *window; | |
74 | resource_size_t offset = 0; | |
75 | ||
76 | list_for_each_entry(window, &bridge->windows, list) { | |
77 | if (resource_type(res) != resource_type(window->res)) | |
78 | continue; | |
79 | ||
80 | if (resource_contains(window->res, res)) { | |
81 | offset = window->offset; | |
82 | break; | |
83 | } | |
84 | } | |
85 | ||
86 | region->start = res->start - offset; | |
87 | region->end = res->end - offset; | |
88 | } | |
fb127cb9 | 89 | EXPORT_SYMBOL(pcibios_resource_to_bus); |
5bfa14ed BH |
90 | |
91 | static bool region_contains(struct pci_bus_region *region1, | |
92 | struct pci_bus_region *region2) | |
93 | { | |
94 | return region1->start <= region2->start && region1->end >= region2->end; | |
95 | } | |
96 | ||
fb127cb9 BH |
97 | void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, |
98 | struct pci_bus_region *region) | |
5bfa14ed BH |
99 | { |
100 | struct pci_host_bridge *bridge = pci_host_bridge(dev); | |
101 | struct pci_host_bridge_window *window; | |
102 | struct pci_bus_region bus_region; | |
103 | resource_size_t offset = 0; | |
104 | ||
105 | list_for_each_entry(window, &bridge->windows, list) { | |
106 | if (resource_type(res) != resource_type(window->res)) | |
107 | continue; | |
108 | ||
109 | bus_region.start = window->res->start - window->offset; | |
110 | bus_region.end = window->res->end - window->offset; | |
111 | ||
112 | if (region_contains(&bus_region, region)) { | |
113 | offset = window->offset; | |
114 | break; | |
115 | } | |
116 | } | |
117 | ||
118 | res->start = region->start + offset; | |
119 | res->end = region->end + offset; | |
120 | } | |
36a66cd6 | 121 | EXPORT_SYMBOL(pcibios_bus_to_resource); |
36a66cd6 | 122 | |
1da177e4 LT |
123 | /* |
124 | * PCI Bus Class | |
125 | */ | |
fd7d1ced | 126 | static void release_pcibus_dev(struct device *dev) |
1da177e4 | 127 | { |
fd7d1ced | 128 | struct pci_bus *pci_bus = to_pci_bus(dev); |
1da177e4 LT |
129 | |
130 | if (pci_bus->bridge) | |
131 | put_device(pci_bus->bridge); | |
2fe2abf8 | 132 | pci_bus_remove_resources(pci_bus); |
98d9f30c | 133 | pci_release_bus_of_node(pci_bus); |
1da177e4 LT |
134 | kfree(pci_bus); |
135 | } | |
136 | ||
137 | static struct class pcibus_class = { | |
138 | .name = "pci_bus", | |
fd7d1ced | 139 | .dev_release = &release_pcibus_dev, |
b9d320fc | 140 | .dev_attrs = pcibus_dev_attrs, |
1da177e4 LT |
141 | }; |
142 | ||
143 | static int __init pcibus_class_init(void) | |
144 | { | |
145 | return class_register(&pcibus_class); | |
146 | } | |
147 | postcore_initcall(pcibus_class_init); | |
148 | ||
6ac665c6 | 149 | static u64 pci_size(u64 base, u64 maxbase, u64 mask) |
1da177e4 | 150 | { |
6ac665c6 | 151 | u64 size = mask & maxbase; /* Find the significant bits */ |
1da177e4 LT |
152 | if (!size) |
153 | return 0; | |
154 | ||
155 | /* Get the lowest of them to find the decode size, and | |
156 | from that the extent. */ | |
157 | size = (size & ~(size-1)) - 1; | |
158 | ||
159 | /* base == maxbase can be valid only if the BAR has | |
160 | already been programmed with all 1s. */ | |
161 | if (base == maxbase && ((base | size) & mask) != mask) | |
162 | return 0; | |
163 | ||
164 | return size; | |
165 | } | |
166 | ||
28c6821a | 167 | static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar) |
6ac665c6 | 168 | { |
8d6a6a47 | 169 | u32 mem_type; |
28c6821a | 170 | unsigned long flags; |
8d6a6a47 | 171 | |
6ac665c6 | 172 | if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { |
28c6821a BH |
173 | flags = bar & ~PCI_BASE_ADDRESS_IO_MASK; |
174 | flags |= IORESOURCE_IO; | |
175 | return flags; | |
6ac665c6 | 176 | } |
07eddf3d | 177 | |
28c6821a BH |
178 | flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK; |
179 | flags |= IORESOURCE_MEM; | |
180 | if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) | |
181 | flags |= IORESOURCE_PREFETCH; | |
07eddf3d | 182 | |
8d6a6a47 BH |
183 | mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK; |
184 | switch (mem_type) { | |
185 | case PCI_BASE_ADDRESS_MEM_TYPE_32: | |
186 | break; | |
187 | case PCI_BASE_ADDRESS_MEM_TYPE_1M: | |
188 | dev_info(&dev->dev, "1M mem BAR treated as 32-bit BAR\n"); | |
189 | break; | |
190 | case PCI_BASE_ADDRESS_MEM_TYPE_64: | |
28c6821a BH |
191 | flags |= IORESOURCE_MEM_64; |
192 | break; | |
8d6a6a47 BH |
193 | default: |
194 | dev_warn(&dev->dev, | |
195 | "mem unknown type %x treated as 32-bit BAR\n", | |
196 | mem_type); | |
197 | break; | |
198 | } | |
28c6821a | 199 | return flags; |
07eddf3d YL |
200 | } |
201 | ||
0b400c7e YZ |
202 | /** |
203 | * pci_read_base - read a PCI BAR | |
204 | * @dev: the PCI device | |
205 | * @type: type of the BAR | |
206 | * @res: resource buffer to be filled in | |
207 | * @pos: BAR position in the config space | |
208 | * | |
209 | * Returns 1 if the BAR is 64-bit, or 0 if 32-bit. | |
6ac665c6 | 210 | */ |
0b400c7e | 211 | int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, |
6ac665c6 | 212 | struct resource *res, unsigned int pos) |
07eddf3d | 213 | { |
6ac665c6 | 214 | u32 l, sz, mask; |
253d2e54 | 215 | u16 orig_cmd; |
5bfa14ed | 216 | struct pci_bus_region region; |
6ac665c6 | 217 | |
1ed67439 | 218 | mask = type ? PCI_ROM_ADDRESS_MASK : ~0; |
6ac665c6 | 219 | |
253d2e54 JP |
220 | if (!dev->mmio_always_on) { |
221 | pci_read_config_word(dev, PCI_COMMAND, &orig_cmd); | |
222 | pci_write_config_word(dev, PCI_COMMAND, | |
223 | orig_cmd & ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); | |
224 | } | |
225 | ||
6ac665c6 MW |
226 | res->name = pci_name(dev); |
227 | ||
228 | pci_read_config_dword(dev, pos, &l); | |
1ed67439 | 229 | pci_write_config_dword(dev, pos, l | mask); |
6ac665c6 MW |
230 | pci_read_config_dword(dev, pos, &sz); |
231 | pci_write_config_dword(dev, pos, l); | |
232 | ||
253d2e54 JP |
233 | if (!dev->mmio_always_on) |
234 | pci_write_config_word(dev, PCI_COMMAND, orig_cmd); | |
235 | ||
6ac665c6 MW |
236 | /* |
237 | * All bits set in sz means the device isn't working properly. | |
45aa23b4 BH |
238 | * If the BAR isn't implemented, all bits must be 0. If it's a |
239 | * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit | |
240 | * 1 must be clear. | |
6ac665c6 | 241 | */ |
45aa23b4 | 242 | if (!sz || sz == 0xffffffff) |
6ac665c6 MW |
243 | goto fail; |
244 | ||
245 | /* | |
246 | * I don't know how l can have all bits set. Copied from old code. | |
247 | * Maybe it fixes a bug on some ancient platform. | |
248 | */ | |
249 | if (l == 0xffffffff) | |
250 | l = 0; | |
251 | ||
252 | if (type == pci_bar_unknown) { | |
28c6821a BH |
253 | res->flags = decode_bar(dev, l); |
254 | res->flags |= IORESOURCE_SIZEALIGN; | |
255 | if (res->flags & IORESOURCE_IO) { | |
6ac665c6 | 256 | l &= PCI_BASE_ADDRESS_IO_MASK; |
5aceca9d | 257 | mask = PCI_BASE_ADDRESS_IO_MASK & (u32) IO_SPACE_LIMIT; |
6ac665c6 MW |
258 | } else { |
259 | l &= PCI_BASE_ADDRESS_MEM_MASK; | |
260 | mask = (u32)PCI_BASE_ADDRESS_MEM_MASK; | |
261 | } | |
262 | } else { | |
263 | res->flags |= (l & IORESOURCE_ROM_ENABLE); | |
264 | l &= PCI_ROM_ADDRESS_MASK; | |
265 | mask = (u32)PCI_ROM_ADDRESS_MASK; | |
266 | } | |
267 | ||
28c6821a | 268 | if (res->flags & IORESOURCE_MEM_64) { |
6ac665c6 MW |
269 | u64 l64 = l; |
270 | u64 sz64 = sz; | |
271 | u64 mask64 = mask | (u64)~0 << 32; | |
272 | ||
273 | pci_read_config_dword(dev, pos + 4, &l); | |
274 | pci_write_config_dword(dev, pos + 4, ~0); | |
275 | pci_read_config_dword(dev, pos + 4, &sz); | |
276 | pci_write_config_dword(dev, pos + 4, l); | |
277 | ||
278 | l64 |= ((u64)l << 32); | |
279 | sz64 |= ((u64)sz << 32); | |
280 | ||
281 | sz64 = pci_size(l64, sz64, mask64); | |
282 | ||
283 | if (!sz64) | |
284 | goto fail; | |
285 | ||
cc5499c3 | 286 | if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) { |
865df576 BH |
287 | dev_err(&dev->dev, "reg %x: can't handle 64-bit BAR\n", |
288 | pos); | |
6ac665c6 | 289 | goto fail; |
c7dabef8 BH |
290 | } |
291 | ||
c7dabef8 | 292 | if ((sizeof(resource_size_t) < 8) && l) { |
6ac665c6 MW |
293 | /* Address above 32-bit boundary; disable the BAR */ |
294 | pci_write_config_dword(dev, pos, 0); | |
295 | pci_write_config_dword(dev, pos + 4, 0); | |
5bfa14ed BH |
296 | region.start = 0; |
297 | region.end = sz64; | |
fb127cb9 | 298 | pcibios_bus_to_resource(dev, res, ®ion); |
6ac665c6 | 299 | } else { |
5bfa14ed BH |
300 | region.start = l64; |
301 | region.end = l64 + sz64; | |
fb127cb9 | 302 | pcibios_bus_to_resource(dev, res, ®ion); |
c7dabef8 | 303 | dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", |
a369c791 | 304 | pos, res); |
6ac665c6 MW |
305 | } |
306 | } else { | |
45aa23b4 | 307 | sz = pci_size(l, sz, mask); |
6ac665c6 | 308 | |
45aa23b4 | 309 | if (!sz) |
6ac665c6 MW |
310 | goto fail; |
311 | ||
5bfa14ed BH |
312 | region.start = l; |
313 | region.end = l + sz; | |
fb127cb9 | 314 | pcibios_bus_to_resource(dev, res, ®ion); |
f393d9b1 | 315 | |
c7dabef8 | 316 | dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", pos, res); |
6ac665c6 MW |
317 | } |
318 | ||
319 | out: | |
28c6821a | 320 | return (res->flags & IORESOURCE_MEM_64) ? 1 : 0; |
6ac665c6 MW |
321 | fail: |
322 | res->flags = 0; | |
323 | goto out; | |
07eddf3d YL |
324 | } |
325 | ||
1da177e4 LT |
326 | static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) |
327 | { | |
6ac665c6 | 328 | unsigned int pos, reg; |
07eddf3d | 329 | |
6ac665c6 MW |
330 | for (pos = 0; pos < howmany; pos++) { |
331 | struct resource *res = &dev->resource[pos]; | |
1da177e4 | 332 | reg = PCI_BASE_ADDRESS_0 + (pos << 2); |
6ac665c6 | 333 | pos += __pci_read_base(dev, pci_bar_unknown, res, reg); |
1da177e4 | 334 | } |
6ac665c6 | 335 | |
1da177e4 | 336 | if (rom) { |
6ac665c6 | 337 | struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; |
1da177e4 | 338 | dev->rom_base_reg = rom; |
6ac665c6 MW |
339 | res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | |
340 | IORESOURCE_READONLY | IORESOURCE_CACHEABLE | | |
341 | IORESOURCE_SIZEALIGN; | |
342 | __pci_read_base(dev, pci_bar_mem32, res, rom); | |
1da177e4 LT |
343 | } |
344 | } | |
345 | ||
fa27b2d1 | 346 | static void __devinit pci_read_bridge_io(struct pci_bus *child) |
1da177e4 LT |
347 | { |
348 | struct pci_dev *dev = child->self; | |
349 | u8 io_base_lo, io_limit_lo; | |
1da177e4 | 350 | unsigned long base, limit; |
5bfa14ed BH |
351 | struct pci_bus_region region; |
352 | struct resource *res, res2; | |
1da177e4 | 353 | |
1da177e4 LT |
354 | res = child->resource[0]; |
355 | pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); | |
356 | pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); | |
357 | base = (io_base_lo & PCI_IO_RANGE_MASK) << 8; | |
358 | limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8; | |
359 | ||
360 | if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { | |
361 | u16 io_base_hi, io_limit_hi; | |
362 | pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); | |
363 | pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); | |
364 | base |= (io_base_hi << 16); | |
365 | limit |= (io_limit_hi << 16); | |
366 | } | |
367 | ||
cd81e1ea | 368 | if (base && base <= limit) { |
1da177e4 | 369 | res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; |
5bfa14ed BH |
370 | region.start = base; |
371 | region.end = limit + 0xfff; | |
fb127cb9 | 372 | pcibios_bus_to_resource(dev, &res2, ®ion); |
9d265124 | 373 | if (!res->start) |
5bfa14ed | 374 | res->start = res2.start; |
9d265124 | 375 | if (!res->end) |
5bfa14ed | 376 | res->end = res2.end; |
c7dabef8 | 377 | dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); |
1da177e4 | 378 | } |
fa27b2d1 BH |
379 | } |
380 | ||
381 | static void __devinit pci_read_bridge_mmio(struct pci_bus *child) | |
382 | { | |
383 | struct pci_dev *dev = child->self; | |
384 | u16 mem_base_lo, mem_limit_lo; | |
385 | unsigned long base, limit; | |
5bfa14ed | 386 | struct pci_bus_region region; |
fa27b2d1 | 387 | struct resource *res; |
1da177e4 LT |
388 | |
389 | res = child->resource[1]; | |
390 | pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); | |
391 | pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); | |
392 | base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; | |
393 | limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; | |
cd81e1ea | 394 | if (base && base <= limit) { |
1da177e4 | 395 | res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; |
5bfa14ed BH |
396 | region.start = base; |
397 | region.end = limit + 0xfffff; | |
fb127cb9 | 398 | pcibios_bus_to_resource(dev, res, ®ion); |
c7dabef8 | 399 | dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); |
1da177e4 | 400 | } |
fa27b2d1 BH |
401 | } |
402 | ||
403 | static void __devinit pci_read_bridge_mmio_pref(struct pci_bus *child) | |
404 | { | |
405 | struct pci_dev *dev = child->self; | |
406 | u16 mem_base_lo, mem_limit_lo; | |
407 | unsigned long base, limit; | |
5bfa14ed | 408 | struct pci_bus_region region; |
fa27b2d1 | 409 | struct resource *res; |
1da177e4 LT |
410 | |
411 | res = child->resource[2]; | |
412 | pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); | |
413 | pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); | |
414 | base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; | |
415 | limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; | |
416 | ||
417 | if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { | |
418 | u32 mem_base_hi, mem_limit_hi; | |
419 | pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); | |
420 | pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); | |
421 | ||
422 | /* | |
423 | * Some bridges set the base > limit by default, and some | |
424 | * (broken) BIOSes do not initialize them. If we find | |
425 | * this, just assume they are not being used. | |
426 | */ | |
427 | if (mem_base_hi <= mem_limit_hi) { | |
428 | #if BITS_PER_LONG == 64 | |
429 | base |= ((long) mem_base_hi) << 32; | |
430 | limit |= ((long) mem_limit_hi) << 32; | |
431 | #else | |
432 | if (mem_base_hi || mem_limit_hi) { | |
80ccba11 BH |
433 | dev_err(&dev->dev, "can't handle 64-bit " |
434 | "address space for bridge\n"); | |
1da177e4 LT |
435 | return; |
436 | } | |
437 | #endif | |
438 | } | |
439 | } | |
cd81e1ea | 440 | if (base && base <= limit) { |
1f82de10 YL |
441 | res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) | |
442 | IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
443 | if (res->flags & PCI_PREF_RANGE_TYPE_64) | |
444 | res->flags |= IORESOURCE_MEM_64; | |
5bfa14ed BH |
445 | region.start = base; |
446 | region.end = limit + 0xfffff; | |
fb127cb9 | 447 | pcibios_bus_to_resource(dev, res, ®ion); |
c7dabef8 | 448 | dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); |
1da177e4 LT |
449 | } |
450 | } | |
451 | ||
fa27b2d1 BH |
452 | void __devinit pci_read_bridge_bases(struct pci_bus *child) |
453 | { | |
454 | struct pci_dev *dev = child->self; | |
2fe2abf8 | 455 | struct resource *res; |
fa27b2d1 BH |
456 | int i; |
457 | ||
458 | if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */ | |
459 | return; | |
460 | ||
461 | dev_info(&dev->dev, "PCI bridge to [bus %02x-%02x]%s\n", | |
462 | child->secondary, child->subordinate, | |
463 | dev->transparent ? " (subtractive decode)" : ""); | |
464 | ||
2fe2abf8 BH |
465 | pci_bus_remove_resources(child); |
466 | for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) | |
467 | child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; | |
468 | ||
fa27b2d1 BH |
469 | pci_read_bridge_io(child); |
470 | pci_read_bridge_mmio(child); | |
471 | pci_read_bridge_mmio_pref(child); | |
2adf7516 BH |
472 | |
473 | if (dev->transparent) { | |
2fe2abf8 BH |
474 | pci_bus_for_each_resource(child->parent, res, i) { |
475 | if (res) { | |
476 | pci_bus_add_resource(child, res, | |
477 | PCI_SUBTRACTIVE_DECODE); | |
2adf7516 BH |
478 | dev_printk(KERN_DEBUG, &dev->dev, |
479 | " bridge window %pR (subtractive decode)\n", | |
2fe2abf8 BH |
480 | res); |
481 | } | |
2adf7516 BH |
482 | } |
483 | } | |
fa27b2d1 BH |
484 | } |
485 | ||
96bde06a | 486 | static struct pci_bus * pci_alloc_bus(void) |
1da177e4 LT |
487 | { |
488 | struct pci_bus *b; | |
489 | ||
f5afe806 | 490 | b = kzalloc(sizeof(*b), GFP_KERNEL); |
1da177e4 | 491 | if (b) { |
1da177e4 LT |
492 | INIT_LIST_HEAD(&b->node); |
493 | INIT_LIST_HEAD(&b->children); | |
494 | INIT_LIST_HEAD(&b->devices); | |
f46753c5 | 495 | INIT_LIST_HEAD(&b->slots); |
2fe2abf8 | 496 | INIT_LIST_HEAD(&b->resources); |
3749c51a MW |
497 | b->max_bus_speed = PCI_SPEED_UNKNOWN; |
498 | b->cur_bus_speed = PCI_SPEED_UNKNOWN; | |
1da177e4 LT |
499 | } |
500 | return b; | |
501 | } | |
502 | ||
9be60ca0 MW |
503 | static unsigned char pcix_bus_speed[] = { |
504 | PCI_SPEED_UNKNOWN, /* 0 */ | |
505 | PCI_SPEED_66MHz_PCIX, /* 1 */ | |
506 | PCI_SPEED_100MHz_PCIX, /* 2 */ | |
507 | PCI_SPEED_133MHz_PCIX, /* 3 */ | |
508 | PCI_SPEED_UNKNOWN, /* 4 */ | |
509 | PCI_SPEED_66MHz_PCIX_ECC, /* 5 */ | |
510 | PCI_SPEED_100MHz_PCIX_ECC, /* 6 */ | |
511 | PCI_SPEED_133MHz_PCIX_ECC, /* 7 */ | |
512 | PCI_SPEED_UNKNOWN, /* 8 */ | |
513 | PCI_SPEED_66MHz_PCIX_266, /* 9 */ | |
514 | PCI_SPEED_100MHz_PCIX_266, /* A */ | |
515 | PCI_SPEED_133MHz_PCIX_266, /* B */ | |
516 | PCI_SPEED_UNKNOWN, /* C */ | |
517 | PCI_SPEED_66MHz_PCIX_533, /* D */ | |
518 | PCI_SPEED_100MHz_PCIX_533, /* E */ | |
519 | PCI_SPEED_133MHz_PCIX_533 /* F */ | |
520 | }; | |
521 | ||
3749c51a MW |
522 | static unsigned char pcie_link_speed[] = { |
523 | PCI_SPEED_UNKNOWN, /* 0 */ | |
524 | PCIE_SPEED_2_5GT, /* 1 */ | |
525 | PCIE_SPEED_5_0GT, /* 2 */ | |
9dfd97fe | 526 | PCIE_SPEED_8_0GT, /* 3 */ |
3749c51a MW |
527 | PCI_SPEED_UNKNOWN, /* 4 */ |
528 | PCI_SPEED_UNKNOWN, /* 5 */ | |
529 | PCI_SPEED_UNKNOWN, /* 6 */ | |
530 | PCI_SPEED_UNKNOWN, /* 7 */ | |
531 | PCI_SPEED_UNKNOWN, /* 8 */ | |
532 | PCI_SPEED_UNKNOWN, /* 9 */ | |
533 | PCI_SPEED_UNKNOWN, /* A */ | |
534 | PCI_SPEED_UNKNOWN, /* B */ | |
535 | PCI_SPEED_UNKNOWN, /* C */ | |
536 | PCI_SPEED_UNKNOWN, /* D */ | |
537 | PCI_SPEED_UNKNOWN, /* E */ | |
538 | PCI_SPEED_UNKNOWN /* F */ | |
539 | }; | |
540 | ||
541 | void pcie_update_link_speed(struct pci_bus *bus, u16 linksta) | |
542 | { | |
543 | bus->cur_bus_speed = pcie_link_speed[linksta & 0xf]; | |
544 | } | |
545 | EXPORT_SYMBOL_GPL(pcie_update_link_speed); | |
546 | ||
45b4cdd5 MW |
547 | static unsigned char agp_speeds[] = { |
548 | AGP_UNKNOWN, | |
549 | AGP_1X, | |
550 | AGP_2X, | |
551 | AGP_4X, | |
552 | AGP_8X | |
553 | }; | |
554 | ||
555 | static enum pci_bus_speed agp_speed(int agp3, int agpstat) | |
556 | { | |
557 | int index = 0; | |
558 | ||
559 | if (agpstat & 4) | |
560 | index = 3; | |
561 | else if (agpstat & 2) | |
562 | index = 2; | |
563 | else if (agpstat & 1) | |
564 | index = 1; | |
565 | else | |
566 | goto out; | |
567 | ||
568 | if (agp3) { | |
569 | index += 2; | |
570 | if (index == 5) | |
571 | index = 0; | |
572 | } | |
573 | ||
574 | out: | |
575 | return agp_speeds[index]; | |
576 | } | |
577 | ||
578 | ||
9be60ca0 MW |
579 | static void pci_set_bus_speed(struct pci_bus *bus) |
580 | { | |
581 | struct pci_dev *bridge = bus->self; | |
582 | int pos; | |
583 | ||
45b4cdd5 MW |
584 | pos = pci_find_capability(bridge, PCI_CAP_ID_AGP); |
585 | if (!pos) | |
586 | pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3); | |
587 | if (pos) { | |
588 | u32 agpstat, agpcmd; | |
589 | ||
590 | pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat); | |
591 | bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7); | |
592 | ||
593 | pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd); | |
594 | bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7); | |
595 | } | |
596 | ||
9be60ca0 MW |
597 | pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); |
598 | if (pos) { | |
599 | u16 status; | |
600 | enum pci_bus_speed max; | |
601 | pci_read_config_word(bridge, pos + 2, &status); | |
602 | ||
603 | if (status & 0x8000) { | |
604 | max = PCI_SPEED_133MHz_PCIX_533; | |
605 | } else if (status & 0x4000) { | |
606 | max = PCI_SPEED_133MHz_PCIX_266; | |
607 | } else if (status & 0x0002) { | |
608 | if (((status >> 12) & 0x3) == 2) { | |
609 | max = PCI_SPEED_133MHz_PCIX_ECC; | |
610 | } else { | |
611 | max = PCI_SPEED_133MHz_PCIX; | |
612 | } | |
613 | } else { | |
614 | max = PCI_SPEED_66MHz_PCIX; | |
615 | } | |
616 | ||
617 | bus->max_bus_speed = max; | |
618 | bus->cur_bus_speed = pcix_bus_speed[(status >> 6) & 0xf]; | |
619 | ||
620 | return; | |
621 | } | |
622 | ||
623 | pos = pci_find_capability(bridge, PCI_CAP_ID_EXP); | |
624 | if (pos) { | |
625 | u32 linkcap; | |
626 | u16 linksta; | |
627 | ||
628 | pci_read_config_dword(bridge, pos + PCI_EXP_LNKCAP, &linkcap); | |
629 | bus->max_bus_speed = pcie_link_speed[linkcap & 0xf]; | |
630 | ||
631 | pci_read_config_word(bridge, pos + PCI_EXP_LNKSTA, &linksta); | |
632 | pcie_update_link_speed(bus, linksta); | |
633 | } | |
634 | } | |
635 | ||
636 | ||
cbd4e055 AB |
637 | static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, |
638 | struct pci_dev *bridge, int busnr) | |
1da177e4 LT |
639 | { |
640 | struct pci_bus *child; | |
641 | int i; | |
642 | ||
643 | /* | |
644 | * Allocate a new bus, and inherit stuff from the parent.. | |
645 | */ | |
646 | child = pci_alloc_bus(); | |
647 | if (!child) | |
648 | return NULL; | |
649 | ||
1da177e4 LT |
650 | child->parent = parent; |
651 | child->ops = parent->ops; | |
652 | child->sysdata = parent->sysdata; | |
6e325a62 | 653 | child->bus_flags = parent->bus_flags; |
1da177e4 | 654 | |
fd7d1ced GKH |
655 | /* initialize some portions of the bus device, but don't register it |
656 | * now as the parent is not properly set up yet. This device will get | |
657 | * registered later in pci_bus_add_devices() | |
658 | */ | |
659 | child->dev.class = &pcibus_class; | |
1a927133 | 660 | dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr); |
1da177e4 LT |
661 | |
662 | /* | |
663 | * Set up the primary, secondary and subordinate | |
664 | * bus numbers. | |
665 | */ | |
666 | child->number = child->secondary = busnr; | |
667 | child->primary = parent->secondary; | |
668 | child->subordinate = 0xff; | |
669 | ||
3789fa8a YZ |
670 | if (!bridge) |
671 | return child; | |
672 | ||
673 | child->self = bridge; | |
674 | child->bridge = get_device(&bridge->dev); | |
98d9f30c | 675 | pci_set_bus_of_node(child); |
9be60ca0 MW |
676 | pci_set_bus_speed(child); |
677 | ||
1da177e4 | 678 | /* Set up default resource pointers and names.. */ |
fde09c6d | 679 | for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { |
1da177e4 LT |
680 | child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; |
681 | child->resource[i]->name = child->name; | |
682 | } | |
683 | bridge->subordinate = child; | |
684 | ||
685 | return child; | |
686 | } | |
687 | ||
451124a7 | 688 | struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr) |
1da177e4 LT |
689 | { |
690 | struct pci_bus *child; | |
691 | ||
692 | child = pci_alloc_child_bus(parent, dev, busnr); | |
e4ea9bb7 | 693 | if (child) { |
d71374da | 694 | down_write(&pci_bus_sem); |
1da177e4 | 695 | list_add_tail(&child->node, &parent->children); |
d71374da | 696 | up_write(&pci_bus_sem); |
e4ea9bb7 | 697 | } |
1da177e4 LT |
698 | return child; |
699 | } | |
700 | ||
96bde06a | 701 | static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max) |
26f674ae GKH |
702 | { |
703 | struct pci_bus *parent = child->parent; | |
12f44f46 IK |
704 | |
705 | /* Attempts to fix that up are really dangerous unless | |
706 | we're going to re-assign all bus numbers. */ | |
707 | if (!pcibios_assign_all_busses()) | |
708 | return; | |
709 | ||
26f674ae GKH |
710 | while (parent->parent && parent->subordinate < max) { |
711 | parent->subordinate = max; | |
712 | pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max); | |
713 | parent = parent->parent; | |
714 | } | |
715 | } | |
716 | ||
1da177e4 LT |
717 | /* |
718 | * If it's a bridge, configure it and scan the bus behind it. | |
719 | * For CardBus bridges, we don't scan behind as the devices will | |
720 | * be handled by the bridge driver itself. | |
721 | * | |
722 | * We need to process bridges in two passes -- first we scan those | |
723 | * already configured by the BIOS and after we are done with all of | |
724 | * them, we proceed to assigning numbers to the remaining buses in | |
725 | * order to avoid overlaps between old and new bus numbers. | |
726 | */ | |
0ab2b57f | 727 | int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) |
1da177e4 LT |
728 | { |
729 | struct pci_bus *child; | |
730 | int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); | |
49887941 | 731 | u32 buses, i, j = 0; |
1da177e4 | 732 | u16 bctl; |
99ddd552 | 733 | u8 primary, secondary, subordinate; |
a1c19894 | 734 | int broken = 0; |
1da177e4 LT |
735 | |
736 | pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); | |
99ddd552 BH |
737 | primary = buses & 0xFF; |
738 | secondary = (buses >> 8) & 0xFF; | |
739 | subordinate = (buses >> 16) & 0xFF; | |
1da177e4 | 740 | |
99ddd552 BH |
741 | dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n", |
742 | secondary, subordinate, pass); | |
1da177e4 | 743 | |
71f6bd4a YL |
744 | if (!primary && (primary != bus->number) && secondary && subordinate) { |
745 | dev_warn(&dev->dev, "Primary bus is hard wired to 0\n"); | |
746 | primary = bus->number; | |
747 | } | |
748 | ||
a1c19894 BH |
749 | /* Check if setup is sensible at all */ |
750 | if (!pass && | |
99ddd552 | 751 | (primary != bus->number || secondary <= bus->number)) { |
a1c19894 BH |
752 | dev_dbg(&dev->dev, "bus configuration invalid, reconfiguring\n"); |
753 | broken = 1; | |
754 | } | |
755 | ||
1da177e4 LT |
756 | /* Disable MasterAbortMode during probing to avoid reporting |
757 | of bus errors (in some architectures) */ | |
758 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); | |
759 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, | |
760 | bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); | |
761 | ||
99ddd552 BH |
762 | if ((secondary || subordinate) && !pcibios_assign_all_busses() && |
763 | !is_cardbus && !broken) { | |
764 | unsigned int cmax; | |
1da177e4 LT |
765 | /* |
766 | * Bus already configured by firmware, process it in the first | |
767 | * pass and just note the configuration. | |
768 | */ | |
769 | if (pass) | |
bbe8f9a3 | 770 | goto out; |
1da177e4 LT |
771 | |
772 | /* | |
773 | * If we already got to this bus through a different bridge, | |
74710ded AC |
774 | * don't re-add it. This can happen with the i450NX chipset. |
775 | * | |
776 | * However, we continue to descend down the hierarchy and | |
777 | * scan remaining child buses. | |
1da177e4 | 778 | */ |
99ddd552 | 779 | child = pci_find_bus(pci_domain_nr(bus), secondary); |
74710ded | 780 | if (!child) { |
99ddd552 | 781 | child = pci_add_new_bus(bus, dev, secondary); |
74710ded AC |
782 | if (!child) |
783 | goto out; | |
99ddd552 BH |
784 | child->primary = primary; |
785 | child->subordinate = subordinate; | |
74710ded | 786 | child->bridge_ctl = bctl; |
1da177e4 LT |
787 | } |
788 | ||
1da177e4 LT |
789 | cmax = pci_scan_child_bus(child); |
790 | if (cmax > max) | |
791 | max = cmax; | |
792 | if (child->subordinate > max) | |
793 | max = child->subordinate; | |
794 | } else { | |
795 | /* | |
796 | * We need to assign a number to this bus which we always | |
797 | * do in the second pass. | |
798 | */ | |
12f44f46 | 799 | if (!pass) { |
a1c19894 | 800 | if (pcibios_assign_all_busses() || broken) |
12f44f46 IK |
801 | /* Temporarily disable forwarding of the |
802 | configuration cycles on all bridges in | |
803 | this bus segment to avoid possible | |
804 | conflicts in the second pass between two | |
805 | bridges programmed with overlapping | |
806 | bus ranges. */ | |
807 | pci_write_config_dword(dev, PCI_PRIMARY_BUS, | |
808 | buses & ~0xffffff); | |
bbe8f9a3 | 809 | goto out; |
12f44f46 | 810 | } |
1da177e4 LT |
811 | |
812 | /* Clear errors */ | |
813 | pci_write_config_word(dev, PCI_STATUS, 0xffff); | |
814 | ||
cc57450f | 815 | /* Prevent assigning a bus number that already exists. |
b1a98b69 TC |
816 | * This can happen when a bridge is hot-plugged, so in |
817 | * this case we only re-scan this bus. */ | |
818 | child = pci_find_bus(pci_domain_nr(bus), max+1); | |
819 | if (!child) { | |
820 | child = pci_add_new_bus(bus, dev, ++max); | |
821 | if (!child) | |
822 | goto out; | |
823 | } | |
1da177e4 LT |
824 | buses = (buses & 0xff000000) |
825 | | ((unsigned int)(child->primary) << 0) | |
826 | | ((unsigned int)(child->secondary) << 8) | |
827 | | ((unsigned int)(child->subordinate) << 16); | |
828 | ||
829 | /* | |
830 | * yenta.c forces a secondary latency timer of 176. | |
831 | * Copy that behaviour here. | |
832 | */ | |
833 | if (is_cardbus) { | |
834 | buses &= ~0xff000000; | |
835 | buses |= CARDBUS_LATENCY_TIMER << 24; | |
836 | } | |
7c867c88 | 837 | |
1da177e4 LT |
838 | /* |
839 | * We need to blast all three values with a single write. | |
840 | */ | |
841 | pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); | |
842 | ||
843 | if (!is_cardbus) { | |
11949255 | 844 | child->bridge_ctl = bctl; |
26f674ae GKH |
845 | /* |
846 | * Adjust subordinate busnr in parent buses. | |
847 | * We do this before scanning for children because | |
848 | * some devices may not be detected if the bios | |
849 | * was lazy. | |
850 | */ | |
851 | pci_fixup_parent_subordinate_busnr(child, max); | |
1da177e4 LT |
852 | /* Now we can scan all subordinate buses... */ |
853 | max = pci_scan_child_bus(child); | |
e3ac86d8 KA |
854 | /* |
855 | * now fix it up again since we have found | |
856 | * the real value of max. | |
857 | */ | |
858 | pci_fixup_parent_subordinate_busnr(child, max); | |
1da177e4 LT |
859 | } else { |
860 | /* | |
861 | * For CardBus bridges, we leave 4 bus numbers | |
862 | * as cards with a PCI-to-PCI bridge can be | |
863 | * inserted later. | |
864 | */ | |
49887941 DB |
865 | for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) { |
866 | struct pci_bus *parent = bus; | |
cc57450f RS |
867 | if (pci_find_bus(pci_domain_nr(bus), |
868 | max+i+1)) | |
869 | break; | |
49887941 DB |
870 | while (parent->parent) { |
871 | if ((!pcibios_assign_all_busses()) && | |
872 | (parent->subordinate > max) && | |
873 | (parent->subordinate <= max+i)) { | |
874 | j = 1; | |
875 | } | |
876 | parent = parent->parent; | |
877 | } | |
878 | if (j) { | |
879 | /* | |
880 | * Often, there are two cardbus bridges | |
881 | * -- try to leave one valid bus number | |
882 | * for each one. | |
883 | */ | |
884 | i /= 2; | |
885 | break; | |
886 | } | |
887 | } | |
cc57450f | 888 | max += i; |
26f674ae | 889 | pci_fixup_parent_subordinate_busnr(child, max); |
1da177e4 LT |
890 | } |
891 | /* | |
892 | * Set the subordinate bus number to its real value. | |
893 | */ | |
894 | child->subordinate = max; | |
895 | pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); | |
896 | } | |
897 | ||
cb3576fa GH |
898 | sprintf(child->name, |
899 | (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), | |
900 | pci_domain_nr(bus), child->number); | |
1da177e4 | 901 | |
d55bef51 | 902 | /* Has only triggered on CardBus, fixup is in yenta_socket */ |
49887941 DB |
903 | while (bus->parent) { |
904 | if ((child->subordinate > bus->subordinate) || | |
905 | (child->number > bus->subordinate) || | |
906 | (child->number < bus->number) || | |
907 | (child->subordinate < bus->number)) { | |
865df576 BH |
908 | dev_info(&child->dev, "[bus %02x-%02x] %s " |
909 | "hidden behind%s bridge %s [bus %02x-%02x]\n", | |
d55bef51 BK |
910 | child->number, child->subordinate, |
911 | (bus->number > child->subordinate && | |
912 | bus->subordinate < child->number) ? | |
a6f29a98 JP |
913 | "wholly" : "partially", |
914 | bus->self->transparent ? " transparent" : "", | |
865df576 | 915 | dev_name(&bus->dev), |
d55bef51 | 916 | bus->number, bus->subordinate); |
49887941 DB |
917 | } |
918 | bus = bus->parent; | |
919 | } | |
920 | ||
bbe8f9a3 RB |
921 | out: |
922 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl); | |
923 | ||
1da177e4 LT |
924 | return max; |
925 | } | |
926 | ||
927 | /* | |
928 | * Read interrupt line and base address registers. | |
929 | * The architecture-dependent code can tweak these, of course. | |
930 | */ | |
931 | static void pci_read_irq(struct pci_dev *dev) | |
932 | { | |
933 | unsigned char irq; | |
934 | ||
935 | pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); | |
ffeff788 | 936 | dev->pin = irq; |
1da177e4 LT |
937 | if (irq) |
938 | pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); | |
939 | dev->irq = irq; | |
940 | } | |
941 | ||
bb209c82 | 942 | void set_pcie_port_type(struct pci_dev *pdev) |
480b93b7 YZ |
943 | { |
944 | int pos; | |
945 | u16 reg16; | |
946 | ||
947 | pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); | |
948 | if (!pos) | |
949 | return; | |
950 | pdev->is_pcie = 1; | |
0efea000 | 951 | pdev->pcie_cap = pos; |
480b93b7 YZ |
952 | pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); |
953 | pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4; | |
b03e7495 JM |
954 | pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16); |
955 | pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; | |
480b93b7 YZ |
956 | } |
957 | ||
bb209c82 | 958 | void set_pcie_hotplug_bridge(struct pci_dev *pdev) |
28760489 EB |
959 | { |
960 | int pos; | |
961 | u16 reg16; | |
962 | u32 reg32; | |
963 | ||
06a1cbaf | 964 | pos = pci_pcie_cap(pdev); |
28760489 EB |
965 | if (!pos) |
966 | return; | |
967 | pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); | |
968 | if (!(reg16 & PCI_EXP_FLAGS_SLOT)) | |
969 | return; | |
970 | pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, ®32); | |
971 | if (reg32 & PCI_EXP_SLTCAP_HPC) | |
972 | pdev->is_hotplug_bridge = 1; | |
973 | } | |
974 | ||
01abc2aa | 975 | #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) |
76e6a1d6 | 976 | |
1da177e4 LT |
977 | /** |
978 | * pci_setup_device - fill in class and map information of a device | |
979 | * @dev: the device structure to fill | |
980 | * | |
981 | * Initialize the device structure with information about the device's | |
982 | * vendor,class,memory and IO-space addresses,IRQ lines etc. | |
983 | * Called at initialisation of the PCI subsystem and by CardBus services. | |
480b93b7 YZ |
984 | * Returns 0 on success and negative if unknown type of device (not normal, |
985 | * bridge or CardBus). | |
1da177e4 | 986 | */ |
480b93b7 | 987 | int pci_setup_device(struct pci_dev *dev) |
1da177e4 LT |
988 | { |
989 | u32 class; | |
480b93b7 YZ |
990 | u8 hdr_type; |
991 | struct pci_slot *slot; | |
bc577d2b | 992 | int pos = 0; |
5bfa14ed BH |
993 | struct pci_bus_region region; |
994 | struct resource *res; | |
480b93b7 YZ |
995 | |
996 | if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type)) | |
997 | return -EIO; | |
998 | ||
999 | dev->sysdata = dev->bus->sysdata; | |
1000 | dev->dev.parent = dev->bus->bridge; | |
1001 | dev->dev.bus = &pci_bus_type; | |
1002 | dev->hdr_type = hdr_type & 0x7f; | |
1003 | dev->multifunction = !!(hdr_type & 0x80); | |
480b93b7 YZ |
1004 | dev->error_state = pci_channel_io_normal; |
1005 | set_pcie_port_type(dev); | |
1006 | ||
1007 | list_for_each_entry(slot, &dev->bus->slots, list) | |
1008 | if (PCI_SLOT(dev->devfn) == slot->number) | |
1009 | dev->slot = slot; | |
1010 | ||
1011 | /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) | |
1012 | set this higher, assuming the system even supports it. */ | |
1013 | dev->dma_mask = 0xffffffff; | |
1da177e4 | 1014 | |
eebfcfb5 GKH |
1015 | dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), |
1016 | dev->bus->number, PCI_SLOT(dev->devfn), | |
1017 | PCI_FUNC(dev->devfn)); | |
1da177e4 LT |
1018 | |
1019 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); | |
b8a3a521 | 1020 | dev->revision = class & 0xff; |
2dd8ba92 | 1021 | dev->class = class >> 8; /* upper 3 bytes */ |
1da177e4 | 1022 | |
2dd8ba92 YL |
1023 | dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n", |
1024 | dev->vendor, dev->device, dev->hdr_type, dev->class); | |
1da177e4 | 1025 | |
853346e4 YZ |
1026 | /* need to have dev->class ready */ |
1027 | dev->cfg_size = pci_cfg_space_size(dev); | |
1028 | ||
1da177e4 | 1029 | /* "Unknown power state" */ |
3fe9d19f | 1030 | dev->current_state = PCI_UNKNOWN; |
1da177e4 LT |
1031 | |
1032 | /* Early fixups, before probing the BARs */ | |
1033 | pci_fixup_device(pci_fixup_early, dev); | |
f79b1b14 YZ |
1034 | /* device class may be changed after fixup */ |
1035 | class = dev->class >> 8; | |
1da177e4 LT |
1036 | |
1037 | switch (dev->hdr_type) { /* header type */ | |
1038 | case PCI_HEADER_TYPE_NORMAL: /* standard header */ | |
1039 | if (class == PCI_CLASS_BRIDGE_PCI) | |
1040 | goto bad; | |
1041 | pci_read_irq(dev); | |
1042 | pci_read_bases(dev, 6, PCI_ROM_ADDRESS); | |
1043 | pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); | |
1044 | pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device); | |
368c73d4 AC |
1045 | |
1046 | /* | |
1047 | * Do the ugly legacy mode stuff here rather than broken chip | |
1048 | * quirk code. Legacy mode ATA controllers have fixed | |
1049 | * addresses. These are not always echoed in BAR0-3, and | |
1050 | * BAR0-3 in a few cases contain junk! | |
1051 | */ | |
1052 | if (class == PCI_CLASS_STORAGE_IDE) { | |
1053 | u8 progif; | |
1054 | pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); | |
1055 | if ((progif & 1) == 0) { | |
5bfa14ed BH |
1056 | region.start = 0x1F0; |
1057 | region.end = 0x1F7; | |
1058 | res = &dev->resource[0]; | |
1059 | res->flags = LEGACY_IO_RESOURCE; | |
fb127cb9 | 1060 | pcibios_bus_to_resource(dev, res, ®ion); |
5bfa14ed BH |
1061 | region.start = 0x3F6; |
1062 | region.end = 0x3F6; | |
1063 | res = &dev->resource[1]; | |
1064 | res->flags = LEGACY_IO_RESOURCE; | |
fb127cb9 | 1065 | pcibios_bus_to_resource(dev, res, ®ion); |
368c73d4 AC |
1066 | } |
1067 | if ((progif & 4) == 0) { | |
5bfa14ed BH |
1068 | region.start = 0x170; |
1069 | region.end = 0x177; | |
1070 | res = &dev->resource[2]; | |
1071 | res->flags = LEGACY_IO_RESOURCE; | |
fb127cb9 | 1072 | pcibios_bus_to_resource(dev, res, ®ion); |
5bfa14ed BH |
1073 | region.start = 0x376; |
1074 | region.end = 0x376; | |
1075 | res = &dev->resource[3]; | |
1076 | res->flags = LEGACY_IO_RESOURCE; | |
fb127cb9 | 1077 | pcibios_bus_to_resource(dev, res, ®ion); |
368c73d4 AC |
1078 | } |
1079 | } | |
1da177e4 LT |
1080 | break; |
1081 | ||
1082 | case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ | |
1083 | if (class != PCI_CLASS_BRIDGE_PCI) | |
1084 | goto bad; | |
1085 | /* The PCI-to-PCI bridge spec requires that subtractive | |
1086 | decoding (i.e. transparent) bridge must have programming | |
1087 | interface code of 0x01. */ | |
3efd273b | 1088 | pci_read_irq(dev); |
1da177e4 LT |
1089 | dev->transparent = ((dev->class & 0xff) == 1); |
1090 | pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); | |
28760489 | 1091 | set_pcie_hotplug_bridge(dev); |
bc577d2b GB |
1092 | pos = pci_find_capability(dev, PCI_CAP_ID_SSVID); |
1093 | if (pos) { | |
1094 | pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor); | |
1095 | pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device); | |
1096 | } | |
1da177e4 LT |
1097 | break; |
1098 | ||
1099 | case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ | |
1100 | if (class != PCI_CLASS_BRIDGE_CARDBUS) | |
1101 | goto bad; | |
1102 | pci_read_irq(dev); | |
1103 | pci_read_bases(dev, 1, 0); | |
1104 | pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); | |
1105 | pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); | |
1106 | break; | |
1107 | ||
1108 | default: /* unknown header */ | |
80ccba11 BH |
1109 | dev_err(&dev->dev, "unknown header type %02x, " |
1110 | "ignoring device\n", dev->hdr_type); | |
480b93b7 | 1111 | return -EIO; |
1da177e4 LT |
1112 | |
1113 | bad: | |
2dd8ba92 YL |
1114 | dev_err(&dev->dev, "ignoring class %#08x (doesn't match header " |
1115 | "type %02x)\n", dev->class, dev->hdr_type); | |
1da177e4 LT |
1116 | dev->class = PCI_CLASS_NOT_DEFINED; |
1117 | } | |
1118 | ||
1119 | /* We found a fine healthy device, go go go... */ | |
1120 | return 0; | |
1121 | } | |
1122 | ||
201de56e ZY |
1123 | static void pci_release_capabilities(struct pci_dev *dev) |
1124 | { | |
1125 | pci_vpd_release(dev); | |
d1b054da | 1126 | pci_iov_release(dev); |
f796841e | 1127 | pci_free_cap_save_buffers(dev); |
201de56e ZY |
1128 | } |
1129 | ||
1da177e4 LT |
1130 | /** |
1131 | * pci_release_dev - free a pci device structure when all users of it are finished. | |
1132 | * @dev: device that's been disconnected | |
1133 | * | |
1134 | * Will be called only by the device core when all users of this pci device are | |
1135 | * done. | |
1136 | */ | |
1137 | static void pci_release_dev(struct device *dev) | |
1138 | { | |
1139 | struct pci_dev *pci_dev; | |
1140 | ||
1141 | pci_dev = to_pci_dev(dev); | |
201de56e | 1142 | pci_release_capabilities(pci_dev); |
98d9f30c | 1143 | pci_release_of_node(pci_dev); |
1da177e4 LT |
1144 | kfree(pci_dev); |
1145 | } | |
1146 | ||
1147 | /** | |
1148 | * pci_cfg_space_size - get the configuration space size of the PCI device. | |
8f7020d3 | 1149 | * @dev: PCI device |
1da177e4 LT |
1150 | * |
1151 | * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices | |
1152 | * have 4096 bytes. Even if the device is capable, that doesn't mean we can | |
1153 | * access it. Maybe we don't have a way to generate extended config space | |
1154 | * accesses, or the device is behind a reverse Express bridge. So we try | |
1155 | * reading the dword at 0x100 which must either be 0 or a valid extended | |
1156 | * capability header. | |
1157 | */ | |
70b9f7dc | 1158 | int pci_cfg_space_size_ext(struct pci_dev *dev) |
1da177e4 | 1159 | { |
1da177e4 | 1160 | u32 status; |
557848c3 | 1161 | int pos = PCI_CFG_SPACE_SIZE; |
1da177e4 | 1162 | |
557848c3 | 1163 | if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL) |
70b9f7dc YL |
1164 | goto fail; |
1165 | if (status == 0xffffffff) | |
1166 | goto fail; | |
1167 | ||
1168 | return PCI_CFG_SPACE_EXP_SIZE; | |
1169 | ||
1170 | fail: | |
1171 | return PCI_CFG_SPACE_SIZE; | |
1172 | } | |
1173 | ||
1174 | int pci_cfg_space_size(struct pci_dev *dev) | |
1175 | { | |
1176 | int pos; | |
1177 | u32 status; | |
dfadd9ed YL |
1178 | u16 class; |
1179 | ||
1180 | class = dev->class >> 8; | |
1181 | if (class == PCI_CLASS_BRIDGE_HOST) | |
1182 | return pci_cfg_space_size_ext(dev); | |
57741a77 | 1183 | |
06a1cbaf | 1184 | pos = pci_pcie_cap(dev); |
1da177e4 LT |
1185 | if (!pos) { |
1186 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
1187 | if (!pos) | |
1188 | goto fail; | |
1189 | ||
1190 | pci_read_config_dword(dev, pos + PCI_X_STATUS, &status); | |
1191 | if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))) | |
1192 | goto fail; | |
1193 | } | |
1194 | ||
70b9f7dc | 1195 | return pci_cfg_space_size_ext(dev); |
1da177e4 LT |
1196 | |
1197 | fail: | |
1198 | return PCI_CFG_SPACE_SIZE; | |
1199 | } | |
1200 | ||
1201 | static void pci_release_bus_bridge_dev(struct device *dev) | |
1202 | { | |
1203 | kfree(dev); | |
1204 | } | |
1205 | ||
65891215 ME |
1206 | struct pci_dev *alloc_pci_dev(void) |
1207 | { | |
1208 | struct pci_dev *dev; | |
1209 | ||
1210 | dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); | |
1211 | if (!dev) | |
1212 | return NULL; | |
1213 | ||
65891215 ME |
1214 | INIT_LIST_HEAD(&dev->bus_list); |
1215 | ||
1216 | return dev; | |
1217 | } | |
1218 | EXPORT_SYMBOL(alloc_pci_dev); | |
1219 | ||
efdc87da YL |
1220 | bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, |
1221 | int crs_timeout) | |
1da177e4 | 1222 | { |
1da177e4 LT |
1223 | int delay = 1; |
1224 | ||
efdc87da YL |
1225 | if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) |
1226 | return false; | |
1da177e4 LT |
1227 | |
1228 | /* some broken boards return 0 or ~0 if a slot is empty: */ | |
efdc87da YL |
1229 | if (*l == 0xffffffff || *l == 0x00000000 || |
1230 | *l == 0x0000ffff || *l == 0xffff0000) | |
1231 | return false; | |
1da177e4 LT |
1232 | |
1233 | /* Configuration request Retry Status */ | |
efdc87da YL |
1234 | while (*l == 0xffff0001) { |
1235 | if (!crs_timeout) | |
1236 | return false; | |
1237 | ||
1da177e4 LT |
1238 | msleep(delay); |
1239 | delay *= 2; | |
efdc87da YL |
1240 | if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) |
1241 | return false; | |
1da177e4 | 1242 | /* Card hasn't responded in 60 seconds? Must be stuck. */ |
efdc87da | 1243 | if (delay > crs_timeout) { |
80ccba11 | 1244 | printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not " |
1da177e4 LT |
1245 | "responding\n", pci_domain_nr(bus), |
1246 | bus->number, PCI_SLOT(devfn), | |
1247 | PCI_FUNC(devfn)); | |
efdc87da | 1248 | return false; |
1da177e4 LT |
1249 | } |
1250 | } | |
1251 | ||
efdc87da YL |
1252 | return true; |
1253 | } | |
1254 | EXPORT_SYMBOL(pci_bus_read_dev_vendor_id); | |
1255 | ||
1256 | /* | |
1257 | * Read the config data for a PCI device, sanity-check it | |
1258 | * and fill in the dev structure... | |
1259 | */ | |
1260 | static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) | |
1261 | { | |
1262 | struct pci_dev *dev; | |
1263 | u32 l; | |
1264 | ||
1265 | if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000)) | |
1266 | return NULL; | |
1267 | ||
bab41e9b | 1268 | dev = alloc_pci_dev(); |
1da177e4 LT |
1269 | if (!dev) |
1270 | return NULL; | |
1271 | ||
1da177e4 | 1272 | dev->bus = bus; |
1da177e4 | 1273 | dev->devfn = devfn; |
1da177e4 LT |
1274 | dev->vendor = l & 0xffff; |
1275 | dev->device = (l >> 16) & 0xffff; | |
cef354db | 1276 | |
98d9f30c BH |
1277 | pci_set_of_node(dev); |
1278 | ||
480b93b7 | 1279 | if (pci_setup_device(dev)) { |
1da177e4 LT |
1280 | kfree(dev); |
1281 | return NULL; | |
1282 | } | |
1da177e4 LT |
1283 | |
1284 | return dev; | |
1285 | } | |
1286 | ||
201de56e ZY |
1287 | static void pci_init_capabilities(struct pci_dev *dev) |
1288 | { | |
1289 | /* MSI/MSI-X list */ | |
1290 | pci_msi_init_pci_dev(dev); | |
1291 | ||
63f4898a RW |
1292 | /* Buffers for saving PCIe and PCI-X capabilities */ |
1293 | pci_allocate_cap_save_buffers(dev); | |
1294 | ||
201de56e ZY |
1295 | /* Power Management */ |
1296 | pci_pm_init(dev); | |
eb9c39d0 | 1297 | platform_pci_wakeup_init(dev); |
201de56e ZY |
1298 | |
1299 | /* Vital Product Data */ | |
1300 | pci_vpd_pci22_init(dev); | |
58c3a727 YZ |
1301 | |
1302 | /* Alternative Routing-ID Forwarding */ | |
1303 | pci_enable_ari(dev); | |
d1b054da YZ |
1304 | |
1305 | /* Single Root I/O Virtualization */ | |
1306 | pci_iov_init(dev); | |
ae21ee65 AK |
1307 | |
1308 | /* Enable ACS P2P upstream forwarding */ | |
5d990b62 | 1309 | pci_enable_acs(dev); |
201de56e ZY |
1310 | } |
1311 | ||
96bde06a | 1312 | void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) |
1da177e4 | 1313 | { |
cdb9b9f7 PM |
1314 | device_initialize(&dev->dev); |
1315 | dev->dev.release = pci_release_dev; | |
1316 | pci_dev_get(dev); | |
1da177e4 | 1317 | |
cdb9b9f7 | 1318 | dev->dev.dma_mask = &dev->dma_mask; |
4d57cdfa | 1319 | dev->dev.dma_parms = &dev->dma_parms; |
cdb9b9f7 | 1320 | dev->dev.coherent_dma_mask = 0xffffffffull; |
1da177e4 | 1321 | |
4d57cdfa | 1322 | pci_set_dma_max_seg_size(dev, 65536); |
59fc67de | 1323 | pci_set_dma_seg_boundary(dev, 0xffffffff); |
4d57cdfa | 1324 | |
1da177e4 LT |
1325 | /* Fix up broken headers */ |
1326 | pci_fixup_device(pci_fixup_header, dev); | |
1327 | ||
4b77b0a2 RW |
1328 | /* Clear the state_saved flag. */ |
1329 | dev->state_saved = false; | |
1330 | ||
201de56e ZY |
1331 | /* Initialize various capabilities */ |
1332 | pci_init_capabilities(dev); | |
eb9d0fe4 | 1333 | |
1da177e4 LT |
1334 | /* |
1335 | * Add the device to our list of discovered devices | |
1336 | * and the bus list for fixup functions, etc. | |
1337 | */ | |
d71374da | 1338 | down_write(&pci_bus_sem); |
1da177e4 | 1339 | list_add_tail(&dev->bus_list, &bus->devices); |
d71374da | 1340 | up_write(&pci_bus_sem); |
cdb9b9f7 PM |
1341 | } |
1342 | ||
451124a7 | 1343 | struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn) |
cdb9b9f7 PM |
1344 | { |
1345 | struct pci_dev *dev; | |
1346 | ||
90bdb311 TP |
1347 | dev = pci_get_slot(bus, devfn); |
1348 | if (dev) { | |
1349 | pci_dev_put(dev); | |
1350 | return dev; | |
1351 | } | |
1352 | ||
cdb9b9f7 PM |
1353 | dev = pci_scan_device(bus, devfn); |
1354 | if (!dev) | |
1355 | return NULL; | |
1356 | ||
1357 | pci_device_add(dev, bus); | |
1da177e4 LT |
1358 | |
1359 | return dev; | |
1360 | } | |
b73e9687 | 1361 | EXPORT_SYMBOL(pci_scan_single_device); |
1da177e4 | 1362 | |
f07852d6 MW |
1363 | static unsigned next_ari_fn(struct pci_dev *dev, unsigned fn) |
1364 | { | |
1365 | u16 cap; | |
4fb88c1a MW |
1366 | unsigned pos, next_fn; |
1367 | ||
1368 | if (!dev) | |
1369 | return 0; | |
1370 | ||
1371 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI); | |
f07852d6 MW |
1372 | if (!pos) |
1373 | return 0; | |
1374 | pci_read_config_word(dev, pos + 4, &cap); | |
4fb88c1a MW |
1375 | next_fn = cap >> 8; |
1376 | if (next_fn <= fn) | |
1377 | return 0; | |
1378 | return next_fn; | |
f07852d6 MW |
1379 | } |
1380 | ||
1381 | static unsigned next_trad_fn(struct pci_dev *dev, unsigned fn) | |
1382 | { | |
1383 | return (fn + 1) % 8; | |
1384 | } | |
1385 | ||
1386 | static unsigned no_next_fn(struct pci_dev *dev, unsigned fn) | |
1387 | { | |
1388 | return 0; | |
1389 | } | |
1390 | ||
1391 | static int only_one_child(struct pci_bus *bus) | |
1392 | { | |
1393 | struct pci_dev *parent = bus->self; | |
1394 | if (!parent || !pci_is_pcie(parent)) | |
1395 | return 0; | |
1396 | if (parent->pcie_type == PCI_EXP_TYPE_ROOT_PORT || | |
1397 | parent->pcie_type == PCI_EXP_TYPE_DOWNSTREAM) | |
1398 | return 1; | |
1399 | return 0; | |
1400 | } | |
1401 | ||
1da177e4 LT |
1402 | /** |
1403 | * pci_scan_slot - scan a PCI slot on a bus for devices. | |
1404 | * @bus: PCI bus to scan | |
1405 | * @devfn: slot number to scan (must have zero function.) | |
1406 | * | |
1407 | * Scan a PCI slot on the specified PCI bus for devices, adding | |
1408 | * discovered devices to the @bus->devices list. New devices | |
8a1bc901 | 1409 | * will not have is_added set. |
1b69dfc6 TP |
1410 | * |
1411 | * Returns the number of new devices found. | |
1da177e4 | 1412 | */ |
96bde06a | 1413 | int pci_scan_slot(struct pci_bus *bus, int devfn) |
1da177e4 | 1414 | { |
f07852d6 | 1415 | unsigned fn, nr = 0; |
1b69dfc6 | 1416 | struct pci_dev *dev; |
f07852d6 MW |
1417 | unsigned (*next_fn)(struct pci_dev *, unsigned) = no_next_fn; |
1418 | ||
1419 | if (only_one_child(bus) && (devfn > 0)) | |
1420 | return 0; /* Already scanned the entire slot */ | |
1da177e4 | 1421 | |
1b69dfc6 | 1422 | dev = pci_scan_single_device(bus, devfn); |
4fb88c1a MW |
1423 | if (!dev) |
1424 | return 0; | |
1425 | if (!dev->is_added) | |
1b69dfc6 TP |
1426 | nr++; |
1427 | ||
f07852d6 MW |
1428 | if (pci_ari_enabled(bus)) |
1429 | next_fn = next_ari_fn; | |
4fb88c1a | 1430 | else if (dev->multifunction) |
f07852d6 MW |
1431 | next_fn = next_trad_fn; |
1432 | ||
1433 | for (fn = next_fn(dev, 0); fn > 0; fn = next_fn(dev, fn)) { | |
1434 | dev = pci_scan_single_device(bus, devfn + fn); | |
1435 | if (dev) { | |
1436 | if (!dev->is_added) | |
1437 | nr++; | |
1438 | dev->multifunction = 1; | |
1da177e4 LT |
1439 | } |
1440 | } | |
7d715a6c | 1441 | |
149e1637 SL |
1442 | /* only one slot has pcie device */ |
1443 | if (bus->self && nr) | |
7d715a6c SL |
1444 | pcie_aspm_init_link_state(bus->self); |
1445 | ||
1da177e4 LT |
1446 | return nr; |
1447 | } | |
1448 | ||
b03e7495 JM |
1449 | static int pcie_find_smpss(struct pci_dev *dev, void *data) |
1450 | { | |
1451 | u8 *smpss = data; | |
1452 | ||
1453 | if (!pci_is_pcie(dev)) | |
1454 | return 0; | |
1455 | ||
1456 | /* For PCIE hotplug enabled slots not connected directly to a | |
1457 | * PCI-E root port, there can be problems when hotplugging | |
1458 | * devices. This is due to the possibility of hotplugging a | |
1459 | * device into the fabric with a smaller MPS that the devices | |
1460 | * currently running have configured. Modifying the MPS on the | |
1461 | * running devices could cause a fatal bus error due to an | |
1462 | * incoming frame being larger than the newly configured MPS. | |
1463 | * To work around this, the MPS for the entire fabric must be | |
1464 | * set to the minimum size. Any devices hotplugged into this | |
1465 | * fabric will have the minimum MPS set. If the PCI hotplug | |
1466 | * slot is directly connected to the root port and there are not | |
1467 | * other devices on the fabric (which seems to be the most | |
1468 | * common case), then this is not an issue and MPS discovery | |
1469 | * will occur as normal. | |
1470 | */ | |
1471 | if (dev->is_hotplug_bridge && (!list_is_singular(&dev->bus->devices) || | |
1a4b1a41 BH |
1472 | (dev->bus->self && |
1473 | dev->bus->self->pcie_type != PCI_EXP_TYPE_ROOT_PORT))) | |
b03e7495 JM |
1474 | *smpss = 0; |
1475 | ||
1476 | if (*smpss > dev->pcie_mpss) | |
1477 | *smpss = dev->pcie_mpss; | |
1478 | ||
1479 | return 0; | |
1480 | } | |
1481 | ||
1482 | static void pcie_write_mps(struct pci_dev *dev, int mps) | |
1483 | { | |
62f392ea | 1484 | int rc; |
b03e7495 JM |
1485 | |
1486 | if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { | |
62f392ea | 1487 | mps = 128 << dev->pcie_mpss; |
b03e7495 | 1488 | |
62f392ea JM |
1489 | if (dev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && dev->bus->self) |
1490 | /* For "Performance", the assumption is made that | |
b03e7495 JM |
1491 | * downstream communication will never be larger than |
1492 | * the MRRS. So, the MPS only needs to be configured | |
1493 | * for the upstream communication. This being the case, | |
1494 | * walk from the top down and set the MPS of the child | |
1495 | * to that of the parent bus. | |
62f392ea JM |
1496 | * |
1497 | * Configure the device MPS with the smaller of the | |
1498 | * device MPSS or the bridge MPS (which is assumed to be | |
1499 | * properly configured at this point to the largest | |
1500 | * allowable MPS based on its parent bus). | |
b03e7495 | 1501 | */ |
62f392ea | 1502 | mps = min(mps, pcie_get_mps(dev->bus->self)); |
b03e7495 JM |
1503 | } |
1504 | ||
1505 | rc = pcie_set_mps(dev, mps); | |
1506 | if (rc) | |
1507 | dev_err(&dev->dev, "Failed attempting to set the MPS\n"); | |
1508 | } | |
1509 | ||
62f392ea | 1510 | static void pcie_write_mrrs(struct pci_dev *dev) |
b03e7495 | 1511 | { |
62f392ea | 1512 | int rc, mrrs; |
b03e7495 | 1513 | |
ed2888e9 JM |
1514 | /* In the "safe" case, do not configure the MRRS. There appear to be |
1515 | * issues with setting MRRS to 0 on a number of devices. | |
1516 | */ | |
ed2888e9 JM |
1517 | if (pcie_bus_config != PCIE_BUS_PERFORMANCE) |
1518 | return; | |
1519 | ||
ed2888e9 JM |
1520 | /* For Max performance, the MRRS must be set to the largest supported |
1521 | * value. However, it cannot be configured larger than the MPS the | |
62f392ea JM |
1522 | * device or the bus can support. This should already be properly |
1523 | * configured by a prior call to pcie_write_mps. | |
ed2888e9 | 1524 | */ |
62f392ea | 1525 | mrrs = pcie_get_mps(dev); |
b03e7495 JM |
1526 | |
1527 | /* MRRS is a R/W register. Invalid values can be written, but a | |
ed2888e9 | 1528 | * subsequent read will verify if the value is acceptable or not. |
b03e7495 JM |
1529 | * If the MRRS value provided is not acceptable (e.g., too large), |
1530 | * shrink the value until it is acceptable to the HW. | |
1531 | */ | |
1532 | while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) { | |
1533 | rc = pcie_set_readrq(dev, mrrs); | |
62f392ea JM |
1534 | if (!rc) |
1535 | break; | |
b03e7495 | 1536 | |
62f392ea | 1537 | dev_warn(&dev->dev, "Failed attempting to set the MRRS\n"); |
b03e7495 JM |
1538 | mrrs /= 2; |
1539 | } | |
62f392ea JM |
1540 | |
1541 | if (mrrs < 128) | |
1542 | dev_err(&dev->dev, "MRRS was unable to be configured with a " | |
1543 | "safe value. If problems are experienced, try running " | |
1544 | "with pci=pcie_bus_safe.\n"); | |
b03e7495 JM |
1545 | } |
1546 | ||
1547 | static int pcie_bus_configure_set(struct pci_dev *dev, void *data) | |
1548 | { | |
a513a99a | 1549 | int mps, orig_mps; |
b03e7495 JM |
1550 | |
1551 | if (!pci_is_pcie(dev)) | |
1552 | return 0; | |
1553 | ||
a513a99a JM |
1554 | mps = 128 << *(u8 *)data; |
1555 | orig_mps = pcie_get_mps(dev); | |
b03e7495 JM |
1556 | |
1557 | pcie_write_mps(dev, mps); | |
62f392ea | 1558 | pcie_write_mrrs(dev); |
b03e7495 | 1559 | |
a513a99a JM |
1560 | dev_info(&dev->dev, "PCI-E Max Payload Size set to %4d/%4d (was %4d), " |
1561 | "Max Read Rq %4d\n", pcie_get_mps(dev), 128 << dev->pcie_mpss, | |
1562 | orig_mps, pcie_get_readrq(dev)); | |
b03e7495 JM |
1563 | |
1564 | return 0; | |
1565 | } | |
1566 | ||
a513a99a | 1567 | /* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down, |
b03e7495 JM |
1568 | * parents then children fashion. If this changes, then this code will not |
1569 | * work as designed. | |
1570 | */ | |
1571 | void pcie_bus_configure_settings(struct pci_bus *bus, u8 mpss) | |
1572 | { | |
5f39e670 | 1573 | u8 smpss; |
b03e7495 | 1574 | |
b03e7495 JM |
1575 | if (!pci_is_pcie(bus->self)) |
1576 | return; | |
1577 | ||
5f39e670 JM |
1578 | if (pcie_bus_config == PCIE_BUS_TUNE_OFF) |
1579 | return; | |
1580 | ||
1581 | /* FIXME - Peer to peer DMA is possible, though the endpoint would need | |
1582 | * to be aware to the MPS of the destination. To work around this, | |
1583 | * simply force the MPS of the entire system to the smallest possible. | |
1584 | */ | |
1585 | if (pcie_bus_config == PCIE_BUS_PEER2PEER) | |
1586 | smpss = 0; | |
1587 | ||
b03e7495 | 1588 | if (pcie_bus_config == PCIE_BUS_SAFE) { |
5f39e670 JM |
1589 | smpss = mpss; |
1590 | ||
b03e7495 JM |
1591 | pcie_find_smpss(bus->self, &smpss); |
1592 | pci_walk_bus(bus, pcie_find_smpss, &smpss); | |
1593 | } | |
1594 | ||
1595 | pcie_bus_configure_set(bus->self, &smpss); | |
1596 | pci_walk_bus(bus, pcie_bus_configure_set, &smpss); | |
1597 | } | |
debc3b77 | 1598 | EXPORT_SYMBOL_GPL(pcie_bus_configure_settings); |
b03e7495 | 1599 | |
0ab2b57f | 1600 | unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus) |
1da177e4 LT |
1601 | { |
1602 | unsigned int devfn, pass, max = bus->secondary; | |
1603 | struct pci_dev *dev; | |
1604 | ||
0207c356 | 1605 | dev_dbg(&bus->dev, "scanning bus\n"); |
1da177e4 LT |
1606 | |
1607 | /* Go find them, Rover! */ | |
1608 | for (devfn = 0; devfn < 0x100; devfn += 8) | |
1609 | pci_scan_slot(bus, devfn); | |
1610 | ||
a28724b0 YZ |
1611 | /* Reserve buses for SR-IOV capability. */ |
1612 | max += pci_iov_bus_range(bus); | |
1613 | ||
1da177e4 LT |
1614 | /* |
1615 | * After performing arch-dependent fixup of the bus, look behind | |
1616 | * all PCI-to-PCI bridges on this bus. | |
1617 | */ | |
74710ded | 1618 | if (!bus->is_added) { |
0207c356 | 1619 | dev_dbg(&bus->dev, "fixups for bus\n"); |
74710ded AC |
1620 | pcibios_fixup_bus(bus); |
1621 | if (pci_is_root_bus(bus)) | |
1622 | bus->is_added = 1; | |
1623 | } | |
1624 | ||
1da177e4 LT |
1625 | for (pass=0; pass < 2; pass++) |
1626 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1627 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || | |
1628 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) | |
1629 | max = pci_scan_bridge(bus, dev, max, pass); | |
1630 | } | |
1631 | ||
1632 | /* | |
1633 | * We've scanned the bus and so we know all about what's on | |
1634 | * the other side of any bridges that may be on this bus plus | |
1635 | * any devices. | |
1636 | * | |
1637 | * Return how far we've got finding sub-buses. | |
1638 | */ | |
0207c356 | 1639 | dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max); |
1da177e4 LT |
1640 | return max; |
1641 | } | |
1642 | ||
166c6370 BH |
1643 | struct pci_bus *pci_create_root_bus(struct device *parent, int bus, |
1644 | struct pci_ops *ops, void *sysdata, struct list_head *resources) | |
1da177e4 | 1645 | { |
0efd5aab | 1646 | int error; |
5a21d70d | 1647 | struct pci_host_bridge *bridge; |
0207c356 | 1648 | struct pci_bus *b, *b2; |
1da177e4 | 1649 | struct device *dev; |
0efd5aab | 1650 | struct pci_host_bridge_window *window, *n; |
a9d9f527 | 1651 | struct resource *res; |
0efd5aab BH |
1652 | resource_size_t offset; |
1653 | char bus_addr[64]; | |
1654 | char *fmt; | |
1da177e4 | 1655 | |
5a21d70d BH |
1656 | bridge = kzalloc(sizeof(*bridge), GFP_KERNEL); |
1657 | if (!bridge) | |
1658 | return NULL; | |
1659 | ||
1da177e4 LT |
1660 | b = pci_alloc_bus(); |
1661 | if (!b) | |
5a21d70d | 1662 | goto err_bus; |
1da177e4 | 1663 | |
6a3b3e26 | 1664 | dev = kzalloc(sizeof(*dev), GFP_KERNEL); |
5a21d70d BH |
1665 | if (!dev) |
1666 | goto err_dev; | |
1da177e4 LT |
1667 | |
1668 | b->sysdata = sysdata; | |
1669 | b->ops = ops; | |
1670 | ||
0207c356 BH |
1671 | b2 = pci_find_bus(pci_domain_nr(b), bus); |
1672 | if (b2) { | |
1da177e4 | 1673 | /* If we already got to this bus through a different bridge, ignore it */ |
0207c356 | 1674 | dev_dbg(&b2->dev, "bus already known\n"); |
1da177e4 LT |
1675 | goto err_out; |
1676 | } | |
d71374da | 1677 | |
1da177e4 LT |
1678 | dev->parent = parent; |
1679 | dev->release = pci_release_bus_bridge_dev; | |
1a927133 | 1680 | dev_set_name(dev, "pci%04x:%02x", pci_domain_nr(b), bus); |
1da177e4 LT |
1681 | error = device_register(dev); |
1682 | if (error) | |
1683 | goto dev_reg_err; | |
1684 | b->bridge = get_device(dev); | |
a1e4d72c | 1685 | device_enable_async_suspend(b->bridge); |
98d9f30c | 1686 | pci_set_bus_of_node(b); |
1da177e4 | 1687 | |
0d358f22 YL |
1688 | if (!parent) |
1689 | set_dev_node(b->bridge, pcibus_to_node(b)); | |
1690 | ||
fd7d1ced GKH |
1691 | b->dev.class = &pcibus_class; |
1692 | b->dev.parent = b->bridge; | |
1a927133 | 1693 | dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus); |
fd7d1ced | 1694 | error = device_register(&b->dev); |
1da177e4 LT |
1695 | if (error) |
1696 | goto class_dev_reg_err; | |
1da177e4 LT |
1697 | |
1698 | /* Create legacy_io and legacy_mem files for this bus */ | |
1699 | pci_create_legacy_files(b); | |
1700 | ||
1da177e4 | 1701 | b->number = b->secondary = bus; |
166c6370 | 1702 | |
5a21d70d | 1703 | bridge->bus = b; |
0efd5aab | 1704 | INIT_LIST_HEAD(&bridge->windows); |
1da177e4 | 1705 | |
a9d9f527 BH |
1706 | if (parent) |
1707 | dev_info(parent, "PCI host bridge to bus %s\n", dev_name(&b->dev)); | |
1708 | else | |
1709 | printk(KERN_INFO "PCI host bridge to bus %s\n", dev_name(&b->dev)); | |
1710 | ||
0efd5aab BH |
1711 | /* Add initial resources to the bus */ |
1712 | list_for_each_entry_safe(window, n, resources, list) { | |
1713 | list_move_tail(&window->list, &bridge->windows); | |
1714 | res = window->res; | |
1715 | offset = window->offset; | |
1716 | pci_bus_add_resource(b, res, 0); | |
1717 | if (offset) { | |
1718 | if (resource_type(res) == IORESOURCE_IO) | |
1719 | fmt = " (bus address [%#06llx-%#06llx])"; | |
1720 | else | |
1721 | fmt = " (bus address [%#010llx-%#010llx])"; | |
1722 | snprintf(bus_addr, sizeof(bus_addr), fmt, | |
1723 | (unsigned long long) (res->start - offset), | |
1724 | (unsigned long long) (res->end - offset)); | |
1725 | } else | |
1726 | bus_addr[0] = '\0'; | |
1727 | dev_info(&b->dev, "root bus resource %pR%s\n", res, bus_addr); | |
a9d9f527 BH |
1728 | } |
1729 | ||
a5390aa6 | 1730 | down_write(&pci_bus_sem); |
5a21d70d | 1731 | list_add_tail(&bridge->list, &pci_host_bridges); |
a5390aa6 BH |
1732 | list_add_tail(&b->node, &pci_root_buses); |
1733 | up_write(&pci_bus_sem); | |
1734 | ||
1da177e4 LT |
1735 | return b; |
1736 | ||
1da177e4 LT |
1737 | class_dev_reg_err: |
1738 | device_unregister(dev); | |
1739 | dev_reg_err: | |
d71374da | 1740 | down_write(&pci_bus_sem); |
5a21d70d | 1741 | list_del(&bridge->list); |
1da177e4 | 1742 | list_del(&b->node); |
d71374da | 1743 | up_write(&pci_bus_sem); |
1da177e4 LT |
1744 | err_out: |
1745 | kfree(dev); | |
5a21d70d | 1746 | err_dev: |
1da177e4 | 1747 | kfree(b); |
5a21d70d BH |
1748 | err_bus: |
1749 | kfree(bridge); | |
1da177e4 LT |
1750 | return NULL; |
1751 | } | |
cdb9b9f7 | 1752 | |
a2ebb827 BH |
1753 | struct pci_bus * __devinit pci_scan_root_bus(struct device *parent, int bus, |
1754 | struct pci_ops *ops, void *sysdata, struct list_head *resources) | |
1755 | { | |
1756 | struct pci_bus *b; | |
1757 | ||
1758 | b = pci_create_root_bus(parent, bus, ops, sysdata, resources); | |
1759 | if (!b) | |
1760 | return NULL; | |
1761 | ||
1762 | b->subordinate = pci_scan_child_bus(b); | |
1763 | pci_bus_add_devices(b); | |
1764 | return b; | |
1765 | } | |
1766 | EXPORT_SYMBOL(pci_scan_root_bus); | |
1767 | ||
7e00fe2e | 1768 | /* Deprecated; use pci_scan_root_bus() instead */ |
0ab2b57f | 1769 | struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent, |
cdb9b9f7 PM |
1770 | int bus, struct pci_ops *ops, void *sysdata) |
1771 | { | |
1e39ae9f | 1772 | LIST_HEAD(resources); |
cdb9b9f7 PM |
1773 | struct pci_bus *b; |
1774 | ||
1e39ae9f BH |
1775 | pci_add_resource(&resources, &ioport_resource); |
1776 | pci_add_resource(&resources, &iomem_resource); | |
1777 | b = pci_create_root_bus(parent, bus, ops, sysdata, &resources); | |
cdb9b9f7 PM |
1778 | if (b) |
1779 | b->subordinate = pci_scan_child_bus(b); | |
1e39ae9f BH |
1780 | else |
1781 | pci_free_resource_list(&resources); | |
cdb9b9f7 PM |
1782 | return b; |
1783 | } | |
1da177e4 LT |
1784 | EXPORT_SYMBOL(pci_scan_bus_parented); |
1785 | ||
de4b2f76 BH |
1786 | struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops, |
1787 | void *sysdata) | |
1788 | { | |
1789 | LIST_HEAD(resources); | |
1790 | struct pci_bus *b; | |
1791 | ||
1792 | pci_add_resource(&resources, &ioport_resource); | |
1793 | pci_add_resource(&resources, &iomem_resource); | |
1794 | b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources); | |
1795 | if (b) { | |
1796 | b->subordinate = pci_scan_child_bus(b); | |
1797 | pci_bus_add_devices(b); | |
1798 | } else { | |
1799 | pci_free_resource_list(&resources); | |
1800 | } | |
1801 | return b; | |
1802 | } | |
1803 | EXPORT_SYMBOL(pci_scan_bus); | |
1804 | ||
1da177e4 | 1805 | #ifdef CONFIG_HOTPLUG |
2f320521 YL |
1806 | /** |
1807 | * pci_rescan_bus_bridge_resize - scan a PCI bus for devices. | |
1808 | * @bridge: PCI bridge for the bus to scan | |
1809 | * | |
1810 | * Scan a PCI bus and child buses for new devices, add them, | |
1811 | * and enable them, resizing bridge mmio/io resource if necessary | |
1812 | * and possible. The caller must ensure the child devices are already | |
1813 | * removed for resizing to occur. | |
1814 | * | |
1815 | * Returns the max number of subordinate bus discovered. | |
1816 | */ | |
1817 | unsigned int __ref pci_rescan_bus_bridge_resize(struct pci_dev *bridge) | |
1818 | { | |
1819 | unsigned int max; | |
1820 | struct pci_bus *bus = bridge->subordinate; | |
1821 | ||
1822 | max = pci_scan_child_bus(bus); | |
1823 | ||
1824 | pci_assign_unassigned_bridge_resources(bridge); | |
1825 | ||
1826 | pci_bus_add_devices(bus); | |
1827 | ||
1828 | return max; | |
1829 | } | |
1830 | ||
1da177e4 | 1831 | EXPORT_SYMBOL(pci_add_new_bus); |
1da177e4 LT |
1832 | EXPORT_SYMBOL(pci_scan_slot); |
1833 | EXPORT_SYMBOL(pci_scan_bridge); | |
1da177e4 LT |
1834 | EXPORT_SYMBOL_GPL(pci_scan_child_bus); |
1835 | #endif | |
6b4b78fe | 1836 | |
99178b03 | 1837 | static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b) |
6b4b78fe | 1838 | { |
99178b03 GKH |
1839 | const struct pci_dev *a = to_pci_dev(d_a); |
1840 | const struct pci_dev *b = to_pci_dev(d_b); | |
1841 | ||
6b4b78fe MD |
1842 | if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1; |
1843 | else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1; | |
1844 | ||
1845 | if (a->bus->number < b->bus->number) return -1; | |
1846 | else if (a->bus->number > b->bus->number) return 1; | |
1847 | ||
1848 | if (a->devfn < b->devfn) return -1; | |
1849 | else if (a->devfn > b->devfn) return 1; | |
1850 | ||
1851 | return 0; | |
1852 | } | |
1853 | ||
5ff580c1 | 1854 | void __init pci_sort_breadthfirst(void) |
6b4b78fe | 1855 | { |
99178b03 | 1856 | bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp); |
6b4b78fe | 1857 | } |