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Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * probe.c - PCI detection and setup code | |
3 | */ | |
4 | ||
5 | #include <linux/kernel.h> | |
6 | #include <linux/delay.h> | |
7 | #include <linux/init.h> | |
8 | #include <linux/pci.h> | |
9 | #include <linux/slab.h> | |
10 | #include <linux/module.h> | |
11 | #include <linux/cpumask.h> | |
7d715a6c | 12 | #include <linux/pci-aspm.h> |
ae21ee65 | 13 | #include <linux/iommu.h> |
05843961 | 14 | #include <acpi/acpi_hest.h> |
df0e97c6 | 15 | #include <xen/xen.h> |
bc56b9e0 | 16 | #include "pci.h" |
1da177e4 LT |
17 | |
18 | #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ | |
19 | #define CARDBUS_RESERVE_BUSNR 3 | |
1da177e4 LT |
20 | |
21 | /* Ugh. Need to stop exporting this to modules. */ | |
22 | LIST_HEAD(pci_root_buses); | |
23 | EXPORT_SYMBOL(pci_root_buses); | |
24 | ||
70308923 GKH |
25 | |
26 | static int find_anything(struct device *dev, void *data) | |
27 | { | |
28 | return 1; | |
29 | } | |
1da177e4 | 30 | |
ed4aaadb ZY |
31 | /* |
32 | * Some device drivers need know if pci is initiated. | |
33 | * Basically, we think pci is not initiated when there | |
70308923 | 34 | * is no device to be found on the pci_bus_type. |
ed4aaadb ZY |
35 | */ |
36 | int no_pci_devices(void) | |
37 | { | |
70308923 GKH |
38 | struct device *dev; |
39 | int no_devices; | |
ed4aaadb | 40 | |
70308923 GKH |
41 | dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything); |
42 | no_devices = (dev == NULL); | |
43 | put_device(dev); | |
44 | return no_devices; | |
45 | } | |
ed4aaadb ZY |
46 | EXPORT_SYMBOL(no_pci_devices); |
47 | ||
1da177e4 LT |
48 | /* |
49 | * PCI Bus Class Devices | |
50 | */ | |
fd7d1ced | 51 | static ssize_t pci_bus_show_cpuaffinity(struct device *dev, |
39106dcf | 52 | int type, |
fd7d1ced | 53 | struct device_attribute *attr, |
4327edf6 | 54 | char *buf) |
1da177e4 | 55 | { |
1da177e4 | 56 | int ret; |
588235bb | 57 | const struct cpumask *cpumask; |
1da177e4 | 58 | |
588235bb | 59 | cpumask = cpumask_of_pcibus(to_pci_bus(dev)); |
39106dcf | 60 | ret = type? |
588235bb MT |
61 | cpulist_scnprintf(buf, PAGE_SIZE-2, cpumask) : |
62 | cpumask_scnprintf(buf, PAGE_SIZE-2, cpumask); | |
39106dcf MT |
63 | buf[ret++] = '\n'; |
64 | buf[ret] = '\0'; | |
1da177e4 LT |
65 | return ret; |
66 | } | |
39106dcf MT |
67 | |
68 | static ssize_t inline pci_bus_show_cpumaskaffinity(struct device *dev, | |
69 | struct device_attribute *attr, | |
70 | char *buf) | |
71 | { | |
72 | return pci_bus_show_cpuaffinity(dev, 0, attr, buf); | |
73 | } | |
74 | ||
75 | static ssize_t inline pci_bus_show_cpulistaffinity(struct device *dev, | |
76 | struct device_attribute *attr, | |
77 | char *buf) | |
78 | { | |
79 | return pci_bus_show_cpuaffinity(dev, 1, attr, buf); | |
80 | } | |
81 | ||
82 | DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpumaskaffinity, NULL); | |
83 | DEVICE_ATTR(cpulistaffinity, S_IRUGO, pci_bus_show_cpulistaffinity, NULL); | |
1da177e4 LT |
84 | |
85 | /* | |
86 | * PCI Bus Class | |
87 | */ | |
fd7d1ced | 88 | static void release_pcibus_dev(struct device *dev) |
1da177e4 | 89 | { |
fd7d1ced | 90 | struct pci_bus *pci_bus = to_pci_bus(dev); |
1da177e4 LT |
91 | |
92 | if (pci_bus->bridge) | |
93 | put_device(pci_bus->bridge); | |
94 | kfree(pci_bus); | |
95 | } | |
96 | ||
97 | static struct class pcibus_class = { | |
98 | .name = "pci_bus", | |
fd7d1ced | 99 | .dev_release = &release_pcibus_dev, |
1da177e4 LT |
100 | }; |
101 | ||
102 | static int __init pcibus_class_init(void) | |
103 | { | |
104 | return class_register(&pcibus_class); | |
105 | } | |
106 | postcore_initcall(pcibus_class_init); | |
107 | ||
108 | /* | |
109 | * Translate the low bits of the PCI base | |
110 | * to the resource type | |
111 | */ | |
112 | static inline unsigned int pci_calc_resource_flags(unsigned int flags) | |
113 | { | |
114 | if (flags & PCI_BASE_ADDRESS_SPACE_IO) | |
115 | return IORESOURCE_IO; | |
116 | ||
117 | if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) | |
118 | return IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
119 | ||
120 | return IORESOURCE_MEM; | |
121 | } | |
122 | ||
6ac665c6 | 123 | static u64 pci_size(u64 base, u64 maxbase, u64 mask) |
1da177e4 | 124 | { |
6ac665c6 | 125 | u64 size = mask & maxbase; /* Find the significant bits */ |
1da177e4 LT |
126 | if (!size) |
127 | return 0; | |
128 | ||
129 | /* Get the lowest of them to find the decode size, and | |
130 | from that the extent. */ | |
131 | size = (size & ~(size-1)) - 1; | |
132 | ||
133 | /* base == maxbase can be valid only if the BAR has | |
134 | already been programmed with all 1s. */ | |
135 | if (base == maxbase && ((base | size) & mask) != mask) | |
136 | return 0; | |
137 | ||
138 | return size; | |
139 | } | |
140 | ||
6ac665c6 MW |
141 | static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar) |
142 | { | |
143 | if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { | |
144 | res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK; | |
145 | return pci_bar_io; | |
146 | } | |
07eddf3d | 147 | |
6ac665c6 | 148 | res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK; |
07eddf3d | 149 | |
e354597c | 150 | if (res->flags & PCI_BASE_ADDRESS_MEM_TYPE_64) |
6ac665c6 MW |
151 | return pci_bar_mem64; |
152 | return pci_bar_mem32; | |
07eddf3d YL |
153 | } |
154 | ||
0b400c7e YZ |
155 | /** |
156 | * pci_read_base - read a PCI BAR | |
157 | * @dev: the PCI device | |
158 | * @type: type of the BAR | |
159 | * @res: resource buffer to be filled in | |
160 | * @pos: BAR position in the config space | |
161 | * | |
162 | * Returns 1 if the BAR is 64-bit, or 0 if 32-bit. | |
6ac665c6 | 163 | */ |
0b400c7e | 164 | int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, |
6ac665c6 | 165 | struct resource *res, unsigned int pos) |
07eddf3d | 166 | { |
6ac665c6 MW |
167 | u32 l, sz, mask; |
168 | ||
1ed67439 | 169 | mask = type ? PCI_ROM_ADDRESS_MASK : ~0; |
6ac665c6 MW |
170 | |
171 | res->name = pci_name(dev); | |
172 | ||
173 | pci_read_config_dword(dev, pos, &l); | |
1ed67439 | 174 | pci_write_config_dword(dev, pos, l | mask); |
6ac665c6 MW |
175 | pci_read_config_dword(dev, pos, &sz); |
176 | pci_write_config_dword(dev, pos, l); | |
177 | ||
178 | /* | |
179 | * All bits set in sz means the device isn't working properly. | |
180 | * If the BAR isn't implemented, all bits must be 0. If it's a | |
181 | * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit | |
182 | * 1 must be clear. | |
183 | */ | |
184 | if (!sz || sz == 0xffffffff) | |
185 | goto fail; | |
186 | ||
187 | /* | |
188 | * I don't know how l can have all bits set. Copied from old code. | |
189 | * Maybe it fixes a bug on some ancient platform. | |
190 | */ | |
191 | if (l == 0xffffffff) | |
192 | l = 0; | |
193 | ||
194 | if (type == pci_bar_unknown) { | |
195 | type = decode_bar(res, l); | |
196 | res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN; | |
197 | if (type == pci_bar_io) { | |
198 | l &= PCI_BASE_ADDRESS_IO_MASK; | |
1f82de10 | 199 | mask = PCI_BASE_ADDRESS_IO_MASK & IO_SPACE_LIMIT; |
6ac665c6 MW |
200 | } else { |
201 | l &= PCI_BASE_ADDRESS_MEM_MASK; | |
202 | mask = (u32)PCI_BASE_ADDRESS_MEM_MASK; | |
203 | } | |
204 | } else { | |
205 | res->flags |= (l & IORESOURCE_ROM_ENABLE); | |
206 | l &= PCI_ROM_ADDRESS_MASK; | |
207 | mask = (u32)PCI_ROM_ADDRESS_MASK; | |
208 | } | |
209 | ||
210 | if (type == pci_bar_mem64) { | |
211 | u64 l64 = l; | |
212 | u64 sz64 = sz; | |
213 | u64 mask64 = mask | (u64)~0 << 32; | |
214 | ||
215 | pci_read_config_dword(dev, pos + 4, &l); | |
216 | pci_write_config_dword(dev, pos + 4, ~0); | |
217 | pci_read_config_dword(dev, pos + 4, &sz); | |
218 | pci_write_config_dword(dev, pos + 4, l); | |
219 | ||
220 | l64 |= ((u64)l << 32); | |
221 | sz64 |= ((u64)sz << 32); | |
222 | ||
223 | sz64 = pci_size(l64, sz64, mask64); | |
224 | ||
225 | if (!sz64) | |
226 | goto fail; | |
227 | ||
cc5499c3 | 228 | if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) { |
6ac665c6 MW |
229 | dev_err(&dev->dev, "can't handle 64-bit BAR\n"); |
230 | goto fail; | |
c7dabef8 BH |
231 | } |
232 | ||
233 | res->flags |= IORESOURCE_MEM_64; | |
234 | if ((sizeof(resource_size_t) < 8) && l) { | |
6ac665c6 MW |
235 | /* Address above 32-bit boundary; disable the BAR */ |
236 | pci_write_config_dword(dev, pos, 0); | |
237 | pci_write_config_dword(dev, pos + 4, 0); | |
238 | res->start = 0; | |
239 | res->end = sz64; | |
240 | } else { | |
241 | res->start = l64; | |
242 | res->end = l64 + sz64; | |
c7dabef8 | 243 | dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", |
a369c791 | 244 | pos, res); |
6ac665c6 MW |
245 | } |
246 | } else { | |
247 | sz = pci_size(l, sz, mask); | |
248 | ||
249 | if (!sz) | |
250 | goto fail; | |
251 | ||
252 | res->start = l; | |
253 | res->end = l + sz; | |
f393d9b1 | 254 | |
c7dabef8 | 255 | dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", pos, res); |
6ac665c6 MW |
256 | } |
257 | ||
258 | out: | |
259 | return (type == pci_bar_mem64) ? 1 : 0; | |
260 | fail: | |
261 | res->flags = 0; | |
262 | goto out; | |
07eddf3d YL |
263 | } |
264 | ||
1da177e4 LT |
265 | static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) |
266 | { | |
6ac665c6 | 267 | unsigned int pos, reg; |
07eddf3d | 268 | |
6ac665c6 MW |
269 | for (pos = 0; pos < howmany; pos++) { |
270 | struct resource *res = &dev->resource[pos]; | |
1da177e4 | 271 | reg = PCI_BASE_ADDRESS_0 + (pos << 2); |
6ac665c6 | 272 | pos += __pci_read_base(dev, pci_bar_unknown, res, reg); |
1da177e4 | 273 | } |
6ac665c6 | 274 | |
1da177e4 | 275 | if (rom) { |
6ac665c6 | 276 | struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; |
1da177e4 | 277 | dev->rom_base_reg = rom; |
6ac665c6 MW |
278 | res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | |
279 | IORESOURCE_READONLY | IORESOURCE_CACHEABLE | | |
280 | IORESOURCE_SIZEALIGN; | |
281 | __pci_read_base(dev, pci_bar_mem32, res, rom); | |
1da177e4 LT |
282 | } |
283 | } | |
284 | ||
0ab2b57f | 285 | void __devinit pci_read_bridge_bases(struct pci_bus *child) |
1da177e4 LT |
286 | { |
287 | struct pci_dev *dev = child->self; | |
288 | u8 io_base_lo, io_limit_lo; | |
289 | u16 mem_base_lo, mem_limit_lo; | |
290 | unsigned long base, limit; | |
291 | struct resource *res; | |
292 | int i; | |
293 | ||
9fc39256 | 294 | if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */ |
1da177e4 LT |
295 | return; |
296 | ||
297 | if (dev->transparent) { | |
80ccba11 | 298 | dev_info(&dev->dev, "transparent bridge\n"); |
90b54929 IK |
299 | for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++) |
300 | child->resource[i] = child->parent->resource[i - 3]; | |
1da177e4 LT |
301 | } |
302 | ||
1da177e4 LT |
303 | res = child->resource[0]; |
304 | pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); | |
305 | pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); | |
306 | base = (io_base_lo & PCI_IO_RANGE_MASK) << 8; | |
307 | limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8; | |
308 | ||
309 | if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { | |
310 | u16 io_base_hi, io_limit_hi; | |
311 | pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); | |
312 | pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); | |
313 | base |= (io_base_hi << 16); | |
314 | limit |= (io_limit_hi << 16); | |
315 | } | |
316 | ||
317 | if (base <= limit) { | |
318 | res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; | |
9d265124 DY |
319 | if (!res->start) |
320 | res->start = base; | |
321 | if (!res->end) | |
322 | res->end = limit + 0xfff; | |
c7dabef8 | 323 | dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); |
1da177e4 LT |
324 | } |
325 | ||
326 | res = child->resource[1]; | |
327 | pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); | |
328 | pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); | |
329 | base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; | |
330 | limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; | |
331 | if (base <= limit) { | |
332 | res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; | |
333 | res->start = base; | |
334 | res->end = limit + 0xfffff; | |
c7dabef8 | 335 | dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); |
1da177e4 LT |
336 | } |
337 | ||
338 | res = child->resource[2]; | |
339 | pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); | |
340 | pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); | |
341 | base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; | |
342 | limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; | |
343 | ||
344 | if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { | |
345 | u32 mem_base_hi, mem_limit_hi; | |
346 | pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); | |
347 | pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); | |
348 | ||
349 | /* | |
350 | * Some bridges set the base > limit by default, and some | |
351 | * (broken) BIOSes do not initialize them. If we find | |
352 | * this, just assume they are not being used. | |
353 | */ | |
354 | if (mem_base_hi <= mem_limit_hi) { | |
355 | #if BITS_PER_LONG == 64 | |
356 | base |= ((long) mem_base_hi) << 32; | |
357 | limit |= ((long) mem_limit_hi) << 32; | |
358 | #else | |
359 | if (mem_base_hi || mem_limit_hi) { | |
80ccba11 BH |
360 | dev_err(&dev->dev, "can't handle 64-bit " |
361 | "address space for bridge\n"); | |
1da177e4 LT |
362 | return; |
363 | } | |
364 | #endif | |
365 | } | |
366 | } | |
367 | if (base <= limit) { | |
1f82de10 YL |
368 | res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) | |
369 | IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
370 | if (res->flags & PCI_PREF_RANGE_TYPE_64) | |
371 | res->flags |= IORESOURCE_MEM_64; | |
1da177e4 LT |
372 | res->start = base; |
373 | res->end = limit + 0xfffff; | |
c7dabef8 | 374 | dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); |
1da177e4 LT |
375 | } |
376 | } | |
377 | ||
96bde06a | 378 | static struct pci_bus * pci_alloc_bus(void) |
1da177e4 LT |
379 | { |
380 | struct pci_bus *b; | |
381 | ||
f5afe806 | 382 | b = kzalloc(sizeof(*b), GFP_KERNEL); |
1da177e4 | 383 | if (b) { |
1da177e4 LT |
384 | INIT_LIST_HEAD(&b->node); |
385 | INIT_LIST_HEAD(&b->children); | |
386 | INIT_LIST_HEAD(&b->devices); | |
f46753c5 | 387 | INIT_LIST_HEAD(&b->slots); |
1da177e4 LT |
388 | } |
389 | return b; | |
390 | } | |
391 | ||
cbd4e055 AB |
392 | static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, |
393 | struct pci_dev *bridge, int busnr) | |
1da177e4 LT |
394 | { |
395 | struct pci_bus *child; | |
396 | int i; | |
397 | ||
398 | /* | |
399 | * Allocate a new bus, and inherit stuff from the parent.. | |
400 | */ | |
401 | child = pci_alloc_bus(); | |
402 | if (!child) | |
403 | return NULL; | |
404 | ||
1da177e4 LT |
405 | child->parent = parent; |
406 | child->ops = parent->ops; | |
407 | child->sysdata = parent->sysdata; | |
6e325a62 | 408 | child->bus_flags = parent->bus_flags; |
1da177e4 | 409 | |
fd7d1ced GKH |
410 | /* initialize some portions of the bus device, but don't register it |
411 | * now as the parent is not properly set up yet. This device will get | |
412 | * registered later in pci_bus_add_devices() | |
413 | */ | |
414 | child->dev.class = &pcibus_class; | |
1a927133 | 415 | dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr); |
1da177e4 LT |
416 | |
417 | /* | |
418 | * Set up the primary, secondary and subordinate | |
419 | * bus numbers. | |
420 | */ | |
421 | child->number = child->secondary = busnr; | |
422 | child->primary = parent->secondary; | |
423 | child->subordinate = 0xff; | |
424 | ||
3789fa8a YZ |
425 | if (!bridge) |
426 | return child; | |
427 | ||
428 | child->self = bridge; | |
429 | child->bridge = get_device(&bridge->dev); | |
430 | ||
1da177e4 | 431 | /* Set up default resource pointers and names.. */ |
fde09c6d | 432 | for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { |
1da177e4 LT |
433 | child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; |
434 | child->resource[i]->name = child->name; | |
435 | } | |
436 | bridge->subordinate = child; | |
437 | ||
438 | return child; | |
439 | } | |
440 | ||
451124a7 | 441 | struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr) |
1da177e4 LT |
442 | { |
443 | struct pci_bus *child; | |
444 | ||
445 | child = pci_alloc_child_bus(parent, dev, busnr); | |
e4ea9bb7 | 446 | if (child) { |
d71374da | 447 | down_write(&pci_bus_sem); |
1da177e4 | 448 | list_add_tail(&child->node, &parent->children); |
d71374da | 449 | up_write(&pci_bus_sem); |
e4ea9bb7 | 450 | } |
1da177e4 LT |
451 | return child; |
452 | } | |
453 | ||
96bde06a | 454 | static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max) |
26f674ae GKH |
455 | { |
456 | struct pci_bus *parent = child->parent; | |
12f44f46 IK |
457 | |
458 | /* Attempts to fix that up are really dangerous unless | |
459 | we're going to re-assign all bus numbers. */ | |
460 | if (!pcibios_assign_all_busses()) | |
461 | return; | |
462 | ||
26f674ae GKH |
463 | while (parent->parent && parent->subordinate < max) { |
464 | parent->subordinate = max; | |
465 | pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max); | |
466 | parent = parent->parent; | |
467 | } | |
468 | } | |
469 | ||
1da177e4 LT |
470 | /* |
471 | * If it's a bridge, configure it and scan the bus behind it. | |
472 | * For CardBus bridges, we don't scan behind as the devices will | |
473 | * be handled by the bridge driver itself. | |
474 | * | |
475 | * We need to process bridges in two passes -- first we scan those | |
476 | * already configured by the BIOS and after we are done with all of | |
477 | * them, we proceed to assigning numbers to the remaining buses in | |
478 | * order to avoid overlaps between old and new bus numbers. | |
479 | */ | |
0ab2b57f | 480 | int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) |
1da177e4 LT |
481 | { |
482 | struct pci_bus *child; | |
483 | int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); | |
49887941 | 484 | u32 buses, i, j = 0; |
1da177e4 | 485 | u16 bctl; |
a1c19894 | 486 | int broken = 0; |
1da177e4 LT |
487 | |
488 | pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); | |
489 | ||
80ccba11 BH |
490 | dev_dbg(&dev->dev, "scanning behind bridge, config %06x, pass %d\n", |
491 | buses & 0xffffff, pass); | |
1da177e4 | 492 | |
a1c19894 BH |
493 | /* Check if setup is sensible at all */ |
494 | if (!pass && | |
495 | ((buses & 0xff) != bus->number || ((buses >> 8) & 0xff) <= bus->number)) { | |
496 | dev_dbg(&dev->dev, "bus configuration invalid, reconfiguring\n"); | |
497 | broken = 1; | |
498 | } | |
499 | ||
1da177e4 LT |
500 | /* Disable MasterAbortMode during probing to avoid reporting |
501 | of bus errors (in some architectures) */ | |
502 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); | |
503 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, | |
504 | bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); | |
505 | ||
a1c19894 | 506 | if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus && !broken) { |
1da177e4 LT |
507 | unsigned int cmax, busnr; |
508 | /* | |
509 | * Bus already configured by firmware, process it in the first | |
510 | * pass and just note the configuration. | |
511 | */ | |
512 | if (pass) | |
bbe8f9a3 | 513 | goto out; |
1da177e4 LT |
514 | busnr = (buses >> 8) & 0xFF; |
515 | ||
516 | /* | |
517 | * If we already got to this bus through a different bridge, | |
74710ded AC |
518 | * don't re-add it. This can happen with the i450NX chipset. |
519 | * | |
520 | * However, we continue to descend down the hierarchy and | |
521 | * scan remaining child buses. | |
1da177e4 | 522 | */ |
74710ded AC |
523 | child = pci_find_bus(pci_domain_nr(bus), busnr); |
524 | if (!child) { | |
525 | child = pci_add_new_bus(bus, dev, busnr); | |
526 | if (!child) | |
527 | goto out; | |
528 | child->primary = buses & 0xFF; | |
529 | child->subordinate = (buses >> 16) & 0xFF; | |
530 | child->bridge_ctl = bctl; | |
1da177e4 LT |
531 | } |
532 | ||
1da177e4 LT |
533 | cmax = pci_scan_child_bus(child); |
534 | if (cmax > max) | |
535 | max = cmax; | |
536 | if (child->subordinate > max) | |
537 | max = child->subordinate; | |
538 | } else { | |
539 | /* | |
540 | * We need to assign a number to this bus which we always | |
541 | * do in the second pass. | |
542 | */ | |
12f44f46 | 543 | if (!pass) { |
a1c19894 | 544 | if (pcibios_assign_all_busses() || broken) |
12f44f46 IK |
545 | /* Temporarily disable forwarding of the |
546 | configuration cycles on all bridges in | |
547 | this bus segment to avoid possible | |
548 | conflicts in the second pass between two | |
549 | bridges programmed with overlapping | |
550 | bus ranges. */ | |
551 | pci_write_config_dword(dev, PCI_PRIMARY_BUS, | |
552 | buses & ~0xffffff); | |
bbe8f9a3 | 553 | goto out; |
12f44f46 | 554 | } |
1da177e4 LT |
555 | |
556 | /* Clear errors */ | |
557 | pci_write_config_word(dev, PCI_STATUS, 0xffff); | |
558 | ||
cc57450f RS |
559 | /* Prevent assigning a bus number that already exists. |
560 | * This can happen when a bridge is hot-plugged */ | |
561 | if (pci_find_bus(pci_domain_nr(bus), max+1)) | |
bbe8f9a3 | 562 | goto out; |
6ef6f0e3 | 563 | child = pci_add_new_bus(bus, dev, ++max); |
1da177e4 LT |
564 | buses = (buses & 0xff000000) |
565 | | ((unsigned int)(child->primary) << 0) | |
566 | | ((unsigned int)(child->secondary) << 8) | |
567 | | ((unsigned int)(child->subordinate) << 16); | |
568 | ||
569 | /* | |
570 | * yenta.c forces a secondary latency timer of 176. | |
571 | * Copy that behaviour here. | |
572 | */ | |
573 | if (is_cardbus) { | |
574 | buses &= ~0xff000000; | |
575 | buses |= CARDBUS_LATENCY_TIMER << 24; | |
576 | } | |
577 | ||
578 | /* | |
579 | * We need to blast all three values with a single write. | |
580 | */ | |
581 | pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); | |
582 | ||
583 | if (!is_cardbus) { | |
11949255 | 584 | child->bridge_ctl = bctl; |
26f674ae GKH |
585 | /* |
586 | * Adjust subordinate busnr in parent buses. | |
587 | * We do this before scanning for children because | |
588 | * some devices may not be detected if the bios | |
589 | * was lazy. | |
590 | */ | |
591 | pci_fixup_parent_subordinate_busnr(child, max); | |
1da177e4 LT |
592 | /* Now we can scan all subordinate buses... */ |
593 | max = pci_scan_child_bus(child); | |
e3ac86d8 KA |
594 | /* |
595 | * now fix it up again since we have found | |
596 | * the real value of max. | |
597 | */ | |
598 | pci_fixup_parent_subordinate_busnr(child, max); | |
1da177e4 LT |
599 | } else { |
600 | /* | |
601 | * For CardBus bridges, we leave 4 bus numbers | |
602 | * as cards with a PCI-to-PCI bridge can be | |
603 | * inserted later. | |
604 | */ | |
49887941 DB |
605 | for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) { |
606 | struct pci_bus *parent = bus; | |
cc57450f RS |
607 | if (pci_find_bus(pci_domain_nr(bus), |
608 | max+i+1)) | |
609 | break; | |
49887941 DB |
610 | while (parent->parent) { |
611 | if ((!pcibios_assign_all_busses()) && | |
612 | (parent->subordinate > max) && | |
613 | (parent->subordinate <= max+i)) { | |
614 | j = 1; | |
615 | } | |
616 | parent = parent->parent; | |
617 | } | |
618 | if (j) { | |
619 | /* | |
620 | * Often, there are two cardbus bridges | |
621 | * -- try to leave one valid bus number | |
622 | * for each one. | |
623 | */ | |
624 | i /= 2; | |
625 | break; | |
626 | } | |
627 | } | |
cc57450f | 628 | max += i; |
26f674ae | 629 | pci_fixup_parent_subordinate_busnr(child, max); |
1da177e4 LT |
630 | } |
631 | /* | |
632 | * Set the subordinate bus number to its real value. | |
633 | */ | |
634 | child->subordinate = max; | |
635 | pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); | |
636 | } | |
637 | ||
cb3576fa GH |
638 | sprintf(child->name, |
639 | (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), | |
640 | pci_domain_nr(bus), child->number); | |
1da177e4 | 641 | |
d55bef51 | 642 | /* Has only triggered on CardBus, fixup is in yenta_socket */ |
49887941 DB |
643 | while (bus->parent) { |
644 | if ((child->subordinate > bus->subordinate) || | |
645 | (child->number > bus->subordinate) || | |
646 | (child->number < bus->number) || | |
647 | (child->subordinate < bus->number)) { | |
a6f29a98 | 648 | pr_debug("PCI: Bus #%02x (-#%02x) is %s " |
d55bef51 BK |
649 | "hidden behind%s bridge #%02x (-#%02x)\n", |
650 | child->number, child->subordinate, | |
651 | (bus->number > child->subordinate && | |
652 | bus->subordinate < child->number) ? | |
a6f29a98 JP |
653 | "wholly" : "partially", |
654 | bus->self->transparent ? " transparent" : "", | |
d55bef51 | 655 | bus->number, bus->subordinate); |
49887941 DB |
656 | } |
657 | bus = bus->parent; | |
658 | } | |
659 | ||
bbe8f9a3 RB |
660 | out: |
661 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl); | |
662 | ||
1da177e4 LT |
663 | return max; |
664 | } | |
665 | ||
666 | /* | |
667 | * Read interrupt line and base address registers. | |
668 | * The architecture-dependent code can tweak these, of course. | |
669 | */ | |
670 | static void pci_read_irq(struct pci_dev *dev) | |
671 | { | |
672 | unsigned char irq; | |
673 | ||
674 | pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); | |
ffeff788 | 675 | dev->pin = irq; |
1da177e4 LT |
676 | if (irq) |
677 | pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); | |
678 | dev->irq = irq; | |
679 | } | |
680 | ||
480b93b7 YZ |
681 | static void set_pcie_port_type(struct pci_dev *pdev) |
682 | { | |
683 | int pos; | |
684 | u16 reg16; | |
685 | ||
686 | pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); | |
687 | if (!pos) | |
688 | return; | |
689 | pdev->is_pcie = 1; | |
690 | pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); | |
691 | pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4; | |
692 | } | |
693 | ||
28760489 EB |
694 | static void set_pcie_hotplug_bridge(struct pci_dev *pdev) |
695 | { | |
696 | int pos; | |
697 | u16 reg16; | |
698 | u32 reg32; | |
699 | ||
700 | pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); | |
701 | if (!pos) | |
702 | return; | |
703 | pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); | |
704 | if (!(reg16 & PCI_EXP_FLAGS_SLOT)) | |
705 | return; | |
706 | pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, ®32); | |
707 | if (reg32 & PCI_EXP_SLTCAP_HPC) | |
708 | pdev->is_hotplug_bridge = 1; | |
709 | } | |
710 | ||
05843961 MD |
711 | static void set_pci_aer_firmware_first(struct pci_dev *pdev) |
712 | { | |
713 | if (acpi_hest_firmware_first_pci(pdev)) | |
714 | pdev->aer_firmware_first = 1; | |
715 | } | |
716 | ||
01abc2aa | 717 | #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) |
76e6a1d6 | 718 | |
1da177e4 LT |
719 | /** |
720 | * pci_setup_device - fill in class and map information of a device | |
721 | * @dev: the device structure to fill | |
722 | * | |
723 | * Initialize the device structure with information about the device's | |
724 | * vendor,class,memory and IO-space addresses,IRQ lines etc. | |
725 | * Called at initialisation of the PCI subsystem and by CardBus services. | |
480b93b7 YZ |
726 | * Returns 0 on success and negative if unknown type of device (not normal, |
727 | * bridge or CardBus). | |
1da177e4 | 728 | */ |
480b93b7 | 729 | int pci_setup_device(struct pci_dev *dev) |
1da177e4 LT |
730 | { |
731 | u32 class; | |
480b93b7 YZ |
732 | u8 hdr_type; |
733 | struct pci_slot *slot; | |
bc577d2b | 734 | int pos = 0; |
480b93b7 YZ |
735 | |
736 | if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type)) | |
737 | return -EIO; | |
738 | ||
739 | dev->sysdata = dev->bus->sysdata; | |
740 | dev->dev.parent = dev->bus->bridge; | |
741 | dev->dev.bus = &pci_bus_type; | |
742 | dev->hdr_type = hdr_type & 0x7f; | |
743 | dev->multifunction = !!(hdr_type & 0x80); | |
480b93b7 YZ |
744 | dev->error_state = pci_channel_io_normal; |
745 | set_pcie_port_type(dev); | |
05843961 | 746 | set_pci_aer_firmware_first(dev); |
480b93b7 YZ |
747 | |
748 | list_for_each_entry(slot, &dev->bus->slots, list) | |
749 | if (PCI_SLOT(dev->devfn) == slot->number) | |
750 | dev->slot = slot; | |
751 | ||
752 | /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) | |
753 | set this higher, assuming the system even supports it. */ | |
754 | dev->dma_mask = 0xffffffff; | |
1da177e4 | 755 | |
eebfcfb5 GKH |
756 | dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), |
757 | dev->bus->number, PCI_SLOT(dev->devfn), | |
758 | PCI_FUNC(dev->devfn)); | |
1da177e4 LT |
759 | |
760 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); | |
b8a3a521 | 761 | dev->revision = class & 0xff; |
1da177e4 LT |
762 | class >>= 8; /* upper 3 bytes */ |
763 | dev->class = class; | |
764 | class >>= 8; | |
765 | ||
34a2e15e | 766 | dev_dbg(&dev->dev, "found [%04x:%04x] class %06x header type %02x\n", |
1da177e4 LT |
767 | dev->vendor, dev->device, class, dev->hdr_type); |
768 | ||
853346e4 YZ |
769 | /* need to have dev->class ready */ |
770 | dev->cfg_size = pci_cfg_space_size(dev); | |
771 | ||
1da177e4 | 772 | /* "Unknown power state" */ |
3fe9d19f | 773 | dev->current_state = PCI_UNKNOWN; |
1da177e4 LT |
774 | |
775 | /* Early fixups, before probing the BARs */ | |
776 | pci_fixup_device(pci_fixup_early, dev); | |
f79b1b14 YZ |
777 | /* device class may be changed after fixup */ |
778 | class = dev->class >> 8; | |
1da177e4 LT |
779 | |
780 | switch (dev->hdr_type) { /* header type */ | |
781 | case PCI_HEADER_TYPE_NORMAL: /* standard header */ | |
782 | if (class == PCI_CLASS_BRIDGE_PCI) | |
783 | goto bad; | |
784 | pci_read_irq(dev); | |
785 | pci_read_bases(dev, 6, PCI_ROM_ADDRESS); | |
786 | pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); | |
787 | pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device); | |
368c73d4 AC |
788 | |
789 | /* | |
790 | * Do the ugly legacy mode stuff here rather than broken chip | |
791 | * quirk code. Legacy mode ATA controllers have fixed | |
792 | * addresses. These are not always echoed in BAR0-3, and | |
793 | * BAR0-3 in a few cases contain junk! | |
794 | */ | |
795 | if (class == PCI_CLASS_STORAGE_IDE) { | |
796 | u8 progif; | |
797 | pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); | |
798 | if ((progif & 1) == 0) { | |
af1bff4f LT |
799 | dev->resource[0].start = 0x1F0; |
800 | dev->resource[0].end = 0x1F7; | |
801 | dev->resource[0].flags = LEGACY_IO_RESOURCE; | |
802 | dev->resource[1].start = 0x3F6; | |
803 | dev->resource[1].end = 0x3F6; | |
804 | dev->resource[1].flags = LEGACY_IO_RESOURCE; | |
368c73d4 AC |
805 | } |
806 | if ((progif & 4) == 0) { | |
af1bff4f LT |
807 | dev->resource[2].start = 0x170; |
808 | dev->resource[2].end = 0x177; | |
809 | dev->resource[2].flags = LEGACY_IO_RESOURCE; | |
810 | dev->resource[3].start = 0x376; | |
811 | dev->resource[3].end = 0x376; | |
812 | dev->resource[3].flags = LEGACY_IO_RESOURCE; | |
368c73d4 AC |
813 | } |
814 | } | |
1da177e4 LT |
815 | break; |
816 | ||
817 | case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ | |
818 | if (class != PCI_CLASS_BRIDGE_PCI) | |
819 | goto bad; | |
820 | /* The PCI-to-PCI bridge spec requires that subtractive | |
821 | decoding (i.e. transparent) bridge must have programming | |
822 | interface code of 0x01. */ | |
3efd273b | 823 | pci_read_irq(dev); |
1da177e4 LT |
824 | dev->transparent = ((dev->class & 0xff) == 1); |
825 | pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); | |
28760489 | 826 | set_pcie_hotplug_bridge(dev); |
bc577d2b GB |
827 | pos = pci_find_capability(dev, PCI_CAP_ID_SSVID); |
828 | if (pos) { | |
829 | pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor); | |
830 | pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device); | |
831 | } | |
1da177e4 LT |
832 | break; |
833 | ||
834 | case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ | |
835 | if (class != PCI_CLASS_BRIDGE_CARDBUS) | |
836 | goto bad; | |
837 | pci_read_irq(dev); | |
838 | pci_read_bases(dev, 1, 0); | |
839 | pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); | |
840 | pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); | |
841 | break; | |
842 | ||
843 | default: /* unknown header */ | |
80ccba11 BH |
844 | dev_err(&dev->dev, "unknown header type %02x, " |
845 | "ignoring device\n", dev->hdr_type); | |
480b93b7 | 846 | return -EIO; |
1da177e4 LT |
847 | |
848 | bad: | |
80ccba11 BH |
849 | dev_err(&dev->dev, "ignoring class %02x (doesn't match header " |
850 | "type %02x)\n", class, dev->hdr_type); | |
1da177e4 LT |
851 | dev->class = PCI_CLASS_NOT_DEFINED; |
852 | } | |
853 | ||
854 | /* We found a fine healthy device, go go go... */ | |
855 | return 0; | |
856 | } | |
857 | ||
201de56e ZY |
858 | static void pci_release_capabilities(struct pci_dev *dev) |
859 | { | |
860 | pci_vpd_release(dev); | |
d1b054da | 861 | pci_iov_release(dev); |
201de56e ZY |
862 | } |
863 | ||
1da177e4 LT |
864 | /** |
865 | * pci_release_dev - free a pci device structure when all users of it are finished. | |
866 | * @dev: device that's been disconnected | |
867 | * | |
868 | * Will be called only by the device core when all users of this pci device are | |
869 | * done. | |
870 | */ | |
871 | static void pci_release_dev(struct device *dev) | |
872 | { | |
873 | struct pci_dev *pci_dev; | |
874 | ||
875 | pci_dev = to_pci_dev(dev); | |
201de56e | 876 | pci_release_capabilities(pci_dev); |
1da177e4 LT |
877 | kfree(pci_dev); |
878 | } | |
879 | ||
880 | /** | |
881 | * pci_cfg_space_size - get the configuration space size of the PCI device. | |
8f7020d3 | 882 | * @dev: PCI device |
1da177e4 LT |
883 | * |
884 | * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices | |
885 | * have 4096 bytes. Even if the device is capable, that doesn't mean we can | |
886 | * access it. Maybe we don't have a way to generate extended config space | |
887 | * accesses, or the device is behind a reverse Express bridge. So we try | |
888 | * reading the dword at 0x100 which must either be 0 or a valid extended | |
889 | * capability header. | |
890 | */ | |
70b9f7dc | 891 | int pci_cfg_space_size_ext(struct pci_dev *dev) |
1da177e4 | 892 | { |
1da177e4 | 893 | u32 status; |
557848c3 | 894 | int pos = PCI_CFG_SPACE_SIZE; |
1da177e4 | 895 | |
557848c3 | 896 | if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL) |
70b9f7dc YL |
897 | goto fail; |
898 | if (status == 0xffffffff) | |
899 | goto fail; | |
900 | ||
901 | return PCI_CFG_SPACE_EXP_SIZE; | |
902 | ||
903 | fail: | |
904 | return PCI_CFG_SPACE_SIZE; | |
905 | } | |
906 | ||
907 | int pci_cfg_space_size(struct pci_dev *dev) | |
908 | { | |
909 | int pos; | |
910 | u32 status; | |
dfadd9ed YL |
911 | u16 class; |
912 | ||
913 | class = dev->class >> 8; | |
914 | if (class == PCI_CLASS_BRIDGE_HOST) | |
915 | return pci_cfg_space_size_ext(dev); | |
57741a77 | 916 | |
1da177e4 LT |
917 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); |
918 | if (!pos) { | |
919 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
920 | if (!pos) | |
921 | goto fail; | |
922 | ||
923 | pci_read_config_dword(dev, pos + PCI_X_STATUS, &status); | |
924 | if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))) | |
925 | goto fail; | |
926 | } | |
927 | ||
70b9f7dc | 928 | return pci_cfg_space_size_ext(dev); |
1da177e4 LT |
929 | |
930 | fail: | |
931 | return PCI_CFG_SPACE_SIZE; | |
932 | } | |
933 | ||
934 | static void pci_release_bus_bridge_dev(struct device *dev) | |
935 | { | |
936 | kfree(dev); | |
937 | } | |
938 | ||
65891215 ME |
939 | struct pci_dev *alloc_pci_dev(void) |
940 | { | |
941 | struct pci_dev *dev; | |
942 | ||
943 | dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); | |
944 | if (!dev) | |
945 | return NULL; | |
946 | ||
65891215 ME |
947 | INIT_LIST_HEAD(&dev->bus_list); |
948 | ||
949 | return dev; | |
950 | } | |
951 | EXPORT_SYMBOL(alloc_pci_dev); | |
952 | ||
1da177e4 LT |
953 | /* |
954 | * Read the config data for a PCI device, sanity-check it | |
955 | * and fill in the dev structure... | |
956 | */ | |
7f7b5de2 | 957 | static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) |
1da177e4 LT |
958 | { |
959 | struct pci_dev *dev; | |
960 | u32 l; | |
1da177e4 LT |
961 | int delay = 1; |
962 | ||
963 | if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l)) | |
964 | return NULL; | |
965 | ||
966 | /* some broken boards return 0 or ~0 if a slot is empty: */ | |
967 | if (l == 0xffffffff || l == 0x00000000 || | |
968 | l == 0x0000ffff || l == 0xffff0000) | |
969 | return NULL; | |
970 | ||
971 | /* Configuration request Retry Status */ | |
972 | while (l == 0xffff0001) { | |
973 | msleep(delay); | |
974 | delay *= 2; | |
975 | if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l)) | |
976 | return NULL; | |
977 | /* Card hasn't responded in 60 seconds? Must be stuck. */ | |
978 | if (delay > 60 * 1000) { | |
80ccba11 | 979 | printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not " |
1da177e4 LT |
980 | "responding\n", pci_domain_nr(bus), |
981 | bus->number, PCI_SLOT(devfn), | |
982 | PCI_FUNC(devfn)); | |
983 | return NULL; | |
984 | } | |
985 | } | |
986 | ||
bab41e9b | 987 | dev = alloc_pci_dev(); |
1da177e4 LT |
988 | if (!dev) |
989 | return NULL; | |
990 | ||
1da177e4 | 991 | dev->bus = bus; |
1da177e4 | 992 | dev->devfn = devfn; |
1da177e4 LT |
993 | dev->vendor = l & 0xffff; |
994 | dev->device = (l >> 16) & 0xffff; | |
cef354db | 995 | |
480b93b7 | 996 | if (pci_setup_device(dev)) { |
1da177e4 LT |
997 | kfree(dev); |
998 | return NULL; | |
999 | } | |
1da177e4 LT |
1000 | |
1001 | return dev; | |
1002 | } | |
1003 | ||
201de56e ZY |
1004 | static void pci_init_capabilities(struct pci_dev *dev) |
1005 | { | |
1006 | /* MSI/MSI-X list */ | |
1007 | pci_msi_init_pci_dev(dev); | |
1008 | ||
63f4898a RW |
1009 | /* Buffers for saving PCIe and PCI-X capabilities */ |
1010 | pci_allocate_cap_save_buffers(dev); | |
1011 | ||
201de56e ZY |
1012 | /* Power Management */ |
1013 | pci_pm_init(dev); | |
eb9c39d0 | 1014 | platform_pci_wakeup_init(dev); |
201de56e ZY |
1015 | |
1016 | /* Vital Product Data */ | |
1017 | pci_vpd_pci22_init(dev); | |
58c3a727 YZ |
1018 | |
1019 | /* Alternative Routing-ID Forwarding */ | |
1020 | pci_enable_ari(dev); | |
d1b054da YZ |
1021 | |
1022 | /* Single Root I/O Virtualization */ | |
1023 | pci_iov_init(dev); | |
ae21ee65 AK |
1024 | |
1025 | /* Enable ACS P2P upstream forwarding */ | |
df0e97c6 | 1026 | if (iommu_found() || xen_initial_domain()) |
ae21ee65 | 1027 | pci_enable_acs(dev); |
201de56e ZY |
1028 | } |
1029 | ||
96bde06a | 1030 | void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) |
1da177e4 | 1031 | { |
cdb9b9f7 PM |
1032 | device_initialize(&dev->dev); |
1033 | dev->dev.release = pci_release_dev; | |
1034 | pci_dev_get(dev); | |
1da177e4 | 1035 | |
cdb9b9f7 | 1036 | dev->dev.dma_mask = &dev->dma_mask; |
4d57cdfa | 1037 | dev->dev.dma_parms = &dev->dma_parms; |
cdb9b9f7 | 1038 | dev->dev.coherent_dma_mask = 0xffffffffull; |
1da177e4 | 1039 | |
4d57cdfa | 1040 | pci_set_dma_max_seg_size(dev, 65536); |
59fc67de | 1041 | pci_set_dma_seg_boundary(dev, 0xffffffff); |
4d57cdfa | 1042 | |
1da177e4 LT |
1043 | /* Fix up broken headers */ |
1044 | pci_fixup_device(pci_fixup_header, dev); | |
1045 | ||
4b77b0a2 RW |
1046 | /* Clear the state_saved flag. */ |
1047 | dev->state_saved = false; | |
1048 | ||
201de56e ZY |
1049 | /* Initialize various capabilities */ |
1050 | pci_init_capabilities(dev); | |
eb9d0fe4 | 1051 | |
1da177e4 LT |
1052 | /* |
1053 | * Add the device to our list of discovered devices | |
1054 | * and the bus list for fixup functions, etc. | |
1055 | */ | |
d71374da | 1056 | down_write(&pci_bus_sem); |
1da177e4 | 1057 | list_add_tail(&dev->bus_list, &bus->devices); |
d71374da | 1058 | up_write(&pci_bus_sem); |
cdb9b9f7 PM |
1059 | } |
1060 | ||
451124a7 | 1061 | struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn) |
cdb9b9f7 PM |
1062 | { |
1063 | struct pci_dev *dev; | |
1064 | ||
90bdb311 TP |
1065 | dev = pci_get_slot(bus, devfn); |
1066 | if (dev) { | |
1067 | pci_dev_put(dev); | |
1068 | return dev; | |
1069 | } | |
1070 | ||
cdb9b9f7 PM |
1071 | dev = pci_scan_device(bus, devfn); |
1072 | if (!dev) | |
1073 | return NULL; | |
1074 | ||
1075 | pci_device_add(dev, bus); | |
1da177e4 LT |
1076 | |
1077 | return dev; | |
1078 | } | |
b73e9687 | 1079 | EXPORT_SYMBOL(pci_scan_single_device); |
1da177e4 LT |
1080 | |
1081 | /** | |
1082 | * pci_scan_slot - scan a PCI slot on a bus for devices. | |
1083 | * @bus: PCI bus to scan | |
1084 | * @devfn: slot number to scan (must have zero function.) | |
1085 | * | |
1086 | * Scan a PCI slot on the specified PCI bus for devices, adding | |
1087 | * discovered devices to the @bus->devices list. New devices | |
8a1bc901 | 1088 | * will not have is_added set. |
1b69dfc6 TP |
1089 | * |
1090 | * Returns the number of new devices found. | |
1da177e4 | 1091 | */ |
96bde06a | 1092 | int pci_scan_slot(struct pci_bus *bus, int devfn) |
1da177e4 | 1093 | { |
1b69dfc6 TP |
1094 | int fn, nr = 0; |
1095 | struct pci_dev *dev; | |
1da177e4 | 1096 | |
1b69dfc6 TP |
1097 | dev = pci_scan_single_device(bus, devfn); |
1098 | if (dev && !dev->is_added) /* new device? */ | |
1099 | nr++; | |
1100 | ||
a7db5040 | 1101 | if (dev && dev->multifunction) { |
1b69dfc6 TP |
1102 | for (fn = 1; fn < 8; fn++) { |
1103 | dev = pci_scan_single_device(bus, devfn + fn); | |
1104 | if (dev) { | |
1105 | if (!dev->is_added) | |
1106 | nr++; | |
1107 | dev->multifunction = 1; | |
1da177e4 | 1108 | } |
1da177e4 LT |
1109 | } |
1110 | } | |
7d715a6c | 1111 | |
149e1637 SL |
1112 | /* only one slot has pcie device */ |
1113 | if (bus->self && nr) | |
7d715a6c SL |
1114 | pcie_aspm_init_link_state(bus->self); |
1115 | ||
1da177e4 LT |
1116 | return nr; |
1117 | } | |
1118 | ||
0ab2b57f | 1119 | unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus) |
1da177e4 LT |
1120 | { |
1121 | unsigned int devfn, pass, max = bus->secondary; | |
1122 | struct pci_dev *dev; | |
1123 | ||
1124 | pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number); | |
1125 | ||
1126 | /* Go find them, Rover! */ | |
1127 | for (devfn = 0; devfn < 0x100; devfn += 8) | |
1128 | pci_scan_slot(bus, devfn); | |
1129 | ||
a28724b0 YZ |
1130 | /* Reserve buses for SR-IOV capability. */ |
1131 | max += pci_iov_bus_range(bus); | |
1132 | ||
1da177e4 LT |
1133 | /* |
1134 | * After performing arch-dependent fixup of the bus, look behind | |
1135 | * all PCI-to-PCI bridges on this bus. | |
1136 | */ | |
74710ded AC |
1137 | if (!bus->is_added) { |
1138 | pr_debug("PCI: Fixups for bus %04x:%02x\n", | |
1139 | pci_domain_nr(bus), bus->number); | |
1140 | pcibios_fixup_bus(bus); | |
1141 | if (pci_is_root_bus(bus)) | |
1142 | bus->is_added = 1; | |
1143 | } | |
1144 | ||
1da177e4 LT |
1145 | for (pass=0; pass < 2; pass++) |
1146 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1147 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || | |
1148 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) | |
1149 | max = pci_scan_bridge(bus, dev, max, pass); | |
1150 | } | |
1151 | ||
1152 | /* | |
1153 | * We've scanned the bus and so we know all about what's on | |
1154 | * the other side of any bridges that may be on this bus plus | |
1155 | * any devices. | |
1156 | * | |
1157 | * Return how far we've got finding sub-buses. | |
1158 | */ | |
1159 | pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n", | |
1160 | pci_domain_nr(bus), bus->number, max); | |
1161 | return max; | |
1162 | } | |
1163 | ||
96bde06a | 1164 | struct pci_bus * pci_create_bus(struct device *parent, |
cdb9b9f7 | 1165 | int bus, struct pci_ops *ops, void *sysdata) |
1da177e4 LT |
1166 | { |
1167 | int error; | |
1168 | struct pci_bus *b; | |
1169 | struct device *dev; | |
1170 | ||
1171 | b = pci_alloc_bus(); | |
1172 | if (!b) | |
1173 | return NULL; | |
1174 | ||
6a3b3e26 | 1175 | dev = kzalloc(sizeof(*dev), GFP_KERNEL); |
1da177e4 LT |
1176 | if (!dev){ |
1177 | kfree(b); | |
1178 | return NULL; | |
1179 | } | |
1180 | ||
1181 | b->sysdata = sysdata; | |
1182 | b->ops = ops; | |
1183 | ||
1184 | if (pci_find_bus(pci_domain_nr(b), bus)) { | |
1185 | /* If we already got to this bus through a different bridge, ignore it */ | |
1186 | pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus); | |
1187 | goto err_out; | |
1188 | } | |
d71374da ZY |
1189 | |
1190 | down_write(&pci_bus_sem); | |
1da177e4 | 1191 | list_add_tail(&b->node, &pci_root_buses); |
d71374da | 1192 | up_write(&pci_bus_sem); |
1da177e4 | 1193 | |
1da177e4 LT |
1194 | dev->parent = parent; |
1195 | dev->release = pci_release_bus_bridge_dev; | |
1a927133 | 1196 | dev_set_name(dev, "pci%04x:%02x", pci_domain_nr(b), bus); |
1da177e4 LT |
1197 | error = device_register(dev); |
1198 | if (error) | |
1199 | goto dev_reg_err; | |
1200 | b->bridge = get_device(dev); | |
1201 | ||
0d358f22 YL |
1202 | if (!parent) |
1203 | set_dev_node(b->bridge, pcibus_to_node(b)); | |
1204 | ||
fd7d1ced GKH |
1205 | b->dev.class = &pcibus_class; |
1206 | b->dev.parent = b->bridge; | |
1a927133 | 1207 | dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus); |
fd7d1ced | 1208 | error = device_register(&b->dev); |
1da177e4 LT |
1209 | if (error) |
1210 | goto class_dev_reg_err; | |
fd7d1ced | 1211 | error = device_create_file(&b->dev, &dev_attr_cpuaffinity); |
1da177e4 | 1212 | if (error) |
fd7d1ced | 1213 | goto dev_create_file_err; |
1da177e4 LT |
1214 | |
1215 | /* Create legacy_io and legacy_mem files for this bus */ | |
1216 | pci_create_legacy_files(b); | |
1217 | ||
1da177e4 LT |
1218 | b->number = b->secondary = bus; |
1219 | b->resource[0] = &ioport_resource; | |
1220 | b->resource[1] = &iomem_resource; | |
1221 | ||
1da177e4 LT |
1222 | return b; |
1223 | ||
fd7d1ced GKH |
1224 | dev_create_file_err: |
1225 | device_unregister(&b->dev); | |
1da177e4 LT |
1226 | class_dev_reg_err: |
1227 | device_unregister(dev); | |
1228 | dev_reg_err: | |
d71374da | 1229 | down_write(&pci_bus_sem); |
1da177e4 | 1230 | list_del(&b->node); |
d71374da | 1231 | up_write(&pci_bus_sem); |
1da177e4 LT |
1232 | err_out: |
1233 | kfree(dev); | |
1234 | kfree(b); | |
1235 | return NULL; | |
1236 | } | |
cdb9b9f7 | 1237 | |
0ab2b57f | 1238 | struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent, |
cdb9b9f7 PM |
1239 | int bus, struct pci_ops *ops, void *sysdata) |
1240 | { | |
1241 | struct pci_bus *b; | |
1242 | ||
1243 | b = pci_create_bus(parent, bus, ops, sysdata); | |
1244 | if (b) | |
1245 | b->subordinate = pci_scan_child_bus(b); | |
1246 | return b; | |
1247 | } | |
1da177e4 LT |
1248 | EXPORT_SYMBOL(pci_scan_bus_parented); |
1249 | ||
1250 | #ifdef CONFIG_HOTPLUG | |
3ed4fd96 AC |
1251 | /** |
1252 | * pci_rescan_bus - scan a PCI bus for devices. | |
1253 | * @bus: PCI bus to scan | |
1254 | * | |
1255 | * Scan a PCI bus and child buses for new devices, adds them, | |
1256 | * and enables them. | |
1257 | * | |
1258 | * Returns the max number of subordinate bus discovered. | |
1259 | */ | |
5446a6bd | 1260 | unsigned int __ref pci_rescan_bus(struct pci_bus *bus) |
3ed4fd96 AC |
1261 | { |
1262 | unsigned int max; | |
1263 | struct pci_dev *dev; | |
1264 | ||
1265 | max = pci_scan_child_bus(bus); | |
1266 | ||
705b1aaa | 1267 | down_read(&pci_bus_sem); |
3ed4fd96 AC |
1268 | list_for_each_entry(dev, &bus->devices, bus_list) |
1269 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || | |
1270 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) | |
1271 | if (dev->subordinate) | |
1272 | pci_bus_size_bridges(dev->subordinate); | |
705b1aaa | 1273 | up_read(&pci_bus_sem); |
3ed4fd96 AC |
1274 | |
1275 | pci_bus_assign_resources(bus); | |
1276 | pci_enable_bridges(bus); | |
1277 | pci_bus_add_devices(bus); | |
1278 | ||
1279 | return max; | |
1280 | } | |
1281 | EXPORT_SYMBOL_GPL(pci_rescan_bus); | |
1282 | ||
1da177e4 | 1283 | EXPORT_SYMBOL(pci_add_new_bus); |
1da177e4 LT |
1284 | EXPORT_SYMBOL(pci_scan_slot); |
1285 | EXPORT_SYMBOL(pci_scan_bridge); | |
1da177e4 LT |
1286 | EXPORT_SYMBOL_GPL(pci_scan_child_bus); |
1287 | #endif | |
6b4b78fe | 1288 | |
99178b03 | 1289 | static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b) |
6b4b78fe | 1290 | { |
99178b03 GKH |
1291 | const struct pci_dev *a = to_pci_dev(d_a); |
1292 | const struct pci_dev *b = to_pci_dev(d_b); | |
1293 | ||
6b4b78fe MD |
1294 | if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1; |
1295 | else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1; | |
1296 | ||
1297 | if (a->bus->number < b->bus->number) return -1; | |
1298 | else if (a->bus->number > b->bus->number) return 1; | |
1299 | ||
1300 | if (a->devfn < b->devfn) return -1; | |
1301 | else if (a->devfn > b->devfn) return 1; | |
1302 | ||
1303 | return 0; | |
1304 | } | |
1305 | ||
5ff580c1 | 1306 | void __init pci_sort_breadthfirst(void) |
6b4b78fe | 1307 | { |
99178b03 | 1308 | bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp); |
6b4b78fe | 1309 | } |