[mirror_ubuntu-zesty-kernel.git] / drivers / pci / proc.c

/*
 *	Procfs interface for the PCI bus.
 *
 *	Copyright (c) 1997--1999 Martin Mares <mj@ucw.cz>
 */

#include <linux/init.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/proc_fs.h>
#include <linux/seq_file.h>
#include <linux/capability.h>
#include <linux/uaccess.h>
#include <asm/byteorder.h>
#include "pci.h"

static int proc_initialized;	/* = 0 */

static loff_t proc_bus_pci_lseek(struct file *file, loff_t off, int whence)
{
	struct pci_dev *dev = PDE_DATA(file_inode(file));
	return fixed_size_llseek(file, off, whence, dev->cfg_size);
}

static ssize_t proc_bus_pci_read(struct file *file, char __user *buf,
				 size_t nbytes, loff_t *ppos)
{
	struct pci_dev *dev = PDE_DATA(file_inode(file));
	unsigned int pos = *ppos;
	unsigned int cnt, size;

	/*
	 * Normal users can read only the standardized portion of the
	 * configuration space as several chips lock up when trying to read
	 * undefined locations (think of Intel PIIX4 as a typical example).
	 */

	if (capable(CAP_SYS_ADMIN))
		size = dev->cfg_size;
	else if (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
		size = 128;
	else
		size = 64;

	if (pos >= size)
		return 0;
	if (nbytes >= size)
		nbytes = size;
	if (pos + nbytes > size)
		nbytes = size - pos;
	cnt = nbytes;

	if (!access_ok(VERIFY_WRITE, buf, cnt))
		return -EINVAL;

	pci_config_pm_runtime_get(dev);

	if ((pos & 1) && cnt) {
		unsigned char val;
		pci_user_read_config_byte(dev, pos, &val);
		__put_user(val, buf);
		buf++;
		pos++;
		cnt--;
	}

	if ((pos & 3) && cnt > 2) {
		unsigned short val;
		pci_user_read_config_word(dev, pos, &val);
		__put_user(cpu_to_le16(val), (__le16 __user *) buf);
		buf += 2;
		pos += 2;
		cnt -= 2;
	}

	while (cnt >= 4) {
		unsigned int val;
		pci_user_read_config_dword(dev, pos, &val);
		__put_user(cpu_to_le32(val), (__le32 __user *) buf);
		buf += 4;
		pos += 4;
		cnt -= 4;
	}

	if (cnt >= 2) {
		unsigned short val;
		pci_user_read_config_word(dev, pos, &val);
		__put_user(cpu_to_le16(val), (__le16 __user *) buf);
		buf += 2;
		pos += 2;
		cnt -= 2;
	}

	if (cnt) {
		unsigned char val;
		pci_user_read_config_byte(dev, pos, &val);
		__put_user(val, buf);
		buf++;
		pos++;
		cnt--;
	}

	pci_config_pm_runtime_put(dev);

	*ppos = pos;
	return nbytes;
}

static ssize_t proc_bus_pci_write(struct file *file, const char __user *buf,
				  size_t nbytes, loff_t *ppos)
{
	struct inode *ino = file_inode(file);
	struct pci_dev *dev = PDE_DATA(ino);
	int pos = *ppos;
	int size = dev->cfg_size;
	int cnt;

	if (secure_modules())
		return -EPERM;

	if (pos >= size)
		return 0;
	if (nbytes >= size)
		nbytes = size;
	if (pos + nbytes > size)
		nbytes = size - pos;
	cnt = nbytes;

	if (!access_ok(VERIFY_READ, buf, cnt))
		return -EINVAL;

	pci_config_pm_runtime_get(dev);

	if ((pos & 1) && cnt) {
		unsigned char val;
		__get_user(val, buf);
		pci_user_write_config_byte(dev, pos, val);
		buf++;
		pos++;
		cnt--;
	}

	if ((pos & 3) && cnt > 2) {
		__le16 val;
		__get_user(val, (__le16 __user *) buf);
		pci_user_write_config_word(dev, pos, le16_to_cpu(val));
		buf += 2;
		pos += 2;
		cnt -= 2;
	}

	while (cnt >= 4) {
		__le32 val;
		__get_user(val, (__le32 __user *) buf);
		pci_user_write_config_dword(dev, pos, le32_to_cpu(val));
		buf += 4;
		pos += 4;
		cnt -= 4;
	}

	if (cnt >= 2) {
		__le16 val;
		__get_user(val, (__le16 __user *) buf);
		pci_user_write_config_word(dev, pos, le16_to_cpu(val));
		buf += 2;
		pos += 2;
		cnt -= 2;
	}

	if (cnt) {
		unsigned char val;
		__get_user(val, buf);
		pci_user_write_config_byte(dev, pos, val);
		buf++;
		pos++;
		cnt--;
	}

	pci_config_pm_runtime_put(dev);

	*ppos = pos;
	i_size_write(ino, dev->cfg_size);
	return nbytes;
}

struct pci_filp_private {
	enum pci_mmap_state mmap_state;
	int write_combine;
};

static long proc_bus_pci_ioctl(struct file *file, unsigned int cmd,
			       unsigned long arg)
{
	struct pci_dev *dev = PDE_DATA(file_inode(file));
#ifdef HAVE_PCI_MMAP
	struct pci_filp_private *fpriv = file->private_data;
#endif /* HAVE_PCI_MMAP */
	int ret = 0;

	if (secure_modules())
		return -EPERM;

	switch (cmd) {
	case PCIIOC_CONTROLLER:
		ret = pci_domain_nr(dev->bus);
		break;

#ifdef HAVE_PCI_MMAP
	case PCIIOC_MMAP_IS_IO:
		fpriv->mmap_state = pci_mmap_io;
		break;

	case PCIIOC_MMAP_IS_MEM:
		fpriv->mmap_state = pci_mmap_mem;
		break;

	case PCIIOC_WRITE_COMBINE:
		if (arg)
			fpriv->write_combine = 1;
		else
			fpriv->write_combine = 0;
		break;

#endif /* HAVE_PCI_MMAP */

	default:
		ret = -EINVAL;
		break;
	}

	return ret;
}

#ifdef HAVE_PCI_MMAP
static int proc_bus_pci_mmap(struct file *file, struct vm_area_struct *vma)
{
	struct pci_dev *dev = PDE_DATA(file_inode(file));
	struct pci_filp_private *fpriv = file->private_data;
	int i, ret, write_combine;

	if (!capable(CAP_SYS_RAWIO) || secure_modules())
		return -EPERM;

	/* Make sure the caller is mapping a real resource for this device */
	for (i = 0; i < PCI_ROM_RESOURCE; i++) {
		if (pci_mmap_fits(dev, i, vma,  PCI_MMAP_PROCFS))
			break;
	}

	if (i >= PCI_ROM_RESOURCE)
		return -ENODEV;

	if (fpriv->mmap_state == pci_mmap_mem)
		write_combine = fpriv->write_combine;
	else
		write_combine = 0;
	ret = pci_mmap_page_range(dev, vma,
				  fpriv->mmap_state, write_combine);
	if (ret < 0)
		return ret;

	return 0;
}

static int proc_bus_pci_open(struct inode *inode, struct file *file)
{
	struct pci_filp_private *fpriv = kmalloc(sizeof(*fpriv), GFP_KERNEL);

	if (!fpriv)
		return -ENOMEM;

	fpriv->mmap_state = pci_mmap_io;
	fpriv->write_combine = 0;

	file->private_data = fpriv;

	return 0;
}

static int proc_bus_pci_release(struct inode *inode, struct file *file)
{
	kfree(file->private_data);
	file->private_data = NULL;

	return 0;
}
#endif /* HAVE_PCI_MMAP */

static const struct file_operations proc_bus_pci_operations = {
	.owner		= THIS_MODULE,
	.llseek		= proc_bus_pci_lseek,
	.read		= proc_bus_pci_read,
	.write		= proc_bus_pci_write,
	.unlocked_ioctl	= proc_bus_pci_ioctl,
	.compat_ioctl	= proc_bus_pci_ioctl,
#ifdef HAVE_PCI_MMAP
	.open		= proc_bus_pci_open,
	.release	= proc_bus_pci_release,
	.mmap		= proc_bus_pci_mmap,
#ifdef HAVE_ARCH_PCI_GET_UNMAPPED_AREA
	.get_unmapped_area = get_pci_unmapped_area,
#endif /* HAVE_ARCH_PCI_GET_UNMAPPED_AREA */
#endif /* HAVE_PCI_MMAP */
};

/* iterator */
static void *pci_seq_start(struct seq_file *m, loff_t *pos)
{
	struct pci_dev *dev = NULL;
	loff_t n = *pos;

	for_each_pci_dev(dev) {
		if (!n--)
			break;
	}
	return dev;
}

static void *pci_seq_next(struct seq_file *m, void *v, loff_t *pos)
{
	struct pci_dev *dev = v;

	(*pos)++;
	dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
	return dev;
}

static void pci_seq_stop(struct seq_file *m, void *v)
{
	if (v) {
		struct pci_dev *dev = v;
		pci_dev_put(dev);
	}
}

static int show_device(struct seq_file *m, void *v)
{
	const struct pci_dev *dev = v;
	const struct pci_driver *drv;
	int i;

	if (dev == NULL)
		return 0;

	drv = pci_dev_driver(dev);
	seq_printf(m, "%02x%02x\t%04x%04x\t%x",
			dev->bus->number,
			dev->devfn,
			dev->vendor,
			dev->device,
			dev->irq);

	/* only print standard and ROM resources to preserve compatibility */
	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
		resource_size_t start, end;
		pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
		seq_printf(m, "\t%16llx",
			(unsigned long long)(start |
			(dev->resource[i].flags & PCI_REGION_FLAG_MASK)));
	}
	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
		resource_size_t start, end;
		pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
		seq_printf(m, "\t%16llx",
			dev->resource[i].start < dev->resource[i].end ?
			(unsigned long long)(end - start) + 1 : 0);
	}
	seq_putc(m, '\t');
	if (drv)
		seq_printf(m, "%s", drv->name);
	seq_putc(m, '\n');
	return 0;
}

static const struct seq_operations proc_bus_pci_devices_op = {
	.start	= pci_seq_start,
	.next	= pci_seq_next,
	.stop	= pci_seq_stop,
	.show	= show_device
};

static struct proc_dir_entry *proc_bus_pci_dir;

int pci_proc_attach_device(struct pci_dev *dev)
{
	struct pci_bus *bus = dev->bus;
	struct proc_dir_entry *e;
	char name[16];

	if (!proc_initialized)
		return -EACCES;

	if (!bus->procdir) {
		if (pci_proc_domain(bus)) {
			sprintf(name, "%04x:%02x", pci_domain_nr(bus),
					bus->number);
		} else {
			sprintf(name, "%02x", bus->number);
		}
		bus->procdir = proc_mkdir(name, proc_bus_pci_dir);
		if (!bus->procdir)
			return -ENOMEM;
	}

	sprintf(name, "%02x.%x", PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
	e = proc_create_data(name, S_IFREG | S_IRUGO | S_IWUSR, bus->procdir,
			     &proc_bus_pci_operations, dev);
	if (!e)
		return -ENOMEM;
	proc_set_size(e, dev->cfg_size);
	dev->procent = e;

	return 0;
}

int pci_proc_detach_device(struct pci_dev *dev)
{
	proc_remove(dev->procent);
	dev->procent = NULL;
	return 0;
}

int pci_proc_detach_bus(struct pci_bus *bus)
{
	proc_remove(bus->procdir);
	return 0;
}

static int proc_bus_pci_dev_open(struct inode *inode, struct file *file)
{
	return seq_open(file, &proc_bus_pci_devices_op);
}

static const struct file_operations proc_bus_pci_dev_operations = {
	.owner		= THIS_MODULE,
	.open		= proc_bus_pci_dev_open,
	.read		= seq_read,
	.llseek		= seq_lseek,
	.release	= seq_release,
};

static int __init pci_proc_init(void)
{
	struct pci_dev *dev = NULL;
	proc_bus_pci_dir = proc_mkdir("bus/pci", NULL);
	proc_create("devices", 0, proc_bus_pci_dir,
		    &proc_bus_pci_dev_operations);
	proc_initialized = 1;
	for_each_pci_dev(dev)
		pci_proc_attach_device(dev);

	return 0;
}
device_initcall(pci_proc_init);
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Procfs interface for the PCI bus.
	3	*
	4	* Copyright (c) 1997--1999 Martin Mares <mj@ucw.cz>
	5	*/
	6
	7	#include <linux/init.h>
	8	#include <linux/pci.h>
5a0e3ad6	9	#include <linux/slab.h>
1da177e4 LT	10	#include <linux/module.h>
	11	#include <linux/proc_fs.h>
	12	#include <linux/seq_file.h>
aa0ac365	13	#include <linux/capability.h>
7c0f6ba6	14	#include <linux/uaccess.h>
1da177e4	15	#include <asm/byteorder.h>
bc56b9e0	16	#include "pci.h"
1da177e4 LT	17
	18	static int proc_initialized; /* = 0 */
	19
3c78bc61	20	static loff_t proc_bus_pci_lseek(struct file *file, loff_t off, int whence)
1da177e4	21	{
54de90d6 AV	22	struct pci_dev *dev = PDE_DATA(file_inode(file));
54de90d6 AV	23	return fixed_size_llseek(file, off, whence, dev->cfg_size);
1da177e4 LT	24	}
1da177e4 LT	25
3c78bc61 RD	26	static ssize_t proc_bus_pci_read(struct file file, char __user buf,
3c78bc61 RD	27	size_t nbytes, loff_t *ppos)
1da177e4	28	{
d9dda78b	29	struct pci_dev *dev = PDE_DATA(file_inode(file));
1da177e4 LT	30	unsigned int pos = *ppos;
	31	unsigned int cnt, size;
	32
	33	/*
	34	* Normal users can read only the standardized portion of the
	35	* configuration space as several chips lock up when trying to read
	36	* undefined locations (think of Intel PIIX4 as a typical example).
	37	*/
	38
	39	if (capable(CAP_SYS_ADMIN))
d9dda78b	40	size = dev->cfg_size;
1da177e4 LT	41	else if (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
	42	size = 128;
	43	else
	44	size = 64;
	45
	46	if (pos >= size)
	47	return 0;
	48	if (nbytes >= size)
	49	nbytes = size;
	50	if (pos + nbytes > size)
	51	nbytes = size - pos;
	52	cnt = nbytes;
	53
	54	if (!access_ok(VERIFY_WRITE, buf, cnt))
	55	return -EINVAL;
	56
b3c32c4f HY	57	pci_config_pm_runtime_get(dev);
b3c32c4f HY	58
1da177e4 LT	59	if ((pos & 1) && cnt) {
1da177e4 LT	60	unsigned char val;
e04b0ea2	61	pci_user_read_config_byte(dev, pos, &val);
1da177e4 LT	62	__put_user(val, buf);
	63	buf++;
	64	pos++;
	65	cnt--;
	66	}
	67
	68	if ((pos & 3) && cnt > 2) {
	69	unsigned short val;
e04b0ea2	70	pci_user_read_config_word(dev, pos, &val);
f17a077e	71	__put_user(cpu_to_le16(val), (__le16 __user *) buf);
1da177e4 LT	72	buf += 2;
	73	pos += 2;
	74	cnt -= 2;
	75	}
	76
	77	while (cnt >= 4) {
	78	unsigned int val;
e04b0ea2	79	pci_user_read_config_dword(dev, pos, &val);
f17a077e	80	__put_user(cpu_to_le32(val), (__le32 __user *) buf);
1da177e4 LT	81	buf += 4;
	82	pos += 4;
	83	cnt -= 4;
	84	}
	85
	86	if (cnt >= 2) {
	87	unsigned short val;
e04b0ea2	88	pci_user_read_config_word(dev, pos, &val);
f17a077e	89	__put_user(cpu_to_le16(val), (__le16 __user *) buf);
1da177e4 LT	90	buf += 2;
	91	pos += 2;
	92	cnt -= 2;
	93	}
	94
	95	if (cnt) {
	96	unsigned char val;
e04b0ea2	97	pci_user_read_config_byte(dev, pos, &val);
1da177e4 LT	98	__put_user(val, buf);
	99	buf++;
	100	pos++;
	101	cnt--;
	102	}
	103
b3c32c4f HY	104	pci_config_pm_runtime_put(dev);
b3c32c4f HY	105
1da177e4 LT	106	*ppos = pos;
	107	return nbytes;
	108	}
	109
3c78bc61 RD	110	static ssize_t proc_bus_pci_write(struct file file, const char __user buf,
3c78bc61 RD	111	size_t nbytes, loff_t *ppos)
1da177e4	112	{
496ad9aa	113	struct inode *ino = file_inode(file);
d9dda78b	114	struct pci_dev *dev = PDE_DATA(ino);
1da177e4	115	int pos = *ppos;
d9dda78b	116	int size = dev->cfg_size;
1da177e4 LT	117	int cnt;
1da177e4 LT	118
dc43f223 MG	119	if (secure_modules())
	120	return -EPERM;
	121
1da177e4 LT	122	if (pos >= size)
	123	return 0;
	124	if (nbytes >= size)
	125	nbytes = size;
	126	if (pos + nbytes > size)
	127	nbytes = size - pos;
	128	cnt = nbytes;
	129
	130	if (!access_ok(VERIFY_READ, buf, cnt))
	131	return -EINVAL;
	132
b3c32c4f HY	133	pci_config_pm_runtime_get(dev);
b3c32c4f HY	134
1da177e4 LT	135	if ((pos & 1) && cnt) {
	136	unsigned char val;
	137	__get_user(val, buf);
e04b0ea2	138	pci_user_write_config_byte(dev, pos, val);
1da177e4 LT	139	buf++;
	140	pos++;
	141	cnt--;
	142	}
	143
	144	if ((pos & 3) && cnt > 2) {
f17a077e HH	145	__le16 val;
f17a077e HH	146	__get_user(val, (__le16 __user *) buf);
e04b0ea2	147	pci_user_write_config_word(dev, pos, le16_to_cpu(val));
1da177e4 LT	148	buf += 2;
	149	pos += 2;
	150	cnt -= 2;
	151	}
	152
	153	while (cnt >= 4) {
f17a077e HH	154	__le32 val;
f17a077e HH	155	__get_user(val, (__le32 __user *) buf);
e04b0ea2	156	pci_user_write_config_dword(dev, pos, le32_to_cpu(val));
1da177e4 LT	157	buf += 4;
	158	pos += 4;
	159	cnt -= 4;
	160	}
	161
	162	if (cnt >= 2) {
f17a077e HH	163	__le16 val;
f17a077e HH	164	__get_user(val, (__le16 __user *) buf);
e04b0ea2	165	pci_user_write_config_word(dev, pos, le16_to_cpu(val));
1da177e4 LT	166	buf += 2;
	167	pos += 2;
	168	cnt -= 2;
	169	}
	170
	171	if (cnt) {
	172	unsigned char val;
	173	__get_user(val, buf);
e04b0ea2	174	pci_user_write_config_byte(dev, pos, val);
1da177e4 LT	175	buf++;
	176	pos++;
	177	cnt--;
	178	}
	179
b3c32c4f HY	180	pci_config_pm_runtime_put(dev);
b3c32c4f HY	181
1da177e4	182	*ppos = pos;
d9dda78b	183	i_size_write(ino, dev->cfg_size);
1da177e4 LT	184	return nbytes;
	185	}
	186
	187	struct pci_filp_private {
	188	enum pci_mmap_state mmap_state;
	189	int write_combine;
	190	};
	191
add77184 MS	192	static long proc_bus_pci_ioctl(struct file *file, unsigned int cmd,
add77184 MS	193	unsigned long arg)
1da177e4	194	{
d9dda78b	195	struct pci_dev *dev = PDE_DATA(file_inode(file));
1da177e4 LT	196	#ifdef HAVE_PCI_MMAP
	197	struct pci_filp_private *fpriv = file->private_data;
	198	#endif /* HAVE_PCI_MMAP */
	199	int ret = 0;
	200
dc43f223 MG	201	if (secure_modules())
	202	return -EPERM;
	203
1da177e4 LT	204	switch (cmd) {
	205	case PCIIOC_CONTROLLER:
	206	ret = pci_domain_nr(dev->bus);
	207	break;
	208
	209	#ifdef HAVE_PCI_MMAP
	210	case PCIIOC_MMAP_IS_IO:
	211	fpriv->mmap_state = pci_mmap_io;
	212	break;
	213
	214	case PCIIOC_MMAP_IS_MEM:
	215	fpriv->mmap_state = pci_mmap_mem;
	216	break;
	217
	218	case PCIIOC_WRITE_COMBINE:
	219	if (arg)
	220	fpriv->write_combine = 1;
	221	else
	222	fpriv->write_combine = 0;
	223	break;
	224
	225	#endif /* HAVE_PCI_MMAP */
	226
	227	default:
	228	ret = -EINVAL;
	229	break;
f7625980	230	}
1da177e4 LT	231
	232	return ret;
	233	}
	234
	235	#ifdef HAVE_PCI_MMAP
	236	static int proc_bus_pci_mmap(struct file file, struct vm_area_struct vma)
	237	{
d9dda78b	238	struct pci_dev *dev = PDE_DATA(file_inode(file));
1da177e4	239	struct pci_filp_private *fpriv = file->private_data;
3a92c319	240	int i, ret, write_combine;
1da177e4	241
dc43f223	242	if (!capable(CAP_SYS_RAWIO) \|\| secure_modules())
1da177e4 LT	243	return -EPERM;
1da177e4 LT	244
9eff02e2 JB	245	/* Make sure the caller is mapping a real resource for this device */
9eff02e2 JB	246	for (i = 0; i < PCI_ROM_RESOURCE; i++) {
3b519e4e	247	if (pci_mmap_fits(dev, i, vma, PCI_MMAP_PROCFS))
9eff02e2 JB	248	break;
	249	}
	250
	251	if (i >= PCI_ROM_RESOURCE)
	252	return -ENODEV;
	253
3a92c319 BH	254	if (fpriv->mmap_state == pci_mmap_mem)
	255	write_combine = fpriv->write_combine;
	256	else
	257	write_combine = 0;
1da177e4	258	ret = pci_mmap_page_range(dev, vma,
3a92c319	259	fpriv->mmap_state, write_combine);
1da177e4 LT	260	if (ret < 0)
	261	return ret;
	262
	263	return 0;
	264	}
	265
	266	static int proc_bus_pci_open(struct inode inode, struct file file)
	267	{
	268	struct pci_filp_private fpriv = kmalloc(sizeof(fpriv), GFP_KERNEL);
	269
	270	if (!fpriv)
	271	return -ENOMEM;
	272
	273	fpriv->mmap_state = pci_mmap_io;
	274	fpriv->write_combine = 0;
	275
	276	file->private_data = fpriv;
	277
	278	return 0;
	279	}
	280
	281	static int proc_bus_pci_release(struct inode inode, struct file file)
	282	{
	283	kfree(file->private_data);
	284	file->private_data = NULL;
	285
	286	return 0;
	287	}
	288	#endif /* HAVE_PCI_MMAP */
	289
d54b1fdb	290	static const struct file_operations proc_bus_pci_operations = {
c7705f34	291	.owner = THIS_MODULE,
1da177e4 LT	292	.llseek = proc_bus_pci_lseek,
	293	.read = proc_bus_pci_read,
	294	.write = proc_bus_pci_write,
add77184	295	.unlocked_ioctl = proc_bus_pci_ioctl,
991f7395	296	.compat_ioctl = proc_bus_pci_ioctl,
1da177e4 LT	297	#ifdef HAVE_PCI_MMAP
	298	.open = proc_bus_pci_open,
	299	.release = proc_bus_pci_release,
	300	.mmap = proc_bus_pci_mmap,
	301	#ifdef HAVE_ARCH_PCI_GET_UNMAPPED_AREA
	302	.get_unmapped_area = get_pci_unmapped_area,
	303	#endif /* HAVE_ARCH_PCI_GET_UNMAPPED_AREA */
	304	#endif /* HAVE_PCI_MMAP */
	305	};
	306
1da177e4 LT	307	/* iterator */
	308	static void pci_seq_start(struct seq_file m, loff_t *pos)
	309	{
	310	struct pci_dev *dev = NULL;
	311	loff_t n = *pos;
	312
	313	for_each_pci_dev(dev) {
	314	if (!n--)
	315	break;
	316	}
	317	return dev;
	318	}
	319
	320	static void pci_seq_next(struct seq_file m, void v, loff_t pos)
	321	{
	322	struct pci_dev *dev = v;
	323
	324	(*pos)++;
	325	dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
	326	return dev;
	327	}
	328
	329	static void pci_seq_stop(struct seq_file m, void v)
	330	{
	331	if (v) {
	332	struct pci_dev *dev = v;
	333	pci_dev_put(dev);
	334	}
	335	}
	336
	337	static int show_device(struct seq_file m, void v)
	338	{
	339	const struct pci_dev *dev = v;
	340	const struct pci_driver *drv;
	341	int i;
	342
	343	if (dev == NULL)
	344	return 0;
	345
	346	drv = pci_dev_driver(dev);
	347	seq_printf(m, "%02x%02x\t%04x%04x\t%x",
	348	dev->bus->number,
	349	dev->devfn,
	350	dev->vendor,
	351	dev->device,
	352	dev->irq);
fde09c6d YZ	353
	354	/* only print standard and ROM resources to preserve compatibility */
	355	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
e31dd6e4	356	resource_size_t start, end;
2311b1f2	357	pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
1396a8c3 GKH	358	seq_printf(m, "\t%16llx",
	359	(unsigned long long)(start \|
	360	(dev->resource[i].flags & PCI_REGION_FLAG_MASK)));
2311b1f2	361	}
fde09c6d	362	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
e31dd6e4	363	resource_size_t start, end;
2311b1f2	364	pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
1396a8c3	365	seq_printf(m, "\t%16llx",
1da177e4	366	dev->resource[i].start < dev->resource[i].end ?
1396a8c3	367	(unsigned long long)(end - start) + 1 : 0);
2311b1f2	368	}
1da177e4 LT	369	seq_putc(m, '\t');
	370	if (drv)
	371	seq_printf(m, "%s", drv->name);
	372	seq_putc(m, '\n');
	373	return 0;
	374	}
	375
02d90fc3	376	static const struct seq_operations proc_bus_pci_devices_op = {
1da177e4 LT	377	.start = pci_seq_start,
	378	.next = pci_seq_next,
	379	.stop = pci_seq_stop,
	380	.show = show_device
	381	};
	382
	383	static struct proc_dir_entry *proc_bus_pci_dir;
	384
	385	int pci_proc_attach_device(struct pci_dev *dev)
	386	{
	387	struct pci_bus *bus = dev->bus;
	388	struct proc_dir_entry *e;
	389	char name[16];
	390
	391	if (!proc_initialized)
	392	return -EACCES;
	393
	394	if (!bus->procdir) {
	395	if (pci_proc_domain(bus)) {
	396	sprintf(name, "%04x:%02x", pci_domain_nr(bus),
	397	bus->number);
	398	} else {
	399	sprintf(name, "%02x", bus->number);
	400	}
	401	bus->procdir = proc_mkdir(name, proc_bus_pci_dir);
	402	if (!bus->procdir)
	403	return -ENOMEM;
	404	}
	405
	406	sprintf(name, "%02x.%x", PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
c7705f34 DL	407	e = proc_create_data(name, S_IFREG \| S_IRUGO \| S_IWUSR, bus->procdir,
c7705f34 DL	408	&proc_bus_pci_operations, dev);
1da177e4 LT	409	if (!e)
1da177e4 LT	410	return -ENOMEM;
271a15ea	411	proc_set_size(e, dev->cfg_size);
1da177e4 LT	412	dev->procent = e;
	413
	414	return 0;
	415	}
	416
	417	int pci_proc_detach_device(struct pci_dev *dev)
	418	{
a8ca16ea DH	419	proc_remove(dev->procent);
a8ca16ea DH	420	dev->procent = NULL;
1da177e4 LT	421	return 0;
	422	}
	423
3c78bc61	424	int pci_proc_detach_bus(struct pci_bus *bus)
1da177e4	425	{
a8ca16ea	426	proc_remove(bus->procdir);
1da177e4 LT	427	return 0;
	428	}
	429
1da177e4 LT	430	static int proc_bus_pci_dev_open(struct inode inode, struct file file)
	431	{
	432	return seq_open(file, &proc_bus_pci_devices_op);
	433	}
3c78bc61	434
d54b1fdb	435	static const struct file_operations proc_bus_pci_dev_operations = {
c7705f34	436	.owner = THIS_MODULE,
1da177e4 LT	437	.open = proc_bus_pci_dev_open,
	438	.read = seq_read,
	439	.llseek = seq_lseek,
	440	.release = seq_release,
	441	};
	442
	443	static int __init pci_proc_init(void)
	444	{
1da177e4	445	struct pci_dev *dev = NULL;
9c37066d	446	proc_bus_pci_dir = proc_mkdir("bus/pci", NULL);
c7705f34 DL	447	proc_create("devices", 0, proc_bus_pci_dir,
c7705f34 DL	448	&proc_bus_pci_dev_operations);
1da177e4	449	proc_initialized = 1;
4e344b1c	450	for_each_pci_dev(dev)
1da177e4	451	pci_proc_attach_device(dev);
4e344b1c	452
1da177e4 LT	453	return 0;
1da177e4 LT	454	}
eaf61142	455	device_initcall(pci_proc_init);