[mirror_ubuntu-bionic-kernel.git] / drivers / pci / proc.c

// SPDX-License-Identifier: GPL-2.0
/*
 *	Procfs interface for the PCI bus.
 *
 *	Copyright (c) 1997--1999 Martin Mares <mj@ucw.cz>
 */

#include <linux/init.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/proc_fs.h>
#include <linux/seq_file.h>
#include <linux/capability.h>
#include <linux/uaccess.h>
#include <asm/byteorder.h>
#include "pci.h"

static int proc_initialized;	/* = 0 */

static loff_t proc_bus_pci_lseek(struct file *file, loff_t off, int whence)
{
	struct pci_dev *dev = PDE_DATA(file_inode(file));
	return fixed_size_llseek(file, off, whence, dev->cfg_size);
}

static ssize_t proc_bus_pci_read(struct file *file, char __user *buf,
				 size_t nbytes, loff_t *ppos)
{
	struct pci_dev *dev = PDE_DATA(file_inode(file));
	unsigned int pos = *ppos;
	unsigned int cnt, size;

	/*
	 * Normal users can read only the standardized portion of the
	 * configuration space as several chips lock up when trying to read
	 * undefined locations (think of Intel PIIX4 as a typical example).
	 */

	if (capable(CAP_SYS_ADMIN))
		size = dev->cfg_size;
	else if (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
		size = 128;
	else
		size = 64;

	if (pos >= size)
		return 0;
	if (nbytes >= size)
		nbytes = size;
	if (pos + nbytes > size)
		nbytes = size - pos;
	cnt = nbytes;

	if (!access_ok(VERIFY_WRITE, buf, cnt))
		return -EINVAL;

	pci_config_pm_runtime_get(dev);

	if ((pos & 1) && cnt) {
		unsigned char val;
		pci_user_read_config_byte(dev, pos, &val);
		__put_user(val, buf);
		buf++;
		pos++;
		cnt--;
	}

	if ((pos & 3) && cnt > 2) {
		unsigned short val;
		pci_user_read_config_word(dev, pos, &val);
		__put_user(cpu_to_le16(val), (__le16 __user *) buf);
		buf += 2;
		pos += 2;
		cnt -= 2;
	}

	while (cnt >= 4) {
		unsigned int val;
		pci_user_read_config_dword(dev, pos, &val);
		__put_user(cpu_to_le32(val), (__le32 __user *) buf);
		buf += 4;
		pos += 4;
		cnt -= 4;
	}

	if (cnt >= 2) {
		unsigned short val;
		pci_user_read_config_word(dev, pos, &val);
		__put_user(cpu_to_le16(val), (__le16 __user *) buf);
		buf += 2;
		pos += 2;
		cnt -= 2;
	}

	if (cnt) {
		unsigned char val;
		pci_user_read_config_byte(dev, pos, &val);
		__put_user(val, buf);
		buf++;
		pos++;
		cnt--;
	}

	pci_config_pm_runtime_put(dev);

	*ppos = pos;
	return nbytes;
}

static ssize_t proc_bus_pci_write(struct file *file, const char __user *buf,
				  size_t nbytes, loff_t *ppos)
{
	struct inode *ino = file_inode(file);
	struct pci_dev *dev = PDE_DATA(ino);
	int pos = *ppos;
	int size = dev->cfg_size;
	int cnt;

	if (kernel_is_locked_down("Direct PCI access"))
		return -EPERM;

	if (pos >= size)
		return 0;
	if (nbytes >= size)
		nbytes = size;
	if (pos + nbytes > size)
		nbytes = size - pos;
	cnt = nbytes;

	if (!access_ok(VERIFY_READ, buf, cnt))
		return -EINVAL;

	pci_config_pm_runtime_get(dev);

	if ((pos & 1) && cnt) {
		unsigned char val;
		__get_user(val, buf);
		pci_user_write_config_byte(dev, pos, val);
		buf++;
		pos++;
		cnt--;
	}

	if ((pos & 3) && cnt > 2) {
		__le16 val;
		__get_user(val, (__le16 __user *) buf);
		pci_user_write_config_word(dev, pos, le16_to_cpu(val));
		buf += 2;
		pos += 2;
		cnt -= 2;
	}

	while (cnt >= 4) {
		__le32 val;
		__get_user(val, (__le32 __user *) buf);
		pci_user_write_config_dword(dev, pos, le32_to_cpu(val));
		buf += 4;
		pos += 4;
		cnt -= 4;
	}

	if (cnt >= 2) {
		__le16 val;
		__get_user(val, (__le16 __user *) buf);
		pci_user_write_config_word(dev, pos, le16_to_cpu(val));
		buf += 2;
		pos += 2;
		cnt -= 2;
	}

	if (cnt) {
		unsigned char val;
		__get_user(val, buf);
		pci_user_write_config_byte(dev, pos, val);
		buf++;
		pos++;
		cnt--;
	}

	pci_config_pm_runtime_put(dev);

	*ppos = pos;
	i_size_write(ino, dev->cfg_size);
	return nbytes;
}

struct pci_filp_private {
	enum pci_mmap_state mmap_state;
	int write_combine;
};

static long proc_bus_pci_ioctl(struct file *file, unsigned int cmd,
			       unsigned long arg)
{
	struct pci_dev *dev = PDE_DATA(file_inode(file));
#ifdef HAVE_PCI_MMAP
	struct pci_filp_private *fpriv = file->private_data;
#endif /* HAVE_PCI_MMAP */
	int ret = 0;

	if (kernel_is_locked_down("Direct PCI access"))
		return -EPERM;

	switch (cmd) {
	case PCIIOC_CONTROLLER:
		ret = pci_domain_nr(dev->bus);
		break;

#ifdef HAVE_PCI_MMAP
	case PCIIOC_MMAP_IS_IO:
		if (!arch_can_pci_mmap_io())
			return -EINVAL;
		fpriv->mmap_state = pci_mmap_io;
		break;

	case PCIIOC_MMAP_IS_MEM:
		fpriv->mmap_state = pci_mmap_mem;
		break;

	case PCIIOC_WRITE_COMBINE:
		if (arch_can_pci_mmap_wc()) {
			if (arg)
				fpriv->write_combine = 1;
			else
				fpriv->write_combine = 0;
			break;
		}
		/* If arch decided it can't, fall through... */
#endif /* HAVE_PCI_MMAP */
	default:
		ret = -EINVAL;
		break;
	}

	return ret;
}

#ifdef HAVE_PCI_MMAP
static int proc_bus_pci_mmap(struct file *file, struct vm_area_struct *vma)
{
	struct pci_dev *dev = PDE_DATA(file_inode(file));
	struct pci_filp_private *fpriv = file->private_data;
	int i, ret, write_combine = 0, res_bit = IORESOURCE_MEM;

	if (!capable(CAP_SYS_RAWIO) ||
	    kernel_is_locked_down("Direct PCI access"))
		return -EPERM;

	if (fpriv->mmap_state == pci_mmap_io) {
		if (!arch_can_pci_mmap_io())
			return -EINVAL;
		res_bit = IORESOURCE_IO;
	}

	/* Make sure the caller is mapping a real resource for this device */
	for (i = 0; i < PCI_ROM_RESOURCE; i++) {
		if (dev->resource[i].flags & res_bit &&
		    pci_mmap_fits(dev, i, vma,  PCI_MMAP_PROCFS))
			break;
	}

	if (i >= PCI_ROM_RESOURCE)
		return -ENODEV;

	if (fpriv->mmap_state == pci_mmap_mem &&
	    fpriv->write_combine) {
		if (dev->resource[i].flags & IORESOURCE_PREFETCH)
			write_combine = 1;
		else
			return -EINVAL;
	}
	ret = pci_mmap_page_range(dev, i, vma,
				  fpriv->mmap_state, write_combine);
	if (ret < 0)
		return ret;

	return 0;
}

static int proc_bus_pci_open(struct inode *inode, struct file *file)
{
	struct pci_filp_private *fpriv = kmalloc(sizeof(*fpriv), GFP_KERNEL);

	if (!fpriv)
		return -ENOMEM;

	fpriv->mmap_state = pci_mmap_io;
	fpriv->write_combine = 0;

	file->private_data = fpriv;

	return 0;
}

static int proc_bus_pci_release(struct inode *inode, struct file *file)
{
	kfree(file->private_data);
	file->private_data = NULL;

	return 0;
}
#endif /* HAVE_PCI_MMAP */

static const struct file_operations proc_bus_pci_operations = {
	.owner		= THIS_MODULE,
	.llseek		= proc_bus_pci_lseek,
	.read		= proc_bus_pci_read,
	.write		= proc_bus_pci_write,
	.unlocked_ioctl	= proc_bus_pci_ioctl,
	.compat_ioctl	= proc_bus_pci_ioctl,
#ifdef HAVE_PCI_MMAP
	.open		= proc_bus_pci_open,
	.release	= proc_bus_pci_release,
	.mmap		= proc_bus_pci_mmap,
#ifdef HAVE_ARCH_PCI_GET_UNMAPPED_AREA
	.get_unmapped_area = get_pci_unmapped_area,
#endif /* HAVE_ARCH_PCI_GET_UNMAPPED_AREA */
#endif /* HAVE_PCI_MMAP */
};

/* iterator */
static void *pci_seq_start(struct seq_file *m, loff_t *pos)
{
	struct pci_dev *dev = NULL;
	loff_t n = *pos;

	for_each_pci_dev(dev) {
		if (!n--)
			break;
	}
	return dev;
}

static void *pci_seq_next(struct seq_file *m, void *v, loff_t *pos)
{
	struct pci_dev *dev = v;

	(*pos)++;
	dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
	return dev;
}

static void pci_seq_stop(struct seq_file *m, void *v)
{
	if (v) {
		struct pci_dev *dev = v;
		pci_dev_put(dev);
	}
}

static int show_device(struct seq_file *m, void *v)
{
	const struct pci_dev *dev = v;
	const struct pci_driver *drv;
	int i;

	if (dev == NULL)
		return 0;

	drv = pci_dev_driver(dev);
	seq_printf(m, "%02x%02x\t%04x%04x\t%x",
			dev->bus->number,
			dev->devfn,
			dev->vendor,
			dev->device,
			dev->irq);

	/* only print standard and ROM resources to preserve compatibility */
	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
		resource_size_t start, end;
		pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
		seq_printf(m, "\t%16llx",
			(unsigned long long)(start |
			(dev->resource[i].flags & PCI_REGION_FLAG_MASK)));
	}
	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
		resource_size_t start, end;
		pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
		seq_printf(m, "\t%16llx",
			dev->resource[i].start < dev->resource[i].end ?
			(unsigned long long)(end - start) + 1 : 0);
	}
	seq_putc(m, '\t');
	if (drv)
		seq_printf(m, "%s", drv->name);
	seq_putc(m, '\n');
	return 0;
}

static const struct seq_operations proc_bus_pci_devices_op = {
	.start	= pci_seq_start,
	.next	= pci_seq_next,
	.stop	= pci_seq_stop,
	.show	= show_device
};

static struct proc_dir_entry *proc_bus_pci_dir;

int pci_proc_attach_device(struct pci_dev *dev)
{
	struct pci_bus *bus = dev->bus;
	struct proc_dir_entry *e;
	char name[16];

	if (!proc_initialized)
		return -EACCES;

	if (!bus->procdir) {
		if (pci_proc_domain(bus)) {
			sprintf(name, "%04x:%02x", pci_domain_nr(bus),
					bus->number);
		} else {
			sprintf(name, "%02x", bus->number);
		}
		bus->procdir = proc_mkdir(name, proc_bus_pci_dir);
		if (!bus->procdir)
			return -ENOMEM;
	}

	sprintf(name, "%02x.%x", PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
	e = proc_create_data(name, S_IFREG | S_IRUGO | S_IWUSR, bus->procdir,
			     &proc_bus_pci_operations, dev);
	if (!e)
		return -ENOMEM;
	proc_set_size(e, dev->cfg_size);
	dev->procent = e;

	return 0;
}

int pci_proc_detach_device(struct pci_dev *dev)
{
	proc_remove(dev->procent);
	dev->procent = NULL;
	return 0;
}

int pci_proc_detach_bus(struct pci_bus *bus)
{
	proc_remove(bus->procdir);
	return 0;
}

static int proc_bus_pci_dev_open(struct inode *inode, struct file *file)
{
	return seq_open(file, &proc_bus_pci_devices_op);
}

static const struct file_operations proc_bus_pci_dev_operations = {
	.owner		= THIS_MODULE,
	.open		= proc_bus_pci_dev_open,
	.read		= seq_read,
	.llseek		= seq_lseek,
	.release	= seq_release,
};

static int __init pci_proc_init(void)
{
	struct pci_dev *dev = NULL;
	proc_bus_pci_dir = proc_mkdir("bus/pci", NULL);
	proc_create("devices", 0, proc_bus_pci_dir,
		    &proc_bus_pci_dev_operations);
	proc_initialized = 1;
	for_each_pci_dev(dev)
		pci_proc_attach_device(dev);

	return 0;
}
device_initcall(pci_proc_init);
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
1da177e4	2	/*
1da177e4 LT	3	* Procfs interface for the PCI bus.
	4	*
	5	* Copyright (c) 1997--1999 Martin Mares <mj@ucw.cz>
	6	*/
	7
	8	#include <linux/init.h>
	9	#include <linux/pci.h>
5a0e3ad6	10	#include <linux/slab.h>
1da177e4 LT	11	#include <linux/module.h>
	12	#include <linux/proc_fs.h>
	13	#include <linux/seq_file.h>
aa0ac365	14	#include <linux/capability.h>
7c0f6ba6	15	#include <linux/uaccess.h>
1da177e4	16	#include <asm/byteorder.h>
bc56b9e0	17	#include "pci.h"
1da177e4 LT	18
	19	static int proc_initialized; /* = 0 */
	20
3c78bc61	21	static loff_t proc_bus_pci_lseek(struct file *file, loff_t off, int whence)
1da177e4	22	{
54de90d6 AV	23	struct pci_dev *dev = PDE_DATA(file_inode(file));
54de90d6 AV	24	return fixed_size_llseek(file, off, whence, dev->cfg_size);
1da177e4 LT	25	}
1da177e4 LT	26
3c78bc61 RD	27	static ssize_t proc_bus_pci_read(struct file file, char __user buf,
3c78bc61 RD	28	size_t nbytes, loff_t *ppos)
1da177e4	29	{
d9dda78b	30	struct pci_dev *dev = PDE_DATA(file_inode(file));
1da177e4 LT	31	unsigned int pos = *ppos;
	32	unsigned int cnt, size;
	33
	34	/*
	35	* Normal users can read only the standardized portion of the
	36	* configuration space as several chips lock up when trying to read
	37	* undefined locations (think of Intel PIIX4 as a typical example).
	38	*/
	39
	40	if (capable(CAP_SYS_ADMIN))
d9dda78b	41	size = dev->cfg_size;
1da177e4 LT	42	else if (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
	43	size = 128;
	44	else
	45	size = 64;
	46
	47	if (pos >= size)
	48	return 0;
	49	if (nbytes >= size)
	50	nbytes = size;
	51	if (pos + nbytes > size)
	52	nbytes = size - pos;
	53	cnt = nbytes;
	54
	55	if (!access_ok(VERIFY_WRITE, buf, cnt))
	56	return -EINVAL;
	57
b3c32c4f HY	58	pci_config_pm_runtime_get(dev);
b3c32c4f HY	59
1da177e4 LT	60	if ((pos & 1) && cnt) {
1da177e4 LT	61	unsigned char val;
e04b0ea2	62	pci_user_read_config_byte(dev, pos, &val);
1da177e4 LT	63	__put_user(val, buf);
	64	buf++;
	65	pos++;
	66	cnt--;
	67	}
	68
	69	if ((pos & 3) && cnt > 2) {
	70	unsigned short val;
e04b0ea2	71	pci_user_read_config_word(dev, pos, &val);
f17a077e	72	__put_user(cpu_to_le16(val), (__le16 __user *) buf);
1da177e4 LT	73	buf += 2;
	74	pos += 2;
	75	cnt -= 2;
	76	}
	77
	78	while (cnt >= 4) {
	79	unsigned int val;
e04b0ea2	80	pci_user_read_config_dword(dev, pos, &val);
f17a077e	81	__put_user(cpu_to_le32(val), (__le32 __user *) buf);
1da177e4 LT	82	buf += 4;
	83	pos += 4;
	84	cnt -= 4;
	85	}
	86
	87	if (cnt >= 2) {
	88	unsigned short val;
e04b0ea2	89	pci_user_read_config_word(dev, pos, &val);
f17a077e	90	__put_user(cpu_to_le16(val), (__le16 __user *) buf);
1da177e4 LT	91	buf += 2;
	92	pos += 2;
	93	cnt -= 2;
	94	}
	95
	96	if (cnt) {
	97	unsigned char val;
e04b0ea2	98	pci_user_read_config_byte(dev, pos, &val);
1da177e4 LT	99	__put_user(val, buf);
	100	buf++;
	101	pos++;
	102	cnt--;
	103	}
	104
b3c32c4f HY	105	pci_config_pm_runtime_put(dev);
b3c32c4f HY	106
1da177e4 LT	107	*ppos = pos;
	108	return nbytes;
	109	}
	110
3c78bc61 RD	111	static ssize_t proc_bus_pci_write(struct file file, const char __user buf,
3c78bc61 RD	112	size_t nbytes, loff_t *ppos)
1da177e4	113	{
496ad9aa	114	struct inode *ino = file_inode(file);
d9dda78b	115	struct pci_dev *dev = PDE_DATA(ino);
1da177e4	116	int pos = *ppos;
d9dda78b	117	int size = dev->cfg_size;
1da177e4 LT	118	int cnt;
1da177e4 LT	119
cf53ecd8 MG	120	if (kernel_is_locked_down("Direct PCI access"))
	121	return -EPERM;
	122
1da177e4 LT	123	if (pos >= size)
	124	return 0;
	125	if (nbytes >= size)
	126	nbytes = size;
	127	if (pos + nbytes > size)
	128	nbytes = size - pos;
	129	cnt = nbytes;
	130
	131	if (!access_ok(VERIFY_READ, buf, cnt))
	132	return -EINVAL;
	133
b3c32c4f HY	134	pci_config_pm_runtime_get(dev);
b3c32c4f HY	135
1da177e4 LT	136	if ((pos & 1) && cnt) {
	137	unsigned char val;
	138	__get_user(val, buf);
e04b0ea2	139	pci_user_write_config_byte(dev, pos, val);
1da177e4 LT	140	buf++;
	141	pos++;
	142	cnt--;
	143	}
	144
	145	if ((pos & 3) && cnt > 2) {
f17a077e HH	146	__le16 val;
f17a077e HH	147	__get_user(val, (__le16 __user *) buf);
e04b0ea2	148	pci_user_write_config_word(dev, pos, le16_to_cpu(val));
1da177e4 LT	149	buf += 2;
	150	pos += 2;
	151	cnt -= 2;
	152	}
	153
	154	while (cnt >= 4) {
f17a077e HH	155	__le32 val;
f17a077e HH	156	__get_user(val, (__le32 __user *) buf);
e04b0ea2	157	pci_user_write_config_dword(dev, pos, le32_to_cpu(val));
1da177e4 LT	158	buf += 4;
	159	pos += 4;
	160	cnt -= 4;
	161	}
	162
	163	if (cnt >= 2) {
f17a077e HH	164	__le16 val;
f17a077e HH	165	__get_user(val, (__le16 __user *) buf);
e04b0ea2	166	pci_user_write_config_word(dev, pos, le16_to_cpu(val));
1da177e4 LT	167	buf += 2;
	168	pos += 2;
	169	cnt -= 2;
	170	}
	171
	172	if (cnt) {
	173	unsigned char val;
	174	__get_user(val, buf);
e04b0ea2	175	pci_user_write_config_byte(dev, pos, val);
1da177e4 LT	176	buf++;
	177	pos++;
	178	cnt--;
	179	}
	180
b3c32c4f HY	181	pci_config_pm_runtime_put(dev);
b3c32c4f HY	182
1da177e4	183	*ppos = pos;
d9dda78b	184	i_size_write(ino, dev->cfg_size);
1da177e4 LT	185	return nbytes;
	186	}
	187
	188	struct pci_filp_private {
	189	enum pci_mmap_state mmap_state;
	190	int write_combine;
	191	};
	192
add77184 MS	193	static long proc_bus_pci_ioctl(struct file *file, unsigned int cmd,
add77184 MS	194	unsigned long arg)
1da177e4	195	{
d9dda78b	196	struct pci_dev *dev = PDE_DATA(file_inode(file));
1da177e4 LT	197	#ifdef HAVE_PCI_MMAP
	198	struct pci_filp_private *fpriv = file->private_data;
	199	#endif /* HAVE_PCI_MMAP */
	200	int ret = 0;
	201
cf53ecd8 MG	202	if (kernel_is_locked_down("Direct PCI access"))
	203	return -EPERM;
	204
1da177e4 LT	205	switch (cmd) {
	206	case PCIIOC_CONTROLLER:
	207	ret = pci_domain_nr(dev->bus);
	208	break;
	209
	210	#ifdef HAVE_PCI_MMAP
	211	case PCIIOC_MMAP_IS_IO:
e854d8b2 DW	212	if (!arch_can_pci_mmap_io())
e854d8b2 DW	213	return -EINVAL;
1da177e4 LT	214	fpriv->mmap_state = pci_mmap_io;
	215	break;
	216
	217	case PCIIOC_MMAP_IS_MEM:
	218	fpriv->mmap_state = pci_mmap_mem;
	219	break;
	220
	221	case PCIIOC_WRITE_COMBINE:
ae749c7a DW	222	if (arch_can_pci_mmap_wc()) {
	223	if (arg)
	224	fpriv->write_combine = 1;
	225	else
	226	fpriv->write_combine = 0;
	227	break;
	228	}
	229	/* If arch decided it can't, fall through... */
1da177e4	230	#endif /* HAVE_PCI_MMAP */
1da177e4 LT	231	default:
	232	ret = -EINVAL;
	233	break;
f7625980	234	}
1da177e4 LT	235
	236	return ret;
	237	}
	238
	239	#ifdef HAVE_PCI_MMAP
	240	static int proc_bus_pci_mmap(struct file file, struct vm_area_struct vma)
	241	{
d9dda78b	242	struct pci_dev *dev = PDE_DATA(file_inode(file));
1da177e4	243	struct pci_filp_private *fpriv = file->private_data;
e854d8b2	244	int i, ret, write_combine = 0, res_bit = IORESOURCE_MEM;
1da177e4	245
cf53ecd8 MG	246	if (!capable(CAP_SYS_RAWIO) \|\|
cf53ecd8 MG	247	kernel_is_locked_down("Direct PCI access"))
1da177e4 LT	248	return -EPERM;
1da177e4 LT	249
e854d8b2 DW	250	if (fpriv->mmap_state == pci_mmap_io) {
	251	if (!arch_can_pci_mmap_io())
	252	return -EINVAL;
17caf567	253	res_bit = IORESOURCE_IO;
e854d8b2	254	}
17caf567	255
9eff02e2 JB	256	/* Make sure the caller is mapping a real resource for this device */
9eff02e2 JB	257	for (i = 0; i < PCI_ROM_RESOURCE; i++) {
17caf567 DW	258	if (dev->resource[i].flags & res_bit &&
17caf567 DW	259	pci_mmap_fits(dev, i, vma, PCI_MMAP_PROCFS))
9eff02e2 JB	260	break;
	261	}
	262
	263	if (i >= PCI_ROM_RESOURCE)
	264	return -ENODEV;
	265
cef4d023 DW	266	if (fpriv->mmap_state == pci_mmap_mem &&
	267	fpriv->write_combine) {
	268	if (dev->resource[i].flags & IORESOURCE_PREFETCH)
	269	write_combine = 1;
	270	else
	271	return -EINVAL;
	272	}
f66e2258	273	ret = pci_mmap_page_range(dev, i, vma,
3a92c319	274	fpriv->mmap_state, write_combine);
1da177e4 LT	275	if (ret < 0)
	276	return ret;
	277
	278	return 0;
	279	}
	280
	281	static int proc_bus_pci_open(struct inode inode, struct file file)
	282	{
	283	struct pci_filp_private fpriv = kmalloc(sizeof(fpriv), GFP_KERNEL);
	284
	285	if (!fpriv)
	286	return -ENOMEM;
	287
	288	fpriv->mmap_state = pci_mmap_io;
	289	fpriv->write_combine = 0;
	290
	291	file->private_data = fpriv;
	292
	293	return 0;
	294	}
	295
	296	static int proc_bus_pci_release(struct inode inode, struct file file)
	297	{
	298	kfree(file->private_data);
	299	file->private_data = NULL;
	300
	301	return 0;
	302	}
	303	#endif /* HAVE_PCI_MMAP */
	304
d54b1fdb	305	static const struct file_operations proc_bus_pci_operations = {
c7705f34	306	.owner = THIS_MODULE,
1da177e4 LT	307	.llseek = proc_bus_pci_lseek,
	308	.read = proc_bus_pci_read,
	309	.write = proc_bus_pci_write,
add77184	310	.unlocked_ioctl = proc_bus_pci_ioctl,
991f7395	311	.compat_ioctl = proc_bus_pci_ioctl,
1da177e4 LT	312	#ifdef HAVE_PCI_MMAP
	313	.open = proc_bus_pci_open,
	314	.release = proc_bus_pci_release,
	315	.mmap = proc_bus_pci_mmap,
	316	#ifdef HAVE_ARCH_PCI_GET_UNMAPPED_AREA
	317	.get_unmapped_area = get_pci_unmapped_area,
	318	#endif /* HAVE_ARCH_PCI_GET_UNMAPPED_AREA */
	319	#endif /* HAVE_PCI_MMAP */
	320	};
	321
1da177e4 LT	322	/* iterator */
	323	static void pci_seq_start(struct seq_file m, loff_t *pos)
	324	{
	325	struct pci_dev *dev = NULL;
	326	loff_t n = *pos;
	327
	328	for_each_pci_dev(dev) {
	329	if (!n--)
	330	break;
	331	}
	332	return dev;
	333	}
	334
	335	static void pci_seq_next(struct seq_file m, void v, loff_t pos)
	336	{
	337	struct pci_dev *dev = v;
	338
	339	(*pos)++;
	340	dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
	341	return dev;
	342	}
	343
	344	static void pci_seq_stop(struct seq_file m, void v)
	345	{
	346	if (v) {
	347	struct pci_dev *dev = v;
	348	pci_dev_put(dev);
	349	}
	350	}
	351
	352	static int show_device(struct seq_file m, void v)
	353	{
	354	const struct pci_dev *dev = v;
	355	const struct pci_driver *drv;
	356	int i;
	357
	358	if (dev == NULL)
	359	return 0;
	360
	361	drv = pci_dev_driver(dev);
	362	seq_printf(m, "%02x%02x\t%04x%04x\t%x",
	363	dev->bus->number,
	364	dev->devfn,
	365	dev->vendor,
	366	dev->device,
	367	dev->irq);
fde09c6d YZ	368
	369	/* only print standard and ROM resources to preserve compatibility */
	370	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
e31dd6e4	371	resource_size_t start, end;
2311b1f2	372	pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
1396a8c3 GKH	373	seq_printf(m, "\t%16llx",
	374	(unsigned long long)(start \|
	375	(dev->resource[i].flags & PCI_REGION_FLAG_MASK)));
2311b1f2	376	}
fde09c6d	377	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
e31dd6e4	378	resource_size_t start, end;
2311b1f2	379	pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
1396a8c3	380	seq_printf(m, "\t%16llx",
1da177e4	381	dev->resource[i].start < dev->resource[i].end ?
1396a8c3	382	(unsigned long long)(end - start) + 1 : 0);
2311b1f2	383	}
1da177e4 LT	384	seq_putc(m, '\t');
	385	if (drv)
	386	seq_printf(m, "%s", drv->name);
	387	seq_putc(m, '\n');
	388	return 0;
	389	}
	390
02d90fc3	391	static const struct seq_operations proc_bus_pci_devices_op = {
1da177e4 LT	392	.start = pci_seq_start,
	393	.next = pci_seq_next,
	394	.stop = pci_seq_stop,
	395	.show = show_device
	396	};
	397
	398	static struct proc_dir_entry *proc_bus_pci_dir;
	399
	400	int pci_proc_attach_device(struct pci_dev *dev)
	401	{
	402	struct pci_bus *bus = dev->bus;
	403	struct proc_dir_entry *e;
	404	char name[16];
	405
	406	if (!proc_initialized)
	407	return -EACCES;
	408
	409	if (!bus->procdir) {
	410	if (pci_proc_domain(bus)) {
	411	sprintf(name, "%04x:%02x", pci_domain_nr(bus),
	412	bus->number);
	413	} else {
	414	sprintf(name, "%02x", bus->number);
	415	}
	416	bus->procdir = proc_mkdir(name, proc_bus_pci_dir);
	417	if (!bus->procdir)
	418	return -ENOMEM;
	419	}
	420
	421	sprintf(name, "%02x.%x", PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
c7705f34 DL	422	e = proc_create_data(name, S_IFREG \| S_IRUGO \| S_IWUSR, bus->procdir,
c7705f34 DL	423	&proc_bus_pci_operations, dev);
1da177e4 LT	424	if (!e)
1da177e4 LT	425	return -ENOMEM;
271a15ea	426	proc_set_size(e, dev->cfg_size);
1da177e4 LT	427	dev->procent = e;
	428
	429	return 0;
	430	}
	431
	432	int pci_proc_detach_device(struct pci_dev *dev)
	433	{
a8ca16ea DH	434	proc_remove(dev->procent);
a8ca16ea DH	435	dev->procent = NULL;
1da177e4 LT	436	return 0;
	437	}
	438
3c78bc61	439	int pci_proc_detach_bus(struct pci_bus *bus)
1da177e4	440	{
a8ca16ea	441	proc_remove(bus->procdir);
1da177e4 LT	442	return 0;
	443	}
	444
1da177e4 LT	445	static int proc_bus_pci_dev_open(struct inode inode, struct file file)
	446	{
	447	return seq_open(file, &proc_bus_pci_devices_op);
	448	}
3c78bc61	449
d54b1fdb	450	static const struct file_operations proc_bus_pci_dev_operations = {
c7705f34	451	.owner = THIS_MODULE,
1da177e4 LT	452	.open = proc_bus_pci_dev_open,
	453	.read = seq_read,
	454	.llseek = seq_lseek,
	455	.release = seq_release,
	456	};
	457
	458	static int __init pci_proc_init(void)
	459	{
1da177e4	460	struct pci_dev *dev = NULL;
9c37066d	461	proc_bus_pci_dir = proc_mkdir("bus/pci", NULL);
c7705f34 DL	462	proc_create("devices", 0, proc_bus_pci_dir,
c7705f34 DL	463	&proc_bus_pci_dev_operations);
1da177e4	464	proc_initialized = 1;
4e344b1c	465	for_each_pci_dev(dev)
1da177e4	466	pci_proc_attach_device(dev);
4e344b1c	467
1da177e4 LT	468	return 0;
1da177e4 LT	469	}
eaf61142	470	device_initcall(pci_proc_init);