[mirror_ubuntu-bionic-kernel.git] / drivers / pci / proc.c

/*
 *	Procfs interface for the PCI bus.
 *
 *	Copyright (c) 1997--1999 Martin Mares <mj@ucw.cz>
 */

#include <linux/init.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/proc_fs.h>
#include <linux/seq_file.h>
#include <linux/capability.h>
#include <asm/uaccess.h>
#include <asm/byteorder.h>
#include "pci.h"

static int proc_initialized;	/* = 0 */

static loff_t
proc_bus_pci_lseek(struct file *file, loff_t off, int whence)
{
	loff_t new = -1;
	struct inode *inode = file_inode(file);

	mutex_lock(&inode->i_mutex);
	switch (whence) {
	case 0:
		new = off;
		break;
	case 1:
		new = file->f_pos + off;
		break;
	case 2:
		new = inode->i_size + off;
		break;
	}
	if (new < 0 || new > inode->i_size)
		new = -EINVAL;
	else
		file->f_pos = new;
	mutex_unlock(&inode->i_mutex);
	return new;
}

static ssize_t
proc_bus_pci_read(struct file *file, char __user *buf, size_t nbytes, loff_t *ppos)
{
	struct pci_dev *dev = PDE_DATA(file_inode(file));
	unsigned int pos = *ppos;
	unsigned int cnt, size;

	/*
	 * Normal users can read only the standardized portion of the
	 * configuration space as several chips lock up when trying to read
	 * undefined locations (think of Intel PIIX4 as a typical example).
	 */

	if (capable(CAP_SYS_ADMIN))
		size = dev->cfg_size;
	else if (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
		size = 128;
	else
		size = 64;

	if (pos >= size)
		return 0;
	if (nbytes >= size)
		nbytes = size;
	if (pos + nbytes > size)
		nbytes = size - pos;
	cnt = nbytes;

	if (!access_ok(VERIFY_WRITE, buf, cnt))
		return -EINVAL;

	pci_config_pm_runtime_get(dev);

	if ((pos & 1) && cnt) {
		unsigned char val;
		pci_user_read_config_byte(dev, pos, &val);
		__put_user(val, buf);
		buf++;
		pos++;
		cnt--;
	}

	if ((pos & 3) && cnt > 2) {
		unsigned short val;
		pci_user_read_config_word(dev, pos, &val);
		__put_user(cpu_to_le16(val), (__le16 __user *) buf);
		buf += 2;
		pos += 2;
		cnt -= 2;
	}

	while (cnt >= 4) {
		unsigned int val;
		pci_user_read_config_dword(dev, pos, &val);
		__put_user(cpu_to_le32(val), (__le32 __user *) buf);
		buf += 4;
		pos += 4;
		cnt -= 4;
	}

	if (cnt >= 2) {
		unsigned short val;
		pci_user_read_config_word(dev, pos, &val);
		__put_user(cpu_to_le16(val), (__le16 __user *) buf);
		buf += 2;
		pos += 2;
		cnt -= 2;
	}

	if (cnt) {
		unsigned char val;
		pci_user_read_config_byte(dev, pos, &val);
		__put_user(val, buf);
		buf++;
		pos++;
		cnt--;
	}

	pci_config_pm_runtime_put(dev);

	*ppos = pos;
	return nbytes;
}

static ssize_t
proc_bus_pci_write(struct file *file, const char __user *buf, size_t nbytes, loff_t *ppos)
{
	struct inode *ino = file_inode(file);
	struct pci_dev *dev = PDE_DATA(ino);
	int pos = *ppos;
	int size = dev->cfg_size;
	int cnt;

	if (pos >= size)
		return 0;
	if (nbytes >= size)
		nbytes = size;
	if (pos + nbytes > size)
		nbytes = size - pos;
	cnt = nbytes;

	if (!access_ok(VERIFY_READ, buf, cnt))
		return -EINVAL;

	pci_config_pm_runtime_get(dev);

	if ((pos & 1) && cnt) {
		unsigned char val;
		__get_user(val, buf);
		pci_user_write_config_byte(dev, pos, val);
		buf++;
		pos++;
		cnt--;
	}

	if ((pos & 3) && cnt > 2) {
		__le16 val;
		__get_user(val, (__le16 __user *) buf);
		pci_user_write_config_word(dev, pos, le16_to_cpu(val));
		buf += 2;
		pos += 2;
		cnt -= 2;
	}

	while (cnt >= 4) {
		__le32 val;
		__get_user(val, (__le32 __user *) buf);
		pci_user_write_config_dword(dev, pos, le32_to_cpu(val));
		buf += 4;
		pos += 4;
		cnt -= 4;
	}

	if (cnt >= 2) {
		__le16 val;
		__get_user(val, (__le16 __user *) buf);
		pci_user_write_config_word(dev, pos, le16_to_cpu(val));
		buf += 2;
		pos += 2;
		cnt -= 2;
	}

	if (cnt) {
		unsigned char val;
		__get_user(val, buf);
		pci_user_write_config_byte(dev, pos, val);
		buf++;
		pos++;
		cnt--;
	}

	pci_config_pm_runtime_put(dev);

	*ppos = pos;
	i_size_write(ino, dev->cfg_size);
	return nbytes;
}

struct pci_filp_private {
	enum pci_mmap_state mmap_state;
	int write_combine;
};

static long proc_bus_pci_ioctl(struct file *file, unsigned int cmd,
			       unsigned long arg)
{
	struct pci_dev *dev = PDE_DATA(file_inode(file));
#ifdef HAVE_PCI_MMAP
	struct pci_filp_private *fpriv = file->private_data;
#endif /* HAVE_PCI_MMAP */
	int ret = 0;

	switch (cmd) {
	case PCIIOC_CONTROLLER:
		ret = pci_domain_nr(dev->bus);
		break;

#ifdef HAVE_PCI_MMAP
	case PCIIOC_MMAP_IS_IO:
		fpriv->mmap_state = pci_mmap_io;
		break;

	case PCIIOC_MMAP_IS_MEM:
		fpriv->mmap_state = pci_mmap_mem;
		break;

	case PCIIOC_WRITE_COMBINE:
		if (arg)
			fpriv->write_combine = 1;
		else
			fpriv->write_combine = 0;
		break;

#endif /* HAVE_PCI_MMAP */

	default:
		ret = -EINVAL;
		break;
	};

	return ret;
}

#ifdef HAVE_PCI_MMAP
static int proc_bus_pci_mmap(struct file *file, struct vm_area_struct *vma)
{
	struct pci_dev *dev = PDE_DATA(file_inode(file));
	struct pci_filp_private *fpriv = file->private_data;
	int i, ret;

	if (!capable(CAP_SYS_RAWIO))
		return -EPERM;

	/* Make sure the caller is mapping a real resource for this device */
	for (i = 0; i < PCI_ROM_RESOURCE; i++) {
		if (pci_mmap_fits(dev, i, vma,  PCI_MMAP_PROCFS))
			break;
	}

	if (i >= PCI_ROM_RESOURCE)
		return -ENODEV;

	ret = pci_mmap_page_range(dev, vma,
				  fpriv->mmap_state,
				  fpriv->write_combine);
	if (ret < 0)
		return ret;

	return 0;
}

static int proc_bus_pci_open(struct inode *inode, struct file *file)
{
	struct pci_filp_private *fpriv = kmalloc(sizeof(*fpriv), GFP_KERNEL);

	if (!fpriv)
		return -ENOMEM;

	fpriv->mmap_state = pci_mmap_io;
	fpriv->write_combine = 0;

	file->private_data = fpriv;

	return 0;
}

static int proc_bus_pci_release(struct inode *inode, struct file *file)
{
	kfree(file->private_data);
	file->private_data = NULL;

	return 0;
}
#endif /* HAVE_PCI_MMAP */

static const struct file_operations proc_bus_pci_operations = {
	.owner		= THIS_MODULE,
	.llseek		= proc_bus_pci_lseek,
	.read		= proc_bus_pci_read,
	.write		= proc_bus_pci_write,
	.unlocked_ioctl	= proc_bus_pci_ioctl,
	.compat_ioctl	= proc_bus_pci_ioctl,
#ifdef HAVE_PCI_MMAP
	.open		= proc_bus_pci_open,
	.release	= proc_bus_pci_release,
	.mmap		= proc_bus_pci_mmap,
#ifdef HAVE_ARCH_PCI_GET_UNMAPPED_AREA
	.get_unmapped_area = get_pci_unmapped_area,
#endif /* HAVE_ARCH_PCI_GET_UNMAPPED_AREA */
#endif /* HAVE_PCI_MMAP */
};

/* iterator */
static void *pci_seq_start(struct seq_file *m, loff_t *pos)
{
	struct pci_dev *dev = NULL;
	loff_t n = *pos;

	for_each_pci_dev(dev) {
		if (!n--)
			break;
	}
	return dev;
}

static void *pci_seq_next(struct seq_file *m, void *v, loff_t *pos)
{
	struct pci_dev *dev = v;

	(*pos)++;
	dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
	return dev;
}

static void pci_seq_stop(struct seq_file *m, void *v)
{
	if (v) {
		struct pci_dev *dev = v;
		pci_dev_put(dev);
	}
}

static int show_device(struct seq_file *m, void *v)
{
	const struct pci_dev *dev = v;
	const struct pci_driver *drv;
	int i;

	if (dev == NULL)
		return 0;

	drv = pci_dev_driver(dev);
	seq_printf(m, "%02x%02x\t%04x%04x\t%x",
			dev->bus->number,
			dev->devfn,
			dev->vendor,
			dev->device,
			dev->irq);

	/* only print standard and ROM resources to preserve compatibility */
	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
		resource_size_t start, end;
		pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
		seq_printf(m, "\t%16llx",
			(unsigned long long)(start |
			(dev->resource[i].flags & PCI_REGION_FLAG_MASK)));
	}
	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
		resource_size_t start, end;
		pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
		seq_printf(m, "\t%16llx",
			dev->resource[i].start < dev->resource[i].end ?
			(unsigned long long)(end - start) + 1 : 0);
	}
	seq_putc(m, '\t');
	if (drv)
		seq_printf(m, "%s", drv->name);
	seq_putc(m, '\n');
	return 0;
}

static const struct seq_operations proc_bus_pci_devices_op = {
	.start	= pci_seq_start,
	.next	= pci_seq_next,
	.stop	= pci_seq_stop,
	.show	= show_device
};

static struct proc_dir_entry *proc_bus_pci_dir;

int pci_proc_attach_device(struct pci_dev *dev)
{
	struct pci_bus *bus = dev->bus;
	struct proc_dir_entry *e;
	char name[16];

	if (!proc_initialized)
		return -EACCES;

	if (!bus->procdir) {
		if (pci_proc_domain(bus)) {
			sprintf(name, "%04x:%02x", pci_domain_nr(bus),
					bus->number);
		} else {
			sprintf(name, "%02x", bus->number);
		}
		bus->procdir = proc_mkdir(name, proc_bus_pci_dir);
		if (!bus->procdir)
			return -ENOMEM;
	}

	sprintf(name, "%02x.%x", PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
	e = proc_create_data(name, S_IFREG | S_IRUGO | S_IWUSR, bus->procdir,
			     &proc_bus_pci_operations, dev);
	if (!e)
		return -ENOMEM;
	e->size = dev->cfg_size;
	dev->procent = e;

	return 0;
}

int pci_proc_detach_device(struct pci_dev *dev)
{
	struct proc_dir_entry *e;

	if ((e = dev->procent)) {
		remove_proc_entry(e->name, dev->bus->procdir);
		dev->procent = NULL;
	}
	return 0;
}

int pci_proc_detach_bus(struct pci_bus* bus)
{
	struct proc_dir_entry *de = bus->procdir;
	if (de)
		remove_proc_entry(de->name, proc_bus_pci_dir);
	return 0;
}

static int proc_bus_pci_dev_open(struct inode *inode, struct file *file)
{
	return seq_open(file, &proc_bus_pci_devices_op);
}
static const struct file_operations proc_bus_pci_dev_operations = {
	.owner		= THIS_MODULE,
	.open		= proc_bus_pci_dev_open,
	.read		= seq_read,
	.llseek		= seq_lseek,
	.release	= seq_release,
};

static int __init pci_proc_init(void)
{
	struct pci_dev *dev = NULL;
	proc_bus_pci_dir = proc_mkdir("bus/pci", NULL);
	proc_create("devices", 0, proc_bus_pci_dir,
		    &proc_bus_pci_dev_operations);
	proc_initialized = 1;
	for_each_pci_dev(dev)
		pci_proc_attach_device(dev);

	return 0;
}

device_initcall(pci_proc_init);
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Procfs interface for the PCI bus.
	3	*
	4	* Copyright (c) 1997--1999 Martin Mares <mj@ucw.cz>
	5	*/
	6
	7	#include <linux/init.h>
	8	#include <linux/pci.h>
5a0e3ad6	9	#include <linux/slab.h>
1da177e4 LT	10	#include <linux/module.h>
	11	#include <linux/proc_fs.h>
	12	#include <linux/seq_file.h>
aa0ac365	13	#include <linux/capability.h>
1da177e4 LT	14	#include <asm/uaccess.h>
1da177e4 LT	15	#include <asm/byteorder.h>
bc56b9e0	16	#include "pci.h"
1da177e4 LT	17
	18	static int proc_initialized; /* = 0 */
	19
	20	static loff_t
	21	proc_bus_pci_lseek(struct file *file, loff_t off, int whence)
	22	{
	23	loff_t new = -1;
496ad9aa	24	struct inode *inode = file_inode(file);
1da177e4	25
1b1dcc1b	26	mutex_lock(&inode->i_mutex);
1da177e4 LT	27	switch (whence) {
	28	case 0:
	29	new = off;
	30	break;
	31	case 1:
	32	new = file->f_pos + off;
	33	break;
	34	case 2:
	35	new = inode->i_size + off;
	36	break;
	37	}
	38	if (new < 0 \|\| new > inode->i_size)
	39	new = -EINVAL;
	40	else
	41	file->f_pos = new;
1b1dcc1b	42	mutex_unlock(&inode->i_mutex);
1da177e4 LT	43	return new;
	44	}
	45
	46	static ssize_t
	47	proc_bus_pci_read(struct file file, char __user buf, size_t nbytes, loff_t *ppos)
	48	{
d9dda78b	49	struct pci_dev *dev = PDE_DATA(file_inode(file));
1da177e4 LT	50	unsigned int pos = *ppos;
	51	unsigned int cnt, size;
	52
	53	/*
	54	* Normal users can read only the standardized portion of the
	55	* configuration space as several chips lock up when trying to read
	56	* undefined locations (think of Intel PIIX4 as a typical example).
	57	*/
	58
	59	if (capable(CAP_SYS_ADMIN))
d9dda78b	60	size = dev->cfg_size;
1da177e4 LT	61	else if (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
	62	size = 128;
	63	else
	64	size = 64;
	65
	66	if (pos >= size)
	67	return 0;
	68	if (nbytes >= size)
	69	nbytes = size;
	70	if (pos + nbytes > size)
	71	nbytes = size - pos;
	72	cnt = nbytes;
	73
	74	if (!access_ok(VERIFY_WRITE, buf, cnt))
	75	return -EINVAL;
	76
b3c32c4f HY	77	pci_config_pm_runtime_get(dev);
b3c32c4f HY	78
1da177e4 LT	79	if ((pos & 1) && cnt) {
1da177e4 LT	80	unsigned char val;
e04b0ea2	81	pci_user_read_config_byte(dev, pos, &val);
1da177e4 LT	82	__put_user(val, buf);
	83	buf++;
	84	pos++;
	85	cnt--;
	86	}
	87
	88	if ((pos & 3) && cnt > 2) {
	89	unsigned short val;
e04b0ea2	90	pci_user_read_config_word(dev, pos, &val);
f17a077e	91	__put_user(cpu_to_le16(val), (__le16 __user *) buf);
1da177e4 LT	92	buf += 2;
	93	pos += 2;
	94	cnt -= 2;
	95	}
	96
	97	while (cnt >= 4) {
	98	unsigned int val;
e04b0ea2	99	pci_user_read_config_dword(dev, pos, &val);
f17a077e	100	__put_user(cpu_to_le32(val), (__le32 __user *) buf);
1da177e4 LT	101	buf += 4;
	102	pos += 4;
	103	cnt -= 4;
	104	}
	105
	106	if (cnt >= 2) {
	107	unsigned short val;
e04b0ea2	108	pci_user_read_config_word(dev, pos, &val);
f17a077e	109	__put_user(cpu_to_le16(val), (__le16 __user *) buf);
1da177e4 LT	110	buf += 2;
	111	pos += 2;
	112	cnt -= 2;
	113	}
	114
	115	if (cnt) {
	116	unsigned char val;
e04b0ea2	117	pci_user_read_config_byte(dev, pos, &val);
1da177e4 LT	118	__put_user(val, buf);
	119	buf++;
	120	pos++;
	121	cnt--;
	122	}
	123
b3c32c4f HY	124	pci_config_pm_runtime_put(dev);
b3c32c4f HY	125
1da177e4 LT	126	*ppos = pos;
	127	return nbytes;
	128	}
	129
	130	static ssize_t
	131	proc_bus_pci_write(struct file file, const char __user buf, size_t nbytes, loff_t *ppos)
	132	{
496ad9aa	133	struct inode *ino = file_inode(file);
d9dda78b	134	struct pci_dev *dev = PDE_DATA(ino);
1da177e4	135	int pos = *ppos;
d9dda78b	136	int size = dev->cfg_size;
1da177e4 LT	137	int cnt;
	138
	139	if (pos >= size)
	140	return 0;
	141	if (nbytes >= size)
	142	nbytes = size;
	143	if (pos + nbytes > size)
	144	nbytes = size - pos;
	145	cnt = nbytes;
	146
	147	if (!access_ok(VERIFY_READ, buf, cnt))
	148	return -EINVAL;
	149
b3c32c4f HY	150	pci_config_pm_runtime_get(dev);
b3c32c4f HY	151
1da177e4 LT	152	if ((pos & 1) && cnt) {
	153	unsigned char val;
	154	__get_user(val, buf);
e04b0ea2	155	pci_user_write_config_byte(dev, pos, val);
1da177e4 LT	156	buf++;
	157	pos++;
	158	cnt--;
	159	}
	160
	161	if ((pos & 3) && cnt > 2) {
f17a077e HH	162	__le16 val;
f17a077e HH	163	__get_user(val, (__le16 __user *) buf);
e04b0ea2	164	pci_user_write_config_word(dev, pos, le16_to_cpu(val));
1da177e4 LT	165	buf += 2;
	166	pos += 2;
	167	cnt -= 2;
	168	}
	169
	170	while (cnt >= 4) {
f17a077e HH	171	__le32 val;
f17a077e HH	172	__get_user(val, (__le32 __user *) buf);
e04b0ea2	173	pci_user_write_config_dword(dev, pos, le32_to_cpu(val));
1da177e4 LT	174	buf += 4;
	175	pos += 4;
	176	cnt -= 4;
	177	}
	178
	179	if (cnt >= 2) {
f17a077e HH	180	__le16 val;
f17a077e HH	181	__get_user(val, (__le16 __user *) buf);
e04b0ea2	182	pci_user_write_config_word(dev, pos, le16_to_cpu(val));
1da177e4 LT	183	buf += 2;
	184	pos += 2;
	185	cnt -= 2;
	186	}
	187
	188	if (cnt) {
	189	unsigned char val;
	190	__get_user(val, buf);
e04b0ea2	191	pci_user_write_config_byte(dev, pos, val);
1da177e4 LT	192	buf++;
	193	pos++;
	194	cnt--;
	195	}
	196
b3c32c4f HY	197	pci_config_pm_runtime_put(dev);
b3c32c4f HY	198
1da177e4	199	*ppos = pos;
d9dda78b	200	i_size_write(ino, dev->cfg_size);
1da177e4 LT	201	return nbytes;
	202	}
	203
	204	struct pci_filp_private {
	205	enum pci_mmap_state mmap_state;
	206	int write_combine;
	207	};
	208
add77184 MS	209	static long proc_bus_pci_ioctl(struct file *file, unsigned int cmd,
add77184 MS	210	unsigned long arg)
1da177e4	211	{
d9dda78b	212	struct pci_dev *dev = PDE_DATA(file_inode(file));
1da177e4 LT	213	#ifdef HAVE_PCI_MMAP
	214	struct pci_filp_private *fpriv = file->private_data;
	215	#endif /* HAVE_PCI_MMAP */
	216	int ret = 0;
	217
	218	switch (cmd) {
	219	case PCIIOC_CONTROLLER:
	220	ret = pci_domain_nr(dev->bus);
	221	break;
	222
	223	#ifdef HAVE_PCI_MMAP
	224	case PCIIOC_MMAP_IS_IO:
	225	fpriv->mmap_state = pci_mmap_io;
	226	break;
	227
	228	case PCIIOC_MMAP_IS_MEM:
	229	fpriv->mmap_state = pci_mmap_mem;
	230	break;
	231
	232	case PCIIOC_WRITE_COMBINE:
	233	if (arg)
	234	fpriv->write_combine = 1;
	235	else
	236	fpriv->write_combine = 0;
	237	break;
	238
	239	#endif /* HAVE_PCI_MMAP */
	240
	241	default:
	242	ret = -EINVAL;
	243	break;
	244	};
	245
	246	return ret;
	247	}
	248
	249	#ifdef HAVE_PCI_MMAP
	250	static int proc_bus_pci_mmap(struct file file, struct vm_area_struct vma)
	251	{
d9dda78b	252	struct pci_dev *dev = PDE_DATA(file_inode(file));
1da177e4	253	struct pci_filp_private *fpriv = file->private_data;
9eff02e2	254	int i, ret;
1da177e4 LT	255
	256	if (!capable(CAP_SYS_RAWIO))
	257	return -EPERM;
	258
9eff02e2 JB	259	/* Make sure the caller is mapping a real resource for this device */
9eff02e2 JB	260	for (i = 0; i < PCI_ROM_RESOURCE; i++) {
3b519e4e	261	if (pci_mmap_fits(dev, i, vma, PCI_MMAP_PROCFS))
9eff02e2 JB	262	break;
	263	}
	264
	265	if (i >= PCI_ROM_RESOURCE)
	266	return -ENODEV;
	267
1da177e4 LT	268	ret = pci_mmap_page_range(dev, vma,
	269	fpriv->mmap_state,
	270	fpriv->write_combine);
	271	if (ret < 0)
	272	return ret;
	273
	274	return 0;
	275	}
	276
	277	static int proc_bus_pci_open(struct inode inode, struct file file)
	278	{
	279	struct pci_filp_private fpriv = kmalloc(sizeof(fpriv), GFP_KERNEL);
	280
	281	if (!fpriv)
	282	return -ENOMEM;
	283
	284	fpriv->mmap_state = pci_mmap_io;
	285	fpriv->write_combine = 0;
	286
	287	file->private_data = fpriv;
	288
	289	return 0;
	290	}
	291
	292	static int proc_bus_pci_release(struct inode inode, struct file file)
	293	{
	294	kfree(file->private_data);
	295	file->private_data = NULL;
	296
	297	return 0;
	298	}
	299	#endif /* HAVE_PCI_MMAP */
	300
d54b1fdb	301	static const struct file_operations proc_bus_pci_operations = {
c7705f34	302	.owner = THIS_MODULE,
1da177e4 LT	303	.llseek = proc_bus_pci_lseek,
	304	.read = proc_bus_pci_read,
	305	.write = proc_bus_pci_write,
add77184	306	.unlocked_ioctl = proc_bus_pci_ioctl,
991f7395	307	.compat_ioctl = proc_bus_pci_ioctl,
1da177e4 LT	308	#ifdef HAVE_PCI_MMAP
	309	.open = proc_bus_pci_open,
	310	.release = proc_bus_pci_release,
	311	.mmap = proc_bus_pci_mmap,
	312	#ifdef HAVE_ARCH_PCI_GET_UNMAPPED_AREA
	313	.get_unmapped_area = get_pci_unmapped_area,
	314	#endif /* HAVE_ARCH_PCI_GET_UNMAPPED_AREA */
	315	#endif /* HAVE_PCI_MMAP */
	316	};
	317
1da177e4 LT	318	/* iterator */
	319	static void pci_seq_start(struct seq_file m, loff_t *pos)
	320	{
	321	struct pci_dev *dev = NULL;
	322	loff_t n = *pos;
	323
	324	for_each_pci_dev(dev) {
	325	if (!n--)
	326	break;
	327	}
	328	return dev;
	329	}
	330
	331	static void pci_seq_next(struct seq_file m, void v, loff_t pos)
	332	{
	333	struct pci_dev *dev = v;
	334
	335	(*pos)++;
	336	dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
	337	return dev;
	338	}
	339
	340	static void pci_seq_stop(struct seq_file m, void v)
	341	{
	342	if (v) {
	343	struct pci_dev *dev = v;
	344	pci_dev_put(dev);
	345	}
	346	}
	347
	348	static int show_device(struct seq_file m, void v)
	349	{
	350	const struct pci_dev *dev = v;
	351	const struct pci_driver *drv;
	352	int i;
	353
	354	if (dev == NULL)
	355	return 0;
	356
	357	drv = pci_dev_driver(dev);
	358	seq_printf(m, "%02x%02x\t%04x%04x\t%x",
	359	dev->bus->number,
	360	dev->devfn,
	361	dev->vendor,
	362	dev->device,
	363	dev->irq);
fde09c6d YZ	364
	365	/* only print standard and ROM resources to preserve compatibility */
	366	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
e31dd6e4	367	resource_size_t start, end;
2311b1f2	368	pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
1396a8c3 GKH	369	seq_printf(m, "\t%16llx",
	370	(unsigned long long)(start \|
	371	(dev->resource[i].flags & PCI_REGION_FLAG_MASK)));
2311b1f2	372	}
fde09c6d	373	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
e31dd6e4	374	resource_size_t start, end;
2311b1f2	375	pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
1396a8c3	376	seq_printf(m, "\t%16llx",
1da177e4	377	dev->resource[i].start < dev->resource[i].end ?
1396a8c3	378	(unsigned long long)(end - start) + 1 : 0);
2311b1f2	379	}
1da177e4 LT	380	seq_putc(m, '\t');
	381	if (drv)
	382	seq_printf(m, "%s", drv->name);
	383	seq_putc(m, '\n');
	384	return 0;
	385	}
	386
02d90fc3	387	static const struct seq_operations proc_bus_pci_devices_op = {
1da177e4 LT	388	.start = pci_seq_start,
	389	.next = pci_seq_next,
	390	.stop = pci_seq_stop,
	391	.show = show_device
	392	};
	393
	394	static struct proc_dir_entry *proc_bus_pci_dir;
	395
	396	int pci_proc_attach_device(struct pci_dev *dev)
	397	{
	398	struct pci_bus *bus = dev->bus;
	399	struct proc_dir_entry *e;
	400	char name[16];
	401
	402	if (!proc_initialized)
	403	return -EACCES;
	404
	405	if (!bus->procdir) {
	406	if (pci_proc_domain(bus)) {
	407	sprintf(name, "%04x:%02x", pci_domain_nr(bus),
	408	bus->number);
	409	} else {
	410	sprintf(name, "%02x", bus->number);
	411	}
	412	bus->procdir = proc_mkdir(name, proc_bus_pci_dir);
	413	if (!bus->procdir)
	414	return -ENOMEM;
	415	}
	416
	417	sprintf(name, "%02x.%x", PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
c7705f34 DL	418	e = proc_create_data(name, S_IFREG \| S_IRUGO \| S_IWUSR, bus->procdir,
c7705f34 DL	419	&proc_bus_pci_operations, dev);
1da177e4 LT	420	if (!e)
1da177e4 LT	421	return -ENOMEM;
1da177e4 LT	422	e->size = dev->cfg_size;
	423	dev->procent = e;
	424
	425	return 0;
	426	}
	427
	428	int pci_proc_detach_device(struct pci_dev *dev)
	429	{
	430	struct proc_dir_entry *e;
	431
	432	if ((e = dev->procent)) {
1da177e4 LT	433	remove_proc_entry(e->name, dev->bus->procdir);
	434	dev->procent = NULL;
	435	}
	436	return 0;
	437	}
	438
1da177e4 LT	439	int pci_proc_detach_bus(struct pci_bus* bus)
	440	{
	441	struct proc_dir_entry *de = bus->procdir;
	442	if (de)
	443	remove_proc_entry(de->name, proc_bus_pci_dir);
	444	return 0;
	445	}
	446
1da177e4 LT	447	static int proc_bus_pci_dev_open(struct inode inode, struct file file)
	448	{
	449	return seq_open(file, &proc_bus_pci_devices_op);
	450	}
d54b1fdb	451	static const struct file_operations proc_bus_pci_dev_operations = {
c7705f34	452	.owner = THIS_MODULE,
1da177e4 LT	453	.open = proc_bus_pci_dev_open,
	454	.read = seq_read,
	455	.llseek = seq_lseek,
	456	.release = seq_release,
	457	};
	458
	459	static int __init pci_proc_init(void)
	460	{
1da177e4	461	struct pci_dev *dev = NULL;
9c37066d	462	proc_bus_pci_dir = proc_mkdir("bus/pci", NULL);
c7705f34 DL	463	proc_create("devices", 0, proc_bus_pci_dir,
c7705f34 DL	464	&proc_bus_pci_dev_operations);
1da177e4	465	proc_initialized = 1;
4e344b1c	466	for_each_pci_dev(dev)
1da177e4	467	pci_proc_attach_device(dev);
4e344b1c	468
1da177e4 LT	469	return 0;
	470	}
	471
eaf61142	472	device_initcall(pci_proc_init);
1da177e4	473