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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1da177e4 LT |
2 | /* |
3 | * This file contains work-arounds for many known PCI hardware | |
4 | * bugs. Devices present only on certain architectures (host | |
5 | * bridges et cetera) should be handled in arch-specific code. | |
6 | * | |
7 | * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. | |
8 | * | |
9 | * Copyright (c) 1999 Martin Mares <mj@ucw.cz> | |
10 | * | |
7586269c DB |
11 | * Init/reset quirks for USB host controllers should be in the |
12 | * USB quirks file, where their drivers can access reuse it. | |
1da177e4 LT |
13 | */ |
14 | ||
1da177e4 LT |
15 | #include <linux/types.h> |
16 | #include <linux/kernel.h> | |
363c75db | 17 | #include <linux/export.h> |
1da177e4 LT |
18 | #include <linux/pci.h> |
19 | #include <linux/init.h> | |
20 | #include <linux/delay.h> | |
25be5e6c | 21 | #include <linux/acpi.h> |
9f23ed3b | 22 | #include <linux/kallsyms.h> |
75e07fc3 | 23 | #include <linux/dmi.h> |
649426ef | 24 | #include <linux/pci-aspm.h> |
32a9a682 | 25 | #include <linux/ioport.h> |
3209874a AV |
26 | #include <linux/sched.h> |
27 | #include <linux/ktime.h> | |
9fe373f9 | 28 | #include <linux/mm.h> |
630b3aff | 29 | #include <linux/platform_data/x86/apple.h> |
93177a74 | 30 | #include <asm/dma.h> /* isa_dma_bridge_buggy */ |
bc56b9e0 | 31 | #include "pci.h" |
1da177e4 | 32 | |
253d2e54 JP |
33 | /* |
34 | * Decoding should be disabled for a PCI device during BAR sizing to avoid | |
35 | * conflict. But doing so may cause problems on host bridge and perhaps other | |
36 | * key system devices. For devices that need to have mmio decoding always-on, | |
37 | * we need to set the dev->mmio_always_on bit. | |
38 | */ | |
15856ad5 | 39 | static void quirk_mmio_always_on(struct pci_dev *dev) |
253d2e54 | 40 | { |
52d21b5e | 41 | dev->mmio_always_on = 1; |
253d2e54 | 42 | } |
52d21b5e YL |
43 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID, |
44 | PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on); | |
253d2e54 | 45 | |
b8e53421 XY |
46 | /* The BAR0 ~ BAR4 of Marvell 9125 device can't be accessed |
47 | * by IO resource file, and need to skip the files | |
48 | */ | |
49 | static void quirk_marvell_mask_bar(struct pci_dev *dev) | |
50 | { | |
51 | int i; | |
52 | ||
53 | for (i = 0; i < 5; i++) | |
54 | if (dev->resource[i].start) | |
55 | dev->resource[i].start = | |
56 | dev->resource[i].end = 0; | |
57 | } | |
58 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9125, | |
59 | quirk_marvell_mask_bar); | |
60 | ||
bd8481e1 DT |
61 | /* The Mellanox Tavor device gives false positive parity errors |
62 | * Mark this device with a broken_parity_status, to allow | |
63 | * PCI scanning code to "skip" this now blacklisted device. | |
64 | */ | |
15856ad5 | 65 | static void quirk_mellanox_tavor(struct pci_dev *dev) |
bd8481e1 DT |
66 | { |
67 | dev->broken_parity_status = 1; /* This device gives false positives */ | |
68 | } | |
3c78bc61 RD |
69 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor); |
70 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor); | |
bd8481e1 | 71 | |
f7625980 | 72 | /* Deal with broken BIOSes that neglect to enable passive release, |
1da177e4 | 73 | which can cause problems in combination with the 82441FX/PPro MTRRs */ |
1597cacb | 74 | static void quirk_passive_release(struct pci_dev *dev) |
1da177e4 LT |
75 | { |
76 | struct pci_dev *d = NULL; | |
77 | unsigned char dlc; | |
78 | ||
79 | /* We have to make sure a particular bit is set in the PIIX3 | |
80 | ISA bridge, so we have to go out and find it. */ | |
81 | while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { | |
82 | pci_read_config_byte(d, 0x82, &dlc); | |
83 | if (!(dlc & 1<<1)) { | |
999da9fd | 84 | dev_info(&d->dev, "PIIX3: Enabling Passive Release\n"); |
1da177e4 LT |
85 | dlc |= 1<<1; |
86 | pci_write_config_byte(d, 0x82, dlc); | |
87 | } | |
88 | } | |
89 | } | |
652c538e AM |
90 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); |
91 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); | |
1da177e4 LT |
92 | |
93 | /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround | |
94 | but VIA don't answer queries. If you happen to have good contacts at VIA | |
f7625980 BH |
95 | ask them for me please -- Alan |
96 | ||
97 | This appears to be BIOS not version dependent. So presumably there is a | |
1da177e4 | 98 | chipset level fix */ |
f7625980 | 99 | |
15856ad5 | 100 | static void quirk_isa_dma_hangs(struct pci_dev *dev) |
1da177e4 LT |
101 | { |
102 | if (!isa_dma_bridge_buggy) { | |
3c78bc61 | 103 | isa_dma_bridge_buggy = 1; |
f0fda801 | 104 | dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n"); |
1da177e4 LT |
105 | } |
106 | } | |
107 | /* | |
108 | * Its not totally clear which chipsets are the problematic ones | |
109 | * We know 82C586 and 82C596 variants are affected. | |
110 | */ | |
652c538e AM |
111 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs); |
112 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs); | |
113 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs); | |
f7625980 | 114 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs); |
652c538e AM |
115 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs); |
116 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs); | |
117 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs); | |
1da177e4 | 118 | |
4731fdcf LB |
119 | /* |
120 | * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear | |
121 | * for some HT machines to use C4 w/o hanging. | |
122 | */ | |
15856ad5 | 123 | static void quirk_tigerpoint_bm_sts(struct pci_dev *dev) |
4731fdcf LB |
124 | { |
125 | u32 pmbase; | |
126 | u16 pm1a; | |
127 | ||
128 | pci_read_config_dword(dev, 0x40, &pmbase); | |
129 | pmbase = pmbase & 0xff80; | |
130 | pm1a = inw(pmbase); | |
131 | ||
132 | if (pm1a & 0x10) { | |
133 | dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n"); | |
134 | outw(0x10, pmbase); | |
135 | } | |
136 | } | |
137 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts); | |
138 | ||
1da177e4 LT |
139 | /* |
140 | * Chipsets where PCI->PCI transfers vanish or hang | |
141 | */ | |
15856ad5 | 142 | static void quirk_nopcipci(struct pci_dev *dev) |
1da177e4 | 143 | { |
3c78bc61 | 144 | if ((pci_pci_problems & PCIPCI_FAIL) == 0) { |
f0fda801 | 145 | dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n"); |
1da177e4 LT |
146 | pci_pci_problems |= PCIPCI_FAIL; |
147 | } | |
148 | } | |
652c538e AM |
149 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci); |
150 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci); | |
236561e5 | 151 | |
15856ad5 | 152 | static void quirk_nopciamd(struct pci_dev *dev) |
236561e5 AC |
153 | { |
154 | u8 rev; | |
155 | pci_read_config_byte(dev, 0x08, &rev); | |
156 | if (rev == 0x13) { | |
157 | /* Erratum 24 */ | |
f0fda801 | 158 | dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); |
236561e5 AC |
159 | pci_pci_problems |= PCIAGP_FAIL; |
160 | } | |
161 | } | |
652c538e | 162 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd); |
1da177e4 LT |
163 | |
164 | /* | |
165 | * Triton requires workarounds to be used by the drivers | |
166 | */ | |
15856ad5 | 167 | static void quirk_triton(struct pci_dev *dev) |
1da177e4 | 168 | { |
3c78bc61 | 169 | if ((pci_pci_problems&PCIPCI_TRITON) == 0) { |
f0fda801 | 170 | dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); |
1da177e4 LT |
171 | pci_pci_problems |= PCIPCI_TRITON; |
172 | } | |
173 | } | |
f7625980 BH |
174 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton); |
175 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton); | |
176 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton); | |
177 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton); | |
1da177e4 LT |
178 | |
179 | /* | |
180 | * VIA Apollo KT133 needs PCI latency patch | |
181 | * Made according to a windows driver based patch by George E. Breese | |
182 | * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm | |
3c78bc61 RD |
183 | * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for |
184 | * the info on which Mr Breese based his work. | |
1da177e4 LT |
185 | * |
186 | * Updated based on further information from the site and also on | |
f7625980 | 187 | * information provided by VIA |
1da177e4 | 188 | */ |
1597cacb | 189 | static void quirk_vialatency(struct pci_dev *dev) |
1da177e4 LT |
190 | { |
191 | struct pci_dev *p; | |
1da177e4 LT |
192 | u8 busarb; |
193 | /* Ok we have a potential problem chipset here. Now see if we have | |
194 | a buggy southbridge */ | |
f7625980 | 195 | |
1da177e4 | 196 | p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); |
3c78bc61 | 197 | if (p != NULL) { |
1da177e4 LT |
198 | /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */ |
199 | /* Check for buggy part revisions */ | |
2b1afa87 | 200 | if (p->revision < 0x40 || p->revision > 0x42) |
1da177e4 LT |
201 | goto exit; |
202 | } else { | |
203 | p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); | |
3c78bc61 | 204 | if (p == NULL) /* No problem parts */ |
1da177e4 | 205 | goto exit; |
1da177e4 | 206 | /* Check for buggy part revisions */ |
2b1afa87 | 207 | if (p->revision < 0x10 || p->revision > 0x12) |
1da177e4 LT |
208 | goto exit; |
209 | } | |
f7625980 | 210 | |
1da177e4 | 211 | /* |
f7625980 | 212 | * Ok we have the problem. Now set the PCI master grant to |
1da177e4 LT |
213 | * occur every master grant. The apparent bug is that under high |
214 | * PCI load (quite common in Linux of course) you can get data | |
215 | * loss when the CPU is held off the bus for 3 bus master requests | |
216 | * This happens to include the IDE controllers.... | |
217 | * | |
218 | * VIA only apply this fix when an SB Live! is present but under | |
25985edc | 219 | * both Linux and Windows this isn't enough, and we have seen |
1da177e4 LT |
220 | * corruption without SB Live! but with things like 3 UDMA IDE |
221 | * controllers. So we ignore that bit of the VIA recommendation.. | |
222 | */ | |
223 | ||
224 | pci_read_config_byte(dev, 0x76, &busarb); | |
f7625980 | 225 | /* Set bit 4 and bi 5 of byte 76 to 0x01 |
1da177e4 LT |
226 | "Master priority rotation on every PCI master grant */ |
227 | busarb &= ~(1<<5); | |
228 | busarb |= (1<<4); | |
229 | pci_write_config_byte(dev, 0x76, busarb); | |
f0fda801 | 230 | dev_info(&dev->dev, "Applying VIA southbridge workaround\n"); |
1da177e4 LT |
231 | exit: |
232 | pci_dev_put(p); | |
233 | } | |
652c538e AM |
234 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); |
235 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); | |
236 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); | |
1597cacb | 237 | /* Must restore this on a resume from RAM */ |
652c538e AM |
238 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); |
239 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); | |
240 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); | |
1da177e4 LT |
241 | |
242 | /* | |
243 | * VIA Apollo VP3 needs ETBF on BT848/878 | |
244 | */ | |
15856ad5 | 245 | static void quirk_viaetbf(struct pci_dev *dev) |
1da177e4 | 246 | { |
3c78bc61 | 247 | if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) { |
f0fda801 | 248 | dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); |
1da177e4 LT |
249 | pci_pci_problems |= PCIPCI_VIAETBF; |
250 | } | |
251 | } | |
652c538e | 252 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf); |
1da177e4 | 253 | |
15856ad5 | 254 | static void quirk_vsfx(struct pci_dev *dev) |
1da177e4 | 255 | { |
3c78bc61 | 256 | if ((pci_pci_problems&PCIPCI_VSFX) == 0) { |
f0fda801 | 257 | dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); |
1da177e4 LT |
258 | pci_pci_problems |= PCIPCI_VSFX; |
259 | } | |
260 | } | |
652c538e | 261 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx); |
1da177e4 LT |
262 | |
263 | /* | |
264 | * Ali Magik requires workarounds to be used by the drivers | |
265 | * that DMA to AGP space. Latency must be set to 0xA and triton | |
266 | * workaround applied too | |
267 | * [Info kindly provided by ALi] | |
f7625980 | 268 | */ |
15856ad5 | 269 | static void quirk_alimagik(struct pci_dev *dev) |
1da177e4 | 270 | { |
3c78bc61 | 271 | if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) { |
f0fda801 | 272 | dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); |
1da177e4 LT |
273 | pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; |
274 | } | |
275 | } | |
f7625980 BH |
276 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik); |
277 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik); | |
1da177e4 LT |
278 | |
279 | /* | |
280 | * Natoma has some interesting boundary conditions with Zoran stuff | |
281 | * at least | |
282 | */ | |
15856ad5 | 283 | static void quirk_natoma(struct pci_dev *dev) |
1da177e4 | 284 | { |
3c78bc61 | 285 | if ((pci_pci_problems&PCIPCI_NATOMA) == 0) { |
f0fda801 | 286 | dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); |
1da177e4 LT |
287 | pci_pci_problems |= PCIPCI_NATOMA; |
288 | } | |
289 | } | |
f7625980 BH |
290 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma); |
291 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma); | |
292 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma); | |
293 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma); | |
294 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma); | |
295 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma); | |
1da177e4 LT |
296 | |
297 | /* | |
298 | * This chip can cause PCI parity errors if config register 0xA0 is read | |
299 | * while DMAs are occurring. | |
300 | */ | |
15856ad5 | 301 | static void quirk_citrine(struct pci_dev *dev) |
1da177e4 LT |
302 | { |
303 | dev->cfg_size = 0xA0; | |
304 | } | |
652c538e | 305 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine); |
1da177e4 | 306 | |
9f33a2ae JM |
307 | /* |
308 | * This chip can cause bus lockups if config addresses above 0x600 | |
309 | * are read or written. | |
310 | */ | |
311 | static void quirk_nfp6000(struct pci_dev *dev) | |
312 | { | |
313 | dev->cfg_size = 0x600; | |
314 | } | |
c2e771b0 | 315 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000); |
9f33a2ae JM |
316 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000); |
317 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000); | |
318 | ||
9fe373f9 DL |
319 | /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */ |
320 | static void quirk_extend_bar_to_page(struct pci_dev *dev) | |
321 | { | |
322 | int i; | |
323 | ||
2f686f1d | 324 | for (i = 0; i <= PCI_STD_RESOURCE_END; i++) { |
9fe373f9 DL |
325 | struct resource *r = &dev->resource[i]; |
326 | ||
327 | if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) { | |
328 | r->end = PAGE_SIZE - 1; | |
329 | r->start = 0; | |
330 | r->flags |= IORESOURCE_UNSET; | |
331 | dev_info(&dev->dev, "expanded BAR %d to page size: %pR\n", | |
332 | i, r); | |
333 | } | |
334 | } | |
335 | } | |
336 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page); | |
337 | ||
1da177e4 LT |
338 | /* |
339 | * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. | |
340 | * If it's needed, re-allocate the region. | |
341 | */ | |
15856ad5 | 342 | static void quirk_s3_64M(struct pci_dev *dev) |
1da177e4 LT |
343 | { |
344 | struct resource *r = &dev->resource[0]; | |
345 | ||
346 | if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { | |
bd064f0a | 347 | r->flags |= IORESOURCE_UNSET; |
1da177e4 LT |
348 | r->start = 0; |
349 | r->end = 0x3ffffff; | |
350 | } | |
351 | } | |
652c538e AM |
352 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M); |
353 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M); | |
1da177e4 | 354 | |
06cf35f9 MS |
355 | static void quirk_io(struct pci_dev *dev, int pos, unsigned size, |
356 | const char *name) | |
357 | { | |
358 | u32 region; | |
359 | struct pci_bus_region bus_region; | |
360 | struct resource *res = dev->resource + pos; | |
361 | ||
362 | pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion); | |
363 | ||
364 | if (!region) | |
365 | return; | |
366 | ||
367 | res->name = pci_name(dev); | |
368 | res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK; | |
369 | res->flags |= | |
370 | (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN); | |
371 | region &= ~(size - 1); | |
372 | ||
373 | /* Convert from PCI bus to resource space */ | |
374 | bus_region.start = region; | |
375 | bus_region.end = region + size - 1; | |
376 | pcibios_bus_to_resource(dev->bus, res, &bus_region); | |
377 | ||
378 | dev_info(&dev->dev, FW_BUG "%s quirk: reg 0x%x: %pR\n", | |
379 | name, PCI_BASE_ADDRESS_0 + (pos << 2), res); | |
380 | } | |
381 | ||
73d2eaac AS |
382 | /* |
383 | * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS | |
384 | * ver. 1.33 20070103) don't set the correct ISA PCI region header info. | |
385 | * BAR0 should be 8 bytes; instead, it may be set to something like 8k | |
386 | * (which conflicts w/ BAR1's memory range). | |
06cf35f9 MS |
387 | * |
388 | * CS553x's ISA PCI BARs may also be read-only (ref: | |
389 | * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward). | |
73d2eaac | 390 | */ |
15856ad5 | 391 | static void quirk_cs5536_vsa(struct pci_dev *dev) |
73d2eaac | 392 | { |
06cf35f9 MS |
393 | static char *name = "CS5536 ISA bridge"; |
394 | ||
73d2eaac | 395 | if (pci_resource_len(dev, 0) != 8) { |
06cf35f9 MS |
396 | quirk_io(dev, 0, 8, name); /* SMB */ |
397 | quirk_io(dev, 1, 256, name); /* GPIO */ | |
398 | quirk_io(dev, 2, 64, name); /* MFGPT */ | |
399 | dev_info(&dev->dev, "%s bug detected (incorrect header); workaround applied\n", | |
400 | name); | |
73d2eaac AS |
401 | } |
402 | } | |
403 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa); | |
404 | ||
65195c76 YL |
405 | static void quirk_io_region(struct pci_dev *dev, int port, |
406 | unsigned size, int nr, const char *name) | |
407 | { | |
408 | u16 region; | |
409 | struct pci_bus_region bus_region; | |
410 | struct resource *res = dev->resource + nr; | |
411 | ||
412 | pci_read_config_word(dev, port, ®ion); | |
413 | region &= ~(size - 1); | |
414 | ||
415 | if (!region) | |
416 | return; | |
417 | ||
418 | res->name = pci_name(dev); | |
419 | res->flags = IORESOURCE_IO; | |
420 | ||
421 | /* Convert from PCI bus to resource space */ | |
422 | bus_region.start = region; | |
423 | bus_region.end = region + size - 1; | |
fc279850 | 424 | pcibios_bus_to_resource(dev->bus, res, &bus_region); |
65195c76 YL |
425 | |
426 | if (!pci_claim_resource(dev, nr)) | |
427 | dev_info(&dev->dev, "quirk: %pR claimed by %s\n", res, name); | |
428 | } | |
1da177e4 LT |
429 | |
430 | /* | |
431 | * ATI Northbridge setups MCE the processor if you even | |
432 | * read somewhere between 0x3b0->0x3bb or read 0x3d3 | |
433 | */ | |
15856ad5 | 434 | static void quirk_ati_exploding_mce(struct pci_dev *dev) |
1da177e4 | 435 | { |
f0fda801 | 436 | dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); |
1da177e4 LT |
437 | /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ |
438 | request_region(0x3b0, 0x0C, "RadeonIGP"); | |
439 | request_region(0x3d3, 0x01, "RadeonIGP"); | |
440 | } | |
652c538e | 441 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce); |
1da177e4 | 442 | |
be6646bf HR |
443 | /* |
444 | * In the AMD NL platform, this device ([1022:7912]) has a class code of | |
445 | * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will | |
446 | * claim it. | |
447 | * But the dwc3 driver is a more specific driver for this device, and we'd | |
448 | * prefer to use it instead of xhci. To prevent xhci from claiming the | |
449 | * device, change the class code to 0x0c03fe, which the PCI r3.0 spec | |
450 | * defines as "USB device (not host controller)". The dwc3 driver can then | |
451 | * claim it based on its Vendor and Device ID. | |
452 | */ | |
453 | static void quirk_amd_nl_class(struct pci_dev *pdev) | |
454 | { | |
cd76d10b BH |
455 | u32 class = pdev->class; |
456 | ||
457 | /* Use "USB Device (not host controller)" class */ | |
7b78f48a | 458 | pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; |
cd76d10b BH |
459 | dev_info(&pdev->dev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", |
460 | class, pdev->class); | |
be6646bf HR |
461 | } |
462 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB, | |
463 | quirk_amd_nl_class); | |
464 | ||
1da177e4 LT |
465 | /* |
466 | * Let's make the southbridge information explicit instead | |
467 | * of having to worry about people probing the ACPI areas, | |
468 | * for example.. (Yes, it happens, and if you read the wrong | |
469 | * ACPI register it will put the machine to sleep with no | |
470 | * way of waking it up again. Bummer). | |
471 | * | |
472 | * ALI M7101: Two IO regions pointed to by words at | |
473 | * 0xE0 (64 bytes of ACPI registers) | |
474 | * 0xE2 (32 bytes of SMB registers) | |
475 | */ | |
15856ad5 | 476 | static void quirk_ali7101_acpi(struct pci_dev *dev) |
1da177e4 | 477 | { |
65195c76 YL |
478 | quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); |
479 | quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); | |
1da177e4 | 480 | } |
652c538e | 481 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi); |
1da177e4 | 482 | |
6693e74a LT |
483 | static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) |
484 | { | |
485 | u32 devres; | |
486 | u32 mask, size, base; | |
487 | ||
488 | pci_read_config_dword(dev, port, &devres); | |
489 | if ((devres & enable) != enable) | |
490 | return; | |
491 | mask = (devres >> 16) & 15; | |
492 | base = devres & 0xffff; | |
493 | size = 16; | |
494 | for (;;) { | |
495 | unsigned bit = size >> 1; | |
496 | if ((bit & mask) == bit) | |
497 | break; | |
498 | size = bit; | |
499 | } | |
500 | /* | |
501 | * For now we only print it out. Eventually we'll want to | |
502 | * reserve it (at least if it's in the 0x1000+ range), but | |
f7625980 | 503 | * let's get enough confirmation reports first. |
6693e74a LT |
504 | */ |
505 | base &= -size; | |
227f0647 RD |
506 | dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, |
507 | base + size - 1); | |
6693e74a LT |
508 | } |
509 | ||
510 | static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) | |
511 | { | |
512 | u32 devres; | |
513 | u32 mask, size, base; | |
514 | ||
515 | pci_read_config_dword(dev, port, &devres); | |
516 | if ((devres & enable) != enable) | |
517 | return; | |
518 | base = devres & 0xffff0000; | |
519 | mask = (devres & 0x3f) << 16; | |
520 | size = 128 << 16; | |
521 | for (;;) { | |
522 | unsigned bit = size >> 1; | |
523 | if ((bit & mask) == bit) | |
524 | break; | |
525 | size = bit; | |
526 | } | |
527 | /* | |
528 | * For now we only print it out. Eventually we'll want to | |
f7625980 | 529 | * reserve it, but let's get enough confirmation reports first. |
6693e74a LT |
530 | */ |
531 | base &= -size; | |
227f0647 RD |
532 | dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, |
533 | base + size - 1); | |
6693e74a LT |
534 | } |
535 | ||
1da177e4 LT |
536 | /* |
537 | * PIIX4 ACPI: Two IO regions pointed to by longwords at | |
538 | * 0x40 (64 bytes of ACPI registers) | |
08db2a70 | 539 | * 0x90 (16 bytes of SMB registers) |
6693e74a | 540 | * and a few strange programmable PIIX4 device resources. |
1da177e4 | 541 | */ |
15856ad5 | 542 | static void quirk_piix4_acpi(struct pci_dev *dev) |
1da177e4 | 543 | { |
65195c76 | 544 | u32 res_a; |
1da177e4 | 545 | |
65195c76 YL |
546 | quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); |
547 | quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); | |
6693e74a LT |
548 | |
549 | /* Device resource A has enables for some of the other ones */ | |
550 | pci_read_config_dword(dev, 0x5c, &res_a); | |
551 | ||
552 | piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); | |
553 | piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); | |
554 | ||
555 | /* Device resource D is just bitfields for static resources */ | |
556 | ||
557 | /* Device 12 enabled? */ | |
558 | if (res_a & (1 << 29)) { | |
559 | piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); | |
560 | piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); | |
561 | } | |
562 | /* Device 13 enabled? */ | |
563 | if (res_a & (1 << 30)) { | |
564 | piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); | |
565 | piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); | |
566 | } | |
567 | piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); | |
568 | piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); | |
1da177e4 | 569 | } |
652c538e AM |
570 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi); |
571 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi); | |
1da177e4 | 572 | |
cdb97558 JS |
573 | #define ICH_PMBASE 0x40 |
574 | #define ICH_ACPI_CNTL 0x44 | |
575 | #define ICH4_ACPI_EN 0x10 | |
576 | #define ICH6_ACPI_EN 0x80 | |
577 | #define ICH4_GPIOBASE 0x58 | |
578 | #define ICH4_GPIO_CNTL 0x5c | |
579 | #define ICH4_GPIO_EN 0x10 | |
580 | #define ICH6_GPIOBASE 0x48 | |
581 | #define ICH6_GPIO_CNTL 0x4c | |
582 | #define ICH6_GPIO_EN 0x10 | |
583 | ||
1da177e4 LT |
584 | /* |
585 | * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at | |
586 | * 0x40 (128 bytes of ACPI, GPIO & TCO registers) | |
587 | * 0x58 (64 bytes of GPIO I/O space) | |
588 | */ | |
15856ad5 | 589 | static void quirk_ich4_lpc_acpi(struct pci_dev *dev) |
1da177e4 | 590 | { |
cdb97558 | 591 | u8 enable; |
1da177e4 | 592 | |
87e3dc38 JS |
593 | /* |
594 | * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict | |
595 | * with low legacy (and fixed) ports. We don't know the decoding | |
596 | * priority and can't tell whether the legacy device or the one created | |
597 | * here is really at that address. This happens on boards with broken | |
598 | * BIOSes. | |
599 | */ | |
600 | ||
cdb97558 | 601 | pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); |
65195c76 YL |
602 | if (enable & ICH4_ACPI_EN) |
603 | quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, | |
604 | "ICH4 ACPI/GPIO/TCO"); | |
1da177e4 | 605 | |
cdb97558 | 606 | pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable); |
65195c76 YL |
607 | if (enable & ICH4_GPIO_EN) |
608 | quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, | |
609 | "ICH4 GPIO"); | |
1da177e4 | 610 | } |
652c538e AM |
611 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi); |
612 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi); | |
613 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi); | |
614 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi); | |
615 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi); | |
616 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi); | |
617 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi); | |
618 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi); | |
619 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi); | |
620 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi); | |
1da177e4 | 621 | |
15856ad5 | 622 | static void ich6_lpc_acpi_gpio(struct pci_dev *dev) |
2cea752f | 623 | { |
cdb97558 | 624 | u8 enable; |
2cea752f | 625 | |
cdb97558 | 626 | pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); |
65195c76 YL |
627 | if (enable & ICH6_ACPI_EN) |
628 | quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, | |
629 | "ICH6 ACPI/GPIO/TCO"); | |
2cea752f | 630 | |
cdb97558 | 631 | pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable); |
65195c76 YL |
632 | if (enable & ICH6_GPIO_EN) |
633 | quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, | |
634 | "ICH6 GPIO"); | |
2cea752f | 635 | } |
894886e5 | 636 | |
15856ad5 | 637 | static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize) |
894886e5 LT |
638 | { |
639 | u32 val; | |
640 | u32 size, base; | |
641 | ||
642 | pci_read_config_dword(dev, reg, &val); | |
643 | ||
644 | /* Enabled? */ | |
645 | if (!(val & 1)) | |
646 | return; | |
647 | base = val & 0xfffc; | |
648 | if (dynsize) { | |
649 | /* | |
650 | * This is not correct. It is 16, 32 or 64 bytes depending on | |
651 | * register D31:F0:ADh bits 5:4. | |
652 | * | |
653 | * But this gets us at least _part_ of it. | |
654 | */ | |
655 | size = 16; | |
656 | } else { | |
657 | size = 128; | |
658 | } | |
659 | base &= ~(size-1); | |
660 | ||
661 | /* Just print it out for now. We should reserve it after more debugging */ | |
662 | dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); | |
663 | } | |
664 | ||
15856ad5 | 665 | static void quirk_ich6_lpc(struct pci_dev *dev) |
894886e5 LT |
666 | { |
667 | /* Shared ACPI/GPIO decode with all ICH6+ */ | |
668 | ich6_lpc_acpi_gpio(dev); | |
669 | ||
670 | /* ICH6-specific generic IO decode */ | |
671 | ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); | |
672 | ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); | |
673 | } | |
674 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc); | |
675 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc); | |
676 | ||
15856ad5 | 677 | static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name) |
894886e5 LT |
678 | { |
679 | u32 val; | |
680 | u32 mask, base; | |
681 | ||
682 | pci_read_config_dword(dev, reg, &val); | |
683 | ||
684 | /* Enabled? */ | |
685 | if (!(val & 1)) | |
686 | return; | |
687 | ||
688 | /* | |
689 | * IO base in bits 15:2, mask in bits 23:18, both | |
690 | * are dword-based | |
691 | */ | |
692 | base = val & 0xfffc; | |
693 | mask = (val >> 16) & 0xfc; | |
694 | mask |= 3; | |
695 | ||
696 | /* Just print it out for now. We should reserve it after more debugging */ | |
697 | dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); | |
698 | } | |
699 | ||
700 | /* ICH7-10 has the same common LPC generic IO decode registers */ | |
15856ad5 | 701 | static void quirk_ich7_lpc(struct pci_dev *dev) |
894886e5 | 702 | { |
5d9c0a79 | 703 | /* We share the common ACPI/GPIO decode with ICH6 */ |
894886e5 LT |
704 | ich6_lpc_acpi_gpio(dev); |
705 | ||
706 | /* And have 4 ICH7+ generic decodes */ | |
707 | ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); | |
708 | ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); | |
709 | ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); | |
710 | ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); | |
711 | } | |
712 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc); | |
713 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc); | |
714 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc); | |
715 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc); | |
716 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc); | |
717 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc); | |
718 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc); | |
719 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc); | |
720 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc); | |
721 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc); | |
722 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc); | |
723 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc); | |
724 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc); | |
2cea752f | 725 | |
1da177e4 LT |
726 | /* |
727 | * VIA ACPI: One IO region pointed to by longword at | |
728 | * 0x48 or 0x20 (256 bytes of ACPI registers) | |
729 | */ | |
15856ad5 | 730 | static void quirk_vt82c586_acpi(struct pci_dev *dev) |
1da177e4 | 731 | { |
65195c76 YL |
732 | if (dev->revision & 0x10) |
733 | quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES, | |
734 | "vt82c586 ACPI"); | |
1da177e4 | 735 | } |
652c538e | 736 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi); |
1da177e4 LT |
737 | |
738 | /* | |
739 | * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at | |
740 | * 0x48 (256 bytes of ACPI registers) | |
741 | * 0x70 (128 bytes of hardware monitoring register) | |
742 | * 0x90 (16 bytes of SMB registers) | |
743 | */ | |
15856ad5 | 744 | static void quirk_vt82c686_acpi(struct pci_dev *dev) |
1da177e4 | 745 | { |
1da177e4 LT |
746 | quirk_vt82c586_acpi(dev); |
747 | ||
65195c76 YL |
748 | quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1, |
749 | "vt82c686 HW-mon"); | |
1da177e4 | 750 | |
65195c76 | 751 | quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB"); |
1da177e4 | 752 | } |
652c538e | 753 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi); |
1da177e4 | 754 | |
6d85f29b IK |
755 | /* |
756 | * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at | |
757 | * 0x88 (128 bytes of power management registers) | |
758 | * 0xd0 (16 bytes of SMB registers) | |
759 | */ | |
15856ad5 | 760 | static void quirk_vt8235_acpi(struct pci_dev *dev) |
6d85f29b | 761 | { |
65195c76 YL |
762 | quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); |
763 | quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB"); | |
6d85f29b IK |
764 | } |
765 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); | |
766 | ||
1f56f4a2 GB |
767 | /* |
768 | * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back: | |
769 | * Disable fast back-to-back on the secondary bus segment | |
770 | */ | |
15856ad5 | 771 | static void quirk_xio2000a(struct pci_dev *dev) |
1f56f4a2 GB |
772 | { |
773 | struct pci_dev *pdev; | |
774 | u16 command; | |
775 | ||
227f0647 | 776 | dev_warn(&dev->dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n"); |
1f56f4a2 GB |
777 | list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { |
778 | pci_read_config_word(pdev, PCI_COMMAND, &command); | |
779 | if (command & PCI_COMMAND_FAST_BACK) | |
780 | pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK); | |
781 | } | |
782 | } | |
783 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A, | |
784 | quirk_xio2000a); | |
1da177e4 | 785 | |
f7625980 | 786 | #ifdef CONFIG_X86_IO_APIC |
1da177e4 LT |
787 | |
788 | #include <asm/io_apic.h> | |
789 | ||
790 | /* | |
791 | * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip | |
792 | * devices to the external APIC. | |
793 | * | |
794 | * TODO: When we have device-specific interrupt routers, | |
795 | * this code will go away from quirks. | |
796 | */ | |
1597cacb | 797 | static void quirk_via_ioapic(struct pci_dev *dev) |
1da177e4 LT |
798 | { |
799 | u8 tmp; | |
f7625980 | 800 | |
1da177e4 LT |
801 | if (nr_ioapics < 1) |
802 | tmp = 0; /* nothing routed to external APIC */ | |
803 | else | |
804 | tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ | |
f7625980 | 805 | |
f0fda801 | 806 | dev_info(&dev->dev, "%sbling VIA external APIC routing\n", |
1da177e4 LT |
807 | tmp == 0 ? "Disa" : "Ena"); |
808 | ||
809 | /* Offset 0x58: External APIC IRQ output control */ | |
3c78bc61 | 810 | pci_write_config_byte(dev, 0x58, tmp); |
1da177e4 | 811 | } |
652c538e | 812 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); |
e1a2a51e | 813 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); |
1da177e4 | 814 | |
a1740913 | 815 | /* |
f7625980 | 816 | * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit. |
a1740913 KW |
817 | * This leads to doubled level interrupt rates. |
818 | * Set this bit to get rid of cycle wastage. | |
819 | * Otherwise uncritical. | |
820 | */ | |
1597cacb | 821 | static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) |
a1740913 KW |
822 | { |
823 | u8 misc_control2; | |
824 | #define BYPASS_APIC_DEASSERT 8 | |
825 | ||
826 | pci_read_config_byte(dev, 0x5B, &misc_control2); | |
827 | if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { | |
f0fda801 | 828 | dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); |
a1740913 KW |
829 | pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); |
830 | } | |
831 | } | |
832 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); | |
e1a2a51e | 833 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); |
a1740913 | 834 | |
1da177e4 LT |
835 | /* |
836 | * The AMD io apic can hang the box when an apic irq is masked. | |
837 | * We check all revs >= B0 (yet not in the pre production!) as the bug | |
838 | * is currently marked NoFix | |
839 | * | |
840 | * We have multiple reports of hangs with this chipset that went away with | |
236561e5 | 841 | * noapic specified. For the moment we assume it's the erratum. We may be wrong |
1da177e4 LT |
842 | * of course. However the advice is demonstrably good even if so.. |
843 | */ | |
15856ad5 | 844 | static void quirk_amd_ioapic(struct pci_dev *dev) |
1da177e4 | 845 | { |
44c10138 | 846 | if (dev->revision >= 0x02) { |
f0fda801 | 847 | dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); |
848 | dev_warn(&dev->dev, " : booting with the \"noapic\" option\n"); | |
1da177e4 LT |
849 | } |
850 | } | |
652c538e | 851 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic); |
1da177e4 LT |
852 | #endif /* CONFIG_X86_IO_APIC */ |
853 | ||
0bec9057 | 854 | #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS) |
21b5b8ee AJ |
855 | |
856 | static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev) | |
857 | { | |
858 | /* Fix for improper SRIOV configuration on Cavium cn88xx RNM device */ | |
859 | if (dev->subsystem_device == 0xa118) | |
860 | dev->sriov->link = dev->devfn; | |
861 | } | |
862 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link); | |
863 | #endif | |
864 | ||
d556ad4b PO |
865 | /* |
866 | * Some settings of MMRBC can lead to data corruption so block changes. | |
867 | * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide | |
868 | */ | |
15856ad5 | 869 | static void quirk_amd_8131_mmrbc(struct pci_dev *dev) |
d556ad4b | 870 | { |
aa288d4d | 871 | if (dev->subordinate && dev->revision <= 0x12) { |
227f0647 RD |
872 | dev_info(&dev->dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n", |
873 | dev->revision); | |
d556ad4b PO |
874 | dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; |
875 | } | |
876 | } | |
877 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc); | |
1da177e4 | 878 | |
1da177e4 LT |
879 | /* |
880 | * FIXME: it is questionable that quirk_via_acpi | |
881 | * is needed. It shows up as an ISA bridge, and does not | |
882 | * support the PCI_INTERRUPT_LINE register at all. Therefore | |
883 | * it seems like setting the pci_dev's 'irq' to the | |
884 | * value of the ACPI SCI interrupt is only done for convenience. | |
885 | * -jgarzik | |
886 | */ | |
15856ad5 | 887 | static void quirk_via_acpi(struct pci_dev *d) |
1da177e4 LT |
888 | { |
889 | /* | |
890 | * VIA ACPI device: SCI IRQ line in PCI config byte 0x42 | |
891 | */ | |
892 | u8 irq; | |
893 | pci_read_config_byte(d, 0x42, &irq); | |
894 | irq &= 0xf; | |
895 | if (irq && (irq != 2)) | |
896 | d->irq = irq; | |
897 | } | |
652c538e AM |
898 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi); |
899 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi); | |
1da177e4 | 900 | |
09d6029f DD |
901 | |
902 | /* | |
1597cacb | 903 | * VIA bridges which have VLink |
09d6029f | 904 | */ |
1597cacb | 905 | |
c06bb5d4 JD |
906 | static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18; |
907 | ||
908 | static void quirk_via_bridge(struct pci_dev *dev) | |
909 | { | |
910 | /* See what bridge we have and find the device ranges */ | |
911 | switch (dev->device) { | |
912 | case PCI_DEVICE_ID_VIA_82C686: | |
cb7468ef JD |
913 | /* The VT82C686 is special, it attaches to PCI and can have |
914 | any device number. All its subdevices are functions of | |
915 | that single device. */ | |
916 | via_vlink_dev_lo = PCI_SLOT(dev->devfn); | |
917 | via_vlink_dev_hi = PCI_SLOT(dev->devfn); | |
c06bb5d4 JD |
918 | break; |
919 | case PCI_DEVICE_ID_VIA_8237: | |
920 | case PCI_DEVICE_ID_VIA_8237A: | |
921 | via_vlink_dev_lo = 15; | |
922 | break; | |
923 | case PCI_DEVICE_ID_VIA_8235: | |
924 | via_vlink_dev_lo = 16; | |
925 | break; | |
926 | case PCI_DEVICE_ID_VIA_8231: | |
927 | case PCI_DEVICE_ID_VIA_8233_0: | |
928 | case PCI_DEVICE_ID_VIA_8233A: | |
929 | case PCI_DEVICE_ID_VIA_8233C_0: | |
930 | via_vlink_dev_lo = 17; | |
931 | break; | |
932 | } | |
933 | } | |
934 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge); | |
935 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge); | |
936 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge); | |
937 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge); | |
938 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge); | |
939 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge); | |
940 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge); | |
941 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge); | |
09d6029f | 942 | |
1597cacb AC |
943 | /** |
944 | * quirk_via_vlink - VIA VLink IRQ number update | |
945 | * @dev: PCI device | |
946 | * | |
947 | * If the device we are dealing with is on a PIC IRQ we need to | |
948 | * ensure that the IRQ line register which usually is not relevant | |
949 | * for PCI cards, is actually written so that interrupts get sent | |
c06bb5d4 JD |
950 | * to the right place. |
951 | * We only do this on systems where a VIA south bridge was detected, | |
952 | * and only for VIA devices on the motherboard (see quirk_via_bridge | |
953 | * above). | |
1597cacb AC |
954 | */ |
955 | ||
956 | static void quirk_via_vlink(struct pci_dev *dev) | |
25be5e6c LB |
957 | { |
958 | u8 irq, new_irq; | |
959 | ||
c06bb5d4 JD |
960 | /* Check if we have VLink at all */ |
961 | if (via_vlink_dev_lo == -1) | |
09d6029f DD |
962 | return; |
963 | ||
964 | new_irq = dev->irq; | |
965 | ||
966 | /* Don't quirk interrupts outside the legacy IRQ range */ | |
967 | if (!new_irq || new_irq > 15) | |
968 | return; | |
969 | ||
1597cacb | 970 | /* Internal device ? */ |
c06bb5d4 JD |
971 | if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || |
972 | PCI_SLOT(dev->devfn) < via_vlink_dev_lo) | |
1597cacb AC |
973 | return; |
974 | ||
975 | /* This is an internal VLink device on a PIC interrupt. The BIOS | |
976 | ought to have set this but may not have, so we redo it */ | |
977 | ||
25be5e6c LB |
978 | pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); |
979 | if (new_irq != irq) { | |
f0fda801 | 980 | dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n", |
981 | irq, new_irq); | |
25be5e6c LB |
982 | udelay(15); /* unknown if delay really needed */ |
983 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); | |
984 | } | |
985 | } | |
1597cacb | 986 | DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink); |
25be5e6c | 987 | |
1da177e4 LT |
988 | /* |
989 | * VIA VT82C598 has its device ID settable and many BIOSes | |
990 | * set it to the ID of VT82C597 for backward compatibility. | |
991 | * We need to switch it off to be able to recognize the real | |
992 | * type of the chip. | |
993 | */ | |
15856ad5 | 994 | static void quirk_vt82c598_id(struct pci_dev *dev) |
1da177e4 LT |
995 | { |
996 | pci_write_config_byte(dev, 0xfc, 0); | |
997 | pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); | |
998 | } | |
652c538e | 999 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id); |
1da177e4 LT |
1000 | |
1001 | /* | |
1002 | * CardBus controllers have a legacy base address that enables them | |
1003 | * to respond as i82365 pcmcia controllers. We don't want them to | |
1004 | * do this even if the Linux CardBus driver is not loaded, because | |
1005 | * the Linux i82365 driver does not (and should not) handle CardBus. | |
1006 | */ | |
1597cacb | 1007 | static void quirk_cardbus_legacy(struct pci_dev *dev) |
1da177e4 | 1008 | { |
1da177e4 LT |
1009 | pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); |
1010 | } | |
ae9de56b YL |
1011 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, |
1012 | PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); | |
1013 | DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, | |
1014 | PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); | |
1da177e4 LT |
1015 | |
1016 | /* | |
1017 | * Following the PCI ordering rules is optional on the AMD762. I'm not | |
1018 | * sure what the designers were smoking but let's not inhale... | |
1019 | * | |
1020 | * To be fair to AMD, it follows the spec by default, its BIOS people | |
1021 | * who turn it off! | |
1022 | */ | |
1597cacb | 1023 | static void quirk_amd_ordering(struct pci_dev *dev) |
1da177e4 LT |
1024 | { |
1025 | u32 pcic; | |
1026 | pci_read_config_dword(dev, 0x4C, &pcic); | |
3c78bc61 | 1027 | if ((pcic & 6) != 6) { |
1da177e4 | 1028 | pcic |= 6; |
f0fda801 | 1029 | dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); |
1da177e4 LT |
1030 | pci_write_config_dword(dev, 0x4C, pcic); |
1031 | pci_read_config_dword(dev, 0x84, &pcic); | |
3c78bc61 | 1032 | pcic |= (1 << 23); /* Required in this mode */ |
1da177e4 LT |
1033 | pci_write_config_dword(dev, 0x84, pcic); |
1034 | } | |
1035 | } | |
652c538e | 1036 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); |
e1a2a51e | 1037 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); |
1da177e4 LT |
1038 | |
1039 | /* | |
1040 | * DreamWorks provided workaround for Dunord I-3000 problem | |
1041 | * | |
1042 | * This card decodes and responds to addresses not apparently | |
1043 | * assigned to it. We force a larger allocation to ensure that | |
1044 | * nothing gets put too close to it. | |
1045 | */ | |
15856ad5 | 1046 | static void quirk_dunord(struct pci_dev *dev) |
1da177e4 | 1047 | { |
3c78bc61 | 1048 | struct resource *r = &dev->resource[1]; |
bd064f0a BH |
1049 | |
1050 | r->flags |= IORESOURCE_UNSET; | |
1da177e4 LT |
1051 | r->start = 0; |
1052 | r->end = 0xffffff; | |
1053 | } | |
652c538e | 1054 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord); |
1da177e4 LT |
1055 | |
1056 | /* | |
1057 | * i82380FB mobile docking controller: its PCI-to-PCI bridge | |
1058 | * is subtractive decoding (transparent), and does indicate this | |
1059 | * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80 | |
1060 | * instead of 0x01. | |
1061 | */ | |
15856ad5 | 1062 | static void quirk_transparent_bridge(struct pci_dev *dev) |
1da177e4 LT |
1063 | { |
1064 | dev->transparent = 1; | |
1065 | } | |
652c538e AM |
1066 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge); |
1067 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge); | |
1da177e4 LT |
1068 | |
1069 | /* | |
1070 | * Common misconfiguration of the MediaGX/Geode PCI master that will | |
1071 | * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 | |
631dd1a8 | 1072 | * datasheets found at http://www.national.com/analog for info on what |
1da177e4 LT |
1073 | * these bits do. <christer@weinigel.se> |
1074 | */ | |
1597cacb | 1075 | static void quirk_mediagx_master(struct pci_dev *dev) |
1da177e4 LT |
1076 | { |
1077 | u8 reg; | |
3c78bc61 | 1078 | |
1da177e4 LT |
1079 | pci_read_config_byte(dev, 0x41, ®); |
1080 | if (reg & 2) { | |
1081 | reg &= ~2; | |
227f0647 RD |
1082 | dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", |
1083 | reg); | |
3c78bc61 | 1084 | pci_write_config_byte(dev, 0x41, reg); |
1da177e4 LT |
1085 | } |
1086 | } | |
652c538e AM |
1087 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); |
1088 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); | |
1da177e4 | 1089 | |
1da177e4 LT |
1090 | /* |
1091 | * Ensure C0 rev restreaming is off. This is normally done by | |
1092 | * the BIOS but in the odd case it is not the results are corruption | |
1093 | * hence the presence of a Linux check | |
1094 | */ | |
1597cacb | 1095 | static void quirk_disable_pxb(struct pci_dev *pdev) |
1da177e4 LT |
1096 | { |
1097 | u16 config; | |
f7625980 | 1098 | |
44c10138 | 1099 | if (pdev->revision != 0x04) /* Only C0 requires this */ |
1da177e4 LT |
1100 | return; |
1101 | pci_read_config_word(pdev, 0x40, &config); | |
1102 | if (config & (1<<6)) { | |
1103 | config &= ~(1<<6); | |
1104 | pci_write_config_word(pdev, 0x40, config); | |
f0fda801 | 1105 | dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n"); |
1da177e4 LT |
1106 | } |
1107 | } | |
652c538e | 1108 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); |
e1a2a51e | 1109 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); |
1da177e4 | 1110 | |
25e742b2 | 1111 | static void quirk_amd_ide_mode(struct pci_dev *pdev) |
ab17443a | 1112 | { |
5deab536 | 1113 | /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ |
05a7d22b | 1114 | u8 tmp; |
ab17443a | 1115 | |
05a7d22b CC |
1116 | pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp); |
1117 | if (tmp == 0x01) { | |
ab17443a CH |
1118 | pci_read_config_byte(pdev, 0x40, &tmp); |
1119 | pci_write_config_byte(pdev, 0x40, tmp|1); | |
1120 | pci_write_config_byte(pdev, 0x9, 1); | |
1121 | pci_write_config_byte(pdev, 0xa, 6); | |
1122 | pci_write_config_byte(pdev, 0x40, tmp); | |
1123 | ||
c9f89475 | 1124 | pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; |
05a7d22b | 1125 | dev_info(&pdev->dev, "set SATA to AHCI mode\n"); |
ab17443a CH |
1126 | } |
1127 | } | |
05a7d22b | 1128 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); |
e1a2a51e | 1129 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); |
05a7d22b | 1130 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); |
e1a2a51e | 1131 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); |
5deab536 SH |
1132 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); |
1133 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); | |
fafe5c3d SH |
1134 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); |
1135 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); | |
ab17443a | 1136 | |
1da177e4 LT |
1137 | /* |
1138 | * Serverworks CSB5 IDE does not fully support native mode | |
1139 | */ | |
15856ad5 | 1140 | static void quirk_svwks_csb5ide(struct pci_dev *pdev) |
1da177e4 LT |
1141 | { |
1142 | u8 prog; | |
1143 | pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); | |
1144 | if (prog & 5) { | |
1145 | prog &= ~5; | |
1146 | pdev->class &= ~5; | |
1147 | pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); | |
368c73d4 | 1148 | /* PCI layer will sort out resources */ |
1da177e4 LT |
1149 | } |
1150 | } | |
652c538e | 1151 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide); |
1da177e4 LT |
1152 | |
1153 | /* | |
1154 | * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same | |
1155 | */ | |
15856ad5 | 1156 | static void quirk_ide_samemode(struct pci_dev *pdev) |
1da177e4 LT |
1157 | { |
1158 | u8 prog; | |
1159 | ||
1160 | pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); | |
1161 | ||
1162 | if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { | |
f0fda801 | 1163 | dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n"); |
1da177e4 LT |
1164 | prog &= ~5; |
1165 | pdev->class &= ~5; | |
1166 | pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); | |
1da177e4 LT |
1167 | } |
1168 | } | |
368c73d4 | 1169 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); |
1da177e4 | 1170 | |
979b1791 AC |
1171 | /* |
1172 | * Some ATA devices break if put into D3 | |
1173 | */ | |
1174 | ||
15856ad5 | 1175 | static void quirk_no_ata_d3(struct pci_dev *pdev) |
979b1791 | 1176 | { |
faa738bb | 1177 | pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; |
979b1791 | 1178 | } |
faa738bb YL |
1179 | /* Quirk the legacy ATA devices only. The AHCI ones are ok */ |
1180 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, | |
1181 | PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); | |
1182 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, | |
1183 | PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); | |
7a661c6f | 1184 | /* ALi loses some register settings that we cannot then restore */ |
faa738bb YL |
1185 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, |
1186 | PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); | |
7a661c6f AC |
1187 | /* VIA comes back fine but we need to keep it alive or ACPI GTM failures |
1188 | occur when mode detecting */ | |
faa738bb YL |
1189 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, |
1190 | PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); | |
62345399 | 1191 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SK_HYNIX, 0x1527, quirk_no_ata_d3); |
979b1791 | 1192 | |
1da177e4 LT |
1193 | /* This was originally an Alpha specific thing, but it really fits here. |
1194 | * The i82375 PCI/EISA bridge appears as non-classified. Fix that. | |
1195 | */ | |
15856ad5 | 1196 | static void quirk_eisa_bridge(struct pci_dev *dev) |
1da177e4 LT |
1197 | { |
1198 | dev->class = PCI_CLASS_BRIDGE_EISA << 8; | |
1199 | } | |
652c538e | 1200 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge); |
1da177e4 | 1201 | |
7daa0c4f | 1202 | |
1da177e4 LT |
1203 | /* |
1204 | * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge | |
1205 | * is not activated. The myth is that Asus said that they do not want the | |
1206 | * users to be irritated by just another PCI Device in the Win98 device | |
f7625980 | 1207 | * manager. (see the file prog/hotplug/README.p4b in the lm_sensors |
1da177e4 LT |
1208 | * package 2.7.0 for details) |
1209 | * | |
f7625980 BH |
1210 | * The SMBus PCI Device can be activated by setting a bit in the ICH LPC |
1211 | * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it | |
d7698edc | 1212 | * becomes necessary to do this tweak in two steps -- the chosen trigger |
1213 | * is either the Host bridge (preferred) or on-board VGA controller. | |
9208ee82 JD |
1214 | * |
1215 | * Note that we used to unhide the SMBus that way on Toshiba laptops | |
1216 | * (Satellite A40 and Tecra M2) but then found that the thermal management | |
1217 | * was done by SMM code, which could cause unsynchronized concurrent | |
1218 | * accesses to the SMBus registers, with potentially bad effects. Thus you | |
1219 | * should be very careful when adding new entries: if SMM is accessing the | |
1220 | * Intel SMBus, this is a very good reason to leave it hidden. | |
a99acc83 JD |
1221 | * |
1222 | * Likewise, many recent laptops use ACPI for thermal management. If the | |
1223 | * ACPI DSDT code accesses the SMBus, then Linux should not access it | |
1224 | * natively, and keeping the SMBus hidden is the right thing to do. If you | |
1225 | * are about to add an entry in the table below, please first disassemble | |
1226 | * the DSDT and double-check that there is no code accessing the SMBus. | |
1da177e4 | 1227 | */ |
9d24a81e | 1228 | static int asus_hides_smbus; |
1da177e4 | 1229 | |
15856ad5 | 1230 | static void asus_hides_smbus_hostbridge(struct pci_dev *dev) |
1da177e4 LT |
1231 | { |
1232 | if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { | |
1233 | if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) | |
3c78bc61 | 1234 | switch (dev->subsystem_device) { |
a00db371 | 1235 | case 0x8025: /* P4B-LX */ |
1da177e4 LT |
1236 | case 0x8070: /* P4B */ |
1237 | case 0x8088: /* P4B533 */ | |
1238 | case 0x1626: /* L3C notebook */ | |
1239 | asus_hides_smbus = 1; | |
1240 | } | |
2f2d39d2 | 1241 | else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) |
3c78bc61 | 1242 | switch (dev->subsystem_device) { |
1da177e4 LT |
1243 | case 0x80b1: /* P4GE-V */ |
1244 | case 0x80b2: /* P4PE */ | |
1245 | case 0x8093: /* P4B533-V */ | |
1246 | asus_hides_smbus = 1; | |
1247 | } | |
2f2d39d2 | 1248 | else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) |
3c78bc61 | 1249 | switch (dev->subsystem_device) { |
1da177e4 LT |
1250 | case 0x8030: /* P4T533 */ |
1251 | asus_hides_smbus = 1; | |
1252 | } | |
2f2d39d2 | 1253 | else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) |
1da177e4 LT |
1254 | switch (dev->subsystem_device) { |
1255 | case 0x8070: /* P4G8X Deluxe */ | |
1256 | asus_hides_smbus = 1; | |
1257 | } | |
2f2d39d2 | 1258 | else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) |
321311af JD |
1259 | switch (dev->subsystem_device) { |
1260 | case 0x80c9: /* PU-DLS */ | |
1261 | asus_hides_smbus = 1; | |
1262 | } | |
2f2d39d2 | 1263 | else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) |
1da177e4 LT |
1264 | switch (dev->subsystem_device) { |
1265 | case 0x1751: /* M2N notebook */ | |
1266 | case 0x1821: /* M5N notebook */ | |
4096ed0f | 1267 | case 0x1897: /* A6L notebook */ |
1da177e4 LT |
1268 | asus_hides_smbus = 1; |
1269 | } | |
2f2d39d2 | 1270 | else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) |
1da177e4 LT |
1271 | switch (dev->subsystem_device) { |
1272 | case 0x184b: /* W1N notebook */ | |
1273 | case 0x186a: /* M6Ne notebook */ | |
1274 | asus_hides_smbus = 1; | |
1275 | } | |
2f2d39d2 | 1276 | else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) |
2e45785c JD |
1277 | switch (dev->subsystem_device) { |
1278 | case 0x80f2: /* P4P800-X */ | |
1279 | asus_hides_smbus = 1; | |
1280 | } | |
2f2d39d2 | 1281 | else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) |
acc06632 RM |
1282 | switch (dev->subsystem_device) { |
1283 | case 0x1882: /* M6V notebook */ | |
2d1e1c75 | 1284 | case 0x1977: /* A6VA notebook */ |
acc06632 RM |
1285 | asus_hides_smbus = 1; |
1286 | } | |
1da177e4 LT |
1287 | } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { |
1288 | if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) | |
3c78bc61 | 1289 | switch (dev->subsystem_device) { |
1da177e4 LT |
1290 | case 0x088C: /* HP Compaq nc8000 */ |
1291 | case 0x0890: /* HP Compaq nc6000 */ | |
1292 | asus_hides_smbus = 1; | |
1293 | } | |
2f2d39d2 | 1294 | else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) |
1da177e4 LT |
1295 | switch (dev->subsystem_device) { |
1296 | case 0x12bc: /* HP D330L */ | |
e3b1bd57 | 1297 | case 0x12bd: /* HP D530 */ |
74c57428 | 1298 | case 0x006a: /* HP Compaq nx9500 */ |
1da177e4 LT |
1299 | asus_hides_smbus = 1; |
1300 | } | |
677cc644 JD |
1301 | else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) |
1302 | switch (dev->subsystem_device) { | |
1303 | case 0x12bf: /* HP xw4100 */ | |
1304 | asus_hides_smbus = 1; | |
1305 | } | |
3c78bc61 RD |
1306 | } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { |
1307 | if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) | |
1308 | switch (dev->subsystem_device) { | |
1309 | case 0xC00C: /* Samsung P35 notebook */ | |
1310 | asus_hides_smbus = 1; | |
1311 | } | |
c87f883e RIZ |
1312 | } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { |
1313 | if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) | |
3c78bc61 | 1314 | switch (dev->subsystem_device) { |
c87f883e RIZ |
1315 | case 0x0058: /* Compaq Evo N620c */ |
1316 | asus_hides_smbus = 1; | |
1317 | } | |
d7698edc | 1318 | else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) |
3c78bc61 | 1319 | switch (dev->subsystem_device) { |
d7698edc | 1320 | case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ |
1321 | /* Motherboard doesn't have Host bridge | |
1322 | * subvendor/subdevice IDs, therefore checking | |
1323 | * its on-board VGA controller */ | |
1324 | asus_hides_smbus = 1; | |
1325 | } | |
8293b0f6 | 1326 | else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) |
3c78bc61 | 1327 | switch (dev->subsystem_device) { |
10260d9a JD |
1328 | case 0x00b8: /* Compaq Evo D510 CMT */ |
1329 | case 0x00b9: /* Compaq Evo D510 SFF */ | |
6b5096e4 | 1330 | case 0x00ba: /* Compaq Evo D510 USDT */ |
8293b0f6 DS |
1331 | /* Motherboard doesn't have Host bridge |
1332 | * subvendor/subdevice IDs and on-board VGA | |
1333 | * controller is disabled if an AGP card is | |
1334 | * inserted, therefore checking USB UHCI | |
1335 | * Controller #1 */ | |
10260d9a JD |
1336 | asus_hides_smbus = 1; |
1337 | } | |
27e46859 KH |
1338 | else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) |
1339 | switch (dev->subsystem_device) { | |
1340 | case 0x001A: /* Compaq Deskpro EN SSF P667 815E */ | |
1341 | /* Motherboard doesn't have host bridge | |
1342 | * subvendor/subdevice IDs, therefore checking | |
1343 | * its on-board VGA controller */ | |
1344 | asus_hides_smbus = 1; | |
1345 | } | |
1da177e4 LT |
1346 | } |
1347 | } | |
652c538e AM |
1348 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge); |
1349 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge); | |
1350 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge); | |
1351 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge); | |
677cc644 | 1352 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge); |
652c538e AM |
1353 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge); |
1354 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge); | |
1355 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge); | |
1356 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge); | |
1357 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge); | |
1358 | ||
1359 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge); | |
8293b0f6 | 1360 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge); |
27e46859 | 1361 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge); |
d7698edc | 1362 | |
1597cacb | 1363 | static void asus_hides_smbus_lpc(struct pci_dev *dev) |
1da177e4 LT |
1364 | { |
1365 | u16 val; | |
f7625980 | 1366 | |
1da177e4 LT |
1367 | if (likely(!asus_hides_smbus)) |
1368 | return; | |
1369 | ||
1370 | pci_read_config_word(dev, 0xF2, &val); | |
1371 | if (val & 0x8) { | |
1372 | pci_write_config_word(dev, 0xF2, val & (~0x8)); | |
1373 | pci_read_config_word(dev, 0xF2, &val); | |
1374 | if (val & 0x8) | |
227f0647 RD |
1375 | dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", |
1376 | val); | |
1da177e4 | 1377 | else |
f0fda801 | 1378 | dev_info(&dev->dev, "Enabled i801 SMBus device\n"); |
1da177e4 LT |
1379 | } |
1380 | } | |
652c538e AM |
1381 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); |
1382 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); | |
1383 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); | |
1384 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); | |
1385 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); | |
1386 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); | |
1387 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); | |
e1a2a51e RW |
1388 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); |
1389 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); | |
1390 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); | |
1391 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); | |
1392 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); | |
1393 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); | |
1394 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); | |
1597cacb | 1395 | |
e1a2a51e RW |
1396 | /* It appears we just have one such device. If not, we have a warning */ |
1397 | static void __iomem *asus_rcba_base; | |
1398 | static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev) | |
acc06632 | 1399 | { |
e1a2a51e | 1400 | u32 rcba; |
acc06632 RM |
1401 | |
1402 | if (likely(!asus_hides_smbus)) | |
1403 | return; | |
e1a2a51e RW |
1404 | WARN_ON(asus_rcba_base); |
1405 | ||
acc06632 | 1406 | pci_read_config_dword(dev, 0xF0, &rcba); |
e1a2a51e RW |
1407 | /* use bits 31:14, 16 kB aligned */ |
1408 | asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); | |
1409 | if (asus_rcba_base == NULL) | |
1410 | return; | |
1411 | } | |
1412 | ||
1413 | static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev) | |
1414 | { | |
1415 | u32 val; | |
1416 | ||
1417 | if (likely(!asus_hides_smbus || !asus_rcba_base)) | |
1418 | return; | |
1419 | /* read the Function Disable register, dword mode only */ | |
1420 | val = readl(asus_rcba_base + 0x3418); | |
1421 | writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */ | |
1422 | } | |
1423 | ||
1424 | static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) | |
1425 | { | |
1426 | if (likely(!asus_hides_smbus || !asus_rcba_base)) | |
1427 | return; | |
1428 | iounmap(asus_rcba_base); | |
1429 | asus_rcba_base = NULL; | |
f0fda801 | 1430 | dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n"); |
acc06632 | 1431 | } |
e1a2a51e RW |
1432 | |
1433 | static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) | |
1434 | { | |
1435 | asus_hides_smbus_lpc_ich6_suspend(dev); | |
1436 | asus_hides_smbus_lpc_ich6_resume_early(dev); | |
1437 | asus_hides_smbus_lpc_ich6_resume(dev); | |
1438 | } | |
652c538e | 1439 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6); |
e1a2a51e RW |
1440 | DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend); |
1441 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume); | |
1442 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early); | |
ce007ea5 | 1443 | |
1da177e4 LT |
1444 | /* |
1445 | * SiS 96x south bridge: BIOS typically hides SMBus device... | |
1446 | */ | |
1597cacb | 1447 | static void quirk_sis_96x_smbus(struct pci_dev *dev) |
1da177e4 LT |
1448 | { |
1449 | u8 val = 0; | |
1da177e4 | 1450 | pci_read_config_byte(dev, 0x77, &val); |
2f5c33b3 | 1451 | if (val & 0x10) { |
f0fda801 | 1452 | dev_info(&dev->dev, "Enabling SiS 96x SMBus\n"); |
2f5c33b3 MH |
1453 | pci_write_config_byte(dev, 0x77, val & ~0x10); |
1454 | } | |
1da177e4 | 1455 | } |
652c538e AM |
1456 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); |
1457 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); | |
1458 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); | |
1459 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); | |
e1a2a51e RW |
1460 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); |
1461 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); | |
1462 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); | |
1463 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); | |
1da177e4 | 1464 | |
1da177e4 LT |
1465 | /* |
1466 | * ... This is further complicated by the fact that some SiS96x south | |
1467 | * bridges pretend to be 85C503/5513 instead. In that case see if we | |
1468 | * spotted a compatible north bridge to make sure. | |
1469 | * (pci_find_device doesn't work yet) | |
1470 | * | |
1471 | * We can also enable the sis96x bit in the discovery register.. | |
1472 | */ | |
1da177e4 LT |
1473 | #define SIS_DETECT_REGISTER 0x40 |
1474 | ||
1597cacb | 1475 | static void quirk_sis_503(struct pci_dev *dev) |
1da177e4 LT |
1476 | { |
1477 | u8 reg; | |
1478 | u16 devid; | |
1479 | ||
1480 | pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); | |
1481 | pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); | |
1482 | pci_read_config_word(dev, PCI_DEVICE_ID, &devid); | |
1483 | if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { | |
1484 | pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); | |
1485 | return; | |
1486 | } | |
1487 | ||
1da177e4 | 1488 | /* |
2f5c33b3 MH |
1489 | * Ok, it now shows up as a 96x.. run the 96x quirk by |
1490 | * hand in case it has already been processed. | |
1491 | * (depends on link order, which is apparently not guaranteed) | |
1da177e4 LT |
1492 | */ |
1493 | dev->device = devid; | |
2f5c33b3 | 1494 | quirk_sis_96x_smbus(dev); |
1da177e4 | 1495 | } |
652c538e | 1496 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); |
e1a2a51e | 1497 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); |
1da177e4 | 1498 | |
1da177e4 | 1499 | |
e5548e96 BJD |
1500 | /* |
1501 | * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller | |
1502 | * and MC97 modem controller are disabled when a second PCI soundcard is | |
1503 | * present. This patch, tweaking the VT8237 ISA bridge, enables them. | |
1504 | * -- bjd | |
1505 | */ | |
1597cacb | 1506 | static void asus_hides_ac97_lpc(struct pci_dev *dev) |
e5548e96 BJD |
1507 | { |
1508 | u8 val; | |
1509 | int asus_hides_ac97 = 0; | |
1510 | ||
1511 | if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { | |
1512 | if (dev->device == PCI_DEVICE_ID_VIA_8237) | |
1513 | asus_hides_ac97 = 1; | |
1514 | } | |
1515 | ||
1516 | if (!asus_hides_ac97) | |
1517 | return; | |
1518 | ||
1519 | pci_read_config_byte(dev, 0x50, &val); | |
1520 | if (val & 0xc0) { | |
1521 | pci_write_config_byte(dev, 0x50, val & (~0xc0)); | |
1522 | pci_read_config_byte(dev, 0x50, &val); | |
1523 | if (val & 0xc0) | |
227f0647 RD |
1524 | dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", |
1525 | val); | |
e5548e96 | 1526 | else |
f0fda801 | 1527 | dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n"); |
e5548e96 BJD |
1528 | } |
1529 | } | |
652c538e | 1530 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); |
e1a2a51e | 1531 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); |
1597cacb | 1532 | |
77967052 | 1533 | #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) |
15e0c694 AC |
1534 | |
1535 | /* | |
1536 | * If we are using libata we can drive this chip properly but must | |
1537 | * do this early on to make the additional device appear during | |
1538 | * the PCI scanning. | |
1539 | */ | |
5ee2ae7f | 1540 | static void quirk_jmicron_ata(struct pci_dev *pdev) |
15e0c694 | 1541 | { |
e34bb370 | 1542 | u32 conf1, conf5, class; |
15e0c694 AC |
1543 | u8 hdr; |
1544 | ||
1545 | /* Only poke fn 0 */ | |
1546 | if (PCI_FUNC(pdev->devfn)) | |
1547 | return; | |
1548 | ||
5ee2ae7f TH |
1549 | pci_read_config_dword(pdev, 0x40, &conf1); |
1550 | pci_read_config_dword(pdev, 0x80, &conf5); | |
15e0c694 | 1551 | |
5ee2ae7f TH |
1552 | conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ |
1553 | conf5 &= ~(1 << 24); /* Clear bit 24 */ | |
1554 | ||
1555 | switch (pdev->device) { | |
4daedcfe TH |
1556 | case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */ |
1557 | case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */ | |
5b6ae5ba | 1558 | case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */ |
5ee2ae7f TH |
1559 | /* The controller should be in single function ahci mode */ |
1560 | conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ | |
1561 | break; | |
1562 | ||
1563 | case PCI_DEVICE_ID_JMICRON_JMB365: | |
1564 | case PCI_DEVICE_ID_JMICRON_JMB366: | |
1565 | /* Redirect IDE second PATA port to the right spot */ | |
1566 | conf5 |= (1 << 24); | |
1567 | /* Fall through */ | |
1568 | case PCI_DEVICE_ID_JMICRON_JMB361: | |
1569 | case PCI_DEVICE_ID_JMICRON_JMB363: | |
5b6ae5ba | 1570 | case PCI_DEVICE_ID_JMICRON_JMB369: |
5ee2ae7f TH |
1571 | /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ |
1572 | /* Set the class codes correctly and then direct IDE 0 */ | |
3a9e3a51 | 1573 | conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ |
5ee2ae7f TH |
1574 | break; |
1575 | ||
1576 | case PCI_DEVICE_ID_JMICRON_JMB368: | |
1577 | /* The controller should be in single function IDE mode */ | |
1578 | conf1 |= 0x00C00000; /* Set 22, 23 */ | |
1579 | break; | |
15e0c694 | 1580 | } |
5ee2ae7f TH |
1581 | |
1582 | pci_write_config_dword(pdev, 0x40, conf1); | |
1583 | pci_write_config_dword(pdev, 0x80, conf5); | |
1584 | ||
1585 | /* Update pdev accordingly */ | |
1586 | pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); | |
1587 | pdev->hdr_type = hdr & 0x7f; | |
1588 | pdev->multifunction = !!(hdr & 0x80); | |
e34bb370 TH |
1589 | |
1590 | pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class); | |
1591 | pdev->class = class >> 8; | |
15e0c694 | 1592 | } |
5ee2ae7f TH |
1593 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); |
1594 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); | |
4daedcfe | 1595 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); |
5ee2ae7f | 1596 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); |
5b6ae5ba | 1597 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); |
5ee2ae7f TH |
1598 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); |
1599 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); | |
1600 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); | |
5b6ae5ba | 1601 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); |
e1a2a51e RW |
1602 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); |
1603 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); | |
4daedcfe | 1604 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); |
e1a2a51e | 1605 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); |
5b6ae5ba | 1606 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); |
e1a2a51e RW |
1607 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); |
1608 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); | |
1609 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); | |
5b6ae5ba | 1610 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); |
15e0c694 AC |
1611 | |
1612 | #endif | |
1613 | ||
91f15fb3 ZR |
1614 | static void quirk_jmicron_async_suspend(struct pci_dev *dev) |
1615 | { | |
1616 | if (dev->multifunction) { | |
1617 | device_disable_async_suspend(&dev->dev); | |
1618 | dev_info(&dev->dev, "async suspend disabled to avoid multi-function power-on ordering issue\n"); | |
1619 | } | |
1620 | } | |
1621 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend); | |
1622 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend); | |
1623 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend); | |
1624 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend); | |
1625 | ||
1da177e4 | 1626 | #ifdef CONFIG_X86_IO_APIC |
15856ad5 | 1627 | static void quirk_alder_ioapic(struct pci_dev *pdev) |
1da177e4 LT |
1628 | { |
1629 | int i; | |
1630 | ||
1631 | if ((pdev->class >> 8) != 0xff00) | |
1632 | return; | |
1633 | ||
1634 | /* the first BAR is the location of the IO APIC...we must | |
1635 | * not touch this (and it's already covered by the fixmap), so | |
1636 | * forcibly insert it into the resource tree */ | |
1637 | if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) | |
1638 | insert_resource(&iomem_resource, &pdev->resource[0]); | |
1639 | ||
1640 | /* The next five BARs all seem to be rubbish, so just clean | |
1641 | * them out */ | |
3c78bc61 | 1642 | for (i = 1; i < 6; i++) |
1da177e4 | 1643 | memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); |
1da177e4 | 1644 | } |
652c538e | 1645 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic); |
1da177e4 LT |
1646 | #endif |
1647 | ||
15856ad5 | 1648 | static void quirk_pcie_mch(struct pci_dev *pdev) |
1da177e4 | 1649 | { |
0ba379ec | 1650 | pdev->no_msi = 1; |
1da177e4 | 1651 | } |
652c538e AM |
1652 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch); |
1653 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch); | |
1654 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch); | |
1da177e4 | 1655 | |
6524723e | 1656 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch); |
4602b88d KA |
1657 | |
1658 | /* | |
1659 | * It's possible for the MSI to get corrupted if shpc and acpi | |
1660 | * are used together on certain PXH-based systems. | |
1661 | */ | |
15856ad5 | 1662 | static void quirk_pcie_pxh(struct pci_dev *dev) |
4602b88d | 1663 | { |
4602b88d | 1664 | dev->no_msi = 1; |
f0fda801 | 1665 | dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n"); |
4602b88d KA |
1666 | } |
1667 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); | |
1668 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); | |
1669 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); | |
1670 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); | |
1671 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); | |
1672 | ||
ffadcc2f KCA |
1673 | /* |
1674 | * Some Intel PCI Express chipsets have trouble with downstream | |
1675 | * device power management. | |
1676 | */ | |
3c78bc61 | 1677 | static void quirk_intel_pcie_pm(struct pci_dev *dev) |
ffadcc2f KCA |
1678 | { |
1679 | pci_pm_d3_delay = 120; | |
1680 | dev->no_d1d2 = 1; | |
1681 | } | |
1682 | ||
1683 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); | |
1684 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); | |
1685 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); | |
1686 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); | |
1687 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); | |
1688 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); | |
1689 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); | |
1690 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); | |
1691 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); | |
1692 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); | |
1693 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); | |
1694 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); | |
1695 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); | |
1696 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); | |
1697 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); | |
1698 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); | |
1699 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); | |
1700 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); | |
1701 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); | |
1702 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); | |
1703 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); | |
4602b88d | 1704 | |
5938628c BH |
1705 | static void quirk_radeon_pm(struct pci_dev *dev) |
1706 | { | |
1707 | if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE && | |
1708 | dev->subsystem_device == 0x00e2) { | |
1709 | if (dev->d3_delay < 20) { | |
1710 | dev->d3_delay = 20; | |
1711 | dev_info(&dev->dev, "extending delay after power-on from D3 to %d msec\n", | |
1712 | dev->d3_delay); | |
1713 | } | |
1714 | } | |
1715 | } | |
1716 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm); | |
1717 | ||
426b3b8d | 1718 | #ifdef CONFIG_X86_IO_APIC |
c4e649b0 SA |
1719 | static int dmi_disable_ioapicreroute(const struct dmi_system_id *d) |
1720 | { | |
1721 | noioapicreroute = 1; | |
1722 | pr_info("%s detected: disable boot interrupt reroute\n", d->ident); | |
1723 | ||
1724 | return 0; | |
1725 | } | |
1726 | ||
6faadbbb | 1727 | static const struct dmi_system_id boot_interrupt_dmi_table[] = { |
c4e649b0 SA |
1728 | /* |
1729 | * Systems to exclude from boot interrupt reroute quirks | |
1730 | */ | |
1731 | { | |
1732 | .callback = dmi_disable_ioapicreroute, | |
1733 | .ident = "ASUSTek Computer INC. M2N-LR", | |
1734 | .matches = { | |
1735 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."), | |
1736 | DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"), | |
1737 | }, | |
1738 | }, | |
1739 | {} | |
1740 | }; | |
1741 | ||
e1d3a908 SA |
1742 | /* |
1743 | * Boot interrupts on some chipsets cannot be turned off. For these chipsets, | |
1744 | * remap the original interrupt in the linux kernel to the boot interrupt, so | |
1745 | * that a PCI device's interrupt handler is installed on the boot interrupt | |
1746 | * line instead. | |
1747 | */ | |
1748 | static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev) | |
1749 | { | |
c4e649b0 | 1750 | dmi_check_system(boot_interrupt_dmi_table); |
41b9eb26 | 1751 | if (noioapicquirk || noioapicreroute) |
e1d3a908 SA |
1752 | return; |
1753 | ||
1754 | dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; | |
fdcdaf6c BH |
1755 | dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n", |
1756 | dev->vendor, dev->device); | |
e1d3a908 | 1757 | } |
88d1dce3 OD |
1758 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); |
1759 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); | |
1760 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); | |
1761 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); | |
1762 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); | |
1763 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); | |
1764 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); | |
1765 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); | |
1766 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); | |
1767 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); | |
1768 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); | |
1769 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); | |
1770 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); | |
1771 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); | |
1772 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); | |
1773 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); | |
e1d3a908 | 1774 | |
426b3b8d SA |
1775 | /* |
1776 | * On some chipsets we can disable the generation of legacy INTx boot | |
1777 | * interrupts. | |
1778 | */ | |
1779 | ||
1780 | /* | |
1781 | * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no | |
1782 | * 300641-004US, section 5.7.3. | |
1783 | */ | |
1784 | #define INTEL_6300_IOAPIC_ABAR 0x40 | |
1785 | #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14) | |
1786 | ||
1787 | static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev) | |
1788 | { | |
1789 | u16 pci_config_word; | |
1790 | ||
1791 | if (noioapicquirk) | |
1792 | return; | |
1793 | ||
1794 | pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word); | |
1795 | pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ; | |
1796 | pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word); | |
1797 | ||
fdcdaf6c BH |
1798 | dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", |
1799 | dev->vendor, dev->device); | |
426b3b8d | 1800 | } |
f7625980 BH |
1801 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); |
1802 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); | |
77251188 OD |
1803 | |
1804 | /* | |
1805 | * disable boot interrupts on HT-1000 | |
1806 | */ | |
1807 | #define BC_HT1000_FEATURE_REG 0x64 | |
1808 | #define BC_HT1000_PIC_REGS_ENABLE (1<<0) | |
1809 | #define BC_HT1000_MAP_IDX 0xC00 | |
1810 | #define BC_HT1000_MAP_DATA 0xC01 | |
1811 | ||
1812 | static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev) | |
1813 | { | |
1814 | u32 pci_config_dword; | |
1815 | u8 irq; | |
1816 | ||
1817 | if (noioapicquirk) | |
1818 | return; | |
1819 | ||
1820 | pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword); | |
1821 | pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword | | |
1822 | BC_HT1000_PIC_REGS_ENABLE); | |
1823 | ||
1824 | for (irq = 0x10; irq < 0x10 + 32; irq++) { | |
1825 | outb(irq, BC_HT1000_MAP_IDX); | |
1826 | outb(0x00, BC_HT1000_MAP_DATA); | |
1827 | } | |
1828 | ||
1829 | pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword); | |
1830 | ||
fdcdaf6c BH |
1831 | dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", |
1832 | dev->vendor, dev->device); | |
77251188 | 1833 | } |
f7625980 BH |
1834 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); |
1835 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); | |
542622da OD |
1836 | |
1837 | /* | |
1838 | * disable boot interrupts on AMD and ATI chipsets | |
1839 | */ | |
1840 | /* | |
1841 | * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131 | |
1842 | * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode | |
1843 | * (due to an erratum). | |
1844 | */ | |
1845 | #define AMD_813X_MISC 0x40 | |
1846 | #define AMD_813X_NOIOAMODE (1<<0) | |
4fd8bdc5 | 1847 | #define AMD_813X_REV_B1 0x12 |
bbe19443 | 1848 | #define AMD_813X_REV_B2 0x13 |
542622da OD |
1849 | |
1850 | static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev) | |
1851 | { | |
1852 | u32 pci_config_dword; | |
1853 | ||
1854 | if (noioapicquirk) | |
1855 | return; | |
4fd8bdc5 SA |
1856 | if ((dev->revision == AMD_813X_REV_B1) || |
1857 | (dev->revision == AMD_813X_REV_B2)) | |
bbe19443 | 1858 | return; |
542622da OD |
1859 | |
1860 | pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword); | |
1861 | pci_config_dword &= ~AMD_813X_NOIOAMODE; | |
1862 | pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword); | |
1863 | ||
fdcdaf6c BH |
1864 | dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", |
1865 | dev->vendor, dev->device); | |
542622da | 1866 | } |
4fd8bdc5 SA |
1867 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); |
1868 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); | |
1869 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); | |
1870 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); | |
542622da OD |
1871 | |
1872 | #define AMD_8111_PCI_IRQ_ROUTING 0x56 | |
1873 | ||
1874 | static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev) | |
1875 | { | |
1876 | u16 pci_config_word; | |
1877 | ||
1878 | if (noioapicquirk) | |
1879 | return; | |
1880 | ||
1881 | pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word); | |
1882 | if (!pci_config_word) { | |
227f0647 RD |
1883 | dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] already disabled\n", |
1884 | dev->vendor, dev->device); | |
542622da OD |
1885 | return; |
1886 | } | |
1887 | pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); | |
fdcdaf6c BH |
1888 | dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", |
1889 | dev->vendor, dev->device); | |
542622da | 1890 | } |
f7625980 BH |
1891 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); |
1892 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); | |
426b3b8d SA |
1893 | #endif /* CONFIG_X86_IO_APIC */ |
1894 | ||
33dced2e SS |
1895 | /* |
1896 | * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size | |
1897 | * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. | |
1898 | * Re-allocate the region if needed... | |
1899 | */ | |
15856ad5 | 1900 | static void quirk_tc86c001_ide(struct pci_dev *dev) |
33dced2e SS |
1901 | { |
1902 | struct resource *r = &dev->resource[0]; | |
1903 | ||
1904 | if (r->start & 0x8) { | |
bd064f0a | 1905 | r->flags |= IORESOURCE_UNSET; |
33dced2e SS |
1906 | r->start = 0; |
1907 | r->end = 0xf; | |
1908 | } | |
1909 | } | |
1910 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2, | |
1911 | PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE, | |
1912 | quirk_tc86c001_ide); | |
1913 | ||
21c5fd97 IA |
1914 | /* |
1915 | * PLX PCI 9050 PCI Target bridge controller has an errata that prevents the | |
1916 | * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o) | |
1917 | * being read correctly if bit 7 of the base address is set. | |
1918 | * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128). | |
1919 | * Re-allocate the regions to a 256-byte boundary if necessary. | |
1920 | */ | |
193c0d68 | 1921 | static void quirk_plx_pci9050(struct pci_dev *dev) |
21c5fd97 IA |
1922 | { |
1923 | unsigned int bar; | |
1924 | ||
1925 | /* Fixed in revision 2 (PCI 9052). */ | |
1926 | if (dev->revision >= 2) | |
1927 | return; | |
1928 | for (bar = 0; bar <= 1; bar++) | |
1929 | if (pci_resource_len(dev, bar) == 0x80 && | |
1930 | (pci_resource_start(dev, bar) & 0x80)) { | |
1931 | struct resource *r = &dev->resource[bar]; | |
227f0647 | 1932 | dev_info(&dev->dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n", |
21c5fd97 | 1933 | bar); |
bd064f0a | 1934 | r->flags |= IORESOURCE_UNSET; |
21c5fd97 IA |
1935 | r->start = 0; |
1936 | r->end = 0xff; | |
1937 | } | |
1938 | } | |
1939 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | |
1940 | quirk_plx_pci9050); | |
2794bb28 IA |
1941 | /* |
1942 | * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others) | |
1943 | * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b, | |
1944 | * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c, | |
1945 | * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b. | |
1946 | * | |
1947 | * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq" | |
1948 | * driver. | |
1949 | */ | |
1950 | DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050); | |
1951 | DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050); | |
21c5fd97 | 1952 | |
15856ad5 | 1953 | static void quirk_netmos(struct pci_dev *dev) |
1da177e4 LT |
1954 | { |
1955 | unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; | |
1956 | unsigned int num_serial = dev->subsystem_device & 0xf; | |
1957 | ||
1958 | /* | |
1959 | * These Netmos parts are multiport serial devices with optional | |
1960 | * parallel ports. Even when parallel ports are present, they | |
1961 | * are identified as class SERIAL, which means the serial driver | |
1962 | * will claim them. To prevent this, mark them as class OTHER. | |
1963 | * These combo devices should be claimed by parport_serial. | |
1964 | * | |
1965 | * The subdevice ID is of the form 0x00PS, where <P> is the number | |
1966 | * of parallel ports and <S> is the number of serial ports. | |
1967 | */ | |
1968 | switch (dev->device) { | |
4c9c1686 JS |
1969 | case PCI_DEVICE_ID_NETMOS_9835: |
1970 | /* Well, this rule doesn't hold for the following 9835 device */ | |
1971 | if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && | |
1972 | dev->subsystem_device == 0x0299) | |
1973 | return; | |
1da177e4 LT |
1974 | case PCI_DEVICE_ID_NETMOS_9735: |
1975 | case PCI_DEVICE_ID_NETMOS_9745: | |
1da177e4 LT |
1976 | case PCI_DEVICE_ID_NETMOS_9845: |
1977 | case PCI_DEVICE_ID_NETMOS_9855: | |
08803efe | 1978 | if (num_parallel) { |
227f0647 | 1979 | dev_info(&dev->dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n", |
1da177e4 LT |
1980 | dev->device, num_parallel, num_serial); |
1981 | dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | | |
1982 | (dev->class & 0xff); | |
1983 | } | |
1984 | } | |
1985 | } | |
08803efe YL |
1986 | DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, |
1987 | PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos); | |
1da177e4 | 1988 | |
da2d03ea AW |
1989 | /* |
1990 | * Quirk non-zero PCI functions to route VPD access through function 0 for | |
1991 | * devices that share VPD resources between functions. The functions are | |
1992 | * expected to be identical devices. | |
1993 | */ | |
7aa6ca4d MR |
1994 | static void quirk_f0_vpd_link(struct pci_dev *dev) |
1995 | { | |
da2d03ea AW |
1996 | struct pci_dev *f0; |
1997 | ||
1998 | if (!PCI_FUNC(dev->devfn)) | |
7aa6ca4d | 1999 | return; |
da2d03ea AW |
2000 | |
2001 | f0 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0)); | |
2002 | if (!f0) | |
2003 | return; | |
2004 | ||
2005 | if (f0->vpd && dev->class == f0->class && | |
2006 | dev->vendor == f0->vendor && dev->device == f0->device) | |
2007 | dev->dev_flags |= PCI_DEV_FLAGS_VPD_REF_F0; | |
2008 | ||
2009 | pci_dev_put(f0); | |
7aa6ca4d MR |
2010 | } |
2011 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, | |
2012 | PCI_CLASS_NETWORK_ETHERNET, 8, quirk_f0_vpd_link); | |
2013 | ||
15856ad5 | 2014 | static void quirk_e100_interrupt(struct pci_dev *dev) |
16a74744 | 2015 | { |
e64aeccb | 2016 | u16 command, pmcsr; |
16a74744 BH |
2017 | u8 __iomem *csr; |
2018 | u8 cmd_hi; | |
2019 | ||
2020 | switch (dev->device) { | |
2021 | /* PCI IDs taken from drivers/net/e100.c */ | |
2022 | case 0x1029: | |
2023 | case 0x1030 ... 0x1034: | |
2024 | case 0x1038 ... 0x103E: | |
2025 | case 0x1050 ... 0x1057: | |
2026 | case 0x1059: | |
2027 | case 0x1064 ... 0x106B: | |
2028 | case 0x1091 ... 0x1095: | |
2029 | case 0x1209: | |
2030 | case 0x1229: | |
2031 | case 0x2449: | |
2032 | case 0x2459: | |
2033 | case 0x245D: | |
2034 | case 0x27DC: | |
2035 | break; | |
2036 | default: | |
2037 | return; | |
2038 | } | |
2039 | ||
2040 | /* | |
2041 | * Some firmware hands off the e100 with interrupts enabled, | |
2042 | * which can cause a flood of interrupts if packets are | |
2043 | * received before the driver attaches to the device. So | |
2044 | * disable all e100 interrupts here. The driver will | |
2045 | * re-enable them when it's ready. | |
2046 | */ | |
2047 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
16a74744 | 2048 | |
1bef7dc0 | 2049 | if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) |
16a74744 BH |
2050 | return; |
2051 | ||
e64aeccb IK |
2052 | /* |
2053 | * Check that the device is in the D0 power state. If it's not, | |
2054 | * there is no point to look any further. | |
2055 | */ | |
728cdb75 YW |
2056 | if (dev->pm_cap) { |
2057 | pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); | |
e64aeccb IK |
2058 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) |
2059 | return; | |
2060 | } | |
2061 | ||
1bef7dc0 BH |
2062 | /* Convert from PCI bus to resource space. */ |
2063 | csr = ioremap(pci_resource_start(dev, 0), 8); | |
16a74744 | 2064 | if (!csr) { |
f0fda801 | 2065 | dev_warn(&dev->dev, "Can't map e100 registers\n"); |
16a74744 BH |
2066 | return; |
2067 | } | |
2068 | ||
2069 | cmd_hi = readb(csr + 3); | |
2070 | if (cmd_hi == 0) { | |
227f0647 | 2071 | dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; disabling\n"); |
16a74744 BH |
2072 | writeb(1, csr + 3); |
2073 | } | |
2074 | ||
2075 | iounmap(csr); | |
2076 | } | |
4c5b28e2 YL |
2077 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, |
2078 | PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt); | |
a5312e28 | 2079 | |
649426ef AD |
2080 | /* |
2081 | * The 82575 and 82598 may experience data corruption issues when transitioning | |
96291d56 | 2082 | * out of L0S. To prevent this we need to disable L0S on the PCIe link. |
649426ef | 2083 | */ |
15856ad5 | 2084 | static void quirk_disable_aspm_l0s(struct pci_dev *dev) |
649426ef AD |
2085 | { |
2086 | dev_info(&dev->dev, "Disabling L0s\n"); | |
2087 | pci_disable_link_state(dev, PCIE_LINK_STATE_L0S); | |
2088 | } | |
2089 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s); | |
2090 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s); | |
2091 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s); | |
2092 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s); | |
2093 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s); | |
2094 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s); | |
2095 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s); | |
2096 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s); | |
2097 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s); | |
2098 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s); | |
2099 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s); | |
2100 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s); | |
2101 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s); | |
2102 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s); | |
2103 | ||
15856ad5 | 2104 | static void fixup_rev1_53c810(struct pci_dev *dev) |
a5312e28 | 2105 | { |
e6323e3c BH |
2106 | u32 class = dev->class; |
2107 | ||
2108 | /* | |
2109 | * rev 1 ncr53c810 chips don't set the class at all which means | |
a5312e28 IK |
2110 | * they don't get their resources remapped. Fix that here. |
2111 | */ | |
e6323e3c BH |
2112 | if (class) |
2113 | return; | |
a5312e28 | 2114 | |
e6323e3c BH |
2115 | dev->class = PCI_CLASS_STORAGE_SCSI << 8; |
2116 | dev_info(&dev->dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n", | |
2117 | class, dev->class); | |
a5312e28 IK |
2118 | } |
2119 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); | |
2120 | ||
9d265124 | 2121 | /* Enable 1k I/O space granularity on the Intel P64H2 */ |
15856ad5 | 2122 | static void quirk_p64h2_1k_io(struct pci_dev *dev) |
9d265124 DY |
2123 | { |
2124 | u16 en1k; | |
9d265124 DY |
2125 | |
2126 | pci_read_config_word(dev, 0x40, &en1k); | |
2127 | ||
2128 | if (en1k & 0x200) { | |
f0fda801 | 2129 | dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n"); |
2b28ae19 | 2130 | dev->io_window_1k = 1; |
9d265124 DY |
2131 | } |
2132 | } | |
2133 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); | |
2134 | ||
cf34a8e0 BG |
2135 | /* Under some circumstances, AER is not linked with extended capabilities. |
2136 | * Force it to be linked by setting the corresponding control bit in the | |
2137 | * config space. | |
2138 | */ | |
1597cacb | 2139 | static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) |
cf34a8e0 BG |
2140 | { |
2141 | uint8_t b; | |
2142 | if (pci_read_config_byte(dev, 0xf41, &b) == 0) { | |
2143 | if (!(b & 0x20)) { | |
2144 | pci_write_config_byte(dev, 0xf41, b | 0x20); | |
227f0647 | 2145 | dev_info(&dev->dev, "Linking AER extended capability\n"); |
cf34a8e0 BG |
2146 | } |
2147 | } | |
2148 | } | |
2149 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, | |
2150 | quirk_nvidia_ck804_pcie_aer_ext_cap); | |
e1a2a51e | 2151 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, |
1597cacb | 2152 | quirk_nvidia_ck804_pcie_aer_ext_cap); |
cf34a8e0 | 2153 | |
15856ad5 | 2154 | static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) |
53a9bf42 TY |
2155 | { |
2156 | /* | |
2157 | * Disable PCI Bus Parking and PCI Master read caching on CX700 | |
2158 | * which causes unspecified timing errors with a VT6212L on the PCI | |
ca846392 TY |
2159 | * bus leading to USB2.0 packet loss. |
2160 | * | |
2161 | * This quirk is only enabled if a second (on the external PCI bus) | |
2162 | * VT6212L is found -- the CX700 core itself also contains a USB | |
2163 | * host controller with the same PCI ID as the VT6212L. | |
53a9bf42 TY |
2164 | */ |
2165 | ||
ca846392 TY |
2166 | /* Count VT6212L instances */ |
2167 | struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA, | |
2168 | PCI_DEVICE_ID_VIA_8235_USB_2, NULL); | |
53a9bf42 | 2169 | uint8_t b; |
ca846392 TY |
2170 | |
2171 | /* p should contain the first (internal) VT6212L -- see if we have | |
2172 | an external one by searching again */ | |
2173 | p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p); | |
2174 | if (!p) | |
2175 | return; | |
2176 | pci_dev_put(p); | |
2177 | ||
53a9bf42 TY |
2178 | if (pci_read_config_byte(dev, 0x76, &b) == 0) { |
2179 | if (b & 0x40) { | |
2180 | /* Turn off PCI Bus Parking */ | |
2181 | pci_write_config_byte(dev, 0x76, b ^ 0x40); | |
2182 | ||
227f0647 | 2183 | dev_info(&dev->dev, "Disabling VIA CX700 PCI parking\n"); |
bc043274 TY |
2184 | } |
2185 | } | |
2186 | ||
2187 | if (pci_read_config_byte(dev, 0x72, &b) == 0) { | |
2188 | if (b != 0) { | |
53a9bf42 TY |
2189 | /* Turn off PCI Master read caching */ |
2190 | pci_write_config_byte(dev, 0x72, 0x0); | |
bc043274 TY |
2191 | |
2192 | /* Set PCI Master Bus time-out to "1x16 PCLK" */ | |
53a9bf42 | 2193 | pci_write_config_byte(dev, 0x75, 0x1); |
bc043274 TY |
2194 | |
2195 | /* Disable "Read FIFO Timer" */ | |
53a9bf42 TY |
2196 | pci_write_config_byte(dev, 0x77, 0x0); |
2197 | ||
227f0647 | 2198 | dev_info(&dev->dev, "Disabling VIA CX700 PCI caching\n"); |
53a9bf42 TY |
2199 | } |
2200 | } | |
2201 | } | |
ca846392 | 2202 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching); |
53a9bf42 | 2203 | |
7c20078a BM |
2204 | /* |
2205 | * If a device follows the VPD format spec, the PCI core will not read or | |
2206 | * write past the VPD End Tag. But some vendors do not follow the VPD | |
2207 | * format spec, so we can't tell how much data is safe to access. Devices | |
2208 | * may behave unpredictably if we access too much. Blacklist these devices | |
2209 | * so we don't touch VPD at all. | |
2210 | */ | |
2211 | static void quirk_blacklist_vpd(struct pci_dev *dev) | |
2212 | { | |
2213 | if (dev->vpd) { | |
2214 | dev->vpd->len = 0; | |
044bc425 | 2215 | dev_warn(&dev->dev, FW_BUG "disabling VPD access (can't determine size of non-standard VPD format)\n"); |
7c20078a BM |
2216 | } |
2217 | } | |
2218 | ||
2219 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0060, quirk_blacklist_vpd); | |
2220 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x007c, quirk_blacklist_vpd); | |
2221 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0413, quirk_blacklist_vpd); | |
2222 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0078, quirk_blacklist_vpd); | |
2223 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0079, quirk_blacklist_vpd); | |
2224 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0073, quirk_blacklist_vpd); | |
2225 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0071, quirk_blacklist_vpd); | |
2226 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005b, quirk_blacklist_vpd); | |
2227 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x002f, quirk_blacklist_vpd); | |
2228 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005d, quirk_blacklist_vpd); | |
2229 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005f, quirk_blacklist_vpd); | |
2230 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, PCI_ANY_ID, | |
2231 | quirk_blacklist_vpd); | |
0d5370d1 | 2232 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_QLOGIC, 0x2261, quirk_blacklist_vpd); |
7c20078a | 2233 | |
99cb233d BL |
2234 | /* |
2235 | * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the | |
2236 | * VPD end tag will hang the device. This problem was initially | |
2237 | * observed when a vpd entry was created in sysfs | |
2238 | * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry | |
2239 | * will dump 32k of data. Reading a full 32k will cause an access | |
2240 | * beyond the VPD end tag causing the device to hang. Once the device | |
2241 | * is hung, the bnx2 driver will not be able to reset the device. | |
2242 | * We believe that it is legal to read beyond the end tag and | |
2243 | * therefore the solution is to limit the read/write length. | |
2244 | */ | |
15856ad5 | 2245 | static void quirk_brcm_570x_limit_vpd(struct pci_dev *dev) |
99cb233d | 2246 | { |
9d82d8ea | 2247 | /* |
35405f25 DH |
2248 | * Only disable the VPD capability for 5706, 5706S, 5708, |
2249 | * 5708S and 5709 rev. A | |
9d82d8ea | 2250 | */ |
99cb233d | 2251 | if ((dev->device == PCI_DEVICE_ID_NX2_5706) || |
35405f25 | 2252 | (dev->device == PCI_DEVICE_ID_NX2_5706S) || |
99cb233d | 2253 | (dev->device == PCI_DEVICE_ID_NX2_5708) || |
9d82d8ea | 2254 | (dev->device == PCI_DEVICE_ID_NX2_5708S) || |
99cb233d BL |
2255 | ((dev->device == PCI_DEVICE_ID_NX2_5709) && |
2256 | (dev->revision & 0xf0) == 0x0)) { | |
2257 | if (dev->vpd) | |
2258 | dev->vpd->len = 0x80; | |
2259 | } | |
2260 | } | |
2261 | ||
bffadffd YZ |
2262 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, |
2263 | PCI_DEVICE_ID_NX2_5706, | |
2264 | quirk_brcm_570x_limit_vpd); | |
2265 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
2266 | PCI_DEVICE_ID_NX2_5706S, | |
2267 | quirk_brcm_570x_limit_vpd); | |
2268 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
2269 | PCI_DEVICE_ID_NX2_5708, | |
2270 | quirk_brcm_570x_limit_vpd); | |
2271 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
2272 | PCI_DEVICE_ID_NX2_5708S, | |
2273 | quirk_brcm_570x_limit_vpd); | |
2274 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
2275 | PCI_DEVICE_ID_NX2_5709, | |
2276 | quirk_brcm_570x_limit_vpd); | |
2277 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
2278 | PCI_DEVICE_ID_NX2_5709S, | |
2279 | quirk_brcm_570x_limit_vpd); | |
99cb233d | 2280 | |
25e742b2 | 2281 | static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev) |
0b471506 MC |
2282 | { |
2283 | u32 rev; | |
2284 | ||
2285 | pci_read_config_dword(dev, 0xf4, &rev); | |
2286 | ||
2287 | /* Only CAP the MRRS if the device is a 5719 A0 */ | |
2288 | if (rev == 0x05719000) { | |
2289 | int readrq = pcie_get_readrq(dev); | |
2290 | if (readrq > 2048) | |
2291 | pcie_set_readrq(dev, 2048); | |
2292 | } | |
2293 | } | |
2294 | ||
2295 | DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM, | |
2296 | PCI_DEVICE_ID_TIGON3_5719, | |
2297 | quirk_brcm_5719_limit_mrrs); | |
2298 | ||
ce709f86 JM |
2299 | #ifdef CONFIG_PCIE_IPROC_PLATFORM |
2300 | static void quirk_paxc_bridge(struct pci_dev *pdev) | |
2301 | { | |
2302 | /* The PCI config space is shared with the PAXC root port and the first | |
2303 | * Ethernet device. So, we need to workaround this by telling the PCI | |
2304 | * code that the bridge is not an Ethernet device. | |
2305 | */ | |
2306 | if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) | |
2307 | pdev->class = PCI_CLASS_BRIDGE_PCI << 8; | |
2308 | ||
2309 | /* MPSS is not being set properly (as it is currently 0). This is | |
2310 | * because that area of the PCI config space is hard coded to zero, and | |
2311 | * is not modifiable by firmware. Set this to 2 (e.g., 512 byte MPS) | |
2312 | * so that the MPS can be set to the real max value. | |
2313 | */ | |
2314 | pdev->pcie_mpss = 2; | |
2315 | } | |
2316 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16cd, quirk_paxc_bridge); | |
2317 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0, quirk_paxc_bridge); | |
2318 | #endif | |
2319 | ||
26c56dc0 MM |
2320 | /* Originally in EDAC sources for i82875P: |
2321 | * Intel tells BIOS developers to hide device 6 which | |
2322 | * configures the overflow device access containing | |
2323 | * the DRBs - this is where we expose device 6. | |
2324 | * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm | |
2325 | */ | |
15856ad5 | 2326 | static void quirk_unhide_mch_dev6(struct pci_dev *dev) |
26c56dc0 MM |
2327 | { |
2328 | u8 reg; | |
2329 | ||
2330 | if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { | |
2331 | dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n"); | |
2332 | pci_write_config_byte(dev, 0xF4, reg | 0x02); | |
2333 | } | |
2334 | } | |
2335 | ||
2336 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, | |
2337 | quirk_unhide_mch_dev6); | |
2338 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, | |
2339 | quirk_unhide_mch_dev6); | |
2340 | ||
12962267 | 2341 | #ifdef CONFIG_TILEPRO |
f02cbbe6 | 2342 | /* |
12962267 | 2343 | * The Tilera TILEmpower tilepro platform needs to set the link speed |
f02cbbe6 CM |
2344 | * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed |
2345 | * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe | |
2346 | * capability register of the PEX8624 PCIe switch. The switch | |
2347 | * supports link speed auto negotiation, but falsely sets | |
2348 | * the link speed to 5GT/s. | |
2349 | */ | |
15856ad5 | 2350 | static void quirk_tile_plx_gen1(struct pci_dev *dev) |
f02cbbe6 CM |
2351 | { |
2352 | if (tile_plx_gen1) { | |
2353 | pci_write_config_dword(dev, 0x98, 0x1); | |
2354 | mdelay(50); | |
2355 | } | |
2356 | } | |
2357 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1); | |
12962267 | 2358 | #endif /* CONFIG_TILEPRO */ |
26c56dc0 | 2359 | |
3f79e107 | 2360 | #ifdef CONFIG_PCI_MSI |
ebdf7d39 TH |
2361 | /* Some chipsets do not support MSI. We cannot easily rely on setting |
2362 | * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually | |
f7625980 BH |
2363 | * some other buses controlled by the chipset even if Linux is not |
2364 | * aware of it. Instead of setting the flag on all buses in the | |
ebdf7d39 | 2365 | * machine, simply disable MSI globally. |
3f79e107 | 2366 | */ |
15856ad5 | 2367 | static void quirk_disable_all_msi(struct pci_dev *dev) |
3f79e107 | 2368 | { |
88187dfa | 2369 | pci_no_msi(); |
f0fda801 | 2370 | dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n"); |
3f79e107 | 2371 | } |
ebdf7d39 TH |
2372 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); |
2373 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); | |
2374 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi); | |
66d715c9 | 2375 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi); |
184b812f | 2376 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi); |
162dedd3 | 2377 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi); |
549e1561 | 2378 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi); |
10b4ad1a | 2379 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi); |
3f79e107 BG |
2380 | |
2381 | /* Disable MSI on chipsets that are known to not support it */ | |
15856ad5 | 2382 | static void quirk_disable_msi(struct pci_dev *dev) |
3f79e107 BG |
2383 | { |
2384 | if (dev->subordinate) { | |
227f0647 | 2385 | dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n"); |
3f79e107 BG |
2386 | dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; |
2387 | } | |
2388 | } | |
2389 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); | |
134b3450 | 2390 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi); |
9313ff45 | 2391 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi); |
6397c75c | 2392 | |
aff61369 CL |
2393 | /* |
2394 | * The APC bridge device in AMD 780 family northbridges has some random | |
2395 | * OEM subsystem ID in its vendor ID register (erratum 18), so instead | |
2396 | * we use the possible vendor/device IDs of the host bridge for the | |
2397 | * declared quirk, and search for the APC bridge by slot number. | |
2398 | */ | |
15856ad5 | 2399 | static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge) |
aff61369 CL |
2400 | { |
2401 | struct pci_dev *apc_bridge; | |
2402 | ||
2403 | apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); | |
2404 | if (apc_bridge) { | |
2405 | if (apc_bridge->device == 0x9602) | |
2406 | quirk_disable_msi(apc_bridge); | |
2407 | pci_dev_put(apc_bridge); | |
2408 | } | |
2409 | } | |
2410 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi); | |
2411 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi); | |
2412 | ||
6397c75c BG |
2413 | /* Go through the list of Hypertransport capabilities and |
2414 | * return 1 if a HT MSI capability is found and enabled */ | |
25e742b2 | 2415 | static int msi_ht_cap_enabled(struct pci_dev *dev) |
6397c75c | 2416 | { |
fff905f3 | 2417 | int pos, ttl = PCI_FIND_CAP_TTL; |
7a380507 ME |
2418 | |
2419 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); | |
2420 | while (pos && ttl--) { | |
2421 | u8 flags; | |
2422 | ||
2423 | if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, | |
3c78bc61 | 2424 | &flags) == 0) { |
f0fda801 | 2425 | dev_info(&dev->dev, "Found %s HT MSI Mapping\n", |
7a380507 | 2426 | flags & HT_MSI_FLAGS_ENABLE ? |
f0fda801 | 2427 | "enabled" : "disabled"); |
7a380507 | 2428 | return (flags & HT_MSI_FLAGS_ENABLE) != 0; |
6397c75c | 2429 | } |
7a380507 ME |
2430 | |
2431 | pos = pci_find_next_ht_capability(dev, pos, | |
2432 | HT_CAPTYPE_MSI_MAPPING); | |
6397c75c BG |
2433 | } |
2434 | return 0; | |
2435 | } | |
2436 | ||
2437 | /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */ | |
25e742b2 | 2438 | static void quirk_msi_ht_cap(struct pci_dev *dev) |
6397c75c BG |
2439 | { |
2440 | if (dev->subordinate && !msi_ht_cap_enabled(dev)) { | |
227f0647 | 2441 | dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n"); |
6397c75c BG |
2442 | dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; |
2443 | } | |
2444 | } | |
2445 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, | |
2446 | quirk_msi_ht_cap); | |
6bae1d96 | 2447 | |
6397c75c BG |
2448 | /* The nVidia CK804 chipset may have 2 HT MSI mappings. |
2449 | * MSI are supported if the MSI capability set in any of these mappings. | |
2450 | */ | |
25e742b2 | 2451 | static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) |
6397c75c BG |
2452 | { |
2453 | struct pci_dev *pdev; | |
2454 | ||
2455 | if (!dev->subordinate) | |
2456 | return; | |
2457 | ||
2458 | /* check HT MSI cap on this chipset and the root one. | |
2459 | * a single one having MSI is enough to be sure that MSI are supported. | |
2460 | */ | |
11f242f0 | 2461 | pdev = pci_get_slot(dev->bus, 0); |
9ac0ce85 JJ |
2462 | if (!pdev) |
2463 | return; | |
0c875c28 | 2464 | if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) { |
227f0647 | 2465 | dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n"); |
6397c75c BG |
2466 | dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; |
2467 | } | |
11f242f0 | 2468 | pci_dev_put(pdev); |
6397c75c BG |
2469 | } |
2470 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, | |
2471 | quirk_nvidia_ck804_msi_ht_cap); | |
ba698ad4 | 2472 | |
415b6d0e | 2473 | /* Force enable MSI mapping capability on HT bridges */ |
25e742b2 | 2474 | static void ht_enable_msi_mapping(struct pci_dev *dev) |
9dc625e7 | 2475 | { |
fff905f3 | 2476 | int pos, ttl = PCI_FIND_CAP_TTL; |
9dc625e7 PC |
2477 | |
2478 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); | |
2479 | while (pos && ttl--) { | |
2480 | u8 flags; | |
2481 | ||
2482 | if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, | |
2483 | &flags) == 0) { | |
2484 | dev_info(&dev->dev, "Enabling HT MSI Mapping\n"); | |
2485 | ||
2486 | pci_write_config_byte(dev, pos + HT_MSI_FLAGS, | |
2487 | flags | HT_MSI_FLAGS_ENABLE); | |
2488 | } | |
2489 | pos = pci_find_next_ht_capability(dev, pos, | |
2490 | HT_CAPTYPE_MSI_MAPPING); | |
2491 | } | |
2492 | } | |
415b6d0e BH |
2493 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, |
2494 | PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, | |
2495 | ht_enable_msi_mapping); | |
9dc625e7 | 2496 | |
e0ae4f55 YL |
2497 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, |
2498 | ht_enable_msi_mapping); | |
2499 | ||
e4146bb9 | 2500 | /* The P5N32-SLI motherboards from Asus have a problem with msi |
75e07fc3 AP |
2501 | * for the MCP55 NIC. It is not yet determined whether the msi problem |
2502 | * also affects other devices. As for now, turn off msi for this device. | |
2503 | */ | |
15856ad5 | 2504 | static void nvenet_msi_disable(struct pci_dev *dev) |
75e07fc3 | 2505 | { |
9251bac9 JD |
2506 | const char *board_name = dmi_get_system_info(DMI_BOARD_NAME); |
2507 | ||
2508 | if (board_name && | |
2509 | (strstr(board_name, "P5N32-SLI PREMIUM") || | |
2510 | strstr(board_name, "P5N32-E SLI"))) { | |
227f0647 | 2511 | dev_info(&dev->dev, "Disabling msi for MCP55 NIC on P5N32-SLI\n"); |
75e07fc3 AP |
2512 | dev->no_msi = 1; |
2513 | } | |
2514 | } | |
2515 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, | |
2516 | PCI_DEVICE_ID_NVIDIA_NVENET_15, | |
2517 | nvenet_msi_disable); | |
2518 | ||
66db60ea | 2519 | /* |
f7625980 BH |
2520 | * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing |
2521 | * config register. This register controls the routing of legacy | |
2522 | * interrupts from devices that route through the MCP55. If this register | |
2523 | * is misprogrammed, interrupts are only sent to the BSP, unlike | |
2524 | * conventional systems where the IRQ is broadcast to all online CPUs. Not | |
2525 | * having this register set properly prevents kdump from booting up | |
2526 | * properly, so let's make sure that we have it set correctly. | |
2527 | * Note that this is an undocumented register. | |
66db60ea | 2528 | */ |
15856ad5 | 2529 | static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev) |
66db60ea NH |
2530 | { |
2531 | u32 cfg; | |
2532 | ||
49c2fa08 NH |
2533 | if (!pci_find_capability(dev, PCI_CAP_ID_HT)) |
2534 | return; | |
2535 | ||
66db60ea NH |
2536 | pci_read_config_dword(dev, 0x74, &cfg); |
2537 | ||
2538 | if (cfg & ((1 << 2) | (1 << 15))) { | |
2539 | printk(KERN_INFO "Rewriting irq routing register on MCP55\n"); | |
2540 | cfg &= ~((1 << 2) | (1 << 15)); | |
2541 | pci_write_config_dword(dev, 0x74, cfg); | |
2542 | } | |
2543 | } | |
2544 | ||
2545 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, | |
2546 | PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0, | |
2547 | nvbridge_check_legacy_irq_routing); | |
2548 | ||
2549 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, | |
2550 | PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4, | |
2551 | nvbridge_check_legacy_irq_routing); | |
2552 | ||
25e742b2 | 2553 | static int ht_check_msi_mapping(struct pci_dev *dev) |
de745306 | 2554 | { |
fff905f3 | 2555 | int pos, ttl = PCI_FIND_CAP_TTL; |
de745306 YL |
2556 | int found = 0; |
2557 | ||
2558 | /* check if there is HT MSI cap or enabled on this device */ | |
2559 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); | |
2560 | while (pos && ttl--) { | |
2561 | u8 flags; | |
2562 | ||
2563 | if (found < 1) | |
2564 | found = 1; | |
2565 | if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, | |
2566 | &flags) == 0) { | |
2567 | if (flags & HT_MSI_FLAGS_ENABLE) { | |
2568 | if (found < 2) { | |
2569 | found = 2; | |
2570 | break; | |
2571 | } | |
2572 | } | |
2573 | } | |
2574 | pos = pci_find_next_ht_capability(dev, pos, | |
2575 | HT_CAPTYPE_MSI_MAPPING); | |
2576 | } | |
2577 | ||
2578 | return found; | |
2579 | } | |
2580 | ||
25e742b2 | 2581 | static int host_bridge_with_leaf(struct pci_dev *host_bridge) |
de745306 YL |
2582 | { |
2583 | struct pci_dev *dev; | |
2584 | int pos; | |
2585 | int i, dev_no; | |
2586 | int found = 0; | |
2587 | ||
2588 | dev_no = host_bridge->devfn >> 3; | |
2589 | for (i = dev_no + 1; i < 0x20; i++) { | |
2590 | dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); | |
2591 | if (!dev) | |
2592 | continue; | |
2593 | ||
2594 | /* found next host bridge ?*/ | |
2595 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); | |
2596 | if (pos != 0) { | |
2597 | pci_dev_put(dev); | |
2598 | break; | |
2599 | } | |
2600 | ||
2601 | if (ht_check_msi_mapping(dev)) { | |
2602 | found = 1; | |
2603 | pci_dev_put(dev); | |
2604 | break; | |
2605 | } | |
2606 | pci_dev_put(dev); | |
2607 | } | |
2608 | ||
2609 | return found; | |
2610 | } | |
2611 | ||
eeafda70 YL |
2612 | #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */ |
2613 | #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */ | |
2614 | ||
25e742b2 | 2615 | static int is_end_of_ht_chain(struct pci_dev *dev) |
eeafda70 YL |
2616 | { |
2617 | int pos, ctrl_off; | |
2618 | int end = 0; | |
2619 | u16 flags, ctrl; | |
2620 | ||
2621 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); | |
2622 | ||
2623 | if (!pos) | |
2624 | goto out; | |
2625 | ||
2626 | pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags); | |
2627 | ||
2628 | ctrl_off = ((flags >> 10) & 1) ? | |
2629 | PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1; | |
2630 | pci_read_config_word(dev, pos + ctrl_off, &ctrl); | |
2631 | ||
2632 | if (ctrl & (1 << 6)) | |
2633 | end = 1; | |
2634 | ||
2635 | out: | |
2636 | return end; | |
2637 | } | |
2638 | ||
25e742b2 | 2639 | static void nv_ht_enable_msi_mapping(struct pci_dev *dev) |
9dc625e7 PC |
2640 | { |
2641 | struct pci_dev *host_bridge; | |
1dec6b05 YL |
2642 | int pos; |
2643 | int i, dev_no; | |
2644 | int found = 0; | |
2645 | ||
2646 | dev_no = dev->devfn >> 3; | |
2647 | for (i = dev_no; i >= 0; i--) { | |
2648 | host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); | |
2649 | if (!host_bridge) | |
2650 | continue; | |
2651 | ||
2652 | pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); | |
2653 | if (pos != 0) { | |
2654 | found = 1; | |
2655 | break; | |
2656 | } | |
2657 | pci_dev_put(host_bridge); | |
2658 | } | |
2659 | ||
2660 | if (!found) | |
2661 | return; | |
2662 | ||
eeafda70 YL |
2663 | /* don't enable end_device/host_bridge with leaf directly here */ |
2664 | if (host_bridge == dev && is_end_of_ht_chain(host_bridge) && | |
2665 | host_bridge_with_leaf(host_bridge)) | |
de745306 YL |
2666 | goto out; |
2667 | ||
1dec6b05 YL |
2668 | /* root did that ! */ |
2669 | if (msi_ht_cap_enabled(host_bridge)) | |
2670 | goto out; | |
2671 | ||
2672 | ht_enable_msi_mapping(dev); | |
2673 | ||
2674 | out: | |
2675 | pci_dev_put(host_bridge); | |
2676 | } | |
2677 | ||
25e742b2 | 2678 | static void ht_disable_msi_mapping(struct pci_dev *dev) |
1dec6b05 | 2679 | { |
fff905f3 | 2680 | int pos, ttl = PCI_FIND_CAP_TTL; |
1dec6b05 YL |
2681 | |
2682 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); | |
2683 | while (pos && ttl--) { | |
2684 | u8 flags; | |
2685 | ||
2686 | if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, | |
2687 | &flags) == 0) { | |
6a958d5b | 2688 | dev_info(&dev->dev, "Disabling HT MSI Mapping\n"); |
1dec6b05 YL |
2689 | |
2690 | pci_write_config_byte(dev, pos + HT_MSI_FLAGS, | |
2691 | flags & ~HT_MSI_FLAGS_ENABLE); | |
2692 | } | |
2693 | pos = pci_find_next_ht_capability(dev, pos, | |
2694 | HT_CAPTYPE_MSI_MAPPING); | |
2695 | } | |
2696 | } | |
2697 | ||
25e742b2 | 2698 | static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) |
1dec6b05 YL |
2699 | { |
2700 | struct pci_dev *host_bridge; | |
2701 | int pos; | |
2702 | int found; | |
2703 | ||
3d2a5318 RW |
2704 | if (!pci_msi_enabled()) |
2705 | return; | |
2706 | ||
1dec6b05 YL |
2707 | /* check if there is HT MSI cap or enabled on this device */ |
2708 | found = ht_check_msi_mapping(dev); | |
2709 | ||
2710 | /* no HT MSI CAP */ | |
2711 | if (found == 0) | |
2712 | return; | |
9dc625e7 PC |
2713 | |
2714 | /* | |
2715 | * HT MSI mapping should be disabled on devices that are below | |
2716 | * a non-Hypertransport host bridge. Locate the host bridge... | |
2717 | */ | |
2718 | host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); | |
2719 | if (host_bridge == NULL) { | |
227f0647 | 2720 | dev_warn(&dev->dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n"); |
9dc625e7 PC |
2721 | return; |
2722 | } | |
2723 | ||
2724 | pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); | |
2725 | if (pos != 0) { | |
2726 | /* Host bridge is to HT */ | |
1dec6b05 YL |
2727 | if (found == 1) { |
2728 | /* it is not enabled, try to enable it */ | |
de745306 YL |
2729 | if (all) |
2730 | ht_enable_msi_mapping(dev); | |
2731 | else | |
2732 | nv_ht_enable_msi_mapping(dev); | |
1dec6b05 | 2733 | } |
dff3aef7 | 2734 | goto out; |
9dc625e7 PC |
2735 | } |
2736 | ||
1dec6b05 YL |
2737 | /* HT MSI is not enabled */ |
2738 | if (found == 1) | |
dff3aef7 | 2739 | goto out; |
9dc625e7 | 2740 | |
1dec6b05 YL |
2741 | /* Host bridge is not to HT, disable HT MSI mapping on this device */ |
2742 | ht_disable_msi_mapping(dev); | |
dff3aef7 MS |
2743 | |
2744 | out: | |
2745 | pci_dev_put(host_bridge); | |
9dc625e7 | 2746 | } |
de745306 | 2747 | |
25e742b2 | 2748 | static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev) |
de745306 YL |
2749 | { |
2750 | return __nv_msi_ht_cap_quirk(dev, 1); | |
2751 | } | |
2752 | ||
25e742b2 | 2753 | static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev) |
de745306 YL |
2754 | { |
2755 | return __nv_msi_ht_cap_quirk(dev, 0); | |
2756 | } | |
2757 | ||
2758 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); | |
6dab62ee | 2759 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); |
de745306 YL |
2760 | |
2761 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); | |
6dab62ee | 2762 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); |
9dc625e7 | 2763 | |
15856ad5 | 2764 | static void quirk_msi_intx_disable_bug(struct pci_dev *dev) |
ba698ad4 DM |
2765 | { |
2766 | dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; | |
2767 | } | |
15856ad5 | 2768 | static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev) |
4600c9d7 SH |
2769 | { |
2770 | struct pci_dev *p; | |
2771 | ||
2772 | /* SB700 MSI issue will be fixed at HW level from revision A21, | |
2773 | * we need check PCI REVISION ID of SMBus controller to get SB700 | |
2774 | * revision. | |
2775 | */ | |
2776 | p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, | |
2777 | NULL); | |
2778 | if (!p) | |
2779 | return; | |
2780 | ||
2781 | if ((p->revision < 0x3B) && (p->revision >= 0x30)) | |
2782 | dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; | |
2783 | pci_dev_put(p); | |
2784 | } | |
70588818 XH |
2785 | static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev) |
2786 | { | |
2787 | /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */ | |
2788 | if (dev->revision < 0x18) { | |
2789 | dev_info(&dev->dev, "set MSI_INTX_DISABLE_BUG flag\n"); | |
2790 | dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; | |
2791 | } | |
2792 | } | |
ba698ad4 DM |
2793 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, |
2794 | PCI_DEVICE_ID_TIGON3_5780, | |
2795 | quirk_msi_intx_disable_bug); | |
2796 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
2797 | PCI_DEVICE_ID_TIGON3_5780S, | |
2798 | quirk_msi_intx_disable_bug); | |
2799 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
2800 | PCI_DEVICE_ID_TIGON3_5714, | |
2801 | quirk_msi_intx_disable_bug); | |
2802 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
2803 | PCI_DEVICE_ID_TIGON3_5714S, | |
2804 | quirk_msi_intx_disable_bug); | |
2805 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
2806 | PCI_DEVICE_ID_TIGON3_5715, | |
2807 | quirk_msi_intx_disable_bug); | |
2808 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
2809 | PCI_DEVICE_ID_TIGON3_5715S, | |
2810 | quirk_msi_intx_disable_bug); | |
2811 | ||
bc38b411 | 2812 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390, |
4600c9d7 | 2813 | quirk_msi_intx_disable_ati_bug); |
bc38b411 | 2814 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391, |
4600c9d7 | 2815 | quirk_msi_intx_disable_ati_bug); |
bc38b411 | 2816 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392, |
4600c9d7 | 2817 | quirk_msi_intx_disable_ati_bug); |
bc38b411 | 2818 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393, |
4600c9d7 | 2819 | quirk_msi_intx_disable_ati_bug); |
bc38b411 | 2820 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394, |
4600c9d7 | 2821 | quirk_msi_intx_disable_ati_bug); |
bc38b411 DM |
2822 | |
2823 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373, | |
2824 | quirk_msi_intx_disable_bug); | |
2825 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374, | |
2826 | quirk_msi_intx_disable_bug); | |
2827 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375, | |
2828 | quirk_msi_intx_disable_bug); | |
2829 | ||
7cb6a291 HX |
2830 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062, |
2831 | quirk_msi_intx_disable_bug); | |
2832 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063, | |
2833 | quirk_msi_intx_disable_bug); | |
2834 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060, | |
2835 | quirk_msi_intx_disable_bug); | |
2836 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062, | |
2837 | quirk_msi_intx_disable_bug); | |
2838 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073, | |
2839 | quirk_msi_intx_disable_bug); | |
2840 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083, | |
2841 | quirk_msi_intx_disable_bug); | |
70588818 XH |
2842 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090, |
2843 | quirk_msi_intx_disable_qca_bug); | |
2844 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091, | |
2845 | quirk_msi_intx_disable_qca_bug); | |
2846 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0, | |
2847 | quirk_msi_intx_disable_qca_bug); | |
2848 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1, | |
2849 | quirk_msi_intx_disable_qca_bug); | |
2850 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091, | |
2851 | quirk_msi_intx_disable_qca_bug); | |
3f79e107 | 2852 | #endif /* CONFIG_PCI_MSI */ |
3d137310 | 2853 | |
3322340a FR |
2854 | /* Allow manual resource allocation for PCI hotplug bridges |
2855 | * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For | |
2856 | * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6), | |
f7625980 | 2857 | * kernel fails to allocate resources when hotplug device is |
3322340a FR |
2858 | * inserted and PCI bus is rescanned. |
2859 | */ | |
15856ad5 | 2860 | static void quirk_hotplug_bridge(struct pci_dev *dev) |
3322340a FR |
2861 | { |
2862 | dev->is_hotplug_bridge = 1; | |
2863 | } | |
2864 | ||
2865 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge); | |
2866 | ||
03cd8f7e ML |
2867 | /* |
2868 | * This is a quirk for the Ricoh MMC controller found as a part of | |
2869 | * some mulifunction chips. | |
2870 | ||
25985edc | 2871 | * This is very similar and based on the ricoh_mmc driver written by |
03cd8f7e ML |
2872 | * Philip Langdale. Thank you for these magic sequences. |
2873 | * | |
2874 | * These chips implement the four main memory card controllers (SD, MMC, MS, xD) | |
2875 | * and one or both of cardbus or firewire. | |
2876 | * | |
2877 | * It happens that they implement SD and MMC | |
2878 | * support as separate controllers (and PCI functions). The linux SDHCI | |
2879 | * driver supports MMC cards but the chip detects MMC cards in hardware | |
2880 | * and directs them to the MMC controller - so the SDHCI driver never sees | |
2881 | * them. | |
2882 | * | |
2883 | * To get around this, we must disable the useless MMC controller. | |
2884 | * At that point, the SDHCI controller will start seeing them | |
2885 | * It seems to be the case that the relevant PCI registers to deactivate the | |
2886 | * MMC controller live on PCI function 0, which might be the cardbus controller | |
2887 | * or the firewire controller, depending on the particular chip in question | |
2888 | * | |
2889 | * This has to be done early, because as soon as we disable the MMC controller | |
2890 | * other pci functions shift up one level, e.g. function #2 becomes function | |
2891 | * #1, and this will confuse the pci core. | |
2892 | */ | |
2893 | ||
2894 | #ifdef CONFIG_MMC_RICOH_MMC | |
2895 | static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev) | |
2896 | { | |
2897 | /* disable via cardbus interface */ | |
2898 | u8 write_enable; | |
2899 | u8 write_target; | |
2900 | u8 disable; | |
2901 | ||
2902 | /* disable must be done via function #0 */ | |
2903 | if (PCI_FUNC(dev->devfn)) | |
2904 | return; | |
2905 | ||
2906 | pci_read_config_byte(dev, 0xB7, &disable); | |
2907 | if (disable & 0x02) | |
2908 | return; | |
2909 | ||
2910 | pci_read_config_byte(dev, 0x8E, &write_enable); | |
2911 | pci_write_config_byte(dev, 0x8E, 0xAA); | |
2912 | pci_read_config_byte(dev, 0x8D, &write_target); | |
2913 | pci_write_config_byte(dev, 0x8D, 0xB7); | |
2914 | pci_write_config_byte(dev, 0xB7, disable | 0x02); | |
2915 | pci_write_config_byte(dev, 0x8E, write_enable); | |
2916 | pci_write_config_byte(dev, 0x8D, write_target); | |
2917 | ||
2918 | dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n"); | |
2919 | dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n"); | |
2920 | } | |
2921 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); | |
2922 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); | |
2923 | ||
2924 | static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev) | |
2925 | { | |
2926 | /* disable via firewire interface */ | |
2927 | u8 write_enable; | |
2928 | u8 disable; | |
2929 | ||
2930 | /* disable must be done via function #0 */ | |
2931 | if (PCI_FUNC(dev->devfn)) | |
2932 | return; | |
15bed0f2 | 2933 | /* |
812089e0 | 2934 | * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize |
15bed0f2 MI |
2935 | * certain types of SD/MMC cards. Lowering the SD base |
2936 | * clock frequency from 200Mhz to 50Mhz fixes this issue. | |
2937 | * | |
2938 | * 0x150 - SD2.0 mode enable for changing base clock | |
2939 | * frequency to 50Mhz | |
2940 | * 0xe1 - Base clock frequency | |
2941 | * 0x32 - 50Mhz new clock frequency | |
2942 | * 0xf9 - Key register for 0x150 | |
2943 | * 0xfc - key register for 0xe1 | |
2944 | */ | |
812089e0 AL |
2945 | if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 || |
2946 | dev->device == PCI_DEVICE_ID_RICOH_R5CE823) { | |
15bed0f2 MI |
2947 | pci_write_config_byte(dev, 0xf9, 0xfc); |
2948 | pci_write_config_byte(dev, 0x150, 0x10); | |
2949 | pci_write_config_byte(dev, 0xf9, 0x00); | |
2950 | pci_write_config_byte(dev, 0xfc, 0x01); | |
2951 | pci_write_config_byte(dev, 0xe1, 0x32); | |
2952 | pci_write_config_byte(dev, 0xfc, 0x00); | |
2953 | ||
2954 | dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n"); | |
2955 | } | |
3e309cdf JB |
2956 | |
2957 | pci_read_config_byte(dev, 0xCB, &disable); | |
2958 | ||
2959 | if (disable & 0x02) | |
2960 | return; | |
2961 | ||
2962 | pci_read_config_byte(dev, 0xCA, &write_enable); | |
2963 | pci_write_config_byte(dev, 0xCA, 0x57); | |
2964 | pci_write_config_byte(dev, 0xCB, disable | 0x02); | |
2965 | pci_write_config_byte(dev, 0xCA, write_enable); | |
2966 | ||
2967 | dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n"); | |
2968 | dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n"); | |
2969 | ||
03cd8f7e ML |
2970 | } |
2971 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); | |
2972 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); | |
812089e0 AL |
2973 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); |
2974 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); | |
be98ca65 MI |
2975 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); |
2976 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); | |
03cd8f7e ML |
2977 | #endif /*CONFIG_MMC_RICOH_MMC*/ |
2978 | ||
d3f13810 | 2979 | #ifdef CONFIG_DMAR_TABLE |
254e4200 SS |
2980 | #define VTUNCERRMSK_REG 0x1ac |
2981 | #define VTD_MSK_SPEC_ERRORS (1 << 31) | |
2982 | /* | |
2983 | * This is a quirk for masking vt-d spec defined errors to platform error | |
2984 | * handling logic. With out this, platforms using Intel 7500, 5500 chipsets | |
2985 | * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based | |
2986 | * on the RAS config settings of the platform) when a vt-d fault happens. | |
2987 | * The resulting SMI caused the system to hang. | |
2988 | * | |
2989 | * VT-d spec related errors are already handled by the VT-d OS code, so no | |
2990 | * need to report the same error through other channels. | |
2991 | */ | |
2992 | static void vtd_mask_spec_errors(struct pci_dev *dev) | |
2993 | { | |
2994 | u32 word; | |
2995 | ||
2996 | pci_read_config_dword(dev, VTUNCERRMSK_REG, &word); | |
2997 | pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS); | |
2998 | } | |
2999 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors); | |
3000 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors); | |
3001 | #endif | |
03cd8f7e | 3002 | |
15856ad5 | 3003 | static void fixup_ti816x_class(struct pci_dev *dev) |
63c44080 | 3004 | { |
d1541dc9 BH |
3005 | u32 class = dev->class; |
3006 | ||
63c44080 | 3007 | /* TI 816x devices do not have class code set when in PCIe boot mode */ |
d1541dc9 BH |
3008 | dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8; |
3009 | dev_info(&dev->dev, "PCI class overridden (%#08x -> %#08x)\n", | |
3010 | class, dev->class); | |
63c44080 | 3011 | } |
40c96236 | 3012 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800, |
2b4aed1d | 3013 | PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class); |
63c44080 | 3014 | |
a94d072b BH |
3015 | /* Some PCIe devices do not work reliably with the claimed maximum |
3016 | * payload size supported. | |
3017 | */ | |
15856ad5 | 3018 | static void fixup_mpss_256(struct pci_dev *dev) |
a94d072b BH |
3019 | { |
3020 | dev->pcie_mpss = 1; /* 256 bytes */ | |
3021 | } | |
3022 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, | |
3023 | PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256); | |
3024 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, | |
3025 | PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256); | |
3026 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, | |
3027 | PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256); | |
3028 | ||
d387a8d6 JM |
3029 | /* Intel 5000 and 5100 Memory controllers have an errata with read completion |
3030 | * coalescing (which is enabled by default on some BIOSes) and MPS of 256B. | |
3031 | * Since there is no way of knowing what the PCIE MPS on each fabric will be | |
3032 | * until all of the devices are discovered and buses walked, read completion | |
3033 | * coalescing must be disabled. Unfortunately, it cannot be re-enabled because | |
3034 | * it is possible to hotplug a device with MPS of 256B. | |
3035 | */ | |
15856ad5 | 3036 | static void quirk_intel_mc_errata(struct pci_dev *dev) |
d387a8d6 JM |
3037 | { |
3038 | int err; | |
3039 | u16 rcc; | |
3040 | ||
27d868b5 KB |
3041 | if (pcie_bus_config == PCIE_BUS_TUNE_OFF || |
3042 | pcie_bus_config == PCIE_BUS_DEFAULT) | |
d387a8d6 JM |
3043 | return; |
3044 | ||
3045 | /* Intel errata specifies bits to change but does not say what they are. | |
3046 | * Keeping them magical until such time as the registers and values can | |
3047 | * be explained. | |
3048 | */ | |
3049 | err = pci_read_config_word(dev, 0x48, &rcc); | |
3050 | if (err) { | |
227f0647 | 3051 | dev_err(&dev->dev, "Error attempting to read the read completion coalescing register\n"); |
d387a8d6 JM |
3052 | return; |
3053 | } | |
3054 | ||
3055 | if (!(rcc & (1 << 10))) | |
3056 | return; | |
3057 | ||
3058 | rcc &= ~(1 << 10); | |
3059 | ||
3060 | err = pci_write_config_word(dev, 0x48, rcc); | |
3061 | if (err) { | |
227f0647 | 3062 | dev_err(&dev->dev, "Error attempting to write the read completion coalescing register\n"); |
d387a8d6 JM |
3063 | return; |
3064 | } | |
3065 | ||
227f0647 | 3066 | pr_info_once("Read completion coalescing disabled due to hardware errata relating to 256B MPS\n"); |
d387a8d6 JM |
3067 | } |
3068 | /* Intel 5000 series memory controllers and ports 2-7 */ | |
3069 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata); | |
3070 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata); | |
3071 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata); | |
3072 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata); | |
3073 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata); | |
3074 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata); | |
3075 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata); | |
3076 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata); | |
3077 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata); | |
3078 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata); | |
3079 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata); | |
3080 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata); | |
3081 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata); | |
3082 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata); | |
3083 | /* Intel 5100 series memory controllers and ports 2-7 */ | |
3084 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata); | |
3085 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata); | |
3086 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata); | |
3087 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata); | |
3088 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata); | |
3089 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata); | |
3090 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata); | |
3091 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata); | |
3092 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata); | |
3093 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata); | |
3094 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata); | |
3095 | ||
3209874a | 3096 | |
12b03188 JM |
3097 | /* |
3098 | * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. To | |
3099 | * work around this, query the size it should be configured to by the device and | |
3100 | * modify the resource end to correspond to this new size. | |
3101 | */ | |
3102 | static void quirk_intel_ntb(struct pci_dev *dev) | |
3103 | { | |
3104 | int rc; | |
3105 | u8 val; | |
3106 | ||
3107 | rc = pci_read_config_byte(dev, 0x00D0, &val); | |
3108 | if (rc) | |
3109 | return; | |
3110 | ||
3111 | dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1; | |
3112 | ||
3113 | rc = pci_read_config_byte(dev, 0x00D1, &val); | |
3114 | if (rc) | |
3115 | return; | |
3116 | ||
3117 | dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1; | |
3118 | } | |
3119 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb); | |
3120 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb); | |
3121 | ||
2729d5b1 MS |
3122 | static ktime_t fixup_debug_start(struct pci_dev *dev, |
3123 | void (*fn)(struct pci_dev *dev)) | |
3209874a | 3124 | { |
8b0e1953 | 3125 | ktime_t calltime = 0; |
2729d5b1 MS |
3126 | |
3127 | dev_dbg(&dev->dev, "calling %pF\n", fn); | |
3128 | if (initcall_debug) { | |
3129 | pr_debug("calling %pF @ %i for %s\n", | |
3130 | fn, task_pid_nr(current), dev_name(&dev->dev)); | |
3131 | calltime = ktime_get(); | |
3132 | } | |
3133 | ||
3134 | return calltime; | |
3135 | } | |
3136 | ||
3137 | static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime, | |
3138 | void (*fn)(struct pci_dev *dev)) | |
3209874a | 3139 | { |
2729d5b1 | 3140 | ktime_t delta, rettime; |
3209874a AV |
3141 | unsigned long long duration; |
3142 | ||
2729d5b1 MS |
3143 | if (initcall_debug) { |
3144 | rettime = ktime_get(); | |
3145 | delta = ktime_sub(rettime, calltime); | |
3146 | duration = (unsigned long long) ktime_to_ns(delta) >> 10; | |
3147 | pr_debug("pci fixup %pF returned after %lld usecs for %s\n", | |
3148 | fn, duration, dev_name(&dev->dev)); | |
3149 | } | |
3209874a AV |
3150 | } |
3151 | ||
f67fd55f TJ |
3152 | /* |
3153 | * Some BIOS implementations leave the Intel GPU interrupts enabled, | |
3154 | * even though no one is handling them (f.e. i915 driver is never loaded). | |
3155 | * Additionally the interrupt destination is not set up properly | |
3156 | * and the interrupt ends up -somewhere-. | |
3157 | * | |
3158 | * These spurious interrupts are "sticky" and the kernel disables | |
3159 | * the (shared) interrupt line after 100.000+ generated interrupts. | |
3160 | * | |
3161 | * Fix it by disabling the still enabled interrupts. | |
3162 | * This resolves crashes often seen on monitor unplug. | |
3163 | */ | |
3164 | #define I915_DEIER_REG 0x4400c | |
15856ad5 | 3165 | static void disable_igfx_irq(struct pci_dev *dev) |
f67fd55f TJ |
3166 | { |
3167 | void __iomem *regs = pci_iomap(dev, 0, 0); | |
3168 | if (regs == NULL) { | |
3169 | dev_warn(&dev->dev, "igfx quirk: Can't iomap PCI device\n"); | |
3170 | return; | |
3171 | } | |
3172 | ||
3173 | /* Check if any interrupt line is still enabled */ | |
3174 | if (readl(regs + I915_DEIER_REG) != 0) { | |
227f0647 | 3175 | dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; disabling\n"); |
f67fd55f TJ |
3176 | |
3177 | writel(0, regs + I915_DEIER_REG); | |
3178 | } | |
3179 | ||
3180 | pci_iounmap(dev, regs); | |
3181 | } | |
3182 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq); | |
3183 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq); | |
7c82126a | 3184 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq); |
f67fd55f | 3185 | |
b8cac70a TB |
3186 | /* |
3187 | * PCI devices which are on Intel chips can skip the 10ms delay | |
3188 | * before entering D3 mode. | |
3189 | */ | |
3190 | static void quirk_remove_d3_delay(struct pci_dev *dev) | |
3191 | { | |
3192 | dev->d3_delay = 0; | |
3193 | } | |
cd3e2eb8 | 3194 | /* C600 Series devices do not need 10ms d3_delay */ |
b8cac70a | 3195 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay); |
cd3e2eb8 | 3196 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay); |
b8cac70a | 3197 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay); |
cd3e2eb8 AS |
3198 | /* Lynxpoint-H PCH devices do not need 10ms d3_delay */ |
3199 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay); | |
b8cac70a TB |
3200 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay); |
3201 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay); | |
cd3e2eb8 AS |
3202 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay); |
3203 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay); | |
b8cac70a | 3204 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay); |
cd3e2eb8 AS |
3205 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay); |
3206 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay); | |
3207 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay); | |
3208 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay); | |
b8cac70a | 3209 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay); |
4a118753 SK |
3210 | /* Intel Cherrytrail devices do not need 10ms d3_delay */ |
3211 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3_delay); | |
cd3e2eb8 AS |
3212 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3_delay); |
3213 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3_delay); | |
4a118753 | 3214 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3_delay); |
cd3e2eb8 AS |
3215 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3_delay); |
3216 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3_delay); | |
4a118753 SK |
3217 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3_delay); |
3218 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3_delay); | |
3219 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3_delay); | |
d76d2fe0 | 3220 | |
fbebb9fd | 3221 | /* |
d76d2fe0 | 3222 | * Some devices may pass our check in pci_intx_mask_supported() if |
fbebb9fd BH |
3223 | * PCI_COMMAND_INTX_DISABLE works though they actually do not properly |
3224 | * support this feature. | |
3225 | */ | |
15856ad5 | 3226 | static void quirk_broken_intx_masking(struct pci_dev *dev) |
fbebb9fd BH |
3227 | { |
3228 | dev->broken_intx_masking = 1; | |
3229 | } | |
b88214ce NO |
3230 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030, |
3231 | quirk_broken_intx_masking); | |
3232 | DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */ | |
3233 | quirk_broken_intx_masking); | |
d76d2fe0 | 3234 | |
3cb30b73 AW |
3235 | /* |
3236 | * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10) | |
3237 | * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC | |
3238 | * | |
3239 | * RTL8110SC - Fails under PCI device assignment using DisINTx masking. | |
3240 | */ | |
b88214ce NO |
3241 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169, |
3242 | quirk_broken_intx_masking); | |
fbebb9fd | 3243 | |
8bcf4525 AW |
3244 | /* |
3245 | * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking, | |
3246 | * DisINTx can be set but the interrupt status bit is non-functional. | |
3247 | */ | |
b88214ce NO |
3248 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, |
3249 | quirk_broken_intx_masking); | |
3250 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, | |
3251 | quirk_broken_intx_masking); | |
3252 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, | |
3253 | quirk_broken_intx_masking); | |
3254 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, | |
3255 | quirk_broken_intx_masking); | |
3256 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, | |
3257 | quirk_broken_intx_masking); | |
3258 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, | |
3259 | quirk_broken_intx_masking); | |
3260 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, | |
3261 | quirk_broken_intx_masking); | |
3262 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, | |
3263 | quirk_broken_intx_masking); | |
3264 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, | |
3265 | quirk_broken_intx_masking); | |
3266 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, | |
3267 | quirk_broken_intx_masking); | |
3268 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, | |
3269 | quirk_broken_intx_masking); | |
d40b7fd2 AW |
3270 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, |
3271 | quirk_broken_intx_masking); | |
3272 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, | |
3273 | quirk_broken_intx_masking); | |
b88214ce NO |
3274 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, |
3275 | quirk_broken_intx_masking); | |
3276 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, | |
3277 | quirk_broken_intx_masking); | |
3278 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, | |
3279 | quirk_broken_intx_masking); | |
8bcf4525 | 3280 | |
d76d2fe0 NO |
3281 | static u16 mellanox_broken_intx_devs[] = { |
3282 | PCI_DEVICE_ID_MELLANOX_HERMON_SDR, | |
3283 | PCI_DEVICE_ID_MELLANOX_HERMON_DDR, | |
3284 | PCI_DEVICE_ID_MELLANOX_HERMON_QDR, | |
3285 | PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2, | |
3286 | PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2, | |
3287 | PCI_DEVICE_ID_MELLANOX_HERMON_EN, | |
3288 | PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2, | |
3289 | PCI_DEVICE_ID_MELLANOX_CONNECTX_EN, | |
3290 | PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2, | |
3291 | PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2, | |
3292 | PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2, | |
3293 | PCI_DEVICE_ID_MELLANOX_CONNECTX2, | |
3294 | PCI_DEVICE_ID_MELLANOX_CONNECTX3, | |
3295 | PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO, | |
d76d2fe0 NO |
3296 | }; |
3297 | ||
1600f625 NO |
3298 | #define CONNECTX_4_CURR_MAX_MINOR 99 |
3299 | #define CONNECTX_4_INTX_SUPPORT_MINOR 14 | |
3300 | ||
3301 | /* | |
3302 | * Check ConnectX-4/LX FW version to see if it supports legacy interrupts. | |
3303 | * If so, don't mark it as broken. | |
3304 | * FW minor > 99 means older FW version format and no INTx masking support. | |
3305 | * FW minor < 14 means new FW version format and no INTx masking support. | |
3306 | */ | |
d76d2fe0 NO |
3307 | static void mellanox_check_broken_intx_masking(struct pci_dev *pdev) |
3308 | { | |
1600f625 NO |
3309 | __be32 __iomem *fw_ver; |
3310 | u16 fw_major; | |
3311 | u16 fw_minor; | |
3312 | u16 fw_subminor; | |
3313 | u32 fw_maj_min; | |
3314 | u32 fw_sub_min; | |
d76d2fe0 NO |
3315 | int i; |
3316 | ||
3317 | for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) { | |
3318 | if (pdev->device == mellanox_broken_intx_devs[i]) { | |
3319 | pdev->broken_intx_masking = 1; | |
3320 | return; | |
3321 | } | |
3322 | } | |
1600f625 NO |
3323 | |
3324 | /* Getting here means Connect-IB cards and up. Connect-IB has no INTx | |
3325 | * support so shouldn't be checked further | |
3326 | */ | |
3327 | if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB) | |
3328 | return; | |
3329 | ||
3330 | if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 && | |
3331 | pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) | |
3332 | return; | |
3333 | ||
3334 | /* For ConnectX-4 and ConnectX-4LX, need to check FW support */ | |
3335 | if (pci_enable_device_mem(pdev)) { | |
3336 | dev_warn(&pdev->dev, "Can't enable device memory\n"); | |
3337 | return; | |
3338 | } | |
3339 | ||
3340 | fw_ver = ioremap(pci_resource_start(pdev, 0), 4); | |
3341 | if (!fw_ver) { | |
3342 | dev_warn(&pdev->dev, "Can't map ConnectX-4 initialization segment\n"); | |
3343 | goto out; | |
3344 | } | |
3345 | ||
3346 | /* Reading from resource space should be 32b aligned */ | |
3347 | fw_maj_min = ioread32be(fw_ver); | |
3348 | fw_sub_min = ioread32be(fw_ver + 1); | |
3349 | fw_major = fw_maj_min & 0xffff; | |
3350 | fw_minor = fw_maj_min >> 16; | |
3351 | fw_subminor = fw_sub_min & 0xffff; | |
3352 | if (fw_minor > CONNECTX_4_CURR_MAX_MINOR || | |
3353 | fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) { | |
3354 | dev_warn(&pdev->dev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n", | |
3355 | fw_major, fw_minor, fw_subminor, pdev->device == | |
3356 | PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14); | |
3357 | pdev->broken_intx_masking = 1; | |
3358 | } | |
3359 | ||
3360 | iounmap(fw_ver); | |
3361 | ||
3362 | out: | |
3363 | pci_disable_device(pdev); | |
d76d2fe0 NO |
3364 | } |
3365 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID, | |
3366 | mellanox_check_broken_intx_masking); | |
8bcf4525 | 3367 | |
c3e59ee4 AW |
3368 | static void quirk_no_bus_reset(struct pci_dev *dev) |
3369 | { | |
3370 | dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; | |
3371 | } | |
3372 | ||
3373 | /* | |
9ac0108c CB |
3374 | * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset. |
3375 | * The device will throw a Link Down error on AER-capable systems and | |
3376 | * regardless of AER, config space of the device is never accessible again | |
3377 | * and typically causes the system to hang or reset when access is attempted. | |
c3e59ee4 AW |
3378 | * http://www.spinics.net/lists/linux-pci/msg34797.html |
3379 | */ | |
3380 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset); | |
9ac0108c CB |
3381 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset); |
3382 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset); | |
8e2e0317 | 3383 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset); |
c3e59ee4 | 3384 | |
82215510 DD |
3385 | /* |
3386 | * Root port on some Cavium CN8xxx chips do not successfully complete a bus | |
3387 | * reset when used with certain child devices. After the reset, config | |
3388 | * accesses to the child may fail. | |
3389 | */ | |
3390 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset); | |
3391 | ||
d84f3174 AW |
3392 | static void quirk_no_pm_reset(struct pci_dev *dev) |
3393 | { | |
3394 | /* | |
3395 | * We can't do a bus reset on root bus devices, but an ineffective | |
3396 | * PM reset may be better than nothing. | |
3397 | */ | |
3398 | if (!pci_is_root_bus(dev->bus)) | |
3399 | dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET; | |
3400 | } | |
3401 | ||
3402 | /* | |
3403 | * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition | |
3404 | * causes a reset (i.e., they advertise NoSoftRst-). This transition seems | |
3405 | * to have no effect on the device: it retains the framebuffer contents and | |
3406 | * monitor sync. Advertising this support makes other layers, like VFIO, | |
3407 | * assume pci_reset_function() is viable for this device. Mark it as | |
3408 | * unavailable to skip it when testing reset methods. | |
3409 | */ | |
3410 | DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID, | |
3411 | PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset); | |
3412 | ||
19bf4d4f LW |
3413 | /* |
3414 | * Thunderbolt controllers with broken MSI hotplug signaling: | |
3415 | * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part | |
3416 | * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge). | |
3417 | */ | |
3418 | static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev) | |
3419 | { | |
3420 | if (pdev->is_hotplug_bridge && | |
3421 | (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C || | |
3422 | pdev->revision <= 1)) | |
3423 | pdev->no_msi = 1; | |
3424 | } | |
3425 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE, | |
3426 | quirk_thunderbolt_hotplug_msi); | |
3427 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE, | |
3428 | quirk_thunderbolt_hotplug_msi); | |
3429 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK, | |
3430 | quirk_thunderbolt_hotplug_msi); | |
3431 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, | |
3432 | quirk_thunderbolt_hotplug_msi); | |
3433 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE, | |
3434 | quirk_thunderbolt_hotplug_msi); | |
3435 | ||
1c7de2b4 AK |
3436 | static void quirk_chelsio_extend_vpd(struct pci_dev *dev) |
3437 | { | |
ac4ae55a CL |
3438 | int chip = (dev->device & 0xf000) >> 12; |
3439 | int func = (dev->device & 0x0f00) >> 8; | |
3440 | int prod = (dev->device & 0x00ff) >> 0; | |
3441 | ||
3442 | /* | |
3443 | * If this is a T3-based adapter, there's a 1KB VPD area at offset | |
3444 | * 0xc00 which contains the preferred VPD values. If this is a T4 or | |
3445 | * later based adapter, the special VPD is at offset 0x400 for the | |
3446 | * Physical Functions (the SR-IOV Virtual Functions have no VPD | |
3447 | * Capabilities). The PCI VPD Access core routines will normally | |
3448 | * compute the size of the VPD by parsing the VPD Data Structure at | |
3449 | * offset 0x000. This will result in silent failures when attempting | |
3450 | * to accesses these other VPD areas which are beyond those computed | |
3451 | * limits. | |
3452 | */ | |
3453 | if (chip == 0x0 && prod >= 0x20) | |
3454 | pci_set_vpd_size(dev, 8192); | |
3455 | else if (chip >= 0x4 && func < 0x8) | |
3456 | pci_set_vpd_size(dev, 2048); | |
3457 | } | |
3458 | ||
3459 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, | |
3460 | quirk_chelsio_extend_vpd); | |
1c7de2b4 | 3461 | |
1df5172c AN |
3462 | #ifdef CONFIG_ACPI |
3463 | /* | |
3464 | * Apple: Shutdown Cactus Ridge Thunderbolt controller. | |
3465 | * | |
3466 | * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be | |
3467 | * shutdown before suspend. Otherwise the native host interface (NHI) will not | |
3468 | * be present after resume if a device was plugged in before suspend. | |
3469 | * | |
3470 | * The thunderbolt controller consists of a pcie switch with downstream | |
3471 | * bridges leading to the NHI and to the tunnel pci bridges. | |
3472 | * | |
3473 | * This quirk cuts power to the whole chip. Therefore we have to apply it | |
3474 | * during suspend_noirq of the upstream bridge. | |
3475 | * | |
3476 | * Power is automagically restored before resume. No action is needed. | |
3477 | */ | |
3478 | static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev) | |
3479 | { | |
3480 | acpi_handle bridge, SXIO, SXFP, SXLV; | |
3481 | ||
630b3aff | 3482 | if (!x86_apple_machine) |
1df5172c AN |
3483 | return; |
3484 | if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) | |
3485 | return; | |
3486 | bridge = ACPI_HANDLE(&dev->dev); | |
3487 | if (!bridge) | |
3488 | return; | |
3489 | /* | |
3490 | * SXIO and SXLV are present only on machines requiring this quirk. | |
3491 | * TB bridges in external devices might have the same device id as those | |
3492 | * on the host, but they will not have the associated ACPI methods. This | |
3493 | * implicitly checks that we are at the right bridge. | |
3494 | */ | |
3495 | if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO)) | |
3496 | || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP)) | |
3497 | || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV))) | |
3498 | return; | |
3499 | dev_info(&dev->dev, "quirk: cutting power to thunderbolt controller...\n"); | |
3500 | ||
3501 | /* magic sequence */ | |
3502 | acpi_execute_simple_method(SXIO, NULL, 1); | |
3503 | acpi_execute_simple_method(SXFP, NULL, 0); | |
3504 | msleep(300); | |
3505 | acpi_execute_simple_method(SXLV, NULL, 0); | |
3506 | acpi_execute_simple_method(SXIO, NULL, 0); | |
3507 | acpi_execute_simple_method(SXLV, NULL, 0); | |
3508 | } | |
1d111406 LW |
3509 | DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL, |
3510 | PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, | |
1df5172c AN |
3511 | quirk_apple_poweroff_thunderbolt); |
3512 | ||
3513 | /* | |
3514 | * Apple: Wait for the thunderbolt controller to reestablish pci tunnels. | |
3515 | * | |
3516 | * During suspend the thunderbolt controller is reset and all pci | |
3517 | * tunnels are lost. The NHI driver will try to reestablish all tunnels | |
3518 | * during resume. We have to manually wait for the NHI since there is | |
3519 | * no parent child relationship between the NHI and the tunneled | |
3520 | * bridges. | |
3521 | */ | |
3522 | static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev) | |
3523 | { | |
3524 | struct pci_dev *sibling = NULL; | |
3525 | struct pci_dev *nhi = NULL; | |
3526 | ||
630b3aff | 3527 | if (!x86_apple_machine) |
1df5172c AN |
3528 | return; |
3529 | if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM) | |
3530 | return; | |
3531 | /* | |
3532 | * Find the NHI and confirm that we are a bridge on the tb host | |
3533 | * controller and not on a tb endpoint. | |
3534 | */ | |
3535 | sibling = pci_get_slot(dev->bus, 0x0); | |
3536 | if (sibling == dev) | |
3537 | goto out; /* we are the downstream bridge to the NHI */ | |
3538 | if (!sibling || !sibling->subordinate) | |
3539 | goto out; | |
3540 | nhi = pci_get_slot(sibling->subordinate, 0x0); | |
3541 | if (!nhi) | |
3542 | goto out; | |
3543 | if (nhi->vendor != PCI_VENDOR_ID_INTEL | |
19bf4d4f LW |
3544 | || (nhi->device != PCI_DEVICE_ID_INTEL_LIGHT_RIDGE && |
3545 | nhi->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C && | |
82a6a81c | 3546 | nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI && |
1d111406 | 3547 | nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI) |
25eb7e5c | 3548 | || nhi->class != PCI_CLASS_SYSTEM_OTHER << 8) |
1df5172c | 3549 | goto out; |
c89ac443 | 3550 | dev_info(&dev->dev, "quirk: waiting for thunderbolt to reestablish PCI tunnels...\n"); |
1df5172c AN |
3551 | device_pm_wait_for_dev(&dev->dev, &nhi->dev); |
3552 | out: | |
3553 | pci_dev_put(nhi); | |
3554 | pci_dev_put(sibling); | |
3555 | } | |
19bf4d4f LW |
3556 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, |
3557 | PCI_DEVICE_ID_INTEL_LIGHT_RIDGE, | |
1df5172c | 3558 | quirk_apple_wait_for_thunderbolt); |
1d111406 LW |
3559 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, |
3560 | PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, | |
1df5172c | 3561 | quirk_apple_wait_for_thunderbolt); |
82a6a81c XG |
3562 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, |
3563 | PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE, | |
3564 | quirk_apple_wait_for_thunderbolt); | |
1d111406 LW |
3565 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, |
3566 | PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE, | |
1df5172c AN |
3567 | quirk_apple_wait_for_thunderbolt); |
3568 | #endif | |
3569 | ||
bfb0f330 JB |
3570 | static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, |
3571 | struct pci_fixup *end) | |
3d137310 | 3572 | { |
2729d5b1 MS |
3573 | ktime_t calltime; |
3574 | ||
f4ca5c6a YL |
3575 | for (; f < end; f++) |
3576 | if ((f->class == (u32) (dev->class >> f->class_shift) || | |
3577 | f->class == (u32) PCI_ANY_ID) && | |
3578 | (f->vendor == dev->vendor || | |
3579 | f->vendor == (u16) PCI_ANY_ID) && | |
3580 | (f->device == dev->device || | |
3581 | f->device == (u16) PCI_ANY_ID)) { | |
2729d5b1 MS |
3582 | calltime = fixup_debug_start(dev, f->hook); |
3583 | f->hook(dev); | |
3584 | fixup_debug_report(dev, calltime, f->hook); | |
3d137310 | 3585 | } |
3d137310 TP |
3586 | } |
3587 | ||
3588 | extern struct pci_fixup __start_pci_fixups_early[]; | |
3589 | extern struct pci_fixup __end_pci_fixups_early[]; | |
3590 | extern struct pci_fixup __start_pci_fixups_header[]; | |
3591 | extern struct pci_fixup __end_pci_fixups_header[]; | |
3592 | extern struct pci_fixup __start_pci_fixups_final[]; | |
3593 | extern struct pci_fixup __end_pci_fixups_final[]; | |
3594 | extern struct pci_fixup __start_pci_fixups_enable[]; | |
3595 | extern struct pci_fixup __end_pci_fixups_enable[]; | |
3596 | extern struct pci_fixup __start_pci_fixups_resume[]; | |
3597 | extern struct pci_fixup __end_pci_fixups_resume[]; | |
3598 | extern struct pci_fixup __start_pci_fixups_resume_early[]; | |
3599 | extern struct pci_fixup __end_pci_fixups_resume_early[]; | |
3600 | extern struct pci_fixup __start_pci_fixups_suspend[]; | |
3601 | extern struct pci_fixup __end_pci_fixups_suspend[]; | |
7d2a01b8 AN |
3602 | extern struct pci_fixup __start_pci_fixups_suspend_late[]; |
3603 | extern struct pci_fixup __end_pci_fixups_suspend_late[]; | |
3d137310 | 3604 | |
95df8b87 | 3605 | static bool pci_apply_fixup_final_quirks; |
3d137310 TP |
3606 | |
3607 | void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) | |
3608 | { | |
3609 | struct pci_fixup *start, *end; | |
3610 | ||
3c78bc61 | 3611 | switch (pass) { |
3d137310 TP |
3612 | case pci_fixup_early: |
3613 | start = __start_pci_fixups_early; | |
3614 | end = __end_pci_fixups_early; | |
3615 | break; | |
3616 | ||
3617 | case pci_fixup_header: | |
3618 | start = __start_pci_fixups_header; | |
3619 | end = __end_pci_fixups_header; | |
3620 | break; | |
3621 | ||
3622 | case pci_fixup_final: | |
95df8b87 MS |
3623 | if (!pci_apply_fixup_final_quirks) |
3624 | return; | |
3d137310 TP |
3625 | start = __start_pci_fixups_final; |
3626 | end = __end_pci_fixups_final; | |
3627 | break; | |
3628 | ||
3629 | case pci_fixup_enable: | |
3630 | start = __start_pci_fixups_enable; | |
3631 | end = __end_pci_fixups_enable; | |
3632 | break; | |
3633 | ||
3634 | case pci_fixup_resume: | |
3635 | start = __start_pci_fixups_resume; | |
3636 | end = __end_pci_fixups_resume; | |
3637 | break; | |
3638 | ||
3639 | case pci_fixup_resume_early: | |
3640 | start = __start_pci_fixups_resume_early; | |
3641 | end = __end_pci_fixups_resume_early; | |
3642 | break; | |
3643 | ||
3644 | case pci_fixup_suspend: | |
3645 | start = __start_pci_fixups_suspend; | |
3646 | end = __end_pci_fixups_suspend; | |
3647 | break; | |
3648 | ||
7d2a01b8 AN |
3649 | case pci_fixup_suspend_late: |
3650 | start = __start_pci_fixups_suspend_late; | |
3651 | end = __end_pci_fixups_suspend_late; | |
3652 | break; | |
3653 | ||
3d137310 TP |
3654 | default: |
3655 | /* stupid compiler warning, you would think with an enum... */ | |
3656 | return; | |
3657 | } | |
3658 | pci_do_fixups(dev, start, end); | |
3659 | } | |
93177a74 | 3660 | EXPORT_SYMBOL(pci_fixup_device); |
8d86fb2c | 3661 | |
735bff10 | 3662 | |
00010268 | 3663 | static int __init pci_apply_final_quirks(void) |
8d86fb2c DW |
3664 | { |
3665 | struct pci_dev *dev = NULL; | |
ac1aa47b JB |
3666 | u8 cls = 0; |
3667 | u8 tmp; | |
3668 | ||
3669 | if (pci_cache_line_size) | |
3670 | printk(KERN_DEBUG "PCI: CLS %u bytes\n", | |
3671 | pci_cache_line_size << 2); | |
8d86fb2c | 3672 | |
95df8b87 | 3673 | pci_apply_fixup_final_quirks = true; |
4e344b1c | 3674 | for_each_pci_dev(dev) { |
8d86fb2c | 3675 | pci_fixup_device(pci_fixup_final, dev); |
ac1aa47b JB |
3676 | /* |
3677 | * If arch hasn't set it explicitly yet, use the CLS | |
3678 | * value shared by all PCI devices. If there's a | |
3679 | * mismatch, fall back to the default value. | |
3680 | */ | |
3681 | if (!pci_cache_line_size) { | |
3682 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp); | |
3683 | if (!cls) | |
3684 | cls = tmp; | |
3685 | if (!tmp || cls == tmp) | |
3686 | continue; | |
3687 | ||
227f0647 RD |
3688 | printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), using %u bytes\n", |
3689 | cls << 2, tmp << 2, | |
ac1aa47b JB |
3690 | pci_dfl_cache_line_size << 2); |
3691 | pci_cache_line_size = pci_dfl_cache_line_size; | |
3692 | } | |
3693 | } | |
735bff10 | 3694 | |
ac1aa47b JB |
3695 | if (!pci_cache_line_size) { |
3696 | printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n", | |
3697 | cls << 2, pci_dfl_cache_line_size << 2); | |
2820f333 | 3698 | pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size; |
8d86fb2c DW |
3699 | } |
3700 | ||
3701 | return 0; | |
3702 | } | |
3703 | ||
cf6f3bf7 | 3704 | fs_initcall_sync(pci_apply_final_quirks); |
b9c3b266 DC |
3705 | |
3706 | /* | |
4091fb95 | 3707 | * Following are device-specific reset methods which can be used to |
b9c3b266 DC |
3708 | * reset a single function if other methods (e.g. FLR, PM D0->D3) are |
3709 | * not available. | |
3710 | */ | |
c763e7b5 DC |
3711 | static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe) |
3712 | { | |
76b57c67 BH |
3713 | /* |
3714 | * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf | |
3715 | * | |
3716 | * The 82599 supports FLR on VFs, but FLR support is reported only | |
3717 | * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5). | |
c8d8096a CH |
3718 | * Thus we must call pcie_flr() directly without first checking if it is |
3719 | * supported. | |
76b57c67 | 3720 | */ |
c8d8096a CH |
3721 | if (!probe) |
3722 | pcie_flr(dev); | |
c763e7b5 DC |
3723 | return 0; |
3724 | } | |
3725 | ||
aba72ddc VS |
3726 | #define SOUTH_CHICKEN2 0xc2004 |
3727 | #define PCH_PP_STATUS 0xc7200 | |
3728 | #define PCH_PP_CONTROL 0xc7204 | |
df558de1 XH |
3729 | #define MSG_CTL 0x45010 |
3730 | #define NSDE_PWR_STATE 0xd0100 | |
3731 | #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */ | |
3732 | ||
3733 | static int reset_ivb_igd(struct pci_dev *dev, int probe) | |
3734 | { | |
3735 | void __iomem *mmio_base; | |
3736 | unsigned long timeout; | |
3737 | u32 val; | |
3738 | ||
3739 | if (probe) | |
3740 | return 0; | |
3741 | ||
3742 | mmio_base = pci_iomap(dev, 0, 0); | |
3743 | if (!mmio_base) | |
3744 | return -ENOMEM; | |
3745 | ||
3746 | iowrite32(0x00000002, mmio_base + MSG_CTL); | |
3747 | ||
3748 | /* | |
3749 | * Clobbering SOUTH_CHICKEN2 register is fine only if the next | |
3750 | * driver loaded sets the right bits. However, this's a reset and | |
3751 | * the bits have been set by i915 previously, so we clobber | |
3752 | * SOUTH_CHICKEN2 register directly here. | |
3753 | */ | |
3754 | iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2); | |
3755 | ||
3756 | val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe; | |
3757 | iowrite32(val, mmio_base + PCH_PP_CONTROL); | |
3758 | ||
3759 | timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT); | |
3760 | do { | |
3761 | val = ioread32(mmio_base + PCH_PP_STATUS); | |
3762 | if ((val & 0xb0000000) == 0) | |
3763 | goto reset_complete; | |
3764 | msleep(10); | |
3765 | } while (time_before(jiffies, timeout)); | |
3766 | dev_warn(&dev->dev, "timeout during reset\n"); | |
3767 | ||
3768 | reset_complete: | |
3769 | iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE); | |
3770 | ||
3771 | pci_iounmap(dev, mmio_base); | |
3772 | return 0; | |
3773 | } | |
3774 | ||
2c6217e0 CL |
3775 | /* |
3776 | * Device-specific reset method for Chelsio T4-based adapters. | |
3777 | */ | |
3778 | static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe) | |
3779 | { | |
3780 | u16 old_command; | |
3781 | u16 msix_flags; | |
3782 | ||
3783 | /* | |
3784 | * If this isn't a Chelsio T4-based device, return -ENOTTY indicating | |
3785 | * that we have no device-specific reset method. | |
3786 | */ | |
3787 | if ((dev->device & 0xf000) != 0x4000) | |
3788 | return -ENOTTY; | |
3789 | ||
3790 | /* | |
3791 | * If this is the "probe" phase, return 0 indicating that we can | |
3792 | * reset this device. | |
3793 | */ | |
3794 | if (probe) | |
3795 | return 0; | |
3796 | ||
3797 | /* | |
3798 | * T4 can wedge if there are DMAs in flight within the chip and Bus | |
3799 | * Master has been disabled. We need to have it on till the Function | |
3800 | * Level Reset completes. (BUS_MASTER is disabled in | |
3801 | * pci_reset_function()). | |
3802 | */ | |
3803 | pci_read_config_word(dev, PCI_COMMAND, &old_command); | |
3804 | pci_write_config_word(dev, PCI_COMMAND, | |
3805 | old_command | PCI_COMMAND_MASTER); | |
3806 | ||
3807 | /* | |
3808 | * Perform the actual device function reset, saving and restoring | |
3809 | * configuration information around the reset. | |
3810 | */ | |
3811 | pci_save_state(dev); | |
3812 | ||
3813 | /* | |
3814 | * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts | |
3815 | * are disabled when an MSI-X interrupt message needs to be delivered. | |
3816 | * So we briefly re-enable MSI-X interrupts for the duration of the | |
3817 | * FLR. The pci_restore_state() below will restore the original | |
3818 | * MSI-X state. | |
3819 | */ | |
3820 | pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags); | |
3821 | if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0) | |
3822 | pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, | |
3823 | msix_flags | | |
3824 | PCI_MSIX_FLAGS_ENABLE | | |
3825 | PCI_MSIX_FLAGS_MASKALL); | |
3826 | ||
48f52d1a | 3827 | pcie_flr(dev); |
2c6217e0 CL |
3828 | |
3829 | /* | |
3830 | * Restore the configuration information (BAR values, etc.) including | |
3831 | * the original PCI Configuration Space Command word, and return | |
3832 | * success. | |
3833 | */ | |
3834 | pci_restore_state(dev); | |
3835 | pci_write_config_word(dev, PCI_COMMAND, old_command); | |
3836 | return 0; | |
3837 | } | |
3838 | ||
c763e7b5 | 3839 | #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed |
df558de1 XH |
3840 | #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156 |
3841 | #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166 | |
c763e7b5 | 3842 | |
5b889bf2 | 3843 | static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { |
c763e7b5 DC |
3844 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF, |
3845 | reset_intel_82599_sfp_virtfn }, | |
df558de1 XH |
3846 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA, |
3847 | reset_ivb_igd }, | |
3848 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA, | |
3849 | reset_ivb_igd }, | |
2c6217e0 CL |
3850 | { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, |
3851 | reset_chelsio_generic_dev }, | |
b9c3b266 DC |
3852 | { 0 } |
3853 | }; | |
5b889bf2 | 3854 | |
df558de1 XH |
3855 | /* |
3856 | * These device-specific reset methods are here rather than in a driver | |
3857 | * because when a host assigns a device to a guest VM, the host may need | |
3858 | * to reset the device but probably doesn't have a driver for it. | |
3859 | */ | |
5b889bf2 RW |
3860 | int pci_dev_specific_reset(struct pci_dev *dev, int probe) |
3861 | { | |
df9d1e8a | 3862 | const struct pci_dev_reset_methods *i; |
5b889bf2 RW |
3863 | |
3864 | for (i = pci_dev_reset_methods; i->reset; i++) { | |
3865 | if ((i->vendor == dev->vendor || | |
3866 | i->vendor == (u16)PCI_ANY_ID) && | |
3867 | (i->device == dev->device || | |
3868 | i->device == (u16)PCI_ANY_ID)) | |
3869 | return i->reset(dev, probe); | |
3870 | } | |
3871 | ||
3872 | return -ENOTTY; | |
3873 | } | |
12ea6cad | 3874 | |
ec637fb2 AW |
3875 | static void quirk_dma_func0_alias(struct pci_dev *dev) |
3876 | { | |
f0af9593 BH |
3877 | if (PCI_FUNC(dev->devfn) != 0) |
3878 | pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0)); | |
ec637fb2 AW |
3879 | } |
3880 | ||
3881 | /* | |
3882 | * https://bugzilla.redhat.com/show_bug.cgi?id=605888 | |
3883 | * | |
3884 | * Some Ricoh devices use function 0 as the PCIe requester ID for DMA. | |
3885 | */ | |
3886 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias); | |
3887 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias); | |
3888 | ||
cc346a47 AW |
3889 | static void quirk_dma_func1_alias(struct pci_dev *dev) |
3890 | { | |
f0af9593 BH |
3891 | if (PCI_FUNC(dev->devfn) != 1) |
3892 | pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1)); | |
cc346a47 AW |
3893 | } |
3894 | ||
3895 | /* | |
3896 | * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some | |
3897 | * SKUs function 1 is present and is a legacy IDE controller, in other | |
3898 | * SKUs this function is not present, making this a ghost requester. | |
3899 | * https://bugzilla.kernel.org/show_bug.cgi?id=42679 | |
3900 | */ | |
247de694 SA |
3901 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120, |
3902 | quirk_dma_func1_alias); | |
cc346a47 AW |
3903 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123, |
3904 | quirk_dma_func1_alias); | |
76aedc42 AW |
3905 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128, |
3906 | quirk_dma_func1_alias); | |
cc346a47 AW |
3907 | /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */ |
3908 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130, | |
3909 | quirk_dma_func1_alias); | |
3910 | /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */ | |
3911 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172, | |
3912 | quirk_dma_func1_alias); | |
3913 | /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */ | |
3914 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a, | |
3915 | quirk_dma_func1_alias); | |
00456b35 AS |
3916 | /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */ |
3917 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182, | |
3918 | quirk_dma_func1_alias); | |
cc346a47 AW |
3919 | /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */ |
3920 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0, | |
3921 | quirk_dma_func1_alias); | |
c1ce08b7 TVC |
3922 | /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */ |
3923 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220, | |
3924 | quirk_dma_func1_alias); | |
cc346a47 AW |
3925 | /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */ |
3926 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230, | |
3927 | quirk_dma_func1_alias); | |
c2e0fb96 JC |
3928 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642, |
3929 | quirk_dma_func1_alias); | |
c5afa2a9 HG |
3930 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645, |
3931 | quirk_dma_func1_alias); | |
cc346a47 AW |
3932 | /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */ |
3933 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON, | |
3934 | PCI_DEVICE_ID_JMICRON_JMB388_ESD, | |
3935 | quirk_dma_func1_alias); | |
8b9b963e TS |
3936 | /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */ |
3937 | DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */ | |
3938 | 0x0122, /* Plextor M6E (Marvell 88SS9183)*/ | |
3939 | quirk_dma_func1_alias); | |
cc346a47 | 3940 | |
d3d2ab43 AW |
3941 | /* |
3942 | * Some devices DMA with the wrong devfn, not just the wrong function. | |
3943 | * quirk_fixed_dma_alias() uses this table to create fixed aliases, where | |
3944 | * the alias is "fixed" and independent of the device devfn. | |
3945 | * | |
3946 | * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O | |
3947 | * processor. To software, this appears as a PCIe-to-PCI/X bridge with a | |
3948 | * single device on the secondary bus. In reality, the single exposed | |
3949 | * device at 0e.0 is the Address Translation Unit (ATU) of the controller | |
3950 | * that provides a bridge to the internal bus of the I/O processor. The | |
3951 | * controller supports private devices, which can be hidden from PCI config | |
3952 | * space. In the case of the Adaptec 3405, a private device at 01.0 | |
3953 | * appears to be the DMA engine, which therefore needs to become a DMA | |
3954 | * alias for the device. | |
3955 | */ | |
3956 | static const struct pci_device_id fixed_dma_alias_tbl[] = { | |
3957 | { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, | |
3958 | PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */ | |
3959 | .driver_data = PCI_DEVFN(1, 0) }, | |
db83f87b AW |
3960 | { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, |
3961 | PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */ | |
3962 | .driver_data = PCI_DEVFN(1, 0) }, | |
d3d2ab43 AW |
3963 | { 0 } |
3964 | }; | |
3965 | ||
3966 | static void quirk_fixed_dma_alias(struct pci_dev *dev) | |
3967 | { | |
3968 | const struct pci_device_id *id; | |
3969 | ||
3970 | id = pci_match_id(fixed_dma_alias_tbl, dev); | |
48c83080 | 3971 | if (id) |
f0af9593 | 3972 | pci_add_dma_alias(dev, id->driver_data); |
d3d2ab43 AW |
3973 | } |
3974 | ||
3975 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias); | |
3976 | ||
ebdb51eb AW |
3977 | /* |
3978 | * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in | |
3979 | * using the wrong DMA alias for the device. Some of these devices can be | |
3980 | * used as either forward or reverse bridges, so we need to test whether the | |
3981 | * device is operating in the correct mode. We could probably apply this | |
3982 | * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test | |
3983 | * is for a non-root, non-PCIe bridge where the upstream device is PCIe and | |
3984 | * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge. | |
3985 | */ | |
3986 | static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev) | |
3987 | { | |
3988 | if (!pci_is_root_bus(pdev->bus) && | |
3989 | pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE && | |
3990 | !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) && | |
3991 | pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE) | |
3992 | pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS; | |
3993 | } | |
3994 | /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */ | |
3995 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080, | |
3996 | quirk_use_pcie_bridge_dma_alias); | |
3997 | /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */ | |
3998 | DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias); | |
98ca50db AW |
3999 | /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */ |
4000 | DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias); | |
fce5d57e JW |
4001 | /* ITE 8893 has the same problem as the 8892 */ |
4002 | DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias); | |
8ab4abbe AW |
4003 | /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */ |
4004 | DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias); | |
ebdb51eb | 4005 | |
b1a928cd JL |
4006 | /* |
4007 | * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to | |
4008 | * be added as aliases to the DMA device in order to allow buffer access | |
4009 | * when IOMMU is enabled. Following devfns have to match RIT-LUT table | |
4010 | * programmed in the EEPROM. | |
4011 | */ | |
4012 | static void quirk_mic_x200_dma_alias(struct pci_dev *pdev) | |
4013 | { | |
4014 | pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0)); | |
4015 | pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0)); | |
4016 | pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3)); | |
4017 | } | |
4018 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias); | |
4019 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias); | |
4020 | ||
45a23293 J |
4021 | /* |
4022 | * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are | |
4023 | * associated not at the root bus, but at a bridge below. This quirk avoids | |
4024 | * generating invalid DMA aliases. | |
4025 | */ | |
4026 | static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev) | |
4027 | { | |
4028 | pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT; | |
4029 | } | |
4030 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000, | |
4031 | quirk_bridge_cavm_thrx2_pcie_root); | |
4032 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084, | |
4033 | quirk_bridge_cavm_thrx2_pcie_root); | |
4034 | ||
3657cebd KHC |
4035 | /* |
4036 | * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero) | |
4037 | * class code. Fix it. | |
4038 | */ | |
4039 | static void quirk_tw686x_class(struct pci_dev *pdev) | |
4040 | { | |
4041 | u32 class = pdev->class; | |
4042 | ||
4043 | /* Use "Multimedia controller" class */ | |
4044 | pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01; | |
4045 | dev_info(&pdev->dev, "TW686x PCI class overridden (%#08x -> %#08x)\n", | |
4046 | class, pdev->class); | |
4047 | } | |
2b4aed1d | 4048 | DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8, |
3657cebd | 4049 | quirk_tw686x_class); |
2b4aed1d | 4050 | DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8, |
3657cebd | 4051 | quirk_tw686x_class); |
2b4aed1d | 4052 | DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8, |
3657cebd | 4053 | quirk_tw686x_class); |
2b4aed1d | 4054 | DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8, |
3657cebd KHC |
4055 | quirk_tw686x_class); |
4056 | ||
a99b646a | 4057 | /* |
4058 | * Some devices have problems with Transaction Layer Packets with the Relaxed | |
4059 | * Ordering Attribute set. Such devices should mark themselves and other | |
4060 | * Device Drivers should check before sending TLPs with RO set. | |
4061 | */ | |
4062 | static void quirk_relaxedordering_disable(struct pci_dev *dev) | |
4063 | { | |
4064 | dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING; | |
4065 | dev_info(&dev->dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n"); | |
4066 | } | |
4067 | ||
87e09cde | 4068 | /* |
4069 | * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root | |
4070 | * Complex has a Flow Control Credit issue which can cause performance | |
4071 | * problems with Upstream Transaction Layer Packets with Relaxed Ordering set. | |
4072 | */ | |
4073 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8, | |
4074 | quirk_relaxedordering_disable); | |
4075 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8, | |
4076 | quirk_relaxedordering_disable); | |
4077 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8, | |
4078 | quirk_relaxedordering_disable); | |
4079 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8, | |
4080 | quirk_relaxedordering_disable); | |
4081 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8, | |
4082 | quirk_relaxedordering_disable); | |
4083 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8, | |
4084 | quirk_relaxedordering_disable); | |
4085 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8, | |
4086 | quirk_relaxedordering_disable); | |
4087 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8, | |
4088 | quirk_relaxedordering_disable); | |
4089 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8, | |
4090 | quirk_relaxedordering_disable); | |
4091 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8, | |
4092 | quirk_relaxedordering_disable); | |
4093 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8, | |
4094 | quirk_relaxedordering_disable); | |
4095 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8, | |
4096 | quirk_relaxedordering_disable); | |
4097 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8, | |
4098 | quirk_relaxedordering_disable); | |
4099 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8, | |
4100 | quirk_relaxedordering_disable); | |
4101 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8, | |
4102 | quirk_relaxedordering_disable); | |
4103 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8, | |
4104 | quirk_relaxedordering_disable); | |
4105 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8, | |
4106 | quirk_relaxedordering_disable); | |
4107 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8, | |
4108 | quirk_relaxedordering_disable); | |
4109 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8, | |
4110 | quirk_relaxedordering_disable); | |
4111 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8, | |
4112 | quirk_relaxedordering_disable); | |
4113 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8, | |
4114 | quirk_relaxedordering_disable); | |
4115 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8, | |
4116 | quirk_relaxedordering_disable); | |
4117 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8, | |
4118 | quirk_relaxedordering_disable); | |
4119 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8, | |
4120 | quirk_relaxedordering_disable); | |
4121 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8, | |
4122 | quirk_relaxedordering_disable); | |
4123 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8, | |
4124 | quirk_relaxedordering_disable); | |
4125 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8, | |
4126 | quirk_relaxedordering_disable); | |
4127 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8, | |
4128 | quirk_relaxedordering_disable); | |
4129 | ||
077fa19c | 4130 | /* |
4131 | * The AMD ARM A1100 (AKA "SEATTLE") SoC has a bug in its PCIe Root Complex | |
4132 | * where Upstream Transaction Layer Packets with the Relaxed Ordering | |
4133 | * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering | |
4134 | * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules | |
4135 | * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0 | |
4136 | * November 10, 2010). As a result, on this platform we can't use Relaxed | |
4137 | * Ordering for Upstream TLPs. | |
4138 | */ | |
4139 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8, | |
4140 | quirk_relaxedordering_disable); | |
4141 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8, | |
4142 | quirk_relaxedordering_disable); | |
4143 | DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8, | |
4144 | quirk_relaxedordering_disable); | |
4145 | ||
c56d4450 HS |
4146 | /* |
4147 | * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same | |
4148 | * values for the Attribute as were supplied in the header of the | |
4149 | * corresponding Request, except as explicitly allowed when IDO is used." | |
4150 | * | |
4151 | * If a non-compliant device generates a completion with a different | |
4152 | * attribute than the request, the receiver may accept it (which itself | |
4153 | * seems non-compliant based on sec 2.3.2), or it may handle it as a | |
4154 | * Malformed TLP or an Unexpected Completion, which will probably lead to a | |
4155 | * device access timeout. | |
4156 | * | |
4157 | * If the non-compliant device generates completions with zero attributes | |
4158 | * (instead of copying the attributes from the request), we can work around | |
4159 | * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in | |
4160 | * upstream devices so they always generate requests with zero attributes. | |
4161 | * | |
4162 | * This affects other devices under the same Root Port, but since these | |
4163 | * attributes are performance hints, there should be no functional problem. | |
4164 | * | |
4165 | * Note that Configuration Space accesses are never supposed to have TLP | |
4166 | * Attributes, so we're safe waiting till after any Configuration Space | |
4167 | * accesses to do the Root Port fixup. | |
4168 | */ | |
4169 | static void quirk_disable_root_port_attributes(struct pci_dev *pdev) | |
4170 | { | |
4171 | struct pci_dev *root_port = pci_find_pcie_root_port(pdev); | |
4172 | ||
4173 | if (!root_port) { | |
4174 | dev_warn(&pdev->dev, "PCIe Completion erratum may cause device errors\n"); | |
4175 | return; | |
4176 | } | |
4177 | ||
4178 | dev_info(&root_port->dev, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n", | |
4179 | dev_name(&pdev->dev)); | |
4180 | pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL, | |
4181 | PCI_EXP_DEVCTL_RELAX_EN | | |
4182 | PCI_EXP_DEVCTL_NOSNOOP_EN, 0); | |
4183 | } | |
4184 | ||
4185 | /* | |
4186 | * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the | |
4187 | * Completion it generates. | |
4188 | */ | |
4189 | static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev) | |
4190 | { | |
4191 | /* | |
4192 | * This mask/compare operation selects for Physical Function 4 on a | |
4193 | * T5. We only need to fix up the Root Port once for any of the | |
4194 | * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely | |
4195 | * 0x54xx so we use that one, | |
4196 | */ | |
4197 | if ((pdev->device & 0xff00) == 0x5400) | |
4198 | quirk_disable_root_port_attributes(pdev); | |
4199 | } | |
4200 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, | |
4201 | quirk_chelsio_T5_disable_root_port_attributes); | |
4202 | ||
15b100df AW |
4203 | /* |
4204 | * AMD has indicated that the devices below do not support peer-to-peer | |
4205 | * in any system where they are found in the southbridge with an AMD | |
4206 | * IOMMU in the system. Multifunction devices that do not support | |
4207 | * peer-to-peer between functions can claim to support a subset of ACS. | |
4208 | * Such devices effectively enable request redirect (RR) and completion | |
4209 | * redirect (CR) since all transactions are redirected to the upstream | |
4210 | * root complex. | |
4211 | * | |
4212 | * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086 | |
4213 | * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102 | |
4214 | * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402 | |
4215 | * | |
4216 | * 1002:4385 SBx00 SMBus Controller | |
4217 | * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller | |
4218 | * 1002:4383 SBx00 Azalia (Intel HDA) | |
4219 | * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller | |
4220 | * 1002:4384 SBx00 PCI to PCI Bridge | |
4221 | * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller | |
3587e625 MR |
4222 | * |
4223 | * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15 | |
4224 | * | |
4225 | * 1022:780f [AMD] FCH PCI Bridge | |
4226 | * 1022:7809 [AMD] FCH USB OHCI Controller | |
15b100df AW |
4227 | */ |
4228 | static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags) | |
4229 | { | |
4230 | #ifdef CONFIG_ACPI | |
4231 | struct acpi_table_header *header = NULL; | |
4232 | acpi_status status; | |
4233 | ||
4234 | /* Targeting multifunction devices on the SB (appears on root bus) */ | |
4235 | if (!dev->multifunction || !pci_is_root_bus(dev->bus)) | |
4236 | return -ENODEV; | |
4237 | ||
4238 | /* The IVRS table describes the AMD IOMMU */ | |
4239 | status = acpi_get_table("IVRS", 0, &header); | |
4240 | if (ACPI_FAILURE(status)) | |
4241 | return -ENODEV; | |
4242 | ||
4243 | /* Filter out flags not applicable to multifunction */ | |
4244 | acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT); | |
4245 | ||
4246 | return acs_flags & ~(PCI_ACS_RR | PCI_ACS_CR) ? 0 : 1; | |
4247 | #else | |
4248 | return -ENODEV; | |
4249 | #endif | |
4250 | } | |
4251 | ||
f2ddaf8d VL |
4252 | static bool pci_quirk_cavium_acs_match(struct pci_dev *dev) |
4253 | { | |
4254 | /* | |
4255 | * Effectively selects all downstream ports for whole ThunderX 1 | |
4256 | * family by 0xf800 mask (which represents 8 SoCs), while the lower | |
4257 | * bits of device ID are used to indicate which subdevice is used | |
4258 | * within the SoC. | |
4259 | */ | |
4260 | return (pci_is_pcie(dev) && | |
4261 | (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) && | |
4262 | ((dev->device & 0xf800) == 0xa000)); | |
4263 | } | |
4264 | ||
b404bcfb MJ |
4265 | static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags) |
4266 | { | |
4267 | /* | |
7f342678 VL |
4268 | * Cavium root ports don't advertise an ACS capability. However, |
4269 | * the RTL internally implements similar protection as if ACS had | |
4270 | * Request Redirection, Completion Redirection, Source Validation, | |
4271 | * and Upstream Forwarding features enabled. Assert that the | |
4272 | * hardware implements and enables equivalent ACS functionality for | |
4273 | * these flags. | |
b404bcfb | 4274 | */ |
7f342678 | 4275 | acs_flags &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_SV | PCI_ACS_UF); |
b404bcfb | 4276 | |
f2ddaf8d | 4277 | if (!pci_quirk_cavium_acs_match(dev)) |
b77d537d MJ |
4278 | return -ENOTTY; |
4279 | ||
b404bcfb MJ |
4280 | return acs_flags ? 0 : 1; |
4281 | } | |
4282 | ||
a0418aa2 FK |
4283 | static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags) |
4284 | { | |
4285 | /* | |
4286 | * X-Gene root matching this quirk do not allow peer-to-peer | |
4287 | * transactions with others, allowing masking out these bits as if they | |
4288 | * were unimplemented in the ACS capability. | |
4289 | */ | |
4290 | acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); | |
4291 | ||
4292 | return acs_flags ? 0 : 1; | |
4293 | } | |
4294 | ||
d99321b6 AW |
4295 | /* |
4296 | * Many Intel PCH root ports do provide ACS-like features to disable peer | |
4297 | * transactions and validate bus numbers in requests, but do not provide an | |
4298 | * actual PCIe ACS capability. This is the list of device IDs known to fall | |
4299 | * into that category as provided by Intel in Red Hat bugzilla 1037684. | |
4300 | */ | |
4301 | static const u16 pci_quirk_intel_pch_acs_ids[] = { | |
4302 | /* Ibexpeak PCH */ | |
4303 | 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49, | |
4304 | 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51, | |
4305 | /* Cougarpoint PCH */ | |
4306 | 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17, | |
4307 | 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f, | |
4308 | /* Pantherpoint PCH */ | |
4309 | 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17, | |
4310 | 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f, | |
4311 | /* Lynxpoint-H PCH */ | |
4312 | 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17, | |
4313 | 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f, | |
4314 | /* Lynxpoint-LP PCH */ | |
4315 | 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17, | |
4316 | 0x9c18, 0x9c19, 0x9c1a, 0x9c1b, | |
4317 | /* Wildcat PCH */ | |
4318 | 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97, | |
4319 | 0x9c98, 0x9c99, 0x9c9a, 0x9c9b, | |
1a30fd0d AW |
4320 | /* Patsburg (X79) PCH */ |
4321 | 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e, | |
78e88358 AW |
4322 | /* Wellsburg (X99) PCH */ |
4323 | 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17, | |
4324 | 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e, | |
dca230d1 AW |
4325 | /* Lynx Point (9 series) PCH */ |
4326 | 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e, | |
d99321b6 AW |
4327 | }; |
4328 | ||
4329 | static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev) | |
4330 | { | |
4331 | int i; | |
4332 | ||
4333 | /* Filter out a few obvious non-matches first */ | |
4334 | if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) | |
4335 | return false; | |
4336 | ||
4337 | for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++) | |
4338 | if (pci_quirk_intel_pch_acs_ids[i] == dev->device) | |
4339 | return true; | |
4340 | ||
4341 | return false; | |
4342 | } | |
4343 | ||
4344 | #define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV) | |
4345 | ||
4346 | static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags) | |
4347 | { | |
4348 | u16 flags = dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK ? | |
4349 | INTEL_PCH_ACS_FLAGS : 0; | |
4350 | ||
4351 | if (!pci_quirk_intel_pch_acs_match(dev)) | |
4352 | return -ENOTTY; | |
4353 | ||
4354 | return acs_flags & ~flags ? 0 : 1; | |
4355 | } | |
4356 | ||
33be632b SK |
4357 | /* |
4358 | * These QCOM root ports do provide ACS-like features to disable peer | |
4359 | * transactions and validate bus numbers in requests, but do not provide an | |
4360 | * actual PCIe ACS capability. Hardware supports source validation but it | |
4361 | * will report the issue as Completer Abort instead of ACS Violation. | |
4362 | * Hardware doesn't support peer-to-peer and each root port is a root | |
4363 | * complex with unique segment numbers. It is not possible for one root | |
4364 | * port to pass traffic to another root port. All PCIe transactions are | |
4365 | * terminated inside the root port. | |
4366 | */ | |
4367 | static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags) | |
4368 | { | |
4369 | u16 flags = (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV); | |
4370 | int ret = acs_flags & ~flags ? 0 : 1; | |
4371 | ||
4372 | dev_info(&dev->dev, "Using QCOM ACS Quirk (%d)\n", ret); | |
4373 | ||
4374 | return ret; | |
4375 | } | |
4376 | ||
1bf2bf22 AW |
4377 | /* |
4378 | * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in | |
4379 | * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2, | |
4380 | * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and | |
4381 | * control registers whereas the PCIe spec packs them into words (Rev 3.0, | |
4382 | * 7.16 ACS Extended Capability). The bit definitions are correct, but the | |
4383 | * control register is at offset 8 instead of 6 and we should probably use | |
4384 | * dword accesses to them. This applies to the following PCI Device IDs, as | |
4385 | * found in volume 1 of the datasheet[2]: | |
4386 | * | |
4387 | * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16} | |
4388 | * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20} | |
4389 | * | |
4390 | * N.B. This doesn't fix what lspci shows. | |
4391 | * | |
7184f5b4 AW |
4392 | * The 100 series chipset specification update includes this as errata #23[3]. |
4393 | * | |
4394 | * The 200 series chipset (Union Point) has the same bug according to the | |
4395 | * specification update (Intel 200 Series Chipset Family Platform Controller | |
4396 | * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001, | |
4397 | * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this | |
4398 | * chipset include: | |
4399 | * | |
4400 | * 0xa290-0xa29f PCI Express Root port #{0-16} | |
4401 | * 0xa2e7-0xa2ee PCI Express Root port #{17-24} | |
4402 | * | |
1bf2bf22 AW |
4403 | * [1] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html |
4404 | * [2] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html | |
7184f5b4 AW |
4405 | * [3] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html |
4406 | * [4] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html | |
4407 | * [5] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html | |
1bf2bf22 AW |
4408 | */ |
4409 | static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev) | |
4410 | { | |
7184f5b4 AW |
4411 | if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) |
4412 | return false; | |
4413 | ||
4414 | switch (dev->device) { | |
4415 | case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */ | |
4416 | case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */ | |
4417 | return true; | |
4418 | } | |
4419 | ||
4420 | return false; | |
1bf2bf22 AW |
4421 | } |
4422 | ||
4423 | #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4) | |
4424 | ||
4425 | static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags) | |
4426 | { | |
4427 | int pos; | |
4428 | u32 cap, ctrl; | |
4429 | ||
4430 | if (!pci_quirk_intel_spt_pch_acs_match(dev)) | |
4431 | return -ENOTTY; | |
4432 | ||
4433 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); | |
4434 | if (!pos) | |
4435 | return -ENOTTY; | |
4436 | ||
4437 | /* see pci_acs_flags_enabled() */ | |
4438 | pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); | |
4439 | acs_flags &= (cap | PCI_ACS_EC); | |
4440 | ||
4441 | pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); | |
4442 | ||
4443 | return acs_flags & ~ctrl ? 0 : 1; | |
4444 | } | |
4445 | ||
100ebb2c | 4446 | static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags) |
89b51cb5 AW |
4447 | { |
4448 | /* | |
4449 | * SV, TB, and UF are not relevant to multifunction endpoints. | |
4450 | * | |
100ebb2c AW |
4451 | * Multifunction devices are only required to implement RR, CR, and DT |
4452 | * in their ACS capability if they support peer-to-peer transactions. | |
4453 | * Devices matching this quirk have been verified by the vendor to not | |
4454 | * perform peer-to-peer with other functions, allowing us to mask out | |
4455 | * these bits as if they were unimplemented in the ACS capability. | |
89b51cb5 AW |
4456 | */ |
4457 | acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR | | |
4458 | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT); | |
4459 | ||
4460 | return acs_flags ? 0 : 1; | |
4461 | } | |
4462 | ||
ad805758 AW |
4463 | static const struct pci_dev_acs_enabled { |
4464 | u16 vendor; | |
4465 | u16 device; | |
4466 | int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags); | |
4467 | } pci_dev_acs_enabled[] = { | |
15b100df AW |
4468 | { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs }, |
4469 | { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs }, | |
4470 | { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs }, | |
4471 | { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs }, | |
4472 | { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs }, | |
4473 | { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs }, | |
3587e625 MR |
4474 | { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs }, |
4475 | { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs }, | |
100ebb2c AW |
4476 | { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs }, |
4477 | { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs }, | |
9fad4012 | 4478 | { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs }, |
100ebb2c AW |
4479 | { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs }, |
4480 | { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs }, | |
4481 | { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs }, | |
4482 | { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs }, | |
4483 | { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs }, | |
4484 | { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs }, | |
4485 | { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs }, | |
4486 | { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs }, | |
4487 | { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs }, | |
4488 | { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs }, | |
4489 | { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs }, | |
4490 | { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs }, | |
4491 | { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs }, | |
4492 | { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs }, | |
4493 | { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs }, | |
4494 | { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs }, | |
4495 | { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs }, | |
4496 | { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs }, | |
4497 | { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs }, | |
4498 | { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs }, | |
d748804f AW |
4499 | /* 82580 */ |
4500 | { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs }, | |
4501 | { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs }, | |
4502 | { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs }, | |
4503 | { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs }, | |
4504 | { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs }, | |
4505 | { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs }, | |
4506 | { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs }, | |
4507 | /* 82576 */ | |
4508 | { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs }, | |
4509 | { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs }, | |
4510 | { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs }, | |
4511 | { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs }, | |
4512 | { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs }, | |
4513 | { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs }, | |
4514 | { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs }, | |
4515 | { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs }, | |
4516 | /* 82575 */ | |
4517 | { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs }, | |
4518 | { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs }, | |
4519 | { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs }, | |
4520 | /* I350 */ | |
4521 | { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs }, | |
4522 | { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs }, | |
4523 | { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs }, | |
4524 | { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs }, | |
4525 | /* 82571 (Quads omitted due to non-ACS switch) */ | |
4526 | { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs }, | |
4527 | { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs }, | |
4528 | { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs }, | |
4529 | { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs }, | |
95e16587 AW |
4530 | /* I219 */ |
4531 | { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs }, | |
4532 | { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs }, | |
33be632b SK |
4533 | /* QCOM QDF2xxx root ports */ |
4534 | { 0x17cb, 0x400, pci_quirk_qcom_rp_acs }, | |
4535 | { 0x17cb, 0x401, pci_quirk_qcom_rp_acs }, | |
d748804f | 4536 | /* Intel PCH root ports */ |
d99321b6 | 4537 | { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs }, |
1bf2bf22 | 4538 | { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs }, |
6a3763d1 VV |
4539 | { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */ |
4540 | { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */ | |
b404bcfb MJ |
4541 | /* Cavium ThunderX */ |
4542 | { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs }, | |
a0418aa2 FK |
4543 | /* APM X-Gene */ |
4544 | { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs }, | |
ad805758 AW |
4545 | { 0 } |
4546 | }; | |
4547 | ||
4548 | int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags) | |
4549 | { | |
4550 | const struct pci_dev_acs_enabled *i; | |
4551 | int ret; | |
4552 | ||
4553 | /* | |
4554 | * Allow devices that do not expose standard PCIe ACS capabilities | |
4555 | * or control to indicate their support here. Multi-function express | |
4556 | * devices which do not allow internal peer-to-peer between functions, | |
4557 | * but do not implement PCIe ACS may wish to return true here. | |
4558 | */ | |
4559 | for (i = pci_dev_acs_enabled; i->acs_enabled; i++) { | |
4560 | if ((i->vendor == dev->vendor || | |
4561 | i->vendor == (u16)PCI_ANY_ID) && | |
4562 | (i->device == dev->device || | |
4563 | i->device == (u16)PCI_ANY_ID)) { | |
4564 | ret = i->acs_enabled(dev, acs_flags); | |
4565 | if (ret >= 0) | |
4566 | return ret; | |
4567 | } | |
4568 | } | |
4569 | ||
4570 | return -ENOTTY; | |
4571 | } | |
2c744244 | 4572 | |
d99321b6 AW |
4573 | /* Config space offset of Root Complex Base Address register */ |
4574 | #define INTEL_LPC_RCBA_REG 0xf0 | |
4575 | /* 31:14 RCBA address */ | |
4576 | #define INTEL_LPC_RCBA_MASK 0xffffc000 | |
4577 | /* RCBA Enable */ | |
4578 | #define INTEL_LPC_RCBA_ENABLE (1 << 0) | |
4579 | ||
4580 | /* Backbone Scratch Pad Register */ | |
4581 | #define INTEL_BSPR_REG 0x1104 | |
4582 | /* Backbone Peer Non-Posted Disable */ | |
4583 | #define INTEL_BSPR_REG_BPNPD (1 << 8) | |
4584 | /* Backbone Peer Posted Disable */ | |
4585 | #define INTEL_BSPR_REG_BPPD (1 << 9) | |
4586 | ||
4587 | /* Upstream Peer Decode Configuration Register */ | |
4588 | #define INTEL_UPDCR_REG 0x1114 | |
4589 | /* 5:0 Peer Decode Enable bits */ | |
4590 | #define INTEL_UPDCR_REG_MASK 0x3f | |
4591 | ||
4592 | static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev) | |
4593 | { | |
4594 | u32 rcba, bspr, updcr; | |
4595 | void __iomem *rcba_mem; | |
4596 | ||
4597 | /* | |
4598 | * Read the RCBA register from the LPC (D31:F0). PCH root ports | |
4599 | * are D28:F* and therefore get probed before LPC, thus we can't | |
4600 | * use pci_get_slot/pci_read_config_dword here. | |
4601 | */ | |
4602 | pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0), | |
4603 | INTEL_LPC_RCBA_REG, &rcba); | |
4604 | if (!(rcba & INTEL_LPC_RCBA_ENABLE)) | |
4605 | return -EINVAL; | |
4606 | ||
4607 | rcba_mem = ioremap_nocache(rcba & INTEL_LPC_RCBA_MASK, | |
4608 | PAGE_ALIGN(INTEL_UPDCR_REG)); | |
4609 | if (!rcba_mem) | |
4610 | return -ENOMEM; | |
4611 | ||
4612 | /* | |
4613 | * The BSPR can disallow peer cycles, but it's set by soft strap and | |
4614 | * therefore read-only. If both posted and non-posted peer cycles are | |
4615 | * disallowed, we're ok. If either are allowed, then we need to use | |
4616 | * the UPDCR to disable peer decodes for each port. This provides the | |
4617 | * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | |
4618 | */ | |
4619 | bspr = readl(rcba_mem + INTEL_BSPR_REG); | |
4620 | bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD; | |
4621 | if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) { | |
4622 | updcr = readl(rcba_mem + INTEL_UPDCR_REG); | |
4623 | if (updcr & INTEL_UPDCR_REG_MASK) { | |
4624 | dev_info(&dev->dev, "Disabling UPDCR peer decodes\n"); | |
4625 | updcr &= ~INTEL_UPDCR_REG_MASK; | |
4626 | writel(updcr, rcba_mem + INTEL_UPDCR_REG); | |
4627 | } | |
4628 | } | |
4629 | ||
4630 | iounmap(rcba_mem); | |
4631 | return 0; | |
4632 | } | |
4633 | ||
4634 | /* Miscellaneous Port Configuration register */ | |
4635 | #define INTEL_MPC_REG 0xd8 | |
4636 | /* MPC: Invalid Receive Bus Number Check Enable */ | |
4637 | #define INTEL_MPC_REG_IRBNCE (1 << 26) | |
4638 | ||
4639 | static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev) | |
4640 | { | |
4641 | u32 mpc; | |
4642 | ||
4643 | /* | |
4644 | * When enabled, the IRBNCE bit of the MPC register enables the | |
4645 | * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which | |
4646 | * ensures that requester IDs fall within the bus number range | |
4647 | * of the bridge. Enable if not already. | |
4648 | */ | |
4649 | pci_read_config_dword(dev, INTEL_MPC_REG, &mpc); | |
4650 | if (!(mpc & INTEL_MPC_REG_IRBNCE)) { | |
4651 | dev_info(&dev->dev, "Enabling MPC IRBNCE\n"); | |
4652 | mpc |= INTEL_MPC_REG_IRBNCE; | |
4653 | pci_write_config_word(dev, INTEL_MPC_REG, mpc); | |
4654 | } | |
4655 | } | |
4656 | ||
4657 | static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev) | |
4658 | { | |
4659 | if (!pci_quirk_intel_pch_acs_match(dev)) | |
4660 | return -ENOTTY; | |
4661 | ||
4662 | if (pci_quirk_enable_intel_lpc_acs(dev)) { | |
4663 | dev_warn(&dev->dev, "Failed to enable Intel PCH ACS quirk\n"); | |
4664 | return 0; | |
4665 | } | |
4666 | ||
4667 | pci_quirk_enable_intel_rp_mpc_acs(dev); | |
4668 | ||
4669 | dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK; | |
4670 | ||
4671 | dev_info(&dev->dev, "Intel PCH root port ACS workaround enabled\n"); | |
4672 | ||
4673 | return 0; | |
4674 | } | |
4675 | ||
1bf2bf22 AW |
4676 | static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev) |
4677 | { | |
4678 | int pos; | |
4679 | u32 cap, ctrl; | |
4680 | ||
4681 | if (!pci_quirk_intel_spt_pch_acs_match(dev)) | |
4682 | return -ENOTTY; | |
4683 | ||
4684 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); | |
4685 | if (!pos) | |
4686 | return -ENOTTY; | |
4687 | ||
4688 | pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); | |
4689 | pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); | |
4690 | ||
4691 | ctrl |= (cap & PCI_ACS_SV); | |
4692 | ctrl |= (cap & PCI_ACS_RR); | |
4693 | ctrl |= (cap & PCI_ACS_CR); | |
4694 | ctrl |= (cap & PCI_ACS_UF); | |
4695 | ||
4696 | pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); | |
4697 | ||
4698 | dev_info(&dev->dev, "Intel SPT PCH root port ACS workaround enabled\n"); | |
4699 | ||
4700 | return 0; | |
4701 | } | |
4702 | ||
2c744244 AW |
4703 | static const struct pci_dev_enable_acs { |
4704 | u16 vendor; | |
4705 | u16 device; | |
4706 | int (*enable_acs)(struct pci_dev *dev); | |
4707 | } pci_dev_enable_acs[] = { | |
d99321b6 | 4708 | { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_pch_acs }, |
1bf2bf22 | 4709 | { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_spt_pch_acs }, |
2c744244 AW |
4710 | { 0 } |
4711 | }; | |
4712 | ||
c1d61c9b | 4713 | int pci_dev_specific_enable_acs(struct pci_dev *dev) |
2c744244 AW |
4714 | { |
4715 | const struct pci_dev_enable_acs *i; | |
4716 | int ret; | |
4717 | ||
4718 | for (i = pci_dev_enable_acs; i->enable_acs; i++) { | |
4719 | if ((i->vendor == dev->vendor || | |
4720 | i->vendor == (u16)PCI_ANY_ID) && | |
4721 | (i->device == dev->device || | |
4722 | i->device == (u16)PCI_ANY_ID)) { | |
4723 | ret = i->enable_acs(dev); | |
4724 | if (ret >= 0) | |
c1d61c9b | 4725 | return ret; |
2c744244 AW |
4726 | } |
4727 | } | |
c1d61c9b AW |
4728 | |
4729 | return -ENOTTY; | |
2c744244 | 4730 | } |
3388a614 TS |
4731 | |
4732 | /* | |
4733 | * The PCI capabilities list for Intel DH895xCC VFs (device id 0x0443) with | |
4734 | * QuickAssist Technology (QAT) is prematurely terminated in hardware. The | |
4735 | * Next Capability pointer in the MSI Capability Structure should point to | |
4736 | * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating | |
4737 | * the list. | |
4738 | */ | |
4739 | static void quirk_intel_qat_vf_cap(struct pci_dev *pdev) | |
4740 | { | |
4741 | int pos, i = 0; | |
4742 | u8 next_cap; | |
4743 | u16 reg16, *cap; | |
4744 | struct pci_cap_saved_state *state; | |
4745 | ||
4746 | /* Bail if the hardware bug is fixed */ | |
4747 | if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP)) | |
4748 | return; | |
4749 | ||
4750 | /* Bail if MSI Capability Structure is not found for some reason */ | |
4751 | pos = pci_find_capability(pdev, PCI_CAP_ID_MSI); | |
4752 | if (!pos) | |
4753 | return; | |
4754 | ||
4755 | /* | |
4756 | * Bail if Next Capability pointer in the MSI Capability Structure | |
4757 | * is not the expected incorrect 0x00. | |
4758 | */ | |
4759 | pci_read_config_byte(pdev, pos + 1, &next_cap); | |
4760 | if (next_cap) | |
4761 | return; | |
4762 | ||
4763 | /* | |
4764 | * PCIe Capability Structure is expected to be at 0x50 and should | |
4765 | * terminate the list (Next Capability pointer is 0x00). Verify | |
4766 | * Capability Id and Next Capability pointer is as expected. | |
4767 | * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext() | |
4768 | * to correctly set kernel data structures which have already been | |
4769 | * set incorrectly due to the hardware bug. | |
4770 | */ | |
4771 | pos = 0x50; | |
4772 | pci_read_config_word(pdev, pos, ®16); | |
4773 | if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) { | |
4774 | u32 status; | |
4775 | #ifndef PCI_EXP_SAVE_REGS | |
4776 | #define PCI_EXP_SAVE_REGS 7 | |
4777 | #endif | |
4778 | int size = PCI_EXP_SAVE_REGS * sizeof(u16); | |
4779 | ||
4780 | pdev->pcie_cap = pos; | |
4781 | pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); | |
4782 | pdev->pcie_flags_reg = reg16; | |
4783 | pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16); | |
4784 | pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; | |
4785 | ||
4786 | pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; | |
4787 | if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) != | |
4788 | PCIBIOS_SUCCESSFUL || (status == 0xffffffff)) | |
4789 | pdev->cfg_size = PCI_CFG_SPACE_SIZE; | |
4790 | ||
4791 | if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP)) | |
4792 | return; | |
4793 | ||
4794 | /* | |
4795 | * Save PCIE cap | |
4796 | */ | |
4797 | state = kzalloc(sizeof(*state) + size, GFP_KERNEL); | |
4798 | if (!state) | |
4799 | return; | |
4800 | ||
4801 | state->cap.cap_nr = PCI_CAP_ID_EXP; | |
4802 | state->cap.cap_extended = 0; | |
4803 | state->cap.size = size; | |
4804 | cap = (u16 *)&state->cap.data[0]; | |
4805 | pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]); | |
4806 | pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]); | |
4807 | pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]); | |
4808 | pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]); | |
4809 | pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]); | |
4810 | pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]); | |
4811 | pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]); | |
4812 | hlist_add_head(&state->next, &pdev->saved_cap_space); | |
4813 | } | |
4814 | } | |
4815 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap); | |
443b40ba | 4816 | |
f65fd1aa SN |
4817 | /* FLR may cause some 82579 devices to hang. */ |
4818 | static void quirk_intel_no_flr(struct pci_dev *dev) | |
4819 | { | |
4820 | dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET; | |
4821 | } | |
4822 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_intel_no_flr); | |
4823 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_intel_no_flr); | |
62ce94a7 | 4824 | |
bce24d90 AS |
4825 | static void quirk_intel_th_rtit_bar(struct pci_dev *dev) |
4826 | { | |
4827 | struct resource *r = &dev->resource[4]; | |
4828 | ||
4829 | /* | |
4830 | * Hello, Denverton! | |
4831 | * Denverton reports 2k of RTIT_BAR (resource 4), which can't be | |
4832 | * right given the 16 threads. When Intel TH gets enabled, the | |
4833 | * actual resource overlaps the XHCI MMIO space and causes it | |
4834 | * to die. | |
4835 | * We're not really using RTIT_BAR at all at the moment, so it's | |
4836 | * a safe choice to disable this resource. | |
4837 | */ | |
4838 | if (r->end == r->start + 0x7ff) { | |
4839 | r->flags = 0; | |
4840 | r->start = 0; | |
4841 | r->end = 0; | |
4842 | } | |
4843 | } | |
4844 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x19e1, quirk_intel_th_rtit_bar); | |
4845 | ||
62ce94a7 SK |
4846 | static void quirk_no_ext_tags(struct pci_dev *pdev) |
4847 | { | |
4848 | struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus); | |
4849 | ||
4850 | if (!bridge) | |
4851 | return; | |
4852 | ||
4853 | bridge->no_ext_tags = 1; | |
4854 | dev_info(&pdev->dev, "disabling Extended Tags (this device can't handle them)\n"); | |
4855 | ||
4856 | pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL); | |
4857 | } | |
1dd1e309 | 4858 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags); |
62ce94a7 | 4859 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags); |
1dd1e309 | 4860 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags); |
62ce94a7 SK |
4861 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags); |
4862 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags); | |
1dd1e309 SK |
4863 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags); |
4864 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags); | |
cf2d8041 | 4865 | |
9b44b0b0 JR |
4866 | #ifdef CONFIG_PCI_ATS |
4867 | /* | |
4868 | * Some devices have a broken ATS implementation causing IOMMU stalls. | |
4869 | * Don't use ATS for those devices. | |
4870 | */ | |
4871 | static void quirk_no_ats(struct pci_dev *pdev) | |
4872 | { | |
4873 | dev_info(&pdev->dev, "disabling ATS (broken on this device)\n"); | |
4874 | pdev->ats_cap = 0; | |
4875 | } | |
4876 | ||
4877 | /* AMD Stoney platform GPU */ | |
4878 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_no_ats); | |
4879 | #endif /* CONFIG_PCI_ATS */ | |
06dc4ee5 HZ |
4880 | |
4881 | /* Freescale PCIe doesn't support MSI in RC mode */ | |
4882 | static void quirk_fsl_no_msi(struct pci_dev *pdev) | |
4883 | { | |
4884 | if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) | |
4885 | pdev->no_msi = 1; | |
4886 | } | |
4887 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi); |