]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/pci/quirks.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
PCI: Update MSI-HOWTO.txt according to pci_msi_supported()
[mirror_ubuntu-bionic-kernel.git] / drivers / pci / quirks.c
CommitLineData
1da177e4
LT		 1/*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
7586269c
DB		 10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 *
1da177e4
LT		 13 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
16 */
17
1da177e4
LT		 18#include <linux/types.h>
19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/init.h>
22#include <linux/delay.h>
25be5e6c 23#include <linux/acpi.h>
bc56b9e0 24#include "pci.h"
1da177e4 25
bd8481e1
DT		 26/* The Mellanox Tavor device gives false positive parity errors
27 * Mark this device with a broken_parity_status, to allow
28 * PCI scanning code to "skip" this now blacklisted device.
29 */
30static void __devinit quirk_mellanox_tavor(struct pci_dev *dev)
31{
32 dev->broken_parity_status = 1; /* This device gives false positives */
33}
34DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
35DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
36
1da177e4
LT		 37/* Deal with broken BIOS'es that neglect to enable passive release,
38 which can cause problems in combination with the 82441FX/PPro MTRRs */
39static void __devinit quirk_passive_release(struct pci_dev *dev)
40{
41 struct pci_dev *d = NULL;
42 unsigned char dlc;
43
44 /* We have to make sure a particular bit is set in the PIIX3
45 ISA bridge, so we have to go out and find it. */
46 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
47 pci_read_config_byte(d, 0x82, &dlc);
48 if (!(dlc & 1<<1)) {
49 printk(KERN_ERR "PCI: PIIX3: Enabling Passive Release on %s\n", pci_name(d));
50 dlc |= 1<<1;
51 pci_write_config_byte(d, 0x82, dlc);
52 }
53 }
54}
55DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release );
56
57/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
58 but VIA don't answer queries. If you happen to have good contacts at VIA
59 ask them for me please -- Alan
60
61 This appears to be BIOS not version dependent. So presumably there is a
62 chipset level fix */
63int isa_dma_bridge_buggy; /* Exported */
64
65static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
66{
67 if (!isa_dma_bridge_buggy) {
68 isa_dma_bridge_buggy=1;
69 printk(KERN_INFO "Activating ISA DMA hang workarounds.\n");
70 }
71}
72 /*
73 * Its not totally clear which chipsets are the problematic ones
74 * We know 82C586 and 82C596 variants are affected.
75 */
76DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs );
77DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs );
78DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs );
79DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs );
80DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs );
81DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs );
82DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs );
83
84int pci_pci_problems;
85
86/*
87 * Chipsets where PCI->PCI transfers vanish or hang
88 */
89static void __devinit quirk_nopcipci(struct pci_dev *dev)
90{
91 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
92 printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n");
93 pci_pci_problems |= PCIPCI_FAIL;
94 }
95}
236561e5
AC		 96
97static void __devinit quirk_nopciamd(struct pci_dev *dev)
98{
99 u8 rev;
100 pci_read_config_byte(dev, 0x08, &rev);
101 if (rev == 0x13) {
102 /* Erratum 24 */
103 printk(KERN_INFO "Chipset erratum: Disabling direct PCI/AGP transfers.\n");
104 pci_pci_problems |= PCIAGP_FAIL;
105 }
106}
107
1da177e4
LT		 108DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci );
109DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci );
236561e5 110DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd );
1da177e4
LT		 111
112/*
113 * Triton requires workarounds to be used by the drivers
114 */
115static void __devinit quirk_triton(struct pci_dev *dev)
116{
117 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
118 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
119 pci_pci_problems |= PCIPCI_TRITON;
120 }
121}
122DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton );
123DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton );
124DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton );
125DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton );
126
127/*
128 * VIA Apollo KT133 needs PCI latency patch
129 * Made according to a windows driver based patch by George E. Breese
130 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
131 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
132 * the info on which Mr Breese based his work.
133 *
134 * Updated based on further information from the site and also on
135 * information provided by VIA
136 */
137static void __devinit quirk_vialatency(struct pci_dev *dev)
138{
139 struct pci_dev *p;
140 u8 rev;
141 u8 busarb;
142 /* Ok we have a potential problem chipset here. Now see if we have
143 a buggy southbridge */
144
145 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
146 if (p!=NULL) {
147 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
148 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
149 /* Check for buggy part revisions */
150 if (rev < 0x40 || rev > 0x42)
151 goto exit;
152 } else {
153 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
154 if (p==NULL) /* No problem parts */
155 goto exit;
156 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
157 /* Check for buggy part revisions */
158 if (rev < 0x10 || rev > 0x12)
159 goto exit;
160 }
161
162 /*
163 * Ok we have the problem. Now set the PCI master grant to
164 * occur every master grant. The apparent bug is that under high
165 * PCI load (quite common in Linux of course) you can get data
166 * loss when the CPU is held off the bus for 3 bus master requests
167 * This happens to include the IDE controllers....
168 *
169 * VIA only apply this fix when an SB Live! is present but under
170 * both Linux and Windows this isnt enough, and we have seen
171 * corruption without SB Live! but with things like 3 UDMA IDE
172 * controllers. So we ignore that bit of the VIA recommendation..
173 */
174
175 pci_read_config_byte(dev, 0x76, &busarb);
176 /* Set bit 4 and bi 5 of byte 76 to 0x01
177 "Master priority rotation on every PCI master grant */
178 busarb &= ~(1<<5);
179 busarb |= (1<<4);
180 pci_write_config_byte(dev, 0x76, busarb);
181 printk(KERN_INFO "Applying VIA southbridge workaround.\n");
182exit:
183 pci_dev_put(p);
184}
185DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency );
186DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency );
187DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency );
188
189/*
190 * VIA Apollo VP3 needs ETBF on BT848/878
191 */
192static void __devinit quirk_viaetbf(struct pci_dev *dev)
193{
194 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
195 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
196 pci_pci_problems |= PCIPCI_VIAETBF;
197 }
198}
199DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf );
200
201static void __devinit quirk_vsfx(struct pci_dev *dev)
202{
203 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
204 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
205 pci_pci_problems |= PCIPCI_VSFX;
206 }
207}
208DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx );
209
210/*
211 * Ali Magik requires workarounds to be used by the drivers
212 * that DMA to AGP space. Latency must be set to 0xA and triton
213 * workaround applied too
214 * [Info kindly provided by ALi]
215 */
216static void __init quirk_alimagik(struct pci_dev *dev)
217{
218 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
219 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
220 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
221 }
222}
223DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik );
224DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik );
225
226/*
227 * Natoma has some interesting boundary conditions with Zoran stuff
228 * at least
229 */
230static void __devinit quirk_natoma(struct pci_dev *dev)
231{
232 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
233 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
234 pci_pci_problems |= PCIPCI_NATOMA;
235 }
236}
237DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma );
238DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma );
239DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma );
240DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma );
241DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma );
242DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma );
243
244/*
245 * This chip can cause PCI parity errors if config register 0xA0 is read
246 * while DMAs are occurring.
247 */
248static void __devinit quirk_citrine(struct pci_dev *dev)
249{
250 dev->cfg_size = 0xA0;
251}
252DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine );
253
254/*
255 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
256 * If it's needed, re-allocate the region.
257 */
258static void __devinit quirk_s3_64M(struct pci_dev *dev)
259{
260 struct resource *r = &dev->resource[0];
261
262 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
263 r->start = 0;
264 r->end = 0x3ffffff;
265 }
266}
267DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M );
268DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M );
269
6693e74a
LT		 270static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
271 unsigned size, int nr, const char *name)
1da177e4
LT		 272{
273 region &= ~(size-1);
274 if (region) {
085ae41f 275 struct pci_bus_region bus_region;
1da177e4
LT		 276 struct resource *res = dev->resource + nr;
277
278 res->name = pci_name(dev);
279 res->start = region;
280 res->end = region + size - 1;
281 res->flags = IORESOURCE_IO;
085ae41f
DM		 282
283 /* Convert from PCI bus to resource space. */
284 bus_region.start = res->start;
285 bus_region.end = res->end;
286 pcibios_bus_to_resource(dev, res, &bus_region);
287
1da177e4 288 pci_claim_resource(dev, nr);
6693e74a 289 printk("PCI quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name);
1da177e4
LT		 290 }
291}
292
293/*
294 * ATI Northbridge setups MCE the processor if you even
295 * read somewhere between 0x3b0->0x3bb or read 0x3d3
296 */
297static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
298{
299 printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n");
300 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
301 request_region(0x3b0, 0x0C, "RadeonIGP");
302 request_region(0x3d3, 0x01, "RadeonIGP");
303}
304DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce );
305
306/*
307 * Let's make the southbridge information explicit instead
308 * of having to worry about people probing the ACPI areas,
309 * for example.. (Yes, it happens, and if you read the wrong
310 * ACPI register it will put the machine to sleep with no
311 * way of waking it up again. Bummer).
312 *
313 * ALI M7101: Two IO regions pointed to by words at
314 * 0xE0 (64 bytes of ACPI registers)
315 * 0xE2 (32 bytes of SMB registers)
316 */
317static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
318{
319 u16 region;
320
321 pci_read_config_word(dev, 0xE0, &region);
6693e74a 322 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
1da177e4 323 pci_read_config_word(dev, 0xE2, &region);
6693e74a 324 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
1da177e4
LT		 325}
326DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi );
327
6693e74a
LT		 328static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
329{
330 u32 devres;
331 u32 mask, size, base;
332
333 pci_read_config_dword(dev, port, &devres);
334 if ((devres & enable) != enable)
335 return;
336 mask = (devres >> 16) & 15;
337 base = devres & 0xffff;
338 size = 16;
339 for (;;) {
340 unsigned bit = size >> 1;
341 if ((bit & mask) == bit)
342 break;
343 size = bit;
344 }
345 /*
346 * For now we only print it out. Eventually we'll want to
347 * reserve it (at least if it's in the 0x1000+ range), but
348 * let's get enough confirmation reports first.
349 */
350 base &= -size;
351 printk("%s PIO at %04x-%04x\n", name, base, base + size - 1);
352}
353
354static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
355{
356 u32 devres;
357 u32 mask, size, base;
358
359 pci_read_config_dword(dev, port, &devres);
360 if ((devres & enable) != enable)
361 return;
362 base = devres & 0xffff0000;
363 mask = (devres & 0x3f) << 16;
364 size = 128 << 16;
365 for (;;) {
366 unsigned bit = size >> 1;
367 if ((bit & mask) == bit)
368 break;
369 size = bit;
370 }
371 /*
372 * For now we only print it out. Eventually we'll want to
373 * reserve it, but let's get enough confirmation reports first.
374 */
375 base &= -size;
376 printk("%s MMIO at %04x-%04x\n", name, base, base + size - 1);
377}
378
1da177e4
LT		 379/*
380 * PIIX4 ACPI: Two IO regions pointed to by longwords at
381 * 0x40 (64 bytes of ACPI registers)
08db2a70 382 * 0x90 (16 bytes of SMB registers)
6693e74a 383 * and a few strange programmable PIIX4 device resources.
1da177e4
LT		 384 */
385static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
386{
6693e74a 387 u32 region, res_a;
1da177e4
LT		 388
389 pci_read_config_dword(dev, 0x40, &region);
6693e74a 390 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
1da177e4 391 pci_read_config_dword(dev, 0x90, &region);
08db2a70 392 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
6693e74a
LT		 393
394 /* Device resource A has enables for some of the other ones */
395 pci_read_config_dword(dev, 0x5c, &res_a);
396
397 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
398 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
399
400 /* Device resource D is just bitfields for static resources */
401
402 /* Device 12 enabled? */
403 if (res_a & (1 << 29)) {
404 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
405 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
406 }
407 /* Device 13 enabled? */
408 if (res_a & (1 << 30)) {
409 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
410 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
411 }
412 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
413 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
1da177e4
LT		 414}
415DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi );
c6764664 416DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi );
1da177e4
LT		 417
418/*
419 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
420 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
421 * 0x58 (64 bytes of GPIO I/O space)
422 */
423static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
424{
425 u32 region;
426
427 pci_read_config_dword(dev, 0x40, &region);
6693e74a 428 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO");
1da177e4
LT		 429
430 pci_read_config_dword(dev, 0x58, &region);
6693e74a 431 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO");
1da177e4
LT		 432}
433DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi );
434DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi );
435DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi );
436DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi );
437DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi );
438DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi );
439DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi );
440DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi );
441DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi );
3aa8c4fe 442DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi );
1da177e4 443
2cea752f
RM		 444static void __devinit quirk_ich6_lpc_acpi(struct pci_dev *dev)
445{
446 u32 region;
447
448 pci_read_config_dword(dev, 0x40, &region);
449 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO");
450
451 pci_read_config_dword(dev, 0x48, &region);
452 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO");
453}
65ae4ddd 454DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc_acpi );
2cea752f 455DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc_acpi );
bacedce3
DR		 456DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich6_lpc_acpi );
457DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich6_lpc_acpi );
458DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich6_lpc_acpi );
459DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich6_lpc_acpi );
460DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich6_lpc_acpi );
461DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich6_lpc_acpi );
2cea752f 462
1da177e4
LT		 463/*
464 * VIA ACPI: One IO region pointed to by longword at
465 * 0x48 or 0x20 (256 bytes of ACPI registers)
466 */
467static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
468{
469 u8 rev;
470 u32 region;
471
472 pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
473 if (rev & 0x10) {
474 pci_read_config_dword(dev, 0x48, &region);
475 region &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 476 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
1da177e4
LT		 477 }
478}
479DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi );
480
481/*
482 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
483 * 0x48 (256 bytes of ACPI registers)
484 * 0x70 (128 bytes of hardware monitoring register)
485 * 0x90 (16 bytes of SMB registers)
486 */
487static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
488{
489 u16 hm;
490 u32 smb;
491
492 quirk_vt82c586_acpi(dev);
493
494 pci_read_config_word(dev, 0x70, &hm);
495 hm &= PCI_BASE_ADDRESS_IO_MASK;
02f313b2 496 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
1da177e4
LT		 497
498 pci_read_config_dword(dev, 0x90, &smb);
499 smb &= PCI_BASE_ADDRESS_IO_MASK;
02f313b2 500 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
1da177e4
LT		 501}
502DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi );
503
6d85f29b
IK		 504/*
505 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
506 * 0x88 (128 bytes of power management registers)
507 * 0xd0 (16 bytes of SMB registers)
508 */
509static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
510{
511 u16 pm, smb;
512
513 pci_read_config_word(dev, 0x88, &pm);
514 pm &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 515 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
6d85f29b
IK		 516
517 pci_read_config_word(dev, 0xd0, &smb);
518 smb &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 519 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
6d85f29b
IK		 520}
521DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
522
1da177e4
LT		 523
524#ifdef CONFIG_X86_IO_APIC
525
526#include <asm/io_apic.h>
527
528/*
529 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
530 * devices to the external APIC.
531 *
532 * TODO: When we have device-specific interrupt routers,
533 * this code will go away from quirks.
534 */
535static void __devinit quirk_via_ioapic(struct pci_dev *dev)
536{
537 u8 tmp;
538
539 if (nr_ioapics < 1)
540 tmp = 0; /* nothing routed to external APIC */
541 else
542 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
543
544 printk(KERN_INFO "PCI: %sbling Via external APIC routing\n",
545 tmp == 0 ? "Disa" : "Ena");
546
547 /* Offset 0x58: External APIC IRQ output control */
548 pci_write_config_byte (dev, 0x58, tmp);
549}
550DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic );
551
a1740913
KW		 552/*
553 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
554 * This leads to doubled level interrupt rates.
555 * Set this bit to get rid of cycle wastage.
556 * Otherwise uncritical.
557 */
558static void __devinit quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
559{
560 u8 misc_control2;
561#define BYPASS_APIC_DEASSERT 8
562
563 pci_read_config_byte(dev, 0x5B, &misc_control2);
564 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
565 printk(KERN_INFO "PCI: Bypassing VIA 8237 APIC De-Assert Message\n");
566 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
567 }
568}
569DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
570
1da177e4
LT		 571/*
572 * The AMD io apic can hang the box when an apic irq is masked.
573 * We check all revs >= B0 (yet not in the pre production!) as the bug
574 * is currently marked NoFix
575 *
576 * We have multiple reports of hangs with this chipset that went away with
236561e5 577 * noapic specified. For the moment we assume it's the erratum. We may be wrong
1da177e4
LT		 578 * of course. However the advice is demonstrably good even if so..
579 */
580static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
581{
582 u8 rev;
583
584 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
585 if (rev >= 0x02) {
236561e5 586 printk(KERN_WARNING "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
1da177e4
LT		 587 printk(KERN_WARNING " : booting with the \"noapic\" option.\n");
588 }
589}
590DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic );
591
592static void __init quirk_ioapic_rmw(struct pci_dev *dev)
593{
594 if (dev->devfn == 0 && dev->bus->number == 0)
595 sis_apic_bug = 1;
596}
597DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw );
598
1da177e4
LT		 599#define AMD8131_revA0 0x01
600#define AMD8131_revB0 0x11
601#define AMD8131_MISC 0x40
602#define AMD8131_NIOAMODE_BIT 0
603static void __init quirk_amd_8131_ioapic(struct pci_dev *dev)
604{
605 unsigned char revid, tmp;
606
1da177e4
LT		 607 if (nr_ioapics == 0)
608 return;
609
610 pci_read_config_byte(dev, PCI_REVISION_ID, &revid);
611 if (revid == AMD8131_revA0 || revid == AMD8131_revB0) {
612 printk(KERN_INFO "Fixing up AMD8131 IOAPIC mode\n");
613 pci_read_config_byte( dev, AMD8131_MISC, &tmp);
614 tmp &= ~(1 << AMD8131_NIOAMODE_BIT);
615 pci_write_config_byte( dev, AMD8131_MISC, tmp);
616 }
617}
5da594b1 618DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic);
1da177e4
LT		 619#endif /* CONFIG_X86_IO_APIC */
620
621
1da177e4
LT		 622/*
623 * FIXME: it is questionable that quirk_via_acpi
624 * is needed. It shows up as an ISA bridge, and does not
625 * support the PCI_INTERRUPT_LINE register at all. Therefore
626 * it seems like setting the pci_dev's 'irq' to the
627 * value of the ACPI SCI interrupt is only done for convenience.
628 * -jgarzik
629 */
630static void __devinit quirk_via_acpi(struct pci_dev *d)
631{
632 /*
633 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
634 */
635 u8 irq;
636 pci_read_config_byte(d, 0x42, &irq);
637 irq &= 0xf;
638 if (irq && (irq != 2))
639 d->irq = irq;
640}
641DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi );
642DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi );
643
93cffffa
BH		 644/*
645 * Via 686A/B: The PCI_INTERRUPT_LINE register for the on-chip
646 * devices, USB0/1, AC97, MC97, and ACPI, has an unusual feature:
647 * when written, it makes an internal connection to the PIC.
648 * For these devices, this register is defined to be 4 bits wide.
649 * Normally this is fine. However for IO-APIC motherboards, or
650 * non-x86 architectures (yes Via exists on PPC among other places),
651 * we must mask the PCI_INTERRUPT_LINE value versus 0xf to get
652 * interrupts delivered properly.
a7b862f6
CW		 653 *
654 * Some of the on-chip devices are actually '586 devices' so they are
655 * listed here.
93cffffa 656 */
09d6029f
DD		 657
658static int via_irq_fixup_needed = -1;
659
660/*
661 * As some VIA hardware is available in PCI-card form, we need to restrict
662 * this quirk to VIA PCI hardware built onto VIA-based motherboards only.
663 * We try to locate a VIA southbridge before deciding whether the quirk
664 * should be applied.
665 */
666static const struct pci_device_id via_irq_fixup_tbl[] = {
667 {
668 .vendor = PCI_VENDOR_ID_VIA,
669 .device = PCI_ANY_ID,
670 .subvendor = PCI_ANY_ID,
671 .subdevice = PCI_ANY_ID,
672 .class = PCI_CLASS_BRIDGE_ISA << 8,
673 .class_mask = 0xffff00,
674 },
675 { 0, },
676};
677
93cffffa 678static void quirk_via_irq(struct pci_dev *dev)
25be5e6c
LB		 679{
680 u8 irq, new_irq;
681
09d6029f
DD		 682 if (via_irq_fixup_needed == -1)
683 via_irq_fixup_needed = pci_dev_present(via_irq_fixup_tbl);
684
685 if (!via_irq_fixup_needed)
686 return;
687
688 new_irq = dev->irq;
689
690 /* Don't quirk interrupts outside the legacy IRQ range */
691 if (!new_irq || new_irq > 15)
692 return;
693
25be5e6c
LB		 694 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
695 if (new_irq != irq) {
75cf7456 696 printk(KERN_INFO "PCI: VIA IRQ fixup for %s, from %d to %d\n",
25be5e6c
LB		 697 pci_name(dev), irq, new_irq);
698 udelay(15); /* unknown if delay really needed */
699 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
700 }
701}
09d6029f 702DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_irq);
25be5e6c 703
1da177e4
LT		 704/*
705 * VIA VT82C598 has its device ID settable and many BIOSes
706 * set it to the ID of VT82C597 for backward compatibility.
707 * We need to switch it off to be able to recognize the real
708 * type of the chip.
709 */
710static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
711{
712 pci_write_config_byte(dev, 0xfc, 0);
713 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
714}
715DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id );
716
709cf5ea
MG		 717#ifdef CONFIG_ACPI_SLEEP
718
719/*
720 * Some VIA systems boot with the abnormal status flag set. This can cause
721 * the BIOS to re-POST the system on resume rather than passing control
722 * back to the OS. Clear the flag on boot
723 */
724static void __devinit quirk_via_abnormal_poweroff(struct pci_dev *dev)
725{
726 u32 reg;
727
728 acpi_hw_register_read(ACPI_MTX_DO_NOT_LOCK, ACPI_REGISTER_PM1_STATUS,
729 &reg);
730
731 if (reg & 0x800) {
732 printk("Clearing abnormal poweroff flag\n");
733 acpi_hw_register_write(ACPI_MTX_DO_NOT_LOCK,
734 ACPI_REGISTER_PM1_STATUS,
735 (u16)0x800);
736 }
737}
738
739DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_abnormal_poweroff);
740DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_abnormal_poweroff);
741
742#endif
743
1da177e4
LT		 744/*
745 * CardBus controllers have a legacy base address that enables them
746 * to respond as i82365 pcmcia controllers. We don't want them to
747 * do this even if the Linux CardBus driver is not loaded, because
748 * the Linux i82365 driver does not (and should not) handle CardBus.
749 */
750static void __devinit quirk_cardbus_legacy(struct pci_dev *dev)
751{
752 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
753 return;
754 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
755}
756DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
757
758/*
759 * Following the PCI ordering rules is optional on the AMD762. I'm not
760 * sure what the designers were smoking but let's not inhale...
761 *
762 * To be fair to AMD, it follows the spec by default, its BIOS people
763 * who turn it off!
764 */
765static void __devinit quirk_amd_ordering(struct pci_dev *dev)
766{
767 u32 pcic;
768 pci_read_config_dword(dev, 0x4C, &pcic);
769 if ((pcic&6)!=6) {
770 pcic |= 6;
771 printk(KERN_WARNING "BIOS failed to enable PCI standards compliance, fixing this error.\n");
772 pci_write_config_dword(dev, 0x4C, pcic);
773 pci_read_config_dword(dev, 0x84, &pcic);
774 pcic |= (1<<23); /* Required in this mode */
775 pci_write_config_dword(dev, 0x84, pcic);
776 }
777}
778DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering );
779
780/*
781 * DreamWorks provided workaround for Dunord I-3000 problem
782 *
783 * This card decodes and responds to addresses not apparently
784 * assigned to it. We force a larger allocation to ensure that
785 * nothing gets put too close to it.
786 */
787static void __devinit quirk_dunord ( struct pci_dev * dev )
788{
789 struct resource *r = &dev->resource [1];
790 r->start = 0;
791 r->end = 0xffffff;
792}
793DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord );
794
795/*
796 * i82380FB mobile docking controller: its PCI-to-PCI bridge
797 * is subtractive decoding (transparent), and does indicate this
798 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
799 * instead of 0x01.
800 */
801static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
802{
803 dev->transparent = 1;
804}
805DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge );
806DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge );
807
808/*
809 * Common misconfiguration of the MediaGX/Geode PCI master that will
810 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
811 * datasheets found at http://www.national.com/ds/GX for info on what
812 * these bits do. <christer@weinigel.se>
813 */
814static void __init quirk_mediagx_master(struct pci_dev *dev)
815{
816 u8 reg;
817 pci_read_config_byte(dev, 0x41, &reg);
818 if (reg & 2) {
819 reg &= ~2;
820 printk(KERN_INFO "PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
821 pci_write_config_byte(dev, 0x41, reg);
822 }
823}
824DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master );
825
826/*
827 * As per PCI spec, ignore base address registers 0-3 of the IDE controllers
828 * running in Compatible mode (bits 0 and 2 in the ProgIf for primary and
829 * secondary channels respectively). If the device reports Compatible mode
830 * but does use BAR0-3 for address decoding, we assume that firmware has
831 * programmed these BARs with standard values (0x1f0,0x3f4 and 0x170,0x374).
832 * Exceptions (if they exist) must be handled in chip/architecture specific
833 * fixups.
834 *
835 * Note: for non x86 people. You may need an arch specific quirk to handle
836 * moving IDE devices to native mode as well. Some plug in card devices power
837 * up in compatible mode and assume the BIOS will adjust them.
838 *
839 * Q: should we load the 0x1f0,0x3f4 into the registers or zap them as
840 * we do now ? We don't want is pci_enable_device to come along
841 * and assign new resources. Both approaches work for that.
842 */
843static void __devinit quirk_ide_bases(struct pci_dev *dev)
844{
845 struct resource *res;
846 int first_bar = 2, last_bar = 0;
847
848 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
849 return;
850
851 res = &dev->resource[0];
852
853 /* primary channel: ProgIf bit 0, BAR0, BAR1 */
854 if (!(dev->class & 1) && (res[0].flags || res[1].flags)) {
855 res[0].start = res[0].end = res[0].flags = 0;
856 res[1].start = res[1].end = res[1].flags = 0;
857 first_bar = 0;
858 last_bar = 1;
859 }
860
861 /* secondary channel: ProgIf bit 2, BAR2, BAR3 */
862 if (!(dev->class & 4) && (res[2].flags || res[3].flags)) {
863 res[2].start = res[2].end = res[2].flags = 0;
864 res[3].start = res[3].end = res[3].flags = 0;
865 last_bar = 3;
866 }
867
868 if (!last_bar)
869 return;
870
871 printk(KERN_INFO "PCI: Ignoring BAR%d-%d of IDE controller %s\n",
872 first_bar, last_bar, pci_name(dev));
873}
874DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_ide_bases);
875
876/*
877 * Ensure C0 rev restreaming is off. This is normally done by
878 * the BIOS but in the odd case it is not the results are corruption
879 * hence the presence of a Linux check
880 */
881static void __init quirk_disable_pxb(struct pci_dev *pdev)
882{
883 u16 config;
884 u8 rev;
885
886 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
887 if (rev != 0x04) /* Only C0 requires this */
888 return;
889 pci_read_config_word(pdev, 0x40, &config);
890 if (config & (1<<6)) {
891 config &= ~(1<<6);
892 pci_write_config_word(pdev, 0x40, config);
893 printk(KERN_INFO "PCI: C0 revision 450NX. Disabling PCI restreaming.\n");
894 }
895}
896DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb );
897
1da177e4
LT		 898
899/*
900 * Serverworks CSB5 IDE does not fully support native mode
901 */
902static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
903{
904 u8 prog;
905 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
906 if (prog & 5) {
907 prog &= ~5;
908 pdev->class &= ~5;
909 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
910 /* need to re-assign BARs for compat mode */
911 quirk_ide_bases(pdev);
912 }
913}
914DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide );
915
916/*
917 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
918 */
919static void __init quirk_ide_samemode(struct pci_dev *pdev)
920{
921 u8 prog;
922
923 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
924
925 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
926 printk(KERN_INFO "PCI: IDE mode mismatch; forcing legacy mode\n");
927 prog &= ~5;
928 pdev->class &= ~5;
929 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
930 /* need to re-assign BARs for compat mode */
931 quirk_ide_bases(pdev);
932 }
933}
934DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
935
936/* This was originally an Alpha specific thing, but it really fits here.
937 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
938 */
939static void __init quirk_eisa_bridge(struct pci_dev *dev)
940{
941 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
942}
943DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge );
944
7daa0c4f
JG		 945/*
946 * On the MSI-K8T-Neo2Fir Board, the internal Soundcard is disabled
947 * when a PCI-Soundcard is added. The BIOS only gives Options
948 * "Disabled" and "AUTO". This Quirk Sets the corresponding
949 * Register-Value to enable the Soundcard.
bd91fde9
CW		 950 *
951 * FIXME: Presently this quirk will run on anything that has an 8237
952 * which isn't correct, we need to check DMI tables or something in
953 * order to make sure it only runs on the MSI-K8T-Neo2Fir. Because it
954 * runs everywhere at present we suppress the printk output in most
955 * irrelevant cases.
7daa0c4f
JG		 956 */
957static void __init k8t_sound_hostbridge(struct pci_dev *dev)
958{
959 unsigned char val;
960
7daa0c4f
JG		 961 pci_read_config_byte(dev, 0x50, &val);
962 if (val == 0x88 || val == 0xc8) {
bd91fde9
CW		 963 /* Assume it's probably a MSI-K8T-Neo2Fir */
964 printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, attempting to turn soundcard ON\n");
7daa0c4f
JG		 965 pci_write_config_byte(dev, 0x50, val & (~0x40));
966
967 /* Verify the Change for Status output */
968 pci_read_config_byte(dev, 0x50, &val);
969 if (val & 0x40)
bd91fde9 970 printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, soundcard still off\n");
7daa0c4f 971 else
bd91fde9 972 printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, soundcard on\n");
7daa0c4f 973 }
7daa0c4f
JG		 974}
975DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, k8t_sound_hostbridge);
976
ce007ea5 977#ifndef CONFIG_ACPI_SLEEP
1da177e4
LT		 978/*
979 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
980 * is not activated. The myth is that Asus said that they do not want the
981 * users to be irritated by just another PCI Device in the Win98 device
982 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
983 * package 2.7.0 for details)
984 *
985 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
986 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
987 * becomes necessary to do this tweak in two steps -- I've chosen the Host
988 * bridge as trigger.
ce007ea5
CDH		 989 *
990 * Actually, leaving it unhidden and not redoing the quirk over suspend2ram
991 * will cause thermal management to break down, and causing machine to
992 * overheat.
1da177e4 993 */
ce007ea5 994static int __initdata asus_hides_smbus;
1da177e4
LT		 995
996static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
997{
998 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
999 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1000 switch(dev->subsystem_device) {
a00db371 1001 case 0x8025: /* P4B-LX */
1da177e4
LT		 1002 case 0x8070: /* P4B */
1003 case 0x8088: /* P4B533 */
1004 case 0x1626: /* L3C notebook */
1005 asus_hides_smbus = 1;
1006 }
1007 if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1008 switch(dev->subsystem_device) {
1009 case 0x80b1: /* P4GE-V */
1010 case 0x80b2: /* P4PE */
1011 case 0x8093: /* P4B533-V */
1012 asus_hides_smbus = 1;
1013 }
1014 if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1015 switch(dev->subsystem_device) {
1016 case 0x8030: /* P4T533 */
1017 asus_hides_smbus = 1;
1018 }
1019 if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1020 switch (dev->subsystem_device) {
1021 case 0x8070: /* P4G8X Deluxe */
1022 asus_hides_smbus = 1;
1023 }
321311af
JD		 1024 if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1025 switch (dev->subsystem_device) {
1026 case 0x80c9: /* PU-DLS */
1027 asus_hides_smbus = 1;
1028 }
1da177e4
LT		 1029 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1030 switch (dev->subsystem_device) {
1031 case 0x1751: /* M2N notebook */
1032 case 0x1821: /* M5N notebook */
1033 asus_hides_smbus = 1;
1034 }
1035 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1036 switch (dev->subsystem_device) {
1037 case 0x184b: /* W1N notebook */
1038 case 0x186a: /* M6Ne notebook */
1039 asus_hides_smbus = 1;
1040 }
acc06632
RM		 1041 if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) {
1042 switch (dev->subsystem_device) {
1043 case 0x1882: /* M6V notebook */
2d1e1c75 1044 case 0x1977: /* A6VA notebook */
acc06632
RM		 1045 asus_hides_smbus = 1;
1046 }
1047 }
1da177e4
LT		 1048 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1049 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1050 switch(dev->subsystem_device) {
1051 case 0x088C: /* HP Compaq nc8000 */
1052 case 0x0890: /* HP Compaq nc6000 */
1053 asus_hides_smbus = 1;
1054 }
1055 if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1056 switch (dev->subsystem_device) {
1057 case 0x12bc: /* HP D330L */
e3b1bd57 1058 case 0x12bd: /* HP D530 */
1da177e4
LT		 1059 asus_hides_smbus = 1;
1060 }
3c0a654e 1061 if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) {
1062 switch (dev->subsystem_device) {
1063 case 0x099c: /* HP Compaq nx6110 */
1064 asus_hides_smbus = 1;
1065 }
1066 }
1da177e4
LT		 1067 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_TOSHIBA)) {
1068 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1069 switch(dev->subsystem_device) {
1070 case 0x0001: /* Toshiba Satellite A40 */
1071 asus_hides_smbus = 1;
1072 }
e96e2f14
DG		 1073 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1074 switch(dev->subsystem_device) {
1075 case 0x0001: /* Toshiba Tecra M2 */
1076 asus_hides_smbus = 1;
1077 }
1da177e4
LT		 1078 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1079 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1080 switch(dev->subsystem_device) {
1081 case 0xC00C: /* Samsung P35 notebook */
1082 asus_hides_smbus = 1;
1083 }
c87f883e
RIZ		 1084 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1085 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1086 switch(dev->subsystem_device) {
1087 case 0x0058: /* Compaq Evo N620c */
1088 asus_hides_smbus = 1;
1089 }
1da177e4
LT		 1090 }
1091}
1092DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge );
1093DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge );
1094DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge );
1095DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge );
1096DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge );
321311af 1097DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge );
1da177e4
LT		 1098DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge );
1099DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge );
acc06632 1100DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge );
1da177e4
LT		 1101
1102static void __init asus_hides_smbus_lpc(struct pci_dev *dev)
1103{
1104 u16 val;
1105
1106 if (likely(!asus_hides_smbus))
1107 return;
1108
1109 pci_read_config_word(dev, 0xF2, &val);
1110 if (val & 0x8) {
1111 pci_write_config_word(dev, 0xF2, val & (~0x8));
1112 pci_read_config_word(dev, 0xF2, &val);
1113 if (val & 0x8)
1114 printk(KERN_INFO "PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1115 else
1116 printk(KERN_INFO "PCI: Enabled i801 SMBus device\n");
1117 }
1118}
1119DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc );
1120DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc );
321311af 1121DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc );
1da177e4
LT		 1122DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc );
1123DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc );
1124DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc );
1125
acc06632
RM		 1126static void __init asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1127{
1128 u32 val, rcba;
1129 void __iomem *base;
1130
1131 if (likely(!asus_hides_smbus))
1132 return;
1133 pci_read_config_dword(dev, 0xF0, &rcba);
1134 base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); /* use bits 31:14, 16 kB aligned */
1135 if (base == NULL) return;
1136 val=readl(base + 0x3418); /* read the Function Disable register, dword mode only */
1137 writel(val & 0xFFFFFFF7, base + 0x3418); /* enable the SMBus device */
1138 iounmap(base);
1139 printk(KERN_INFO "PCI: Enabled ICH6/i801 SMBus device\n");
1140}
1141DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6 );
1142
ce007ea5
CDH		 1143#endif
1144
1da177e4
LT		 1145/*
1146 * SiS 96x south bridge: BIOS typically hides SMBus device...
1147 */
1148static void __init quirk_sis_96x_smbus(struct pci_dev *dev)
1149{
1150 u8 val = 0;
1151 printk(KERN_INFO "Enabling SiS 96x SMBus.\n");
1152 pci_read_config_byte(dev, 0x77, &val);
1153 pci_write_config_byte(dev, 0x77, val & ~0x10);
1154 pci_read_config_byte(dev, 0x77, &val);
1155}
1156
1da177e4
LT		 1157/*
1158 * ... This is further complicated by the fact that some SiS96x south
1159 * bridges pretend to be 85C503/5513 instead. In that case see if we
1160 * spotted a compatible north bridge to make sure.
1161 * (pci_find_device doesn't work yet)
1162 *
1163 * We can also enable the sis96x bit in the discovery register..
1164 */
1165static int __devinitdata sis_96x_compatible = 0;
1166
1167#define SIS_DETECT_REGISTER 0x40
1168
1169static void __init quirk_sis_503(struct pci_dev *dev)
1170{
1171 u8 reg;
1172 u16 devid;
1173
1174 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1175 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1176 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1177 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1178 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1179 return;
1180 }
1181
1182 /* Make people aware that we changed the config.. */
1183 printk(KERN_WARNING "Uncovering SIS%x that hid as a SIS503 (compatible=%d)\n", devid, sis_96x_compatible);
1184
1185 /*
1186 * Ok, it now shows up as a 96x.. The 96x quirks are after
1187 * the 503 quirk in the quirk table, so they'll automatically
1188 * run and enable things like the SMBus device
1189 */
1190 dev->device = devid;
1191}
1192
1193static void __init quirk_sis_96x_compatible(struct pci_dev *dev)
1194{
1195 sis_96x_compatible = 1;
1196}
1197DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_645, quirk_sis_96x_compatible );
1198DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_646, quirk_sis_96x_compatible );
1199DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_648, quirk_sis_96x_compatible );
1200DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_650, quirk_sis_96x_compatible );
1201DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_651, quirk_sis_96x_compatible );
1202DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_735, quirk_sis_96x_compatible );
1203
1204DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503 );
e5548e96
BJD		 1205/*
1206 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1207 * and MC97 modem controller are disabled when a second PCI soundcard is
1208 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1209 * -- bjd
1210 */
1211static void __init asus_hides_ac97_lpc(struct pci_dev *dev)
1212{
1213 u8 val;
1214 int asus_hides_ac97 = 0;
1215
1216 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1217 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1218 asus_hides_ac97 = 1;
1219 }
1220
1221 if (!asus_hides_ac97)
1222 return;
1223
1224 pci_read_config_byte(dev, 0x50, &val);
1225 if (val & 0xc0) {
1226 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1227 pci_read_config_byte(dev, 0x50, &val);
1228 if (val & 0xc0)
1229 printk(KERN_INFO "PCI: onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
1230 else
1231 printk(KERN_INFO "PCI: enabled onboard AC97/MC97 devices\n");
1232 }
1233}
1234DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc );
1235
1da177e4
LT		 1236
1237DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus );
1238DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus );
1239DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus );
1240DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus );
1241
77967052 1242#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
15e0c694
AC		 1243
1244/*
1245 * If we are using libata we can drive this chip properly but must
1246 * do this early on to make the additional device appear during
1247 * the PCI scanning.
1248 */
1249
1250static void __devinit quirk_jmicron_dualfn(struct pci_dev *pdev)
1251{
1252 u32 conf;
1253 u8 hdr;
1254
1255 /* Only poke fn 0 */
1256 if (PCI_FUNC(pdev->devfn))
1257 return;
1258
1259 switch(pdev->device) {
1260 case PCI_DEVICE_ID_JMICRON_JMB365:
1261 case PCI_DEVICE_ID_JMICRON_JMB366:
1262 /* Redirect IDE second PATA port to the right spot */
1263 pci_read_config_dword(pdev, 0x80, &conf);
1264 conf |= (1 << 24);
1265 /* Fall through */
1266 pci_write_config_dword(pdev, 0x80, conf);
1267 case PCI_DEVICE_ID_JMICRON_JMB361:
1268 case PCI_DEVICE_ID_JMICRON_JMB363:
1269 pci_read_config_dword(pdev, 0x40, &conf);
1270 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1271 /* Set the class codes correctly and then direct IDE 0 */
1272 conf &= ~0x000F0200; /* Clear bit 9 and 16-19 */
1273 conf |= 0x00C20002; /* Set bit 1, 17, 22, 23 */
1274 pci_write_config_dword(pdev, 0x40, conf);
1275
1276 /* Reconfigure so that the PCI scanner discovers the
1277 device is now multifunction */
1278
1279 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1280 pdev->hdr_type = hdr & 0x7f;
1281 pdev->multifunction = !!(hdr & 0x80);
1282
1283 break;
1284 }
1285}
1286
1287DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, quirk_jmicron_dualfn);
1288
1289#endif
1290
1da177e4
LT		 1291#ifdef CONFIG_X86_IO_APIC
1292static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1293{
1294 int i;
1295
1296 if ((pdev->class >> 8) != 0xff00)
1297 return;
1298
1299 /* the first BAR is the location of the IO APIC...we must
1300 * not touch this (and it's already covered by the fixmap), so
1301 * forcibly insert it into the resource tree */
1302 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1303 insert_resource(&iomem_resource, &pdev->resource[0]);
1304
1305 /* The next five BARs all seem to be rubbish, so just clean
1306 * them out */
1307 for (i=1; i < 6; i++) {
1308 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1309 }
1310
1311}
1312DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic );
1313#endif
1314
2bd0fa3b
JB		 1315enum ide_combined_type { COMBINED = 0, IDE = 1, LIBATA = 2 };
1316/* Defaults to combined */
1317static enum ide_combined_type combined_mode;
1318
1319static int __init combined_setup(char *str)
1320{
1321 if (!strncmp(str, "ide", 3))
1322 combined_mode = IDE;
1323 else if (!strncmp(str, "libata", 6))
1324 combined_mode = LIBATA;
1325 else /* "combined" or anything else defaults to old behavior */
1326 combined_mode = COMBINED;
1327
1328 return 1;
1329}
1330__setup("combined_mode=", combined_setup);
1331
77967052 1332#ifdef CONFIG_SATA_INTEL_COMBINED
1da177e4
LT		 1333static void __devinit quirk_intel_ide_combined(struct pci_dev *pdev)
1334{
1335 u8 prog, comb, tmp;
1336 int ich = 0;
1337
1338 /*
1339 * Narrow down to Intel SATA PCI devices.
1340 */
1341 switch (pdev->device) {
1342 /* PCI ids taken from drivers/scsi/ata_piix.c */
1343 case 0x24d1:
1344 case 0x24df:
1345 case 0x25a3:
1346 case 0x25b0:
1347 ich = 5;
1348 break;
1349 case 0x2651:
1350 case 0x2652:
1351 case 0x2653:
c368ca4e 1352 case 0x2680: /* ESB2 */
1da177e4
LT		 1353 ich = 6;
1354 break;
1355 case 0x27c0:
1356 case 0x27c4:
1357 ich = 7;
1358 break;
012b265f
JG		 1359 case 0x2828: /* ICH8M */
1360 ich = 8;
1361 break;
1da177e4
LT		 1362 default:
1363 /* we do not handle this PCI device */
1364 return;
1365 }
1366
1367 /*
1368 * Read combined mode register.
1369 */
1370 pci_read_config_byte(pdev, 0x90, &tmp); /* combined mode reg */
1371
1372 if (ich == 5) {
1373 tmp &= 0x6; /* interesting bits 2:1, PATA primary/secondary */
1374 if (tmp == 0x4) /* bits 10x */
1375 comb = (1 << 0); /* SATA port 0, PATA port 1 */
1376 else if (tmp == 0x6) /* bits 11x */
1377 comb = (1 << 2); /* PATA port 0, SATA port 1 */
1378 else
1379 return; /* not in combined mode */
1380 } else {
012b265f 1381 WARN_ON((ich != 6) && (ich != 7) && (ich != 8));
1da177e4
LT		 1382 tmp &= 0x3; /* interesting bits 1:0 */
1383 if (tmp & (1 << 0))
1384 comb = (1 << 2); /* PATA port 0, SATA port 1 */
1385 else if (tmp & (1 << 1))
1386 comb = (1 << 0); /* SATA port 0, PATA port 1 */
1387 else
1388 return; /* not in combined mode */
1389 }
1390
1391 /*
1392 * Read programming interface register.
1393 * (Tells us if it's legacy or native mode)
1394 */
1395 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1396
1397 /* if SATA port is in native mode, we're ok. */
1398 if (prog & comb)
1399 return;
1400
2bd0fa3b
JB		 1401 /* Don't reserve any so the IDE driver can get them (but only if
1402 * combined_mode=ide).
1403 */
1404 if (combined_mode == IDE)
1405 return;
1406
1407 /* Grab them both for libata if combined_mode=libata. */
1408 if (combined_mode == LIBATA) {
1409 request_region(0x1f0, 8, "libata"); /* port 0 */
1410 request_region(0x170, 8, "libata"); /* port 1 */
1411 return;
1412 }
1413
1da177e4
LT		 1414 /* SATA port is in legacy mode. Reserve port so that
1415 * IDE driver does not attempt to use it. If request_region
1416 * fails, it will be obvious at boot time, so we don't bother
1417 * checking return values.
1418 */
1419 if (comb == (1 << 0))
1420 request_region(0x1f0, 8, "libata"); /* port 0 */
1421 else
1422 request_region(0x170, 8, "libata"); /* port 1 */
1423}
1424DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_intel_ide_combined );
77967052 1425#endif /* CONFIG_SATA_INTEL_COMBINED */
1da177e4
LT		 1426
1427
1428int pcie_mch_quirk;
1429
1430static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1431{
1432 pcie_mch_quirk = 1;
1433}
1434DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch );
1435DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch );
1436DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch );
1437
4602b88d
KA		 1438
1439/*
1440 * It's possible for the MSI to get corrupted if shpc and acpi
1441 * are used together on certain PXH-based systems.
1442 */
1443static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1444{
1445 disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI),
1446 PCI_CAP_ID_MSI);
1447 dev->no_msi = 1;
1448
1449 printk(KERN_WARNING "PCI: PXH quirk detected, "
1450 "disabling MSI for SHPC device\n");
1451}
1452DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1453DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1454DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1455DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1456DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1457
ffadcc2f
KCA		 1458/*
1459 * Some Intel PCI Express chipsets have trouble with downstream
1460 * device power management.
1461 */
1462static void quirk_intel_pcie_pm(struct pci_dev * dev)
1463{
1464 pci_pm_d3_delay = 120;
1465 dev->no_d1d2 = 1;
1466}
1467
1468DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1469DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1470DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1471DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1472DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1473DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1474DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1475DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1476DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1477DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1478DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1479DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1480DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1481DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1482DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1483DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1484DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1485DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1486DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1487DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1488DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
4602b88d 1489
c408a379
KA		 1490/*
1491 * Fixup the cardbus bridges on the IBM Dock II docking station
1492 */
1493static void __devinit quirk_ibm_dock2_cardbus(struct pci_dev *dev)
1494{
1495 u32 val;
1496
1497 /*
1498 * tie the 2 interrupt pins to INTA, and configure the
1499 * multifunction routing register to handle this.
1500 */
1501 if ((dev->subsystem_vendor == PCI_VENDOR_ID_IBM) &&
1502 (dev->subsystem_device == 0x0148)) {
1503 printk(KERN_INFO "PCI: Found IBM Dock II Cardbus Bridge "
1504 "applying quirk\n");
1505 pci_read_config_dword(dev, 0x8c, &val);
1506 val = ((val & 0xffffff00) | 0x1002);
1507 pci_write_config_dword(dev, 0x8c, val);
1508 pci_read_config_dword(dev, 0x80, &val);
1509 val = ((val & 0x00ffff00) | 0x2864c077);
1510 pci_write_config_dword(dev, 0x80, val);
1511 }
1512}
1513
1514DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1420,
1515 quirk_ibm_dock2_cardbus);
1516
1da177e4
LT		 1517static void __devinit quirk_netmos(struct pci_dev *dev)
1518{
1519 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1520 unsigned int num_serial = dev->subsystem_device & 0xf;
1521
1522 /*
1523 * These Netmos parts are multiport serial devices with optional
1524 * parallel ports. Even when parallel ports are present, they
1525 * are identified as class SERIAL, which means the serial driver
1526 * will claim them. To prevent this, mark them as class OTHER.
1527 * These combo devices should be claimed by parport_serial.
1528 *
1529 * The subdevice ID is of the form 0x00PS, where <P> is the number
1530 * of parallel ports and <S> is the number of serial ports.
1531 */
1532 switch (dev->device) {
1533 case PCI_DEVICE_ID_NETMOS_9735:
1534 case PCI_DEVICE_ID_NETMOS_9745:
1535 case PCI_DEVICE_ID_NETMOS_9835:
1536 case PCI_DEVICE_ID_NETMOS_9845:
1537 case PCI_DEVICE_ID_NETMOS_9855:
1538 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1539 num_parallel) {
1540 printk(KERN_INFO "PCI: Netmos %04x (%u parallel, "
1541 "%u serial); changing class SERIAL to OTHER "
1542 "(use parport_serial)\n",
1543 dev->device, num_parallel, num_serial);
1544 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1545 (dev->class & 0xff);
1546 }
1547 }
1548}
1549DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1550
16a74744
BH		 1551static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1552{
1553 u16 command;
1554 u32 bar;
1555 u8 __iomem *csr;
1556 u8 cmd_hi;
1557
1558 switch (dev->device) {
1559 /* PCI IDs taken from drivers/net/e100.c */
1560 case 0x1029:
1561 case 0x1030 ... 0x1034:
1562 case 0x1038 ... 0x103E:
1563 case 0x1050 ... 0x1057:
1564 case 0x1059:
1565 case 0x1064 ... 0x106B:
1566 case 0x1091 ... 0x1095:
1567 case 0x1209:
1568 case 0x1229:
1569 case 0x2449:
1570 case 0x2459:
1571 case 0x245D:
1572 case 0x27DC:
1573 break;
1574 default:
1575 return;
1576 }
1577
1578 /*
1579 * Some firmware hands off the e100 with interrupts enabled,
1580 * which can cause a flood of interrupts if packets are
1581 * received before the driver attaches to the device. So
1582 * disable all e100 interrupts here. The driver will
1583 * re-enable them when it's ready.
1584 */
1585 pci_read_config_word(dev, PCI_COMMAND, &command);
1586 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar);
1587
1588 if (!(command & PCI_COMMAND_MEMORY) || !bar)
1589 return;
1590
1591 csr = ioremap(bar, 8);
1592 if (!csr) {
1593 printk(KERN_WARNING "PCI: Can't map %s e100 registers\n",
1594 pci_name(dev));
1595 return;
1596 }
1597
1598 cmd_hi = readb(csr + 3);
1599 if (cmd_hi == 0) {
1600 printk(KERN_WARNING "PCI: Firmware left %s e100 interrupts "
1601 "enabled, disabling\n", pci_name(dev));
1602 writeb(1, csr + 3);
1603 }
1604
1605 iounmap(csr);
1606}
1607DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt);
a5312e28
IK		 1608
1609static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1610{
1611 /* rev 1 ncr53c810 chips don't set the class at all which means
1612 * they don't get their resources remapped. Fix that here.
1613 */
1614
1615 if (dev->class == PCI_CLASS_NOT_DEFINED) {
1616 printk(KERN_INFO "NCR 53c810 rev 1 detected, setting PCI class.\n");
1617 dev->class = PCI_CLASS_STORAGE_SCSI;
1618 }
1619}
1620DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1621
b5e4efe7 1622/*
1623 * Fixup to mark boot BIOS video selected by BIOS before it changes
1624 *
1625 * From information provided by "Jon Smirl" <jonsmirl@gmail.com>
1626 *
1627 * The standard boot ROM sequence for an x86 machine uses the BIOS
1628 * to select an initial video card for boot display. This boot video
1629 * card will have it's BIOS copied to C0000 in system RAM.
1630 * IORESOURCE_ROM_SHADOW is used to associate the boot video
1631 * card with this copy. On laptops this copy has to be used since
1632 * the main ROM may be compressed or combined with another image.
1633 * See pci_map_rom() for use of this flag. IORESOURCE_ROM_SHADOW
1634 * is marked here since the boot video device will be the only enabled
1635 * video device at this point.
1636 */
1637
1638static void __devinit fixup_video(struct pci_dev *pdev)
1639{
1640 struct pci_dev *bridge;
1641 struct pci_bus *bus;
1642 u16 config;
1643
1644 if ((pdev->class >> 8) != PCI_CLASS_DISPLAY_VGA)
1645 return;
1646
1647 /* Is VGA routed to us? */
1648 bus = pdev->bus;
1649 while (bus) {
1650 bridge = bus->self;
1651 if (bridge) {
1652 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
1653 &config);
1654 if (!(config & PCI_BRIDGE_CTL_VGA))
1655 return;
1656 }
1657 bus = bus->parent;
1658 }
1659 pci_read_config_word(pdev, PCI_COMMAND, &config);
1660 if (config & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
1661 pdev->resource[PCI_ROM_RESOURCE].flags |= IORESOURCE_ROM_SHADOW;
1662 printk(KERN_DEBUG "Boot video device is %s\n", pci_name(pdev));
1663 }
1664}
1665DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, fixup_video);
1666
a5312e28 1667
1da177e4
LT		 1668static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end)
1669{
1670 while (f < end) {
1671 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
1672 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
1673 pr_debug("PCI: Calling quirk %p for %s\n", f->hook, pci_name(dev));
1674 f->hook(dev);
1675 }
1676 f++;
1677 }
1678}
1679
1680extern struct pci_fixup __start_pci_fixups_early[];
1681extern struct pci_fixup __end_pci_fixups_early[];
1682extern struct pci_fixup __start_pci_fixups_header[];
1683extern struct pci_fixup __end_pci_fixups_header[];
1684extern struct pci_fixup __start_pci_fixups_final[];
1685extern struct pci_fixup __end_pci_fixups_final[];
1686extern struct pci_fixup __start_pci_fixups_enable[];
1687extern struct pci_fixup __end_pci_fixups_enable[];
1688
1689
1690void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
1691{
1692 struct pci_fixup *start, *end;
1693
1694 switch(pass) {
1695 case pci_fixup_early:
1696 start = __start_pci_fixups_early;
1697 end = __end_pci_fixups_early;
1698 break;
1699
1700 case pci_fixup_header:
1701 start = __start_pci_fixups_header;
1702 end = __end_pci_fixups_header;
1703 break;
1704
1705 case pci_fixup_final:
1706 start = __start_pci_fixups_final;
1707 end = __end_pci_fixups_final;
1708 break;
1709
1710 case pci_fixup_enable:
1711 start = __start_pci_fixups_enable;
1712 end = __end_pci_fixups_enable;
1713 break;
1714
1715 default:
1716 /* stupid compiler warning, you would think with an enum... */
1717 return;
1718 }
1719 pci_do_fixups(dev, start, end);
1720}
1721
9d265124
DY		 1722/* Enable 1k I/O space granularity on the Intel P64H2 */
1723static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1724{
1725 u16 en1k;
1726 u8 io_base_lo, io_limit_lo;
1727 unsigned long base, limit;
1728 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1729
1730 pci_read_config_word(dev, 0x40, &en1k);
1731
1732 if (en1k & 0x200) {
1733 printk(KERN_INFO "PCI: Enable I/O Space to 1 KB Granularity\n");
1734
1735 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
1736 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
1737 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1738 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1739
1740 if (base <= limit) {
1741 res->start = base;
1742 res->end = limit + 0x3ff;
1743 }
1744 }
1745}
1746DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
1747
cf34a8e0
BG		 1748/* Under some circumstances, AER is not linked with extended capabilities.
1749 * Force it to be linked by setting the corresponding control bit in the
1750 * config space.
1751 */
1752static void __devinit quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
1753{
1754 uint8_t b;
1755 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
1756 if (!(b & 0x20)) {
1757 pci_write_config_byte(dev, 0xf41, b | 0x20);
1758 printk(KERN_INFO
1759 "PCI: Linking AER extended capability on %s\n",
1760 pci_name(dev));
1761 }
1762 }
1763}
1764DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1765 quirk_nvidia_ck804_pcie_aer_ext_cap);
1766
3f79e107
BG		 1767#ifdef CONFIG_PCI_MSI
1768/* To disable MSI globally */
1769int pci_msi_quirk;
1770
1771/* The Serverworks PCI-X chipset does not support MSI. We cannot easily rely
1772 * on setting PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
1773 * some other busses controlled by the chipset even if Linux is not aware of it.
1774 * Instead of setting the flag on all busses in the machine, simply disable MSI
1775 * globally.
1776 */
1777static void __init quirk_svw_msi(struct pci_dev *dev)
1778{
1779 pci_msi_quirk = 1;
1780 printk(KERN_WARNING "PCI: MSI quirk detected. pci_msi_quirk set.\n");
1781}
1782DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_svw_msi);
1783
1784/* Disable MSI on chipsets that are known to not support it */
1785static void __devinit quirk_disable_msi(struct pci_dev *dev)
1786{
1787 if (dev->subordinate) {
1788 printk(KERN_WARNING "PCI: MSI quirk detected. "
1789 "PCI_BUS_FLAGS_NO_MSI set for %s subordinate bus.\n",
1790 pci_name(dev));
1791 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1792 }
1793}
1794DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
6397c75c
BG		 1795
1796/* Go through the list of Hypertransport capabilities and
1797 * return 1 if a HT MSI capability is found and enabled */
1798static int __devinit msi_ht_cap_enabled(struct pci_dev *dev)
1799{
1800 u8 pos;
1801 int ttl;
1802 for (pos = pci_find_capability(dev, PCI_CAP_ID_HT), ttl = 48;
1803 pos && ttl;
1804 pos = pci_find_next_capability(dev, pos, PCI_CAP_ID_HT), ttl--) {
1805 u32 cap_hdr;
1806 /* MSI mapping section according to Hypertransport spec */
1807 if (pci_read_config_dword(dev, pos, &cap_hdr) == 0
1808 && (cap_hdr & 0xf8000000) == 0xa8000000 /* MSI mapping */) {
1809 printk(KERN_INFO "PCI: Found HT MSI mapping on %s with capability %s\n",
1810 pci_name(dev), cap_hdr & 0x10000 ? "enabled" : "disabled");
1811 return (cap_hdr & 0x10000) != 0; /* MSI mapping cap enabled */
1812 }
1813 }
1814 return 0;
1815}
1816
1817/* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
1818static void __devinit quirk_msi_ht_cap(struct pci_dev *dev)
1819{
1820 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
1821 printk(KERN_WARNING "PCI: MSI quirk detected. "
1822 "MSI disabled on chipset %s.\n",
1823 pci_name(dev));
1824 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1825 }
1826}
1827DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
1828 quirk_msi_ht_cap);
1829
1830/* The nVidia CK804 chipset may have 2 HT MSI mappings.
1831 * MSI are supported if the MSI capability set in any of these mappings.
1832 */
1833static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
1834{
1835 struct pci_dev *pdev;
1836
1837 if (!dev->subordinate)
1838 return;
1839
1840 /* check HT MSI cap on this chipset and the root one.
1841 * a single one having MSI is enough to be sure that MSI are supported.
1842 */
1843 pdev = pci_find_slot(dev->bus->number, 0);
1844 if (dev->subordinate && !msi_ht_cap_enabled(dev)
1845 && !msi_ht_cap_enabled(pdev)) {
1846 printk(KERN_WARNING "PCI: MSI quirk detected. "
1847 "MSI disabled on chipset %s.\n",
1848 pci_name(dev));
1849 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1850 }
1851}
1852DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1853 quirk_nvidia_ck804_msi_ht_cap);
3f79e107
BG		 1854#endif /* CONFIG_PCI_MSI */
1855
1da177e4
LT		 1856EXPORT_SYMBOL(pcie_mch_quirk);
1857#ifdef CONFIG_HOTPLUG
1858EXPORT_SYMBOL(pci_fixup_device);
1859#endif
ubuntu-bionic-kernel mirror