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PCI: Enable PCIe AER only after checking firmware support
[mirror_ubuntu-bionic-kernel.git] / drivers / pci / quirks.c
CommitLineData
1da177e4
LT		 1/*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
7586269c
DB		 10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 *
1da177e4
LT		 13 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
16 */
17
1da177e4
LT		 18#include <linux/types.h>
19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/init.h>
22#include <linux/delay.h>
25be5e6c 23#include <linux/acpi.h>
9f23ed3b 24#include <linux/kallsyms.h>
75e07fc3 25#include <linux/dmi.h>
bc56b9e0 26#include "pci.h"
1da177e4 27
3d137310
TP		 28int isa_dma_bridge_buggy;
29EXPORT_SYMBOL(isa_dma_bridge_buggy);
30int pci_pci_problems;
31EXPORT_SYMBOL(pci_pci_problems);
32int pcie_mch_quirk;
33EXPORT_SYMBOL(pcie_mch_quirk);
34
35#ifdef CONFIG_PCI_QUIRKS
bd8481e1
DT		 36/* The Mellanox Tavor device gives false positive parity errors
37 * Mark this device with a broken_parity_status, to allow
38 * PCI scanning code to "skip" this now blacklisted device.
39 */
40static void __devinit quirk_mellanox_tavor(struct pci_dev *dev)
41{
42 dev->broken_parity_status = 1; /* This device gives false positives */
43}
44DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
45DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
46
1da177e4
LT		 47/* Deal with broken BIOS'es that neglect to enable passive release,
48 which can cause problems in combination with the 82441FX/PPro MTRRs */
1597cacb 49static void quirk_passive_release(struct pci_dev *dev)
1da177e4
LT		 50{
51 struct pci_dev *d = NULL;
52 unsigned char dlc;
53
54 /* We have to make sure a particular bit is set in the PIIX3
55 ISA bridge, so we have to go out and find it. */
56 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
57 pci_read_config_byte(d, 0x82, &dlc);
58 if (!(dlc & 1<<1)) {
999da9fd 59 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
1da177e4
LT		 60 dlc |= 1<<1;
61 pci_write_config_byte(d, 0x82, dlc);
62 }
63 }
64}
652c538e
AM		 65DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
66DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
1da177e4
LT		 67
68/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
69 but VIA don't answer queries. If you happen to have good contacts at VIA
70 ask them for me please -- Alan
71
72 This appears to be BIOS not version dependent. So presumably there is a
73 chipset level fix */
1da177e4
LT		 74
75static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
76{
77 if (!isa_dma_bridge_buggy) {
78 isa_dma_bridge_buggy=1;
f0fda801 79 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
1da177e4
LT		 80 }
81}
82 /*
83 * Its not totally clear which chipsets are the problematic ones
84 * We know 82C586 and 82C596 variants are affected.
85 */
652c538e
AM		 86DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
87DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
88DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
89DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
90DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
91DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
92DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
1da177e4 93
1da177e4
LT		 94/*
95 * Chipsets where PCI->PCI transfers vanish or hang
96 */
97static void __devinit quirk_nopcipci(struct pci_dev *dev)
98{
99 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
f0fda801 100 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
1da177e4
LT		 101 pci_pci_problems |= PCIPCI_FAIL;
102 }
103}
652c538e
AM		 104DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
105DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
236561e5
AC		 106
107static void __devinit quirk_nopciamd(struct pci_dev *dev)
108{
109 u8 rev;
110 pci_read_config_byte(dev, 0x08, &rev);
111 if (rev == 0x13) {
112 /* Erratum 24 */
f0fda801 113 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
236561e5
AC		 114 pci_pci_problems |= PCIAGP_FAIL;
115 }
116}
652c538e 117DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
1da177e4
LT		 118
119/*
120 * Triton requires workarounds to be used by the drivers
121 */
122static void __devinit quirk_triton(struct pci_dev *dev)
123{
124 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
f0fda801 125 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 126 pci_pci_problems |= PCIPCI_TRITON;
127 }
128}
652c538e
AM		 129DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
130DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
131DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
132DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
1da177e4
LT		 133
134/*
135 * VIA Apollo KT133 needs PCI latency patch
136 * Made according to a windows driver based patch by George E. Breese
137 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
138 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
139 * the info on which Mr Breese based his work.
140 *
141 * Updated based on further information from the site and also on
142 * information provided by VIA
143 */
1597cacb 144static void quirk_vialatency(struct pci_dev *dev)
1da177e4
LT		 145{
146 struct pci_dev *p;
1da177e4
LT		 147 u8 busarb;
148 /* Ok we have a potential problem chipset here. Now see if we have
149 a buggy southbridge */
150
151 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
152 if (p!=NULL) {
1da177e4
LT		 153 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
154 /* Check for buggy part revisions */
2b1afa87 155 if (p->revision < 0x40 || p->revision > 0x42)
1da177e4
LT		 156 goto exit;
157 } else {
158 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
159 if (p==NULL) /* No problem parts */
160 goto exit;
1da177e4 161 /* Check for buggy part revisions */
2b1afa87 162 if (p->revision < 0x10 || p->revision > 0x12)
1da177e4
LT		 163 goto exit;
164 }
165
166 /*
167 * Ok we have the problem. Now set the PCI master grant to
168 * occur every master grant. The apparent bug is that under high
169 * PCI load (quite common in Linux of course) you can get data
170 * loss when the CPU is held off the bus for 3 bus master requests
171 * This happens to include the IDE controllers....
172 *
173 * VIA only apply this fix when an SB Live! is present but under
174 * both Linux and Windows this isnt enough, and we have seen
175 * corruption without SB Live! but with things like 3 UDMA IDE
176 * controllers. So we ignore that bit of the VIA recommendation..
177 */
178
179 pci_read_config_byte(dev, 0x76, &busarb);
180 /* Set bit 4 and bi 5 of byte 76 to 0x01
181 "Master priority rotation on every PCI master grant */
182 busarb &= ~(1<<5);
183 busarb |= (1<<4);
184 pci_write_config_byte(dev, 0x76, busarb);
f0fda801 185 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
1da177e4
LT		 186exit:
187 pci_dev_put(p);
188}
652c538e
AM		 189DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
190DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
191DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
1597cacb 192/* Must restore this on a resume from RAM */
652c538e
AM		 193DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
194DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
195DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
1da177e4
LT		 196
197/*
198 * VIA Apollo VP3 needs ETBF on BT848/878
199 */
200static void __devinit quirk_viaetbf(struct pci_dev *dev)
201{
202 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
f0fda801 203 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 204 pci_pci_problems |= PCIPCI_VIAETBF;
205 }
206}
652c538e 207DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
1da177e4
LT		 208
209static void __devinit quirk_vsfx(struct pci_dev *dev)
210{
211 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
f0fda801 212 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 213 pci_pci_problems |= PCIPCI_VSFX;
214 }
215}
652c538e 216DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
1da177e4
LT		 217
218/*
219 * Ali Magik requires workarounds to be used by the drivers
220 * that DMA to AGP space. Latency must be set to 0xA and triton
221 * workaround applied too
222 * [Info kindly provided by ALi]
223 */
224static void __init quirk_alimagik(struct pci_dev *dev)
225{
226 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
f0fda801 227 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 228 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
229 }
230}
652c538e
AM		 231DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
232DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
1da177e4
LT		 233
234/*
235 * Natoma has some interesting boundary conditions with Zoran stuff
236 * at least
237 */
238static void __devinit quirk_natoma(struct pci_dev *dev)
239{
240 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
f0fda801 241 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 242 pci_pci_problems |= PCIPCI_NATOMA;
243 }
244}
652c538e
AM		 245DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
246DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
247DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
248DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
249DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
250DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
1da177e4
LT		 251
252/*
253 * This chip can cause PCI parity errors if config register 0xA0 is read
254 * while DMAs are occurring.
255 */
256static void __devinit quirk_citrine(struct pci_dev *dev)
257{
258 dev->cfg_size = 0xA0;
259}
652c538e 260DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
1da177e4
LT		 261
262/*
263 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
264 * If it's needed, re-allocate the region.
265 */
266static void __devinit quirk_s3_64M(struct pci_dev *dev)
267{
268 struct resource *r = &dev->resource[0];
269
270 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
271 r->start = 0;
272 r->end = 0x3ffffff;
273 }
274}
652c538e
AM		 275DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
276DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
1da177e4 277
6693e74a
LT		 278static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
279 unsigned size, int nr, const char *name)
1da177e4
LT		 280{
281 region &= ~(size-1);
282 if (region) {
085ae41f 283 struct pci_bus_region bus_region;
1da177e4
LT		 284 struct resource *res = dev->resource + nr;
285
286 res->name = pci_name(dev);
287 res->start = region;
288 res->end = region + size - 1;
289 res->flags = IORESOURCE_IO;
085ae41f
DM		 290
291 /* Convert from PCI bus to resource space. */
292 bus_region.start = res->start;
293 bus_region.end = res->end;
294 pcibios_bus_to_resource(dev, res, &bus_region);
295
1da177e4 296 pci_claim_resource(dev, nr);
f0fda801 297 dev_info(&dev->dev, "quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name);
1da177e4
LT		 298 }
299}
300
301/*
302 * ATI Northbridge setups MCE the processor if you even
303 * read somewhere between 0x3b0->0x3bb or read 0x3d3
304 */
305static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
306{
f0fda801 307 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
1da177e4
LT		 308 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
309 request_region(0x3b0, 0x0C, "RadeonIGP");
310 request_region(0x3d3, 0x01, "RadeonIGP");
311}
652c538e 312DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
1da177e4
LT		 313
314/*
315 * Let's make the southbridge information explicit instead
316 * of having to worry about people probing the ACPI areas,
317 * for example.. (Yes, it happens, and if you read the wrong
318 * ACPI register it will put the machine to sleep with no
319 * way of waking it up again. Bummer).
320 *
321 * ALI M7101: Two IO regions pointed to by words at
322 * 0xE0 (64 bytes of ACPI registers)
323 * 0xE2 (32 bytes of SMB registers)
324 */
325static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
326{
327 u16 region;
328
329 pci_read_config_word(dev, 0xE0, &region);
6693e74a 330 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
1da177e4 331 pci_read_config_word(dev, 0xE2, &region);
6693e74a 332 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
1da177e4 333}
652c538e 334DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
1da177e4 335
6693e74a
LT		 336static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
337{
338 u32 devres;
339 u32 mask, size, base;
340
341 pci_read_config_dword(dev, port, &devres);
342 if ((devres & enable) != enable)
343 return;
344 mask = (devres >> 16) & 15;
345 base = devres & 0xffff;
346 size = 16;
347 for (;;) {
348 unsigned bit = size >> 1;
349 if ((bit & mask) == bit)
350 break;
351 size = bit;
352 }
353 /*
354 * For now we only print it out. Eventually we'll want to
355 * reserve it (at least if it's in the 0x1000+ range), but
356 * let's get enough confirmation reports first.
357 */
358 base &= -size;
f0fda801 359 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
6693e74a
LT		 360}
361
362static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
363{
364 u32 devres;
365 u32 mask, size, base;
366
367 pci_read_config_dword(dev, port, &devres);
368 if ((devres & enable) != enable)
369 return;
370 base = devres & 0xffff0000;
371 mask = (devres & 0x3f) << 16;
372 size = 128 << 16;
373 for (;;) {
374 unsigned bit = size >> 1;
375 if ((bit & mask) == bit)
376 break;
377 size = bit;
378 }
379 /*
380 * For now we only print it out. Eventually we'll want to
381 * reserve it, but let's get enough confirmation reports first.
382 */
383 base &= -size;
f0fda801 384 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
6693e74a
LT		 385}
386
1da177e4
LT		 387/*
388 * PIIX4 ACPI: Two IO regions pointed to by longwords at
389 * 0x40 (64 bytes of ACPI registers)
08db2a70 390 * 0x90 (16 bytes of SMB registers)
6693e74a 391 * and a few strange programmable PIIX4 device resources.
1da177e4
LT		 392 */
393static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
394{
6693e74a 395 u32 region, res_a;
1da177e4
LT		 396
397 pci_read_config_dword(dev, 0x40, &region);
6693e74a 398 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
1da177e4 399 pci_read_config_dword(dev, 0x90, &region);
08db2a70 400 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
6693e74a
LT		 401
402 /* Device resource A has enables for some of the other ones */
403 pci_read_config_dword(dev, 0x5c, &res_a);
404
405 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
406 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
407
408 /* Device resource D is just bitfields for static resources */
409
410 /* Device 12 enabled? */
411 if (res_a & (1 << 29)) {
412 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
413 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
414 }
415 /* Device 13 enabled? */
416 if (res_a & (1 << 30)) {
417 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
418 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
419 }
420 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
421 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
1da177e4 422}
652c538e
AM		 423DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
424DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
1da177e4
LT		 425
426/*
427 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
428 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
429 * 0x58 (64 bytes of GPIO I/O space)
430 */
431static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
432{
433 u32 region;
434
435 pci_read_config_dword(dev, 0x40, &region);
6693e74a 436 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO");
1da177e4
LT		 437
438 pci_read_config_dword(dev, 0x58, &region);
6693e74a 439 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO");
1da177e4 440}
652c538e
AM		 441DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
442DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
443DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
444DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
445DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
446DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
447DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
448DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
449DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
450DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
1da177e4 451
894886e5 452static void __devinit ich6_lpc_acpi_gpio(struct pci_dev *dev)
2cea752f
RM		 453{
454 u32 region;
455
456 pci_read_config_dword(dev, 0x40, &region);
457 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO");
458
459 pci_read_config_dword(dev, 0x48, &region);
460 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO");
461}
894886e5
LT		 462
463static void __devinit ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
464{
465 u32 val;
466 u32 size, base;
467
468 pci_read_config_dword(dev, reg, &val);
469
470 /* Enabled? */
471 if (!(val & 1))
472 return;
473 base = val & 0xfffc;
474 if (dynsize) {
475 /*
476 * This is not correct. It is 16, 32 or 64 bytes depending on
477 * register D31:F0:ADh bits 5:4.
478 *
479 * But this gets us at least _part_ of it.
480 */
481 size = 16;
482 } else {
483 size = 128;
484 }
485 base &= ~(size-1);
486
487 /* Just print it out for now. We should reserve it after more debugging */
488 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
489}
490
491static void __devinit quirk_ich6_lpc(struct pci_dev *dev)
492{
493 /* Shared ACPI/GPIO decode with all ICH6+ */
494 ich6_lpc_acpi_gpio(dev);
495
496 /* ICH6-specific generic IO decode */
497 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
498 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
499}
500DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
501DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
502
503static void __devinit ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
504{
505 u32 val;
506 u32 mask, base;
507
508 pci_read_config_dword(dev, reg, &val);
509
510 /* Enabled? */
511 if (!(val & 1))
512 return;
513
514 /*
515 * IO base in bits 15:2, mask in bits 23:18, both
516 * are dword-based
517 */
518 base = val & 0xfffc;
519 mask = (val >> 16) & 0xfc;
520 mask |= 3;
521
522 /* Just print it out for now. We should reserve it after more debugging */
523 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
524}
525
526/* ICH7-10 has the same common LPC generic IO decode registers */
527static void __devinit quirk_ich7_lpc(struct pci_dev *dev)
528{
529 /* We share the common ACPI/DPIO decode with ICH6 */
530 ich6_lpc_acpi_gpio(dev);
531
532 /* And have 4 ICH7+ generic decodes */
533 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
534 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
535 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
536 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
537}
538DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
539DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
540DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
541DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
542DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
543DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
544DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
545DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
546DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
547DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
548DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
549DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
550DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
2cea752f 551
1da177e4
LT		 552/*
553 * VIA ACPI: One IO region pointed to by longword at
554 * 0x48 or 0x20 (256 bytes of ACPI registers)
555 */
556static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
557{
1da177e4
LT		 558 u32 region;
559
651472fb 560 if (dev->revision & 0x10) {
1da177e4
LT		 561 pci_read_config_dword(dev, 0x48, &region);
562 region &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 563 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
1da177e4
LT		 564 }
565}
652c538e 566DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
1da177e4
LT		 567
568/*
569 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
570 * 0x48 (256 bytes of ACPI registers)
571 * 0x70 (128 bytes of hardware monitoring register)
572 * 0x90 (16 bytes of SMB registers)
573 */
574static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
575{
576 u16 hm;
577 u32 smb;
578
579 quirk_vt82c586_acpi(dev);
580
581 pci_read_config_word(dev, 0x70, &hm);
582 hm &= PCI_BASE_ADDRESS_IO_MASK;
02f313b2 583 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
1da177e4
LT		 584
585 pci_read_config_dword(dev, 0x90, &smb);
586 smb &= PCI_BASE_ADDRESS_IO_MASK;
02f313b2 587 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
1da177e4 588}
652c538e 589DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
1da177e4 590
6d85f29b
IK		 591/*
592 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
593 * 0x88 (128 bytes of power management registers)
594 * 0xd0 (16 bytes of SMB registers)
595 */
596static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
597{
598 u16 pm, smb;
599
600 pci_read_config_word(dev, 0x88, &pm);
601 pm &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 602 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
6d85f29b
IK		 603
604 pci_read_config_word(dev, 0xd0, &smb);
605 smb &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 606 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
6d85f29b
IK		 607}
608DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
609
1da177e4
LT		 610
611#ifdef CONFIG_X86_IO_APIC
612
613#include <asm/io_apic.h>
614
615/*
616 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
617 * devices to the external APIC.
618 *
619 * TODO: When we have device-specific interrupt routers,
620 * this code will go away from quirks.
621 */
1597cacb 622static void quirk_via_ioapic(struct pci_dev *dev)
1da177e4
LT		 623{
624 u8 tmp;
625
626 if (nr_ioapics < 1)
627 tmp = 0; /* nothing routed to external APIC */
628 else
629 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
630
f0fda801 631 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
1da177e4
LT		 632 tmp == 0 ? "Disa" : "Ena");
633
634 /* Offset 0x58: External APIC IRQ output control */
635 pci_write_config_byte (dev, 0x58, tmp);
636}
652c538e 637DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
e1a2a51e 638DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
1da177e4 639
a1740913
KW		 640/*
641 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
642 * This leads to doubled level interrupt rates.
643 * Set this bit to get rid of cycle wastage.
644 * Otherwise uncritical.
645 */
1597cacb 646static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
a1740913
KW		 647{
648 u8 misc_control2;
649#define BYPASS_APIC_DEASSERT 8
650
651 pci_read_config_byte(dev, 0x5B, &misc_control2);
652 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
f0fda801 653 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
a1740913
KW		 654 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
655 }
656}
657DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
e1a2a51e 658DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
a1740913 659
1da177e4
LT		 660/*
661 * The AMD io apic can hang the box when an apic irq is masked.
662 * We check all revs >= B0 (yet not in the pre production!) as the bug
663 * is currently marked NoFix
664 *
665 * We have multiple reports of hangs with this chipset that went away with
236561e5 666 * noapic specified. For the moment we assume it's the erratum. We may be wrong
1da177e4
LT		 667 * of course. However the advice is demonstrably good even if so..
668 */
669static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
670{
44c10138 671 if (dev->revision >= 0x02) {
f0fda801 672 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
673 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
1da177e4
LT		 674 }
675}
652c538e 676DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
1da177e4
LT		 677
678static void __init quirk_ioapic_rmw(struct pci_dev *dev)
679{
680 if (dev->devfn == 0 && dev->bus->number == 0)
681 sis_apic_bug = 1;
682}
652c538e 683DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw);
1da177e4
LT		 684#endif /* CONFIG_X86_IO_APIC */
685
d556ad4b
PO		 686/*
687 * Some settings of MMRBC can lead to data corruption so block changes.
688 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
689 */
690static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev)
691{
aa288d4d 692 if (dev->subordinate && dev->revision <= 0x12) {
f0fda801 693 dev_info(&dev->dev, "AMD8131 rev %x detected; "
694 "disabling PCI-X MMRBC\n", dev->revision);
d556ad4b
PO		 695 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
696 }
697}
698DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
1da177e4 699
1da177e4
LT		 700/*
701 * FIXME: it is questionable that quirk_via_acpi
702 * is needed. It shows up as an ISA bridge, and does not
703 * support the PCI_INTERRUPT_LINE register at all. Therefore
704 * it seems like setting the pci_dev's 'irq' to the
705 * value of the ACPI SCI interrupt is only done for convenience.
706 * -jgarzik
707 */
708static void __devinit quirk_via_acpi(struct pci_dev *d)
709{
710 /*
711 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
712 */
713 u8 irq;
714 pci_read_config_byte(d, 0x42, &irq);
715 irq &= 0xf;
716 if (irq && (irq != 2))
717 d->irq = irq;
718}
652c538e
AM		 719DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
720DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
1da177e4 721
09d6029f
DD		 722
723/*
1597cacb 724 * VIA bridges which have VLink
09d6029f 725 */
1597cacb 726
c06bb5d4
JD		 727static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
728
729static void quirk_via_bridge(struct pci_dev *dev)
730{
731 /* See what bridge we have and find the device ranges */
732 switch (dev->device) {
733 case PCI_DEVICE_ID_VIA_82C686:
cb7468ef
JD		 734 /* The VT82C686 is special, it attaches to PCI and can have
735 any device number. All its subdevices are functions of
736 that single device. */
737 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
738 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
c06bb5d4
JD		 739 break;
740 case PCI_DEVICE_ID_VIA_8237:
741 case PCI_DEVICE_ID_VIA_8237A:
742 via_vlink_dev_lo = 15;
743 break;
744 case PCI_DEVICE_ID_VIA_8235:
745 via_vlink_dev_lo = 16;
746 break;
747 case PCI_DEVICE_ID_VIA_8231:
748 case PCI_DEVICE_ID_VIA_8233_0:
749 case PCI_DEVICE_ID_VIA_8233A:
750 case PCI_DEVICE_ID_VIA_8233C_0:
751 via_vlink_dev_lo = 17;
752 break;
753 }
754}
755DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
756DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
757DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
758DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
759DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
760DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
761DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
762DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
09d6029f 763
1597cacb
AC		 764/**
765 * quirk_via_vlink - VIA VLink IRQ number update
766 * @dev: PCI device
767 *
768 * If the device we are dealing with is on a PIC IRQ we need to
769 * ensure that the IRQ line register which usually is not relevant
770 * for PCI cards, is actually written so that interrupts get sent
c06bb5d4
JD		 771 * to the right place.
772 * We only do this on systems where a VIA south bridge was detected,
773 * and only for VIA devices on the motherboard (see quirk_via_bridge
774 * above).
1597cacb
AC		 775 */
776
777static void quirk_via_vlink(struct pci_dev *dev)
25be5e6c
LB		 778{
779 u8 irq, new_irq;
780
c06bb5d4
JD		 781 /* Check if we have VLink at all */
782 if (via_vlink_dev_lo == -1)
09d6029f
DD		 783 return;
784
785 new_irq = dev->irq;
786
787 /* Don't quirk interrupts outside the legacy IRQ range */
788 if (!new_irq || new_irq > 15)
789 return;
790
1597cacb 791 /* Internal device ? */
c06bb5d4
JD		 792 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
793 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
1597cacb
AC		 794 return;
795
796 /* This is an internal VLink device on a PIC interrupt. The BIOS
797 ought to have set this but may not have, so we redo it */
798
25be5e6c
LB		 799 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
800 if (new_irq != irq) {
f0fda801 801 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
802 irq, new_irq);
25be5e6c
LB		 803 udelay(15); /* unknown if delay really needed */
804 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
805 }
806}
1597cacb 807DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
25be5e6c 808
1da177e4
LT		 809/*
810 * VIA VT82C598 has its device ID settable and many BIOSes
811 * set it to the ID of VT82C597 for backward compatibility.
812 * We need to switch it off to be able to recognize the real
813 * type of the chip.
814 */
815static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
816{
817 pci_write_config_byte(dev, 0xfc, 0);
818 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
819}
652c538e 820DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
1da177e4
LT		 821
822/*
823 * CardBus controllers have a legacy base address that enables them
824 * to respond as i82365 pcmcia controllers. We don't want them to
825 * do this even if the Linux CardBus driver is not loaded, because
826 * the Linux i82365 driver does not (and should not) handle CardBus.
827 */
1597cacb 828static void quirk_cardbus_legacy(struct pci_dev *dev)
1da177e4
LT		 829{
830 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
831 return;
832 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
833}
834DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
e1a2a51e 835DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
1da177e4
LT		 836
837/*
838 * Following the PCI ordering rules is optional on the AMD762. I'm not
839 * sure what the designers were smoking but let's not inhale...
840 *
841 * To be fair to AMD, it follows the spec by default, its BIOS people
842 * who turn it off!
843 */
1597cacb 844static void quirk_amd_ordering(struct pci_dev *dev)
1da177e4
LT		 845{
846 u32 pcic;
847 pci_read_config_dword(dev, 0x4C, &pcic);
848 if ((pcic&6)!=6) {
849 pcic |= 6;
f0fda801 850 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1da177e4
LT		 851 pci_write_config_dword(dev, 0x4C, pcic);
852 pci_read_config_dword(dev, 0x84, &pcic);
853 pcic |= (1<<23); /* Required in this mode */
854 pci_write_config_dword(dev, 0x84, pcic);
855 }
856}
652c538e 857DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
e1a2a51e 858DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1da177e4
LT		 859
860/*
861 * DreamWorks provided workaround for Dunord I-3000 problem
862 *
863 * This card decodes and responds to addresses not apparently
864 * assigned to it. We force a larger allocation to ensure that
865 * nothing gets put too close to it.
866 */
867static void __devinit quirk_dunord ( struct pci_dev * dev )
868{
869 struct resource *r = &dev->resource [1];
870 r->start = 0;
871 r->end = 0xffffff;
872}
652c538e 873DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1da177e4
LT		 874
875/*
876 * i82380FB mobile docking controller: its PCI-to-PCI bridge
877 * is subtractive decoding (transparent), and does indicate this
878 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
879 * instead of 0x01.
880 */
881static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
882{
883 dev->transparent = 1;
884}
652c538e
AM		 885DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
886DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1da177e4
LT		 887
888/*
889 * Common misconfiguration of the MediaGX/Geode PCI master that will
890 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
891 * datasheets found at http://www.national.com/ds/GX for info on what
892 * these bits do. <christer@weinigel.se>
893 */
1597cacb 894static void quirk_mediagx_master(struct pci_dev *dev)
1da177e4
LT		 895{
896 u8 reg;
897 pci_read_config_byte(dev, 0x41, &reg);
898 if (reg & 2) {
899 reg &= ~2;
f0fda801 900 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
1da177e4
LT		 901 pci_write_config_byte(dev, 0x41, reg);
902 }
903}
652c538e
AM		 904DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
905DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1da177e4 906
1da177e4
LT		 907/*
908 * Ensure C0 rev restreaming is off. This is normally done by
909 * the BIOS but in the odd case it is not the results are corruption
910 * hence the presence of a Linux check
911 */
1597cacb 912static void quirk_disable_pxb(struct pci_dev *pdev)
1da177e4
LT		 913{
914 u16 config;
1da177e4 915
44c10138 916 if (pdev->revision != 0x04) /* Only C0 requires this */
1da177e4
LT		 917 return;
918 pci_read_config_word(pdev, 0x40, &config);
919 if (config & (1<<6)) {
920 config &= ~(1<<6);
921 pci_write_config_word(pdev, 0x40, config);
f0fda801 922 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
1da177e4
LT		 923 }
924}
652c538e 925DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
e1a2a51e 926DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1da177e4 927
05a7d22b 928static void __devinit quirk_amd_ide_mode(struct pci_dev *pdev)
ab17443a 929{
05a7d22b
CC		 930 /* set sb600/sb700/sb800 sata to ahci mode */
931 u8 tmp;
ab17443a 932
05a7d22b
CC		 933 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
934 if (tmp == 0x01) {
ab17443a
CH		 935 pci_read_config_byte(pdev, 0x40, &tmp);
936 pci_write_config_byte(pdev, 0x40, tmp|1);
937 pci_write_config_byte(pdev, 0x9, 1);
938 pci_write_config_byte(pdev, 0xa, 6);
939 pci_write_config_byte(pdev, 0x40, tmp);
940
c9f89475 941 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
05a7d22b 942 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
ab17443a
CH		 943 }
944}
05a7d22b 945DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
e1a2a51e 946DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
05a7d22b 947DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
e1a2a51e 948DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
ab17443a 949
1da177e4
LT		 950/*
951 * Serverworks CSB5 IDE does not fully support native mode
952 */
953static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
954{
955 u8 prog;
956 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
957 if (prog & 5) {
958 prog &= ~5;
959 pdev->class &= ~5;
960 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
368c73d4 961 /* PCI layer will sort out resources */
1da177e4
LT		 962 }
963}
652c538e 964DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1da177e4
LT		 965
966/*
967 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
968 */
969static void __init quirk_ide_samemode(struct pci_dev *pdev)
970{
971 u8 prog;
972
973 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
974
975 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
f0fda801 976 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
1da177e4
LT		 977 prog &= ~5;
978 pdev->class &= ~5;
979 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1da177e4
LT		 980 }
981}
368c73d4 982DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1da177e4 983
979b1791
AC		 984/*
985 * Some ATA devices break if put into D3
986 */
987
988static void __devinit quirk_no_ata_d3(struct pci_dev *pdev)
989{
990 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
991 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE)
992 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
993}
994DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, quirk_no_ata_d3);
995DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, quirk_no_ata_d3);
996
1da177e4
LT		 997/* This was originally an Alpha specific thing, but it really fits here.
998 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
999 */
1000static void __init quirk_eisa_bridge(struct pci_dev *dev)
1001{
1002 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1003}
652c538e 1004DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1da177e4 1005
7daa0c4f 1006
1da177e4
LT		 1007/*
1008 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1009 * is not activated. The myth is that Asus said that they do not want the
1010 * users to be irritated by just another PCI Device in the Win98 device
1011 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1012 * package 2.7.0 for details)
1013 *
1014 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1015 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
d7698edc 1016 * becomes necessary to do this tweak in two steps -- the chosen trigger
1017 * is either the Host bridge (preferred) or on-board VGA controller.
9208ee82
JD		 1018 *
1019 * Note that we used to unhide the SMBus that way on Toshiba laptops
1020 * (Satellite A40 and Tecra M2) but then found that the thermal management
1021 * was done by SMM code, which could cause unsynchronized concurrent
1022 * accesses to the SMBus registers, with potentially bad effects. Thus you
1023 * should be very careful when adding new entries: if SMM is accessing the
1024 * Intel SMBus, this is a very good reason to leave it hidden.
a99acc83
JD		 1025 *
1026 * Likewise, many recent laptops use ACPI for thermal management. If the
1027 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1028 * natively, and keeping the SMBus hidden is the right thing to do. If you
1029 * are about to add an entry in the table below, please first disassemble
1030 * the DSDT and double-check that there is no code accessing the SMBus.
1da177e4 1031 */
9d24a81e 1032static int asus_hides_smbus;
1da177e4
LT		 1033
1034static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
1035{
1036 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1037 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1038 switch(dev->subsystem_device) {
a00db371 1039 case 0x8025: /* P4B-LX */
1da177e4
LT		 1040 case 0x8070: /* P4B */
1041 case 0x8088: /* P4B533 */
1042 case 0x1626: /* L3C notebook */
1043 asus_hides_smbus = 1;
1044 }
2f2d39d2 1045 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1da177e4
LT		 1046 switch(dev->subsystem_device) {
1047 case 0x80b1: /* P4GE-V */
1048 case 0x80b2: /* P4PE */
1049 case 0x8093: /* P4B533-V */
1050 asus_hides_smbus = 1;
1051 }
2f2d39d2 1052 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1da177e4
LT		 1053 switch(dev->subsystem_device) {
1054 case 0x8030: /* P4T533 */
1055 asus_hides_smbus = 1;
1056 }
2f2d39d2 1057 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1da177e4
LT		 1058 switch (dev->subsystem_device) {
1059 case 0x8070: /* P4G8X Deluxe */
1060 asus_hides_smbus = 1;
1061 }
2f2d39d2 1062 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
321311af
JD		 1063 switch (dev->subsystem_device) {
1064 case 0x80c9: /* PU-DLS */
1065 asus_hides_smbus = 1;
1066 }
2f2d39d2 1067 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1da177e4
LT		 1068 switch (dev->subsystem_device) {
1069 case 0x1751: /* M2N notebook */
1070 case 0x1821: /* M5N notebook */
1071 asus_hides_smbus = 1;
1072 }
2f2d39d2 1073 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1da177e4
LT		 1074 switch (dev->subsystem_device) {
1075 case 0x184b: /* W1N notebook */
1076 case 0x186a: /* M6Ne notebook */
1077 asus_hides_smbus = 1;
1078 }
2f2d39d2 1079 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
2e45785c
JD		 1080 switch (dev->subsystem_device) {
1081 case 0x80f2: /* P4P800-X */
1082 asus_hides_smbus = 1;
1083 }
2f2d39d2 1084 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
acc06632
RM		 1085 switch (dev->subsystem_device) {
1086 case 0x1882: /* M6V notebook */
2d1e1c75 1087 case 0x1977: /* A6VA notebook */
acc06632
RM		 1088 asus_hides_smbus = 1;
1089 }
1da177e4
LT		 1090 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1091 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1092 switch(dev->subsystem_device) {
1093 case 0x088C: /* HP Compaq nc8000 */
1094 case 0x0890: /* HP Compaq nc6000 */
1095 asus_hides_smbus = 1;
1096 }
2f2d39d2 1097 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1da177e4
LT		 1098 switch (dev->subsystem_device) {
1099 case 0x12bc: /* HP D330L */
e3b1bd57 1100 case 0x12bd: /* HP D530 */
1da177e4
LT		 1101 asus_hides_smbus = 1;
1102 }
677cc644
JD		 1103 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1104 switch (dev->subsystem_device) {
1105 case 0x12bf: /* HP xw4100 */
1106 asus_hides_smbus = 1;
1107 }
1da177e4
LT		 1108 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1109 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1110 switch(dev->subsystem_device) {
1111 case 0xC00C: /* Samsung P35 notebook */
1112 asus_hides_smbus = 1;
1113 }
c87f883e
RIZ		 1114 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1115 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1116 switch(dev->subsystem_device) {
1117 case 0x0058: /* Compaq Evo N620c */
1118 asus_hides_smbus = 1;
1119 }
d7698edc 1120 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1121 switch(dev->subsystem_device) {
1122 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1123 /* Motherboard doesn't have Host bridge
1124 * subvendor/subdevice IDs, therefore checking
1125 * its on-board VGA controller */
1126 asus_hides_smbus = 1;
1127 }
10260d9a
JD		 1128 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_IG)
1129 switch(dev->subsystem_device) {
1130 case 0x00b8: /* Compaq Evo D510 CMT */
1131 case 0x00b9: /* Compaq Evo D510 SFF */
1132 asus_hides_smbus = 1;
1133 }
27e46859
KH		 1134 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1135 switch (dev->subsystem_device) {
1136 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1137 /* Motherboard doesn't have host bridge
1138 * subvendor/subdevice IDs, therefore checking
1139 * its on-board VGA controller */
1140 asus_hides_smbus = 1;
1141 }
1da177e4
LT		 1142 }
1143}
652c538e
AM		 1144DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1145DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1146DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1147DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
677cc644 1148DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
652c538e
AM		 1149DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1150DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1151DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1152DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1153DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1154
1155DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
10260d9a 1156DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_IG, asus_hides_smbus_hostbridge);
27e46859 1157DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
d7698edc 1158
1597cacb 1159static void asus_hides_smbus_lpc(struct pci_dev *dev)
1da177e4
LT		 1160{
1161 u16 val;
1162
1163 if (likely(!asus_hides_smbus))
1164 return;
1165
1166 pci_read_config_word(dev, 0xF2, &val);
1167 if (val & 0x8) {
1168 pci_write_config_word(dev, 0xF2, val & (~0x8));
1169 pci_read_config_word(dev, 0xF2, &val);
1170 if (val & 0x8)
f0fda801 1171 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1da177e4 1172 else
f0fda801 1173 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1da177e4
LT		 1174 }
1175}
652c538e
AM		 1176DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1177DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1178DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1179DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1180DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1181DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1182DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
e1a2a51e
RW		 1183DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1184DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1185DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1186DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1187DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1188DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1189DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1597cacb 1190
e1a2a51e
RW		 1191/* It appears we just have one such device. If not, we have a warning */
1192static void __iomem *asus_rcba_base;
1193static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
acc06632 1194{
e1a2a51e 1195 u32 rcba;
acc06632
RM		 1196
1197 if (likely(!asus_hides_smbus))
1198 return;
e1a2a51e
RW		 1199 WARN_ON(asus_rcba_base);
1200
acc06632 1201 pci_read_config_dword(dev, 0xF0, &rcba);
e1a2a51e
RW		 1202 /* use bits 31:14, 16 kB aligned */
1203 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1204 if (asus_rcba_base == NULL)
1205 return;
1206}
1207
1208static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1209{
1210 u32 val;
1211
1212 if (likely(!asus_hides_smbus || !asus_rcba_base))
1213 return;
1214 /* read the Function Disable register, dword mode only */
1215 val = readl(asus_rcba_base + 0x3418);
1216 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1217}
1218
1219static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1220{
1221 if (likely(!asus_hides_smbus || !asus_rcba_base))
1222 return;
1223 iounmap(asus_rcba_base);
1224 asus_rcba_base = NULL;
f0fda801 1225 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
acc06632 1226}
e1a2a51e
RW		 1227
1228static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1229{
1230 asus_hides_smbus_lpc_ich6_suspend(dev);
1231 asus_hides_smbus_lpc_ich6_resume_early(dev);
1232 asus_hides_smbus_lpc_ich6_resume(dev);
1233}
652c538e 1234DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
e1a2a51e
RW		 1235DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1236DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1237DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
ce007ea5 1238
1da177e4
LT		 1239/*
1240 * SiS 96x south bridge: BIOS typically hides SMBus device...
1241 */
1597cacb 1242static void quirk_sis_96x_smbus(struct pci_dev *dev)
1da177e4
LT		 1243{
1244 u8 val = 0;
1da177e4 1245 pci_read_config_byte(dev, 0x77, &val);
2f5c33b3 1246 if (val & 0x10) {
f0fda801 1247 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
2f5c33b3
MH		 1248 pci_write_config_byte(dev, 0x77, val & ~0x10);
1249 }
1da177e4 1250}
652c538e
AM		 1251DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1252DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1253DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1254DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
e1a2a51e
RW		 1255DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1256DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1257DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1258DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1da177e4 1259
1da177e4
LT		 1260/*
1261 * ... This is further complicated by the fact that some SiS96x south
1262 * bridges pretend to be 85C503/5513 instead. In that case see if we
1263 * spotted a compatible north bridge to make sure.
1264 * (pci_find_device doesn't work yet)
1265 *
1266 * We can also enable the sis96x bit in the discovery register..
1267 */
1da177e4
LT		 1268#define SIS_DETECT_REGISTER 0x40
1269
1597cacb 1270static void quirk_sis_503(struct pci_dev *dev)
1da177e4
LT		 1271{
1272 u8 reg;
1273 u16 devid;
1274
1275 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1276 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1277 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1278 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1279 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1280 return;
1281 }
1282
1da177e4 1283 /*
2f5c33b3
MH		 1284 * Ok, it now shows up as a 96x.. run the 96x quirk by
1285 * hand in case it has already been processed.
1286 * (depends on link order, which is apparently not guaranteed)
1da177e4
LT		 1287 */
1288 dev->device = devid;
2f5c33b3 1289 quirk_sis_96x_smbus(dev);
1da177e4 1290}
652c538e 1291DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
e1a2a51e 1292DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1da177e4 1293
1da177e4 1294
e5548e96
BJD		 1295/*
1296 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1297 * and MC97 modem controller are disabled when a second PCI soundcard is
1298 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1299 * -- bjd
1300 */
1597cacb 1301static void asus_hides_ac97_lpc(struct pci_dev *dev)
e5548e96
BJD		 1302{
1303 u8 val;
1304 int asus_hides_ac97 = 0;
1305
1306 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1307 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1308 asus_hides_ac97 = 1;
1309 }
1310
1311 if (!asus_hides_ac97)
1312 return;
1313
1314 pci_read_config_byte(dev, 0x50, &val);
1315 if (val & 0xc0) {
1316 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1317 pci_read_config_byte(dev, 0x50, &val);
1318 if (val & 0xc0)
f0fda801 1319 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
e5548e96 1320 else
f0fda801 1321 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
e5548e96
BJD		 1322 }
1323}
652c538e 1324DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
e1a2a51e 1325DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1597cacb 1326
77967052 1327#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
15e0c694
AC		 1328
1329/*
1330 * If we are using libata we can drive this chip properly but must
1331 * do this early on to make the additional device appear during
1332 * the PCI scanning.
1333 */
5ee2ae7f 1334static void quirk_jmicron_ata(struct pci_dev *pdev)
15e0c694 1335{
e34bb370 1336 u32 conf1, conf5, class;
15e0c694
AC		 1337 u8 hdr;
1338
1339 /* Only poke fn 0 */
1340 if (PCI_FUNC(pdev->devfn))
1341 return;
1342
5ee2ae7f
TH		 1343 pci_read_config_dword(pdev, 0x40, &conf1);
1344 pci_read_config_dword(pdev, 0x80, &conf5);
15e0c694 1345
5ee2ae7f
TH		 1346 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1347 conf5 &= ~(1 << 24); /* Clear bit 24 */
1348
1349 switch (pdev->device) {
1350 case PCI_DEVICE_ID_JMICRON_JMB360:
1351 /* The controller should be in single function ahci mode */
1352 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1353 break;
1354
1355 case PCI_DEVICE_ID_JMICRON_JMB365:
1356 case PCI_DEVICE_ID_JMICRON_JMB366:
1357 /* Redirect IDE second PATA port to the right spot */
1358 conf5 |= (1 << 24);
1359 /* Fall through */
1360 case PCI_DEVICE_ID_JMICRON_JMB361:
1361 case PCI_DEVICE_ID_JMICRON_JMB363:
1362 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1363 /* Set the class codes correctly and then direct IDE 0 */
3a9e3a51 1364 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
5ee2ae7f
TH		 1365 break;
1366
1367 case PCI_DEVICE_ID_JMICRON_JMB368:
1368 /* The controller should be in single function IDE mode */
1369 conf1 |= 0x00C00000; /* Set 22, 23 */
1370 break;
15e0c694 1371 }
5ee2ae7f
TH		 1372
1373 pci_write_config_dword(pdev, 0x40, conf1);
1374 pci_write_config_dword(pdev, 0x80, conf5);
1375
1376 /* Update pdev accordingly */
1377 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1378 pdev->hdr_type = hdr & 0x7f;
1379 pdev->multifunction = !!(hdr & 0x80);
e34bb370
TH		 1380
1381 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1382 pdev->class = class >> 8;
15e0c694 1383}
5ee2ae7f
TH		 1384DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1385DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1386DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1387DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1388DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1389DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
e1a2a51e
RW		 1390DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1391DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1392DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1393DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1394DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1395DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
15e0c694
AC		 1396
1397#endif
1398
1da177e4
LT		 1399#ifdef CONFIG_X86_IO_APIC
1400static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1401{
1402 int i;
1403
1404 if ((pdev->class >> 8) != 0xff00)
1405 return;
1406
1407 /* the first BAR is the location of the IO APIC...we must
1408 * not touch this (and it's already covered by the fixmap), so
1409 * forcibly insert it into the resource tree */
1410 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1411 insert_resource(&iomem_resource, &pdev->resource[0]);
1412
1413 /* The next five BARs all seem to be rubbish, so just clean
1414 * them out */
1415 for (i=1; i < 6; i++) {
1416 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1417 }
1418
1419}
652c538e 1420DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1da177e4
LT		 1421#endif
1422
1da177e4
LT		 1423static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1424{
1425 pcie_mch_quirk = 1;
1426}
652c538e
AM		 1427DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1428DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1429DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1da177e4 1430
4602b88d
KA		 1431
1432/*
1433 * It's possible for the MSI to get corrupted if shpc and acpi
1434 * are used together on certain PXH-based systems.
1435 */
1436static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1437{
f5f2b131 1438 pci_msi_off(dev);
4602b88d 1439 dev->no_msi = 1;
f0fda801 1440 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
4602b88d
KA		 1441}
1442DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1443DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1444DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1445DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1446DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1447
ffadcc2f
KCA		 1448/*
1449 * Some Intel PCI Express chipsets have trouble with downstream
1450 * device power management.
1451 */
1452static void quirk_intel_pcie_pm(struct pci_dev * dev)
1453{
1454 pci_pm_d3_delay = 120;
1455 dev->no_d1d2 = 1;
1456}
1457
1458DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1459DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1460DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1461DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1462DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1463DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1464DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1465DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1466DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1467DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1468DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1469DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1470DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1471DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1472DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1473DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1474DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1475DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1476DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1477DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1478DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
4602b88d 1479
426b3b8d 1480#ifdef CONFIG_X86_IO_APIC
e1d3a908
SA		 1481/*
1482 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1483 * remap the original interrupt in the linux kernel to the boot interrupt, so
1484 * that a PCI device's interrupt handler is installed on the boot interrupt
1485 * line instead.
1486 */
1487static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1488{
41b9eb26 1489 if (noioapicquirk || noioapicreroute)
e1d3a908
SA		 1490 return;
1491
1492 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1493
1494 printk(KERN_INFO "PCI quirk: reroute interrupts for 0x%04x:0x%04x\n",
1495 dev->vendor, dev->device);
1496 return;
1497}
88d1dce3
OD		 1498DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1499DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1500DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1501DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1502DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1503DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1504DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1505DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1506DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1507DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1508DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1509DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1510DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1511DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1512DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1513DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
e1d3a908 1514
426b3b8d
SA		 1515/*
1516 * On some chipsets we can disable the generation of legacy INTx boot
1517 * interrupts.
1518 */
1519
1520/*
1521 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1522 * 300641-004US, section 5.7.3.
1523 */
1524#define INTEL_6300_IOAPIC_ABAR 0x40
1525#define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1526
1527static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1528{
1529 u16 pci_config_word;
1530
1531 if (noioapicquirk)
1532 return;
1533
1534 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1535 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1536 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1537
1538 printk(KERN_INFO "disabled boot interrupt on device 0x%04x:0x%04x\n",
1539 dev->vendor, dev->device);
1540}
88d1dce3
OD		 1541DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1542DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
77251188
OD		 1543
1544/*
1545 * disable boot interrupts on HT-1000
1546 */
1547#define BC_HT1000_FEATURE_REG 0x64
1548#define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1549#define BC_HT1000_MAP_IDX 0xC00
1550#define BC_HT1000_MAP_DATA 0xC01
1551
1552static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1553{
1554 u32 pci_config_dword;
1555 u8 irq;
1556
1557 if (noioapicquirk)
1558 return;
1559
1560 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1561 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1562 BC_HT1000_PIC_REGS_ENABLE);
1563
1564 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1565 outb(irq, BC_HT1000_MAP_IDX);
1566 outb(0x00, BC_HT1000_MAP_DATA);
1567 }
1568
1569 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1570
1571 printk(KERN_INFO "disabled boot interrupts on PCI device"
1572 "0x%04x:0x%04x\n", dev->vendor, dev->device);
1573}
88d1dce3
OD		 1574DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1575DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
542622da
OD		 1576
1577/*
1578 * disable boot interrupts on AMD and ATI chipsets
1579 */
1580/*
1581 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1582 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1583 * (due to an erratum).
1584 */
1585#define AMD_813X_MISC 0x40
1586#define AMD_813X_NOIOAMODE (1<<0)
1587
1588static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1589{
1590 u32 pci_config_dword;
1591
1592 if (noioapicquirk)
1593 return;
1594
1595 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1596 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1597 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1598
1599 printk(KERN_INFO "disabled boot interrupts on PCI device "
1600 "0x%04x:0x%04x\n", dev->vendor, dev->device);
1601}
88d1dce3
OD		 1602DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1603DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
542622da
OD		 1604
1605#define AMD_8111_PCI_IRQ_ROUTING 0x56
1606
1607static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1608{
1609 u16 pci_config_word;
1610
1611 if (noioapicquirk)
1612 return;
1613
1614 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1615 if (!pci_config_word) {
1616 printk(KERN_INFO "boot interrupts on PCI device 0x%04x:0x%04x "
1617 "already disabled\n",
1618 dev->vendor, dev->device);
1619 return;
1620 }
1621 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
1622 printk(KERN_INFO "disabled boot interrupts on PCI device "
1623 "0x%04x:0x%04x\n", dev->vendor, dev->device);
1624}
88d1dce3
OD		 1625DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1626DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
426b3b8d
SA		 1627#endif /* CONFIG_X86_IO_APIC */
1628
33dced2e
SS		 1629/*
1630 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1631 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1632 * Re-allocate the region if needed...
1633 */
1634static void __init quirk_tc86c001_ide(struct pci_dev *dev)
1635{
1636 struct resource *r = &dev->resource[0];
1637
1638 if (r->start & 0x8) {
1639 r->start = 0;
1640 r->end = 0xf;
1641 }
1642}
1643DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1644 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1645 quirk_tc86c001_ide);
1646
1da177e4
LT		 1647static void __devinit quirk_netmos(struct pci_dev *dev)
1648{
1649 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1650 unsigned int num_serial = dev->subsystem_device & 0xf;
1651
1652 /*
1653 * These Netmos parts are multiport serial devices with optional
1654 * parallel ports. Even when parallel ports are present, they
1655 * are identified as class SERIAL, which means the serial driver
1656 * will claim them. To prevent this, mark them as class OTHER.
1657 * These combo devices should be claimed by parport_serial.
1658 *
1659 * The subdevice ID is of the form 0x00PS, where <P> is the number
1660 * of parallel ports and <S> is the number of serial ports.
1661 */
1662 switch (dev->device) {
1663 case PCI_DEVICE_ID_NETMOS_9735:
1664 case PCI_DEVICE_ID_NETMOS_9745:
1665 case PCI_DEVICE_ID_NETMOS_9835:
1666 case PCI_DEVICE_ID_NETMOS_9845:
1667 case PCI_DEVICE_ID_NETMOS_9855:
1668 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1669 num_parallel) {
f0fda801 1670 dev_info(&dev->dev, "Netmos %04x (%u parallel, "
1da177e4
LT		 1671 "%u serial); changing class SERIAL to OTHER "
1672 "(use parport_serial)\n",
1673 dev->device, num_parallel, num_serial);
1674 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1675 (dev->class & 0xff);
1676 }
1677 }
1678}
1679DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1680
16a74744
BH		 1681static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1682{
e64aeccb 1683 u16 command, pmcsr;
16a74744
BH		 1684 u8 __iomem *csr;
1685 u8 cmd_hi;
e64aeccb 1686 int pm;
16a74744
BH		 1687
1688 switch (dev->device) {
1689 /* PCI IDs taken from drivers/net/e100.c */
1690 case 0x1029:
1691 case 0x1030 ... 0x1034:
1692 case 0x1038 ... 0x103E:
1693 case 0x1050 ... 0x1057:
1694 case 0x1059:
1695 case 0x1064 ... 0x106B:
1696 case 0x1091 ... 0x1095:
1697 case 0x1209:
1698 case 0x1229:
1699 case 0x2449:
1700 case 0x2459:
1701 case 0x245D:
1702 case 0x27DC:
1703 break;
1704 default:
1705 return;
1706 }
1707
1708 /*
1709 * Some firmware hands off the e100 with interrupts enabled,
1710 * which can cause a flood of interrupts if packets are
1711 * received before the driver attaches to the device. So
1712 * disable all e100 interrupts here. The driver will
1713 * re-enable them when it's ready.
1714 */
1715 pci_read_config_word(dev, PCI_COMMAND, &command);
16a74744 1716
1bef7dc0 1717 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
16a74744
BH		 1718 return;
1719
e64aeccb
IK		 1720 /*
1721 * Check that the device is in the D0 power state. If it's not,
1722 * there is no point to look any further.
1723 */
1724 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1725 if (pm) {
1726 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
1727 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1728 return;
1729 }
1730
1bef7dc0
BH		 1731 /* Convert from PCI bus to resource space. */
1732 csr = ioremap(pci_resource_start(dev, 0), 8);
16a74744 1733 if (!csr) {
f0fda801 1734 dev_warn(&dev->dev, "Can't map e100 registers\n");
16a74744
BH		 1735 return;
1736 }
1737
1738 cmd_hi = readb(csr + 3);
1739 if (cmd_hi == 0) {
f0fda801 1740 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; "
1741 "disabling\n");
16a74744
BH		 1742 writeb(1, csr + 3);
1743 }
1744
1745 iounmap(csr);
1746}
4e68fc97 1747DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt);
a5312e28
IK		 1748
1749static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1750{
1751 /* rev 1 ncr53c810 chips don't set the class at all which means
1752 * they don't get their resources remapped. Fix that here.
1753 */
1754
1755 if (dev->class == PCI_CLASS_NOT_DEFINED) {
f0fda801 1756 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n");
a5312e28
IK		 1757 dev->class = PCI_CLASS_STORAGE_SCSI;
1758 }
1759}
1760DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1761
9d265124
DY		 1762/* Enable 1k I/O space granularity on the Intel P64H2 */
1763static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1764{
1765 u16 en1k;
1766 u8 io_base_lo, io_limit_lo;
1767 unsigned long base, limit;
1768 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1769
1770 pci_read_config_word(dev, 0x40, &en1k);
1771
1772 if (en1k & 0x200) {
f0fda801 1773 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
9d265124
DY		 1774
1775 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
1776 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
1777 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1778 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1779
1780 if (base <= limit) {
1781 res->start = base;
1782 res->end = limit + 0x3ff;
1783 }
1784 }
1785}
1786DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
1787
15a260d5
DY		 1788/* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2
1789 * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge()
1790 * in drivers/pci/setup-bus.c
1791 */
1792static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev)
1793{
1794 u16 en1k, iobl_adr, iobl_adr_1k;
1795 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1796
1797 pci_read_config_word(dev, 0x40, &en1k);
1798
1799 if (en1k & 0x200) {
1800 pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr);
1801
1802 iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00);
1803
1804 if (iobl_adr != iobl_adr_1k) {
f0fda801 1805 dev_info(&dev->dev, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n",
15a260d5
DY		 1806 iobl_adr,iobl_adr_1k);
1807 pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k);
1808 }
1809 }
1810}
1811DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl);
1812
cf34a8e0
BG		 1813/* Under some circumstances, AER is not linked with extended capabilities.
1814 * Force it to be linked by setting the corresponding control bit in the
1815 * config space.
1816 */
1597cacb 1817static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
cf34a8e0
BG		 1818{
1819 uint8_t b;
1820 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
1821 if (!(b & 0x20)) {
1822 pci_write_config_byte(dev, 0xf41, b | 0x20);
f0fda801 1823 dev_info(&dev->dev,
1824 "Linking AER extended capability\n");
cf34a8e0
BG		 1825 }
1826 }
1827}
1828DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1829 quirk_nvidia_ck804_pcie_aer_ext_cap);
e1a2a51e 1830DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1597cacb 1831 quirk_nvidia_ck804_pcie_aer_ext_cap);
cf34a8e0 1832
53a9bf42
TY		 1833static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
1834{
1835 /*
1836 * Disable PCI Bus Parking and PCI Master read caching on CX700
1837 * which causes unspecified timing errors with a VT6212L on the PCI
1838 * bus leading to USB2.0 packet loss. The defaults are that these
1839 * features are turned off but some BIOSes turn them on.
1840 */
1841
1842 uint8_t b;
1843 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
1844 if (b & 0x40) {
1845 /* Turn off PCI Bus Parking */
1846 pci_write_config_byte(dev, 0x76, b ^ 0x40);
1847
bc043274
TY		 1848 dev_info(&dev->dev,
1849 "Disabling VIA CX700 PCI parking\n");
1850 }
1851 }
1852
1853 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
1854 if (b != 0) {
53a9bf42
TY		 1855 /* Turn off PCI Master read caching */
1856 pci_write_config_byte(dev, 0x72, 0x0);
bc043274
TY		 1857
1858 /* Set PCI Master Bus time-out to "1x16 PCLK" */
53a9bf42 1859 pci_write_config_byte(dev, 0x75, 0x1);
bc043274
TY		 1860
1861 /* Disable "Read FIFO Timer" */
53a9bf42
TY		 1862 pci_write_config_byte(dev, 0x77, 0x0);
1863
d6505a52 1864 dev_info(&dev->dev,
bc043274 1865 "Disabling VIA CX700 PCI caching\n");
53a9bf42
TY		 1866 }
1867 }
1868}
1869DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
1870
99cb233d
BL		 1871/*
1872 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
1873 * VPD end tag will hang the device. This problem was initially
1874 * observed when a vpd entry was created in sysfs
1875 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
1876 * will dump 32k of data. Reading a full 32k will cause an access
1877 * beyond the VPD end tag causing the device to hang. Once the device
1878 * is hung, the bnx2 driver will not be able to reset the device.
1879 * We believe that it is legal to read beyond the end tag and
1880 * therefore the solution is to limit the read/write length.
1881 */
1882static void __devinit quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
1883{
9d82d8ea 1884 /*
35405f25
DH		 1885 * Only disable the VPD capability for 5706, 5706S, 5708,
1886 * 5708S and 5709 rev. A
9d82d8ea 1887 */
99cb233d 1888 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
35405f25 1889 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
99cb233d 1890 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
9d82d8ea 1891 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
99cb233d
BL		 1892 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
1893 (dev->revision & 0xf0) == 0x0)) {
1894 if (dev->vpd)
1895 dev->vpd->len = 0x80;
1896 }
1897}
1898
bffadffd
YZ		 1899DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1900 PCI_DEVICE_ID_NX2_5706,
1901 quirk_brcm_570x_limit_vpd);
1902DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1903 PCI_DEVICE_ID_NX2_5706S,
1904 quirk_brcm_570x_limit_vpd);
1905DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1906 PCI_DEVICE_ID_NX2_5708,
1907 quirk_brcm_570x_limit_vpd);
1908DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1909 PCI_DEVICE_ID_NX2_5708S,
1910 quirk_brcm_570x_limit_vpd);
1911DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1912 PCI_DEVICE_ID_NX2_5709,
1913 quirk_brcm_570x_limit_vpd);
1914DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1915 PCI_DEVICE_ID_NX2_5709S,
1916 quirk_brcm_570x_limit_vpd);
99cb233d 1917
3f79e107 1918#ifdef CONFIG_PCI_MSI
ebdf7d39
TH		 1919/* Some chipsets do not support MSI. We cannot easily rely on setting
1920 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
1921 * some other busses controlled by the chipset even if Linux is not
1922 * aware of it. Instead of setting the flag on all busses in the
1923 * machine, simply disable MSI globally.
3f79e107 1924 */
ebdf7d39 1925static void __init quirk_disable_all_msi(struct pci_dev *dev)
3f79e107 1926{
88187dfa 1927 pci_no_msi();
f0fda801 1928 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
3f79e107 1929}
ebdf7d39
TH		 1930DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
1931DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
1932DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
66d715c9 1933DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
184b812f 1934DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
3f79e107
BG		 1935
1936/* Disable MSI on chipsets that are known to not support it */
1937static void __devinit quirk_disable_msi(struct pci_dev *dev)
1938{
1939 if (dev->subordinate) {
f0fda801 1940 dev_warn(&dev->dev, "MSI quirk detected; "
1941 "subordinate MSI disabled\n");
3f79e107
BG		 1942 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1943 }
1944}
1945DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
6397c75c
BG		 1946
1947/* Go through the list of Hypertransport capabilities and
1948 * return 1 if a HT MSI capability is found and enabled */
1949static int __devinit msi_ht_cap_enabled(struct pci_dev *dev)
1950{
7a380507
ME		 1951 int pos, ttl = 48;
1952
1953 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
1954 while (pos && ttl--) {
1955 u8 flags;
1956
1957 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
1958 &flags) == 0)
1959 {
f0fda801 1960 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
7a380507 1961 flags & HT_MSI_FLAGS_ENABLE ?
f0fda801 1962 "enabled" : "disabled");
7a380507 1963 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
6397c75c 1964 }
7a380507
ME		 1965
1966 pos = pci_find_next_ht_capability(dev, pos,
1967 HT_CAPTYPE_MSI_MAPPING);
6397c75c
BG		 1968 }
1969 return 0;
1970}
1971
1972/* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
1973static void __devinit quirk_msi_ht_cap(struct pci_dev *dev)
1974{
1975 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
f0fda801 1976 dev_warn(&dev->dev, "MSI quirk detected; "
1977 "subordinate MSI disabled\n");
6397c75c
BG		 1978 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1979 }
1980}
1981DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
1982 quirk_msi_ht_cap);
6bae1d96 1983
6397c75c
BG		 1984/* The nVidia CK804 chipset may have 2 HT MSI mappings.
1985 * MSI are supported if the MSI capability set in any of these mappings.
1986 */
1987static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
1988{
1989 struct pci_dev *pdev;
1990
1991 if (!dev->subordinate)
1992 return;
1993
1994 /* check HT MSI cap on this chipset and the root one.
1995 * a single one having MSI is enough to be sure that MSI are supported.
1996 */
11f242f0 1997 pdev = pci_get_slot(dev->bus, 0);
9ac0ce85
JJ		 1998 if (!pdev)
1999 return;
0c875c28 2000 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
f0fda801 2001 dev_warn(&dev->dev, "MSI quirk detected; "
2002 "subordinate MSI disabled\n");
6397c75c
BG		 2003 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2004 }
11f242f0 2005 pci_dev_put(pdev);
6397c75c
BG		 2006}
2007DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2008 quirk_nvidia_ck804_msi_ht_cap);
ba698ad4 2009
415b6d0e
BH		 2010/* Force enable MSI mapping capability on HT bridges */
2011static void __devinit ht_enable_msi_mapping(struct pci_dev *dev)
9dc625e7
PC		 2012{
2013 int pos, ttl = 48;
2014
2015 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2016 while (pos && ttl--) {
2017 u8 flags;
2018
2019 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2020 &flags) == 0) {
2021 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2022
2023 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2024 flags | HT_MSI_FLAGS_ENABLE);
2025 }
2026 pos = pci_find_next_ht_capability(dev, pos,
2027 HT_CAPTYPE_MSI_MAPPING);
2028 }
2029}
415b6d0e
BH		 2030DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2031 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2032 ht_enable_msi_mapping);
9dc625e7 2033
e0ae4f55
YL		 2034DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2035 ht_enable_msi_mapping);
2036
75e07fc3
AP		 2037/* The P5N32-SLI Premium motherboard from Asus has a problem with msi
2038 * for the MCP55 NIC. It is not yet determined whether the msi problem
2039 * also affects other devices. As for now, turn off msi for this device.
2040 */
2041static void __devinit nvenet_msi_disable(struct pci_dev *dev)
2042{
2043 if (dmi_name_in_vendors("P5N32-SLI PREMIUM")) {
2044 dev_info(&dev->dev,
2045 "Disabling msi for MCP55 NIC on P5N32-SLI Premium\n");
2046 dev->no_msi = 1;
2047 }
2048}
2049DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2050 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2051 nvenet_msi_disable);
2052
1dec6b05 2053static void __devinit nv_ht_enable_msi_mapping(struct pci_dev *dev)
9dc625e7
PC		 2054{
2055 struct pci_dev *host_bridge;
1dec6b05
YL		 2056 int pos;
2057 int i, dev_no;
2058 int found = 0;
2059
2060 dev_no = dev->devfn >> 3;
2061 for (i = dev_no; i >= 0; i--) {
2062 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2063 if (!host_bridge)
2064 continue;
2065
2066 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2067 if (pos != 0) {
2068 found = 1;
2069 break;
2070 }
2071 pci_dev_put(host_bridge);
2072 }
2073
2074 if (!found)
2075 return;
2076
2077 /* root did that ! */
2078 if (msi_ht_cap_enabled(host_bridge))
2079 goto out;
2080
2081 ht_enable_msi_mapping(dev);
2082
2083out:
2084 pci_dev_put(host_bridge);
2085}
2086
2087static void __devinit ht_disable_msi_mapping(struct pci_dev *dev)
2088{
2089 int pos, ttl = 48;
2090
2091 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2092 while (pos && ttl--) {
2093 u8 flags;
2094
2095 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2096 &flags) == 0) {
2097 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2098
2099 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2100 flags & ~HT_MSI_FLAGS_ENABLE);
2101 }
2102 pos = pci_find_next_ht_capability(dev, pos,
2103 HT_CAPTYPE_MSI_MAPPING);
2104 }
2105}
2106
2107static int __devinit ht_check_msi_mapping(struct pci_dev *dev)
2108{
9dc625e7 2109 int pos, ttl = 48;
1dec6b05
YL		 2110 int found = 0;
2111
2112 /* check if there is HT MSI cap or enabled on this device */
2113 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2114 while (pos && ttl--) {
2115 u8 flags;
2116
2117 if (found < 1)
2118 found = 1;
2119 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2120 &flags) == 0) {
2121 if (flags & HT_MSI_FLAGS_ENABLE) {
2122 if (found < 2) {
2123 found = 2;
2124 break;
2125 }
2126 }
2127 }
2128 pos = pci_find_next_ht_capability(dev, pos,
2129 HT_CAPTYPE_MSI_MAPPING);
2130 }
2131
2132 return found;
2133}
2134
2135static void __devinit nv_msi_ht_cap_quirk(struct pci_dev *dev)
2136{
2137 struct pci_dev *host_bridge;
2138 int pos;
2139 int found;
2140
2141 /* check if there is HT MSI cap or enabled on this device */
2142 found = ht_check_msi_mapping(dev);
2143
2144 /* no HT MSI CAP */
2145 if (found == 0)
2146 return;
9dc625e7
PC		 2147
2148 /*
2149 * HT MSI mapping should be disabled on devices that are below
2150 * a non-Hypertransport host bridge. Locate the host bridge...
2151 */
2152 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2153 if (host_bridge == NULL) {
2154 dev_warn(&dev->dev,
2155 "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2156 return;
2157 }
2158
2159 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2160 if (pos != 0) {
2161 /* Host bridge is to HT */
1dec6b05
YL		 2162 if (found == 1) {
2163 /* it is not enabled, try to enable it */
2164 nv_ht_enable_msi_mapping(dev);
2165 }
9dc625e7
PC		 2166 return;
2167 }
2168
1dec6b05
YL		 2169 /* HT MSI is not enabled */
2170 if (found == 1)
2171 return;
9dc625e7 2172
1dec6b05
YL		 2173 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2174 ht_disable_msi_mapping(dev);
9dc625e7
PC		 2175}
2176DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk);
439a7733 2177DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk);
9dc625e7 2178
ba698ad4
DM		 2179static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev)
2180{
2181 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2182}
4600c9d7
SH		 2183static void __devinit quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2184{
2185 struct pci_dev *p;
2186
2187 /* SB700 MSI issue will be fixed at HW level from revision A21,
2188 * we need check PCI REVISION ID of SMBus controller to get SB700
2189 * revision.
2190 */
2191 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2192 NULL);
2193 if (!p)
2194 return;
2195
2196 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2197 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2198 pci_dev_put(p);
2199}
ba698ad4
DM		 2200DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2201 PCI_DEVICE_ID_TIGON3_5780,
2202 quirk_msi_intx_disable_bug);
2203DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2204 PCI_DEVICE_ID_TIGON3_5780S,
2205 quirk_msi_intx_disable_bug);
2206DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2207 PCI_DEVICE_ID_TIGON3_5714,
2208 quirk_msi_intx_disable_bug);
2209DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2210 PCI_DEVICE_ID_TIGON3_5714S,
2211 quirk_msi_intx_disable_bug);
2212DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2213 PCI_DEVICE_ID_TIGON3_5715,
2214 quirk_msi_intx_disable_bug);
2215DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2216 PCI_DEVICE_ID_TIGON3_5715S,
2217 quirk_msi_intx_disable_bug);
2218
bc38b411 2219DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
4600c9d7 2220 quirk_msi_intx_disable_ati_bug);
bc38b411 2221DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
4600c9d7 2222 quirk_msi_intx_disable_ati_bug);
bc38b411 2223DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
4600c9d7 2224 quirk_msi_intx_disable_ati_bug);
bc38b411 2225DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
4600c9d7 2226 quirk_msi_intx_disable_ati_bug);
bc38b411 2227DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
4600c9d7 2228 quirk_msi_intx_disable_ati_bug);
bc38b411
DM		 2229
2230DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2231 quirk_msi_intx_disable_bug);
2232DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2233 quirk_msi_intx_disable_bug);
2234DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2235 quirk_msi_intx_disable_bug);
2236
3f79e107 2237#endif /* CONFIG_PCI_MSI */
3d137310 2238
bfb0f330
JB		 2239static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
2240 struct pci_fixup *end)
3d137310
TP		 2241{
2242 while (f < end) {
2243 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
bfb0f330 2244 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
c9bbb4ab 2245 dev_dbg(&dev->dev, "calling %pF\n", f->hook);
3d137310
TP		 2246 f->hook(dev);
2247 }
2248 f++;
2249 }
2250}
2251
2252extern struct pci_fixup __start_pci_fixups_early[];
2253extern struct pci_fixup __end_pci_fixups_early[];
2254extern struct pci_fixup __start_pci_fixups_header[];
2255extern struct pci_fixup __end_pci_fixups_header[];
2256extern struct pci_fixup __start_pci_fixups_final[];
2257extern struct pci_fixup __end_pci_fixups_final[];
2258extern struct pci_fixup __start_pci_fixups_enable[];
2259extern struct pci_fixup __end_pci_fixups_enable[];
2260extern struct pci_fixup __start_pci_fixups_resume[];
2261extern struct pci_fixup __end_pci_fixups_resume[];
2262extern struct pci_fixup __start_pci_fixups_resume_early[];
2263extern struct pci_fixup __end_pci_fixups_resume_early[];
2264extern struct pci_fixup __start_pci_fixups_suspend[];
2265extern struct pci_fixup __end_pci_fixups_suspend[];
2266
2267
2268void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
2269{
2270 struct pci_fixup *start, *end;
2271
2272 switch(pass) {
2273 case pci_fixup_early:
2274 start = __start_pci_fixups_early;
2275 end = __end_pci_fixups_early;
2276 break;
2277
2278 case pci_fixup_header:
2279 start = __start_pci_fixups_header;
2280 end = __end_pci_fixups_header;
2281 break;
2282
2283 case pci_fixup_final:
2284 start = __start_pci_fixups_final;
2285 end = __end_pci_fixups_final;
2286 break;
2287
2288 case pci_fixup_enable:
2289 start = __start_pci_fixups_enable;
2290 end = __end_pci_fixups_enable;
2291 break;
2292
2293 case pci_fixup_resume:
2294 start = __start_pci_fixups_resume;
2295 end = __end_pci_fixups_resume;
2296 break;
2297
2298 case pci_fixup_resume_early:
2299 start = __start_pci_fixups_resume_early;
2300 end = __end_pci_fixups_resume_early;
2301 break;
2302
2303 case pci_fixup_suspend:
2304 start = __start_pci_fixups_suspend;
2305 end = __end_pci_fixups_suspend;
2306 break;
2307
2308 default:
2309 /* stupid compiler warning, you would think with an enum... */
2310 return;
2311 }
2312 pci_do_fixups(dev, start, end);
2313}
2314#else
2315void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) {}
2316#endif
2317EXPORT_SYMBOL(pci_fixup_device);
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