]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/pci/quirks.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[PATCH] NOMMU: don't try and give NULL to fput()
[mirror_ubuntu-bionic-kernel.git] / drivers / pci / quirks.c
CommitLineData
1da177e4
LT		 1/*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
7586269c
DB		 10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 *
1da177e4
LT		 13 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
16 */
17
1da177e4
LT		 18#include <linux/types.h>
19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/init.h>
22#include <linux/delay.h>
25be5e6c 23#include <linux/acpi.h>
bc56b9e0 24#include "pci.h"
1da177e4 25
bd8481e1
DT		 26/* The Mellanox Tavor device gives false positive parity errors
27 * Mark this device with a broken_parity_status, to allow
28 * PCI scanning code to "skip" this now blacklisted device.
29 */
30static void __devinit quirk_mellanox_tavor(struct pci_dev *dev)
31{
32 dev->broken_parity_status = 1; /* This device gives false positives */
33}
34DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
35DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
36
1da177e4
LT		 37/* Deal with broken BIOS'es that neglect to enable passive release,
38 which can cause problems in combination with the 82441FX/PPro MTRRs */
39static void __devinit quirk_passive_release(struct pci_dev *dev)
40{
41 struct pci_dev *d = NULL;
42 unsigned char dlc;
43
44 /* We have to make sure a particular bit is set in the PIIX3
45 ISA bridge, so we have to go out and find it. */
46 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
47 pci_read_config_byte(d, 0x82, &dlc);
48 if (!(dlc & 1<<1)) {
49 printk(KERN_ERR "PCI: PIIX3: Enabling Passive Release on %s\n", pci_name(d));
50 dlc |= 1<<1;
51 pci_write_config_byte(d, 0x82, dlc);
52 }
53 }
54}
55DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release );
56
57/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
58 but VIA don't answer queries. If you happen to have good contacts at VIA
59 ask them for me please -- Alan
60
61 This appears to be BIOS not version dependent. So presumably there is a
62 chipset level fix */
63int isa_dma_bridge_buggy; /* Exported */
64
65static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
66{
67 if (!isa_dma_bridge_buggy) {
68 isa_dma_bridge_buggy=1;
69 printk(KERN_INFO "Activating ISA DMA hang workarounds.\n");
70 }
71}
72 /*
73 * Its not totally clear which chipsets are the problematic ones
74 * We know 82C586 and 82C596 variants are affected.
75 */
76DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs );
77DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs );
78DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs );
79DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs );
80DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs );
81DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs );
82DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs );
83
84int pci_pci_problems;
85
86/*
87 * Chipsets where PCI->PCI transfers vanish or hang
88 */
89static void __devinit quirk_nopcipci(struct pci_dev *dev)
90{
91 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
92 printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n");
93 pci_pci_problems |= PCIPCI_FAIL;
94 }
95}
96DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci );
97DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci );
98
99/*
100 * Triton requires workarounds to be used by the drivers
101 */
102static void __devinit quirk_triton(struct pci_dev *dev)
103{
104 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
105 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
106 pci_pci_problems |= PCIPCI_TRITON;
107 }
108}
109DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton );
110DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton );
111DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton );
112DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton );
113
114/*
115 * VIA Apollo KT133 needs PCI latency patch
116 * Made according to a windows driver based patch by George E. Breese
117 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
118 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
119 * the info on which Mr Breese based his work.
120 *
121 * Updated based on further information from the site and also on
122 * information provided by VIA
123 */
124static void __devinit quirk_vialatency(struct pci_dev *dev)
125{
126 struct pci_dev *p;
127 u8 rev;
128 u8 busarb;
129 /* Ok we have a potential problem chipset here. Now see if we have
130 a buggy southbridge */
131
132 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
133 if (p!=NULL) {
134 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
135 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
136 /* Check for buggy part revisions */
137 if (rev < 0x40 || rev > 0x42)
138 goto exit;
139 } else {
140 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
141 if (p==NULL) /* No problem parts */
142 goto exit;
143 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
144 /* Check for buggy part revisions */
145 if (rev < 0x10 || rev > 0x12)
146 goto exit;
147 }
148
149 /*
150 * Ok we have the problem. Now set the PCI master grant to
151 * occur every master grant. The apparent bug is that under high
152 * PCI load (quite common in Linux of course) you can get data
153 * loss when the CPU is held off the bus for 3 bus master requests
154 * This happens to include the IDE controllers....
155 *
156 * VIA only apply this fix when an SB Live! is present but under
157 * both Linux and Windows this isnt enough, and we have seen
158 * corruption without SB Live! but with things like 3 UDMA IDE
159 * controllers. So we ignore that bit of the VIA recommendation..
160 */
161
162 pci_read_config_byte(dev, 0x76, &busarb);
163 /* Set bit 4 and bi 5 of byte 76 to 0x01
164 "Master priority rotation on every PCI master grant */
165 busarb &= ~(1<<5);
166 busarb |= (1<<4);
167 pci_write_config_byte(dev, 0x76, busarb);
168 printk(KERN_INFO "Applying VIA southbridge workaround.\n");
169exit:
170 pci_dev_put(p);
171}
172DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency );
173DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency );
174DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency );
175
176/*
177 * VIA Apollo VP3 needs ETBF on BT848/878
178 */
179static void __devinit quirk_viaetbf(struct pci_dev *dev)
180{
181 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
182 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
183 pci_pci_problems |= PCIPCI_VIAETBF;
184 }
185}
186DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf );
187
188static void __devinit quirk_vsfx(struct pci_dev *dev)
189{
190 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
191 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
192 pci_pci_problems |= PCIPCI_VSFX;
193 }
194}
195DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx );
196
197/*
198 * Ali Magik requires workarounds to be used by the drivers
199 * that DMA to AGP space. Latency must be set to 0xA and triton
200 * workaround applied too
201 * [Info kindly provided by ALi]
202 */
203static void __init quirk_alimagik(struct pci_dev *dev)
204{
205 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
206 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
207 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
208 }
209}
210DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik );
211DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik );
212
213/*
214 * Natoma has some interesting boundary conditions with Zoran stuff
215 * at least
216 */
217static void __devinit quirk_natoma(struct pci_dev *dev)
218{
219 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
220 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
221 pci_pci_problems |= PCIPCI_NATOMA;
222 }
223}
224DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma );
225DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma );
226DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma );
227DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma );
228DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma );
229DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma );
230
231/*
232 * This chip can cause PCI parity errors if config register 0xA0 is read
233 * while DMAs are occurring.
234 */
235static void __devinit quirk_citrine(struct pci_dev *dev)
236{
237 dev->cfg_size = 0xA0;
238}
239DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine );
240
241/*
242 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
243 * If it's needed, re-allocate the region.
244 */
245static void __devinit quirk_s3_64M(struct pci_dev *dev)
246{
247 struct resource *r = &dev->resource[0];
248
249 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
250 r->start = 0;
251 r->end = 0x3ffffff;
252 }
253}
254DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M );
255DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M );
256
6693e74a
LT		 257static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
258 unsigned size, int nr, const char *name)
1da177e4
LT		 259{
260 region &= ~(size-1);
261 if (region) {
085ae41f 262 struct pci_bus_region bus_region;
1da177e4
LT		 263 struct resource *res = dev->resource + nr;
264
265 res->name = pci_name(dev);
266 res->start = region;
267 res->end = region + size - 1;
268 res->flags = IORESOURCE_IO;
085ae41f
DM		 269
270 /* Convert from PCI bus to resource space. */
271 bus_region.start = res->start;
272 bus_region.end = res->end;
273 pcibios_bus_to_resource(dev, res, &bus_region);
274
1da177e4 275 pci_claim_resource(dev, nr);
6693e74a 276 printk("PCI quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name);
1da177e4
LT		 277 }
278}
279
280/*
281 * ATI Northbridge setups MCE the processor if you even
282 * read somewhere between 0x3b0->0x3bb or read 0x3d3
283 */
284static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
285{
286 printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n");
287 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
288 request_region(0x3b0, 0x0C, "RadeonIGP");
289 request_region(0x3d3, 0x01, "RadeonIGP");
290}
291DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce );
292
293/*
294 * Let's make the southbridge information explicit instead
295 * of having to worry about people probing the ACPI areas,
296 * for example.. (Yes, it happens, and if you read the wrong
297 * ACPI register it will put the machine to sleep with no
298 * way of waking it up again. Bummer).
299 *
300 * ALI M7101: Two IO regions pointed to by words at
301 * 0xE0 (64 bytes of ACPI registers)
302 * 0xE2 (32 bytes of SMB registers)
303 */
304static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
305{
306 u16 region;
307
308 pci_read_config_word(dev, 0xE0, &region);
6693e74a 309 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
1da177e4 310 pci_read_config_word(dev, 0xE2, &region);
6693e74a 311 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
1da177e4
LT		 312}
313DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi );
314
6693e74a
LT		 315static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
316{
317 u32 devres;
318 u32 mask, size, base;
319
320 pci_read_config_dword(dev, port, &devres);
321 if ((devres & enable) != enable)
322 return;
323 mask = (devres >> 16) & 15;
324 base = devres & 0xffff;
325 size = 16;
326 for (;;) {
327 unsigned bit = size >> 1;
328 if ((bit & mask) == bit)
329 break;
330 size = bit;
331 }
332 /*
333 * For now we only print it out. Eventually we'll want to
334 * reserve it (at least if it's in the 0x1000+ range), but
335 * let's get enough confirmation reports first.
336 */
337 base &= -size;
338 printk("%s PIO at %04x-%04x\n", name, base, base + size - 1);
339}
340
341static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
342{
343 u32 devres;
344 u32 mask, size, base;
345
346 pci_read_config_dword(dev, port, &devres);
347 if ((devres & enable) != enable)
348 return;
349 base = devres & 0xffff0000;
350 mask = (devres & 0x3f) << 16;
351 size = 128 << 16;
352 for (;;) {
353 unsigned bit = size >> 1;
354 if ((bit & mask) == bit)
355 break;
356 size = bit;
357 }
358 /*
359 * For now we only print it out. Eventually we'll want to
360 * reserve it, but let's get enough confirmation reports first.
361 */
362 base &= -size;
363 printk("%s MMIO at %04x-%04x\n", name, base, base + size - 1);
364}
365
1da177e4
LT		 366/*
367 * PIIX4 ACPI: Two IO regions pointed to by longwords at
368 * 0x40 (64 bytes of ACPI registers)
08db2a70 369 * 0x90 (16 bytes of SMB registers)
6693e74a 370 * and a few strange programmable PIIX4 device resources.
1da177e4
LT		 371 */
372static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
373{
6693e74a 374 u32 region, res_a;
1da177e4
LT		 375
376 pci_read_config_dword(dev, 0x40, &region);
6693e74a 377 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
1da177e4 378 pci_read_config_dword(dev, 0x90, &region);
08db2a70 379 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
6693e74a
LT		 380
381 /* Device resource A has enables for some of the other ones */
382 pci_read_config_dword(dev, 0x5c, &res_a);
383
384 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
385 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
386
387 /* Device resource D is just bitfields for static resources */
388
389 /* Device 12 enabled? */
390 if (res_a & (1 << 29)) {
391 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
392 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
393 }
394 /* Device 13 enabled? */
395 if (res_a & (1 << 30)) {
396 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
397 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
398 }
399 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
400 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
1da177e4
LT		 401}
402DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi );
c6764664 403DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi );
1da177e4
LT		 404
405/*
406 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
407 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
408 * 0x58 (64 bytes of GPIO I/O space)
409 */
410static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
411{
412 u32 region;
413
414 pci_read_config_dword(dev, 0x40, &region);
6693e74a 415 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO");
1da177e4
LT		 416
417 pci_read_config_dword(dev, 0x58, &region);
6693e74a 418 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO");
1da177e4
LT		 419}
420DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi );
421DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi );
422DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi );
423DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi );
424DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi );
425DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi );
426DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi );
427DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi );
428DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi );
3aa8c4fe 429DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi );
1da177e4 430
2cea752f
RM		 431static void __devinit quirk_ich6_lpc_acpi(struct pci_dev *dev)
432{
433 u32 region;
434
435 pci_read_config_dword(dev, 0x40, &region);
436 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO");
437
438 pci_read_config_dword(dev, 0x48, &region);
439 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO");
440}
65ae4ddd 441DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc_acpi );
2cea752f
RM		 442DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc_acpi );
443
1da177e4
LT		 444/*
445 * VIA ACPI: One IO region pointed to by longword at
446 * 0x48 or 0x20 (256 bytes of ACPI registers)
447 */
448static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
449{
450 u8 rev;
451 u32 region;
452
453 pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
454 if (rev & 0x10) {
455 pci_read_config_dword(dev, 0x48, &region);
456 region &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 457 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
1da177e4
LT		 458 }
459}
460DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi );
461
462/*
463 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
464 * 0x48 (256 bytes of ACPI registers)
465 * 0x70 (128 bytes of hardware monitoring register)
466 * 0x90 (16 bytes of SMB registers)
467 */
468static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
469{
470 u16 hm;
471 u32 smb;
472
473 quirk_vt82c586_acpi(dev);
474
475 pci_read_config_word(dev, 0x70, &hm);
476 hm &= PCI_BASE_ADDRESS_IO_MASK;
02f313b2 477 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
1da177e4
LT		 478
479 pci_read_config_dword(dev, 0x90, &smb);
480 smb &= PCI_BASE_ADDRESS_IO_MASK;
02f313b2 481 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
1da177e4
LT		 482}
483DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi );
484
6d85f29b
IK		 485/*
486 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
487 * 0x88 (128 bytes of power management registers)
488 * 0xd0 (16 bytes of SMB registers)
489 */
490static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
491{
492 u16 pm, smb;
493
494 pci_read_config_word(dev, 0x88, &pm);
495 pm &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 496 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
6d85f29b
IK		 497
498 pci_read_config_word(dev, 0xd0, &smb);
499 smb &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 500 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
6d85f29b
IK		 501}
502DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
503
1da177e4
LT		 504
505#ifdef CONFIG_X86_IO_APIC
506
507#include <asm/io_apic.h>
508
509/*
510 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
511 * devices to the external APIC.
512 *
513 * TODO: When we have device-specific interrupt routers,
514 * this code will go away from quirks.
515 */
516static void __devinit quirk_via_ioapic(struct pci_dev *dev)
517{
518 u8 tmp;
519
520 if (nr_ioapics < 1)
521 tmp = 0; /* nothing routed to external APIC */
522 else
523 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
524
525 printk(KERN_INFO "PCI: %sbling Via external APIC routing\n",
526 tmp == 0 ? "Disa" : "Ena");
527
528 /* Offset 0x58: External APIC IRQ output control */
529 pci_write_config_byte (dev, 0x58, tmp);
530}
531DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic );
532
a1740913
KW		 533/*
534 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
535 * This leads to doubled level interrupt rates.
536 * Set this bit to get rid of cycle wastage.
537 * Otherwise uncritical.
538 */
539static void __devinit quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
540{
541 u8 misc_control2;
542#define BYPASS_APIC_DEASSERT 8
543
544 pci_read_config_byte(dev, 0x5B, &misc_control2);
545 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
546 printk(KERN_INFO "PCI: Bypassing VIA 8237 APIC De-Assert Message\n");
547 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
548 }
549}
550DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
551
1da177e4
LT		 552/*
553 * The AMD io apic can hang the box when an apic irq is masked.
554 * We check all revs >= B0 (yet not in the pre production!) as the bug
555 * is currently marked NoFix
556 *
557 * We have multiple reports of hangs with this chipset that went away with
558 * noapic specified. For the moment we assume its the errata. We may be wrong
559 * of course. However the advice is demonstrably good even if so..
560 */
561static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
562{
563 u8 rev;
564
565 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
566 if (rev >= 0x02) {
567 printk(KERN_WARNING "I/O APIC: AMD Errata #22 may be present. In the event of instability try\n");
568 printk(KERN_WARNING " : booting with the \"noapic\" option.\n");
569 }
570}
571DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic );
572
573static void __init quirk_ioapic_rmw(struct pci_dev *dev)
574{
575 if (dev->devfn == 0 && dev->bus->number == 0)
576 sis_apic_bug = 1;
577}
578DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw );
579
1da177e4
LT		 580#define AMD8131_revA0 0x01
581#define AMD8131_revB0 0x11
582#define AMD8131_MISC 0x40
583#define AMD8131_NIOAMODE_BIT 0
584static void __init quirk_amd_8131_ioapic(struct pci_dev *dev)
585{
586 unsigned char revid, tmp;
587
1da177e4
LT		 588 if (nr_ioapics == 0)
589 return;
590
591 pci_read_config_byte(dev, PCI_REVISION_ID, &revid);
592 if (revid == AMD8131_revA0 || revid == AMD8131_revB0) {
593 printk(KERN_INFO "Fixing up AMD8131 IOAPIC mode\n");
594 pci_read_config_byte( dev, AMD8131_MISC, &tmp);
595 tmp &= ~(1 << AMD8131_NIOAMODE_BIT);
596 pci_write_config_byte( dev, AMD8131_MISC, tmp);
597 }
598}
5da594b1 599DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic);
1da177e4
LT		 600#endif /* CONFIG_X86_IO_APIC */
601
602
1da177e4
LT		 603/*
604 * FIXME: it is questionable that quirk_via_acpi
605 * is needed. It shows up as an ISA bridge, and does not
606 * support the PCI_INTERRUPT_LINE register at all. Therefore
607 * it seems like setting the pci_dev's 'irq' to the
608 * value of the ACPI SCI interrupt is only done for convenience.
609 * -jgarzik
610 */
611static void __devinit quirk_via_acpi(struct pci_dev *d)
612{
613 /*
614 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
615 */
616 u8 irq;
617 pci_read_config_byte(d, 0x42, &irq);
618 irq &= 0xf;
619 if (irq && (irq != 2))
620 d->irq = irq;
621}
622DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi );
623DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi );
624
93cffffa
BH		 625/*
626 * Via 686A/B: The PCI_INTERRUPT_LINE register for the on-chip
627 * devices, USB0/1, AC97, MC97, and ACPI, has an unusual feature:
628 * when written, it makes an internal connection to the PIC.
629 * For these devices, this register is defined to be 4 bits wide.
630 * Normally this is fine. However for IO-APIC motherboards, or
631 * non-x86 architectures (yes Via exists on PPC among other places),
632 * we must mask the PCI_INTERRUPT_LINE value versus 0xf to get
633 * interrupts delivered properly.
a7b862f6
CW		 634 *
635 * Some of the on-chip devices are actually '586 devices' so they are
636 * listed here.
93cffffa
BH		 637 */
638static void quirk_via_irq(struct pci_dev *dev)
25be5e6c
LB		 639{
640 u8 irq, new_irq;
641
25be5e6c
LB		 642 new_irq = dev->irq & 0xf;
643 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
644 if (new_irq != irq) {
75cf7456 645 printk(KERN_INFO "PCI: VIA IRQ fixup for %s, from %d to %d\n",
25be5e6c
LB		 646 pci_name(dev), irq, new_irq);
647 udelay(15); /* unknown if delay really needed */
648 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
649 }
650}
a7b862f6
CW		 651DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_via_irq);
652DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, quirk_via_irq);
653DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, quirk_via_irq);
654DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_irq);
1ae4f9ba 655DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, quirk_via_irq);
75cf7456
CW		 656DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_irq);
657DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_irq);
658DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_5, quirk_via_irq);
25be5e6c 659
1da177e4
LT		 660/*
661 * VIA VT82C598 has its device ID settable and many BIOSes
662 * set it to the ID of VT82C597 for backward compatibility.
663 * We need to switch it off to be able to recognize the real
664 * type of the chip.
665 */
666static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
667{
668 pci_write_config_byte(dev, 0xfc, 0);
669 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
670}
671DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id );
672
709cf5ea
MG		 673#ifdef CONFIG_ACPI_SLEEP
674
675/*
676 * Some VIA systems boot with the abnormal status flag set. This can cause
677 * the BIOS to re-POST the system on resume rather than passing control
678 * back to the OS. Clear the flag on boot
679 */
680static void __devinit quirk_via_abnormal_poweroff(struct pci_dev *dev)
681{
682 u32 reg;
683
684 acpi_hw_register_read(ACPI_MTX_DO_NOT_LOCK, ACPI_REGISTER_PM1_STATUS,
685 &reg);
686
687 if (reg & 0x800) {
688 printk("Clearing abnormal poweroff flag\n");
689 acpi_hw_register_write(ACPI_MTX_DO_NOT_LOCK,
690 ACPI_REGISTER_PM1_STATUS,
691 (u16)0x800);
692 }
693}
694
695DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_abnormal_poweroff);
696DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_abnormal_poweroff);
697
698#endif
699
1da177e4
LT		 700/*
701 * CardBus controllers have a legacy base address that enables them
702 * to respond as i82365 pcmcia controllers. We don't want them to
703 * do this even if the Linux CardBus driver is not loaded, because
704 * the Linux i82365 driver does not (and should not) handle CardBus.
705 */
706static void __devinit quirk_cardbus_legacy(struct pci_dev *dev)
707{
708 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
709 return;
710 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
711}
712DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
713
714/*
715 * Following the PCI ordering rules is optional on the AMD762. I'm not
716 * sure what the designers were smoking but let's not inhale...
717 *
718 * To be fair to AMD, it follows the spec by default, its BIOS people
719 * who turn it off!
720 */
721static void __devinit quirk_amd_ordering(struct pci_dev *dev)
722{
723 u32 pcic;
724 pci_read_config_dword(dev, 0x4C, &pcic);
725 if ((pcic&6)!=6) {
726 pcic |= 6;
727 printk(KERN_WARNING "BIOS failed to enable PCI standards compliance, fixing this error.\n");
728 pci_write_config_dword(dev, 0x4C, pcic);
729 pci_read_config_dword(dev, 0x84, &pcic);
730 pcic |= (1<<23); /* Required in this mode */
731 pci_write_config_dword(dev, 0x84, pcic);
732 }
733}
734DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering );
735
736/*
737 * DreamWorks provided workaround for Dunord I-3000 problem
738 *
739 * This card decodes and responds to addresses not apparently
740 * assigned to it. We force a larger allocation to ensure that
741 * nothing gets put too close to it.
742 */
743static void __devinit quirk_dunord ( struct pci_dev * dev )
744{
745 struct resource *r = &dev->resource [1];
746 r->start = 0;
747 r->end = 0xffffff;
748}
749DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord );
750
751/*
752 * i82380FB mobile docking controller: its PCI-to-PCI bridge
753 * is subtractive decoding (transparent), and does indicate this
754 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
755 * instead of 0x01.
756 */
757static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
758{
759 dev->transparent = 1;
760}
761DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge );
762DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge );
763
764/*
765 * Common misconfiguration of the MediaGX/Geode PCI master that will
766 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
767 * datasheets found at http://www.national.com/ds/GX for info on what
768 * these bits do. <christer@weinigel.se>
769 */
770static void __init quirk_mediagx_master(struct pci_dev *dev)
771{
772 u8 reg;
773 pci_read_config_byte(dev, 0x41, &reg);
774 if (reg & 2) {
775 reg &= ~2;
776 printk(KERN_INFO "PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
777 pci_write_config_byte(dev, 0x41, reg);
778 }
779}
780DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master );
781
782/*
783 * As per PCI spec, ignore base address registers 0-3 of the IDE controllers
784 * running in Compatible mode (bits 0 and 2 in the ProgIf for primary and
785 * secondary channels respectively). If the device reports Compatible mode
786 * but does use BAR0-3 for address decoding, we assume that firmware has
787 * programmed these BARs with standard values (0x1f0,0x3f4 and 0x170,0x374).
788 * Exceptions (if they exist) must be handled in chip/architecture specific
789 * fixups.
790 *
791 * Note: for non x86 people. You may need an arch specific quirk to handle
792 * moving IDE devices to native mode as well. Some plug in card devices power
793 * up in compatible mode and assume the BIOS will adjust them.
794 *
795 * Q: should we load the 0x1f0,0x3f4 into the registers or zap them as
796 * we do now ? We don't want is pci_enable_device to come along
797 * and assign new resources. Both approaches work for that.
798 */
799static void __devinit quirk_ide_bases(struct pci_dev *dev)
800{
801 struct resource *res;
802 int first_bar = 2, last_bar = 0;
803
804 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
805 return;
806
807 res = &dev->resource[0];
808
809 /* primary channel: ProgIf bit 0, BAR0, BAR1 */
810 if (!(dev->class & 1) && (res[0].flags || res[1].flags)) {
811 res[0].start = res[0].end = res[0].flags = 0;
812 res[1].start = res[1].end = res[1].flags = 0;
813 first_bar = 0;
814 last_bar = 1;
815 }
816
817 /* secondary channel: ProgIf bit 2, BAR2, BAR3 */
818 if (!(dev->class & 4) && (res[2].flags || res[3].flags)) {
819 res[2].start = res[2].end = res[2].flags = 0;
820 res[3].start = res[3].end = res[3].flags = 0;
821 last_bar = 3;
822 }
823
824 if (!last_bar)
825 return;
826
827 printk(KERN_INFO "PCI: Ignoring BAR%d-%d of IDE controller %s\n",
828 first_bar, last_bar, pci_name(dev));
829}
830DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_ide_bases);
831
832/*
833 * Ensure C0 rev restreaming is off. This is normally done by
834 * the BIOS but in the odd case it is not the results are corruption
835 * hence the presence of a Linux check
836 */
837static void __init quirk_disable_pxb(struct pci_dev *pdev)
838{
839 u16 config;
840 u8 rev;
841
842 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
843 if (rev != 0x04) /* Only C0 requires this */
844 return;
845 pci_read_config_word(pdev, 0x40, &config);
846 if (config & (1<<6)) {
847 config &= ~(1<<6);
848 pci_write_config_word(pdev, 0x40, config);
849 printk(KERN_INFO "PCI: C0 revision 450NX. Disabling PCI restreaming.\n");
850 }
851}
852DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb );
853
1da177e4
LT		 854
855/*
856 * Serverworks CSB5 IDE does not fully support native mode
857 */
858static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
859{
860 u8 prog;
861 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
862 if (prog & 5) {
863 prog &= ~5;
864 pdev->class &= ~5;
865 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
866 /* need to re-assign BARs for compat mode */
867 quirk_ide_bases(pdev);
868 }
869}
870DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide );
871
872/*
873 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
874 */
875static void __init quirk_ide_samemode(struct pci_dev *pdev)
876{
877 u8 prog;
878
879 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
880
881 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
882 printk(KERN_INFO "PCI: IDE mode mismatch; forcing legacy mode\n");
883 prog &= ~5;
884 pdev->class &= ~5;
885 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
886 /* need to re-assign BARs for compat mode */
887 quirk_ide_bases(pdev);
888 }
889}
890DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
891
892/* This was originally an Alpha specific thing, but it really fits here.
893 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
894 */
895static void __init quirk_eisa_bridge(struct pci_dev *dev)
896{
897 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
898}
899DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge );
900
7daa0c4f
JG		 901/*
902 * On the MSI-K8T-Neo2Fir Board, the internal Soundcard is disabled
903 * when a PCI-Soundcard is added. The BIOS only gives Options
904 * "Disabled" and "AUTO". This Quirk Sets the corresponding
905 * Register-Value to enable the Soundcard.
bd91fde9
CW		 906 *
907 * FIXME: Presently this quirk will run on anything that has an 8237
908 * which isn't correct, we need to check DMI tables or something in
909 * order to make sure it only runs on the MSI-K8T-Neo2Fir. Because it
910 * runs everywhere at present we suppress the printk output in most
911 * irrelevant cases.
7daa0c4f
JG		 912 */
913static void __init k8t_sound_hostbridge(struct pci_dev *dev)
914{
915 unsigned char val;
916
7daa0c4f
JG		 917 pci_read_config_byte(dev, 0x50, &val);
918 if (val == 0x88 || val == 0xc8) {
bd91fde9
CW		 919 /* Assume it's probably a MSI-K8T-Neo2Fir */
920 printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, attempting to turn soundcard ON\n");
7daa0c4f
JG		 921 pci_write_config_byte(dev, 0x50, val & (~0x40));
922
923 /* Verify the Change for Status output */
924 pci_read_config_byte(dev, 0x50, &val);
925 if (val & 0x40)
bd91fde9 926 printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, soundcard still off\n");
7daa0c4f 927 else
bd91fde9 928 printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, soundcard on\n");
7daa0c4f 929 }
7daa0c4f
JG		 930}
931DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, k8t_sound_hostbridge);
932
ce007ea5 933#ifndef CONFIG_ACPI_SLEEP
1da177e4
LT		 934/*
935 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
936 * is not activated. The myth is that Asus said that they do not want the
937 * users to be irritated by just another PCI Device in the Win98 device
938 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
939 * package 2.7.0 for details)
940 *
941 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
942 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
943 * becomes necessary to do this tweak in two steps -- I've chosen the Host
944 * bridge as trigger.
ce007ea5
CDH		 945 *
946 * Actually, leaving it unhidden and not redoing the quirk over suspend2ram
947 * will cause thermal management to break down, and causing machine to
948 * overheat.
1da177e4 949 */
ce007ea5 950static int __initdata asus_hides_smbus;
1da177e4
LT		 951
952static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
953{
954 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
955 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
956 switch(dev->subsystem_device) {
a00db371 957 case 0x8025: /* P4B-LX */
1da177e4
LT		 958 case 0x8070: /* P4B */
959 case 0x8088: /* P4B533 */
960 case 0x1626: /* L3C notebook */
961 asus_hides_smbus = 1;
962 }
963 if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
964 switch(dev->subsystem_device) {
965 case 0x80b1: /* P4GE-V */
966 case 0x80b2: /* P4PE */
967 case 0x8093: /* P4B533-V */
968 asus_hides_smbus = 1;
969 }
970 if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
971 switch(dev->subsystem_device) {
972 case 0x8030: /* P4T533 */
973 asus_hides_smbus = 1;
974 }
975 if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
976 switch (dev->subsystem_device) {
977 case 0x8070: /* P4G8X Deluxe */
978 asus_hides_smbus = 1;
979 }
321311af
JD		 980 if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
981 switch (dev->subsystem_device) {
982 case 0x80c9: /* PU-DLS */
983 asus_hides_smbus = 1;
984 }
1da177e4
LT		 985 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
986 switch (dev->subsystem_device) {
987 case 0x1751: /* M2N notebook */
988 case 0x1821: /* M5N notebook */
989 asus_hides_smbus = 1;
990 }
991 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
992 switch (dev->subsystem_device) {
993 case 0x184b: /* W1N notebook */
994 case 0x186a: /* M6Ne notebook */
995 asus_hides_smbus = 1;
996 }
acc06632
RM		 997 if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) {
998 switch (dev->subsystem_device) {
999 case 0x1882: /* M6V notebook */
2d1e1c75 1000 case 0x1977: /* A6VA notebook */
acc06632
RM		 1001 asus_hides_smbus = 1;
1002 }
1003 }
1da177e4
LT		 1004 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1005 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1006 switch(dev->subsystem_device) {
1007 case 0x088C: /* HP Compaq nc8000 */
1008 case 0x0890: /* HP Compaq nc6000 */
1009 asus_hides_smbus = 1;
1010 }
1011 if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1012 switch (dev->subsystem_device) {
1013 case 0x12bc: /* HP D330L */
e3b1bd57 1014 case 0x12bd: /* HP D530 */
1da177e4
LT		 1015 asus_hides_smbus = 1;
1016 }
3c0a654e 1017 if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) {
1018 switch (dev->subsystem_device) {
1019 case 0x099c: /* HP Compaq nx6110 */
1020 asus_hides_smbus = 1;
1021 }
1022 }
1da177e4
LT		 1023 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_TOSHIBA)) {
1024 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1025 switch(dev->subsystem_device) {
1026 case 0x0001: /* Toshiba Satellite A40 */
1027 asus_hides_smbus = 1;
1028 }
e96e2f14
DG		 1029 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1030 switch(dev->subsystem_device) {
1031 case 0x0001: /* Toshiba Tecra M2 */
1032 asus_hides_smbus = 1;
1033 }
1da177e4
LT		 1034 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1035 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1036 switch(dev->subsystem_device) {
1037 case 0xC00C: /* Samsung P35 notebook */
1038 asus_hides_smbus = 1;
1039 }
c87f883e
RIZ		 1040 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1041 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1042 switch(dev->subsystem_device) {
1043 case 0x0058: /* Compaq Evo N620c */
1044 asus_hides_smbus = 1;
1045 }
1da177e4
LT		 1046 }
1047}
1048DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge );
1049DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge );
1050DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge );
1051DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge );
1052DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge );
321311af 1053DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge );
1da177e4
LT		 1054DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge );
1055DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge );
acc06632 1056DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge );
1da177e4
LT		 1057
1058static void __init asus_hides_smbus_lpc(struct pci_dev *dev)
1059{
1060 u16 val;
1061
1062 if (likely(!asus_hides_smbus))
1063 return;
1064
1065 pci_read_config_word(dev, 0xF2, &val);
1066 if (val & 0x8) {
1067 pci_write_config_word(dev, 0xF2, val & (~0x8));
1068 pci_read_config_word(dev, 0xF2, &val);
1069 if (val & 0x8)
1070 printk(KERN_INFO "PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1071 else
1072 printk(KERN_INFO "PCI: Enabled i801 SMBus device\n");
1073 }
1074}
1075DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc );
1076DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc );
321311af 1077DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc );
1da177e4
LT		 1078DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc );
1079DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc );
1080DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc );
1081
acc06632
RM		 1082static void __init asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1083{
1084 u32 val, rcba;
1085 void __iomem *base;
1086
1087 if (likely(!asus_hides_smbus))
1088 return;
1089 pci_read_config_dword(dev, 0xF0, &rcba);
1090 base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); /* use bits 31:14, 16 kB aligned */
1091 if (base == NULL) return;
1092 val=readl(base + 0x3418); /* read the Function Disable register, dword mode only */
1093 writel(val & 0xFFFFFFF7, base + 0x3418); /* enable the SMBus device */
1094 iounmap(base);
1095 printk(KERN_INFO "PCI: Enabled ICH6/i801 SMBus device\n");
1096}
1097DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6 );
1098
ce007ea5
CDH		 1099#endif
1100
1da177e4
LT		 1101/*
1102 * SiS 96x south bridge: BIOS typically hides SMBus device...
1103 */
1104static void __init quirk_sis_96x_smbus(struct pci_dev *dev)
1105{
1106 u8 val = 0;
1107 printk(KERN_INFO "Enabling SiS 96x SMBus.\n");
1108 pci_read_config_byte(dev, 0x77, &val);
1109 pci_write_config_byte(dev, 0x77, val & ~0x10);
1110 pci_read_config_byte(dev, 0x77, &val);
1111}
1112
1da177e4
LT		 1113/*
1114 * ... This is further complicated by the fact that some SiS96x south
1115 * bridges pretend to be 85C503/5513 instead. In that case see if we
1116 * spotted a compatible north bridge to make sure.
1117 * (pci_find_device doesn't work yet)
1118 *
1119 * We can also enable the sis96x bit in the discovery register..
1120 */
1121static int __devinitdata sis_96x_compatible = 0;
1122
1123#define SIS_DETECT_REGISTER 0x40
1124
1125static void __init quirk_sis_503(struct pci_dev *dev)
1126{
1127 u8 reg;
1128 u16 devid;
1129
1130 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1131 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1132 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1133 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1134 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1135 return;
1136 }
1137
1138 /* Make people aware that we changed the config.. */
1139 printk(KERN_WARNING "Uncovering SIS%x that hid as a SIS503 (compatible=%d)\n", devid, sis_96x_compatible);
1140
1141 /*
1142 * Ok, it now shows up as a 96x.. The 96x quirks are after
1143 * the 503 quirk in the quirk table, so they'll automatically
1144 * run and enable things like the SMBus device
1145 */
1146 dev->device = devid;
1147}
1148
1149static void __init quirk_sis_96x_compatible(struct pci_dev *dev)
1150{
1151 sis_96x_compatible = 1;
1152}
1153DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_645, quirk_sis_96x_compatible );
1154DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_646, quirk_sis_96x_compatible );
1155DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_648, quirk_sis_96x_compatible );
1156DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_650, quirk_sis_96x_compatible );
1157DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_651, quirk_sis_96x_compatible );
1158DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_735, quirk_sis_96x_compatible );
1159
1160DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503 );
e5548e96
BJD		 1161/*
1162 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1163 * and MC97 modem controller are disabled when a second PCI soundcard is
1164 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1165 * -- bjd
1166 */
1167static void __init asus_hides_ac97_lpc(struct pci_dev *dev)
1168{
1169 u8 val;
1170 int asus_hides_ac97 = 0;
1171
1172 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1173 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1174 asus_hides_ac97 = 1;
1175 }
1176
1177 if (!asus_hides_ac97)
1178 return;
1179
1180 pci_read_config_byte(dev, 0x50, &val);
1181 if (val & 0xc0) {
1182 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1183 pci_read_config_byte(dev, 0x50, &val);
1184 if (val & 0xc0)
1185 printk(KERN_INFO "PCI: onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
1186 else
1187 printk(KERN_INFO "PCI: enabled onboard AC97/MC97 devices\n");
1188 }
1189}
1190DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc );
1191
1da177e4
LT		 1192
1193DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus );
1194DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus );
1195DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus );
1196DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus );
1197
77967052 1198#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
15e0c694
AC		 1199
1200/*
1201 * If we are using libata we can drive this chip properly but must
1202 * do this early on to make the additional device appear during
1203 * the PCI scanning.
1204 */
1205
1206static void __devinit quirk_jmicron_dualfn(struct pci_dev *pdev)
1207{
1208 u32 conf;
1209 u8 hdr;
1210
1211 /* Only poke fn 0 */
1212 if (PCI_FUNC(pdev->devfn))
1213 return;
1214
1215 switch(pdev->device) {
1216 case PCI_DEVICE_ID_JMICRON_JMB365:
1217 case PCI_DEVICE_ID_JMICRON_JMB366:
1218 /* Redirect IDE second PATA port to the right spot */
1219 pci_read_config_dword(pdev, 0x80, &conf);
1220 conf |= (1 << 24);
1221 /* Fall through */
1222 pci_write_config_dword(pdev, 0x80, conf);
1223 case PCI_DEVICE_ID_JMICRON_JMB361:
1224 case PCI_DEVICE_ID_JMICRON_JMB363:
1225 pci_read_config_dword(pdev, 0x40, &conf);
1226 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1227 /* Set the class codes correctly and then direct IDE 0 */
1228 conf &= ~0x000F0200; /* Clear bit 9 and 16-19 */
1229 conf |= 0x00C20002; /* Set bit 1, 17, 22, 23 */
1230 pci_write_config_dword(pdev, 0x40, conf);
1231
1232 /* Reconfigure so that the PCI scanner discovers the
1233 device is now multifunction */
1234
1235 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1236 pdev->hdr_type = hdr & 0x7f;
1237 pdev->multifunction = !!(hdr & 0x80);
1238
1239 break;
1240 }
1241}
1242
1243DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, quirk_jmicron_dualfn);
1244
1245#endif
1246
1da177e4
LT		 1247#ifdef CONFIG_X86_IO_APIC
1248static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1249{
1250 int i;
1251
1252 if ((pdev->class >> 8) != 0xff00)
1253 return;
1254
1255 /* the first BAR is the location of the IO APIC...we must
1256 * not touch this (and it's already covered by the fixmap), so
1257 * forcibly insert it into the resource tree */
1258 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1259 insert_resource(&iomem_resource, &pdev->resource[0]);
1260
1261 /* The next five BARs all seem to be rubbish, so just clean
1262 * them out */
1263 for (i=1; i < 6; i++) {
1264 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1265 }
1266
1267}
1268DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic );
1269#endif
1270
2bd0fa3b
JB		 1271enum ide_combined_type { COMBINED = 0, IDE = 1, LIBATA = 2 };
1272/* Defaults to combined */
1273static enum ide_combined_type combined_mode;
1274
1275static int __init combined_setup(char *str)
1276{
1277 if (!strncmp(str, "ide", 3))
1278 combined_mode = IDE;
1279 else if (!strncmp(str, "libata", 6))
1280 combined_mode = LIBATA;
1281 else /* "combined" or anything else defaults to old behavior */
1282 combined_mode = COMBINED;
1283
1284 return 1;
1285}
1286__setup("combined_mode=", combined_setup);
1287
77967052 1288#ifdef CONFIG_SATA_INTEL_COMBINED
1da177e4
LT		 1289static void __devinit quirk_intel_ide_combined(struct pci_dev *pdev)
1290{
1291 u8 prog, comb, tmp;
1292 int ich = 0;
1293
1294 /*
1295 * Narrow down to Intel SATA PCI devices.
1296 */
1297 switch (pdev->device) {
1298 /* PCI ids taken from drivers/scsi/ata_piix.c */
1299 case 0x24d1:
1300 case 0x24df:
1301 case 0x25a3:
1302 case 0x25b0:
1303 ich = 5;
1304 break;
1305 case 0x2651:
1306 case 0x2652:
1307 case 0x2653:
c368ca4e 1308 case 0x2680: /* ESB2 */
1da177e4
LT		 1309 ich = 6;
1310 break;
1311 case 0x27c0:
1312 case 0x27c4:
1313 ich = 7;
1314 break;
012b265f
JG		 1315 case 0x2828: /* ICH8M */
1316 ich = 8;
1317 break;
1da177e4
LT		 1318 default:
1319 /* we do not handle this PCI device */
1320 return;
1321 }
1322
1323 /*
1324 * Read combined mode register.
1325 */
1326 pci_read_config_byte(pdev, 0x90, &tmp); /* combined mode reg */
1327
1328 if (ich == 5) {
1329 tmp &= 0x6; /* interesting bits 2:1, PATA primary/secondary */
1330 if (tmp == 0x4) /* bits 10x */
1331 comb = (1 << 0); /* SATA port 0, PATA port 1 */
1332 else if (tmp == 0x6) /* bits 11x */
1333 comb = (1 << 2); /* PATA port 0, SATA port 1 */
1334 else
1335 return; /* not in combined mode */
1336 } else {
012b265f 1337 WARN_ON((ich != 6) && (ich != 7) && (ich != 8));
1da177e4
LT		 1338 tmp &= 0x3; /* interesting bits 1:0 */
1339 if (tmp & (1 << 0))
1340 comb = (1 << 2); /* PATA port 0, SATA port 1 */
1341 else if (tmp & (1 << 1))
1342 comb = (1 << 0); /* SATA port 0, PATA port 1 */
1343 else
1344 return; /* not in combined mode */
1345 }
1346
1347 /*
1348 * Read programming interface register.
1349 * (Tells us if it's legacy or native mode)
1350 */
1351 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1352
1353 /* if SATA port is in native mode, we're ok. */
1354 if (prog & comb)
1355 return;
1356
2bd0fa3b
JB		 1357 /* Don't reserve any so the IDE driver can get them (but only if
1358 * combined_mode=ide).
1359 */
1360 if (combined_mode == IDE)
1361 return;
1362
1363 /* Grab them both for libata if combined_mode=libata. */
1364 if (combined_mode == LIBATA) {
1365 request_region(0x1f0, 8, "libata"); /* port 0 */
1366 request_region(0x170, 8, "libata"); /* port 1 */
1367 return;
1368 }
1369
1da177e4
LT		 1370 /* SATA port is in legacy mode. Reserve port so that
1371 * IDE driver does not attempt to use it. If request_region
1372 * fails, it will be obvious at boot time, so we don't bother
1373 * checking return values.
1374 */
1375 if (comb == (1 << 0))
1376 request_region(0x1f0, 8, "libata"); /* port 0 */
1377 else
1378 request_region(0x170, 8, "libata"); /* port 1 */
1379}
1380DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_intel_ide_combined );
77967052 1381#endif /* CONFIG_SATA_INTEL_COMBINED */
1da177e4
LT		 1382
1383
1384int pcie_mch_quirk;
1385
1386static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1387{
1388 pcie_mch_quirk = 1;
1389}
1390DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch );
1391DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch );
1392DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch );
1393
4602b88d
KA		 1394
1395/*
1396 * It's possible for the MSI to get corrupted if shpc and acpi
1397 * are used together on certain PXH-based systems.
1398 */
1399static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1400{
1401 disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI),
1402 PCI_CAP_ID_MSI);
1403 dev->no_msi = 1;
1404
1405 printk(KERN_WARNING "PCI: PXH quirk detected, "
1406 "disabling MSI for SHPC device\n");
1407}
1408DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1409DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1410DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1411DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1412DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1413
ffadcc2f
KCA		 1414/*
1415 * Some Intel PCI Express chipsets have trouble with downstream
1416 * device power management.
1417 */
1418static void quirk_intel_pcie_pm(struct pci_dev * dev)
1419{
1420 pci_pm_d3_delay = 120;
1421 dev->no_d1d2 = 1;
1422}
1423
1424DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1425DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1426DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1427DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1428DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1429DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1430DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1431DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1432DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1433DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1434DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1435DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1436DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1437DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1438DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1439DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1440DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1441DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1442DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1443DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1444DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
4602b88d 1445
c408a379
KA		 1446/*
1447 * Fixup the cardbus bridges on the IBM Dock II docking station
1448 */
1449static void __devinit quirk_ibm_dock2_cardbus(struct pci_dev *dev)
1450{
1451 u32 val;
1452
1453 /*
1454 * tie the 2 interrupt pins to INTA, and configure the
1455 * multifunction routing register to handle this.
1456 */
1457 if ((dev->subsystem_vendor == PCI_VENDOR_ID_IBM) &&
1458 (dev->subsystem_device == 0x0148)) {
1459 printk(KERN_INFO "PCI: Found IBM Dock II Cardbus Bridge "
1460 "applying quirk\n");
1461 pci_read_config_dword(dev, 0x8c, &val);
1462 val = ((val & 0xffffff00) | 0x1002);
1463 pci_write_config_dword(dev, 0x8c, val);
1464 pci_read_config_dword(dev, 0x80, &val);
1465 val = ((val & 0x00ffff00) | 0x2864c077);
1466 pci_write_config_dword(dev, 0x80, val);
1467 }
1468}
1469
1470DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1420,
1471 quirk_ibm_dock2_cardbus);
1472
1da177e4
LT		 1473static void __devinit quirk_netmos(struct pci_dev *dev)
1474{
1475 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1476 unsigned int num_serial = dev->subsystem_device & 0xf;
1477
1478 /*
1479 * These Netmos parts are multiport serial devices with optional
1480 * parallel ports. Even when parallel ports are present, they
1481 * are identified as class SERIAL, which means the serial driver
1482 * will claim them. To prevent this, mark them as class OTHER.
1483 * These combo devices should be claimed by parport_serial.
1484 *
1485 * The subdevice ID is of the form 0x00PS, where <P> is the number
1486 * of parallel ports and <S> is the number of serial ports.
1487 */
1488 switch (dev->device) {
1489 case PCI_DEVICE_ID_NETMOS_9735:
1490 case PCI_DEVICE_ID_NETMOS_9745:
1491 case PCI_DEVICE_ID_NETMOS_9835:
1492 case PCI_DEVICE_ID_NETMOS_9845:
1493 case PCI_DEVICE_ID_NETMOS_9855:
1494 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1495 num_parallel) {
1496 printk(KERN_INFO "PCI: Netmos %04x (%u parallel, "
1497 "%u serial); changing class SERIAL to OTHER "
1498 "(use parport_serial)\n",
1499 dev->device, num_parallel, num_serial);
1500 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1501 (dev->class & 0xff);
1502 }
1503 }
1504}
1505DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1506
16a74744
BH		 1507static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1508{
1509 u16 command;
1510 u32 bar;
1511 u8 __iomem *csr;
1512 u8 cmd_hi;
1513
1514 switch (dev->device) {
1515 /* PCI IDs taken from drivers/net/e100.c */
1516 case 0x1029:
1517 case 0x1030 ... 0x1034:
1518 case 0x1038 ... 0x103E:
1519 case 0x1050 ... 0x1057:
1520 case 0x1059:
1521 case 0x1064 ... 0x106B:
1522 case 0x1091 ... 0x1095:
1523 case 0x1209:
1524 case 0x1229:
1525 case 0x2449:
1526 case 0x2459:
1527 case 0x245D:
1528 case 0x27DC:
1529 break;
1530 default:
1531 return;
1532 }
1533
1534 /*
1535 * Some firmware hands off the e100 with interrupts enabled,
1536 * which can cause a flood of interrupts if packets are
1537 * received before the driver attaches to the device. So
1538 * disable all e100 interrupts here. The driver will
1539 * re-enable them when it's ready.
1540 */
1541 pci_read_config_word(dev, PCI_COMMAND, &command);
1542 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar);
1543
1544 if (!(command & PCI_COMMAND_MEMORY) || !bar)
1545 return;
1546
1547 csr = ioremap(bar, 8);
1548 if (!csr) {
1549 printk(KERN_WARNING "PCI: Can't map %s e100 registers\n",
1550 pci_name(dev));
1551 return;
1552 }
1553
1554 cmd_hi = readb(csr + 3);
1555 if (cmd_hi == 0) {
1556 printk(KERN_WARNING "PCI: Firmware left %s e100 interrupts "
1557 "enabled, disabling\n", pci_name(dev));
1558 writeb(1, csr + 3);
1559 }
1560
1561 iounmap(csr);
1562}
1563DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt);
a5312e28
IK		 1564
1565static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1566{
1567 /* rev 1 ncr53c810 chips don't set the class at all which means
1568 * they don't get their resources remapped. Fix that here.
1569 */
1570
1571 if (dev->class == PCI_CLASS_NOT_DEFINED) {
1572 printk(KERN_INFO "NCR 53c810 rev 1 detected, setting PCI class.\n");
1573 dev->class = PCI_CLASS_STORAGE_SCSI;
1574 }
1575}
1576DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1577
1578
1da177e4
LT		 1579static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end)
1580{
1581 while (f < end) {
1582 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
1583 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
1584 pr_debug("PCI: Calling quirk %p for %s\n", f->hook, pci_name(dev));
1585 f->hook(dev);
1586 }
1587 f++;
1588 }
1589}
1590
1591extern struct pci_fixup __start_pci_fixups_early[];
1592extern struct pci_fixup __end_pci_fixups_early[];
1593extern struct pci_fixup __start_pci_fixups_header[];
1594extern struct pci_fixup __end_pci_fixups_header[];
1595extern struct pci_fixup __start_pci_fixups_final[];
1596extern struct pci_fixup __end_pci_fixups_final[];
1597extern struct pci_fixup __start_pci_fixups_enable[];
1598extern struct pci_fixup __end_pci_fixups_enable[];
1599
1600
1601void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
1602{
1603 struct pci_fixup *start, *end;
1604
1605 switch(pass) {
1606 case pci_fixup_early:
1607 start = __start_pci_fixups_early;
1608 end = __end_pci_fixups_early;
1609 break;
1610
1611 case pci_fixup_header:
1612 start = __start_pci_fixups_header;
1613 end = __end_pci_fixups_header;
1614 break;
1615
1616 case pci_fixup_final:
1617 start = __start_pci_fixups_final;
1618 end = __end_pci_fixups_final;
1619 break;
1620
1621 case pci_fixup_enable:
1622 start = __start_pci_fixups_enable;
1623 end = __end_pci_fixups_enable;
1624 break;
1625
1626 default:
1627 /* stupid compiler warning, you would think with an enum... */
1628 return;
1629 }
1630 pci_do_fixups(dev, start, end);
1631}
1632
9d265124
DY		 1633/* Enable 1k I/O space granularity on the Intel P64H2 */
1634static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1635{
1636 u16 en1k;
1637 u8 io_base_lo, io_limit_lo;
1638 unsigned long base, limit;
1639 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1640
1641 pci_read_config_word(dev, 0x40, &en1k);
1642
1643 if (en1k & 0x200) {
1644 printk(KERN_INFO "PCI: Enable I/O Space to 1 KB Granularity\n");
1645
1646 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
1647 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
1648 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1649 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1650
1651 if (base <= limit) {
1652 res->start = base;
1653 res->end = limit + 0x3ff;
1654 }
1655 }
1656}
1657DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
1658
cf34a8e0
BG		 1659/* Under some circumstances, AER is not linked with extended capabilities.
1660 * Force it to be linked by setting the corresponding control bit in the
1661 * config space.
1662 */
1663static void __devinit quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
1664{
1665 uint8_t b;
1666 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
1667 if (!(b & 0x20)) {
1668 pci_write_config_byte(dev, 0xf41, b | 0x20);
1669 printk(KERN_INFO
1670 "PCI: Linking AER extended capability on %s\n",
1671 pci_name(dev));
1672 }
1673 }
1674}
1675DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1676 quirk_nvidia_ck804_pcie_aer_ext_cap);
1677
3f79e107
BG		 1678#ifdef CONFIG_PCI_MSI
1679/* To disable MSI globally */
1680int pci_msi_quirk;
1681
1682/* The Serverworks PCI-X chipset does not support MSI. We cannot easily rely
1683 * on setting PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
1684 * some other busses controlled by the chipset even if Linux is not aware of it.
1685 * Instead of setting the flag on all busses in the machine, simply disable MSI
1686 * globally.
1687 */
1688static void __init quirk_svw_msi(struct pci_dev *dev)
1689{
1690 pci_msi_quirk = 1;
1691 printk(KERN_WARNING "PCI: MSI quirk detected. pci_msi_quirk set.\n");
1692}
1693DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_svw_msi);
1694
1695/* Disable MSI on chipsets that are known to not support it */
1696static void __devinit quirk_disable_msi(struct pci_dev *dev)
1697{
1698 if (dev->subordinate) {
1699 printk(KERN_WARNING "PCI: MSI quirk detected. "
1700 "PCI_BUS_FLAGS_NO_MSI set for %s subordinate bus.\n",
1701 pci_name(dev));
1702 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1703 }
1704}
1705DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
6397c75c
BG		 1706
1707/* Go through the list of Hypertransport capabilities and
1708 * return 1 if a HT MSI capability is found and enabled */
1709static int __devinit msi_ht_cap_enabled(struct pci_dev *dev)
1710{
1711 u8 pos;
1712 int ttl;
1713 for (pos = pci_find_capability(dev, PCI_CAP_ID_HT), ttl = 48;
1714 pos && ttl;
1715 pos = pci_find_next_capability(dev, pos, PCI_CAP_ID_HT), ttl--) {
1716 u32 cap_hdr;
1717 /* MSI mapping section according to Hypertransport spec */
1718 if (pci_read_config_dword(dev, pos, &cap_hdr) == 0
1719 && (cap_hdr & 0xf8000000) == 0xa8000000 /* MSI mapping */) {
1720 printk(KERN_INFO "PCI: Found HT MSI mapping on %s with capability %s\n",
1721 pci_name(dev), cap_hdr & 0x10000 ? "enabled" : "disabled");
1722 return (cap_hdr & 0x10000) != 0; /* MSI mapping cap enabled */
1723 }
1724 }
1725 return 0;
1726}
1727
1728/* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
1729static void __devinit quirk_msi_ht_cap(struct pci_dev *dev)
1730{
1731 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
1732 printk(KERN_WARNING "PCI: MSI quirk detected. "
1733 "MSI disabled on chipset %s.\n",
1734 pci_name(dev));
1735 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1736 }
1737}
1738DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
1739 quirk_msi_ht_cap);
1740
1741/* The nVidia CK804 chipset may have 2 HT MSI mappings.
1742 * MSI are supported if the MSI capability set in any of these mappings.
1743 */
1744static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
1745{
1746 struct pci_dev *pdev;
1747
1748 if (!dev->subordinate)
1749 return;
1750
1751 /* check HT MSI cap on this chipset and the root one.
1752 * a single one having MSI is enough to be sure that MSI are supported.
1753 */
1754 pdev = pci_find_slot(dev->bus->number, 0);
1755 if (dev->subordinate && !msi_ht_cap_enabled(dev)
1756 && !msi_ht_cap_enabled(pdev)) {
1757 printk(KERN_WARNING "PCI: MSI quirk detected. "
1758 "MSI disabled on chipset %s.\n",
1759 pci_name(dev));
1760 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1761 }
1762}
1763DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1764 quirk_nvidia_ck804_msi_ht_cap);
3f79e107
BG		 1765#endif /* CONFIG_PCI_MSI */
1766
1da177e4
LT		 1767EXPORT_SYMBOL(pcie_mch_quirk);
1768#ifdef CONFIG_HOTPLUG
1769EXPORT_SYMBOL(pci_fixup_device);
1770#endif
ubuntu-bionic-kernel mirror