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PCI: read revision ID by default
[mirror_ubuntu-bionic-kernel.git] / drivers / pci / quirks.c
CommitLineData
1da177e4
LT		 1/*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
7586269c
DB		 10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 *
1da177e4
LT		 13 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
16 */
17
1da177e4
LT		 18#include <linux/types.h>
19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/init.h>
22#include <linux/delay.h>
25be5e6c 23#include <linux/acpi.h>
bc56b9e0 24#include "pci.h"
1da177e4 25
bd8481e1
DT		 26/* The Mellanox Tavor device gives false positive parity errors
27 * Mark this device with a broken_parity_status, to allow
28 * PCI scanning code to "skip" this now blacklisted device.
29 */
30static void __devinit quirk_mellanox_tavor(struct pci_dev *dev)
31{
32 dev->broken_parity_status = 1; /* This device gives false positives */
33}
34DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
35DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
36
1da177e4
LT		 37/* Deal with broken BIOS'es that neglect to enable passive release,
38 which can cause problems in combination with the 82441FX/PPro MTRRs */
1597cacb 39static void quirk_passive_release(struct pci_dev *dev)
1da177e4
LT		 40{
41 struct pci_dev *d = NULL;
42 unsigned char dlc;
43
44 /* We have to make sure a particular bit is set in the PIIX3
45 ISA bridge, so we have to go out and find it. */
46 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
47 pci_read_config_byte(d, 0x82, &dlc);
48 if (!(dlc & 1<<1)) {
49 printk(KERN_ERR "PCI: PIIX3: Enabling Passive Release on %s\n", pci_name(d));
50 dlc |= 1<<1;
51 pci_write_config_byte(d, 0x82, dlc);
52 }
53 }
54}
55DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release );
1597cacb 56DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release );
1da177e4
LT		 57
58/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
59 but VIA don't answer queries. If you happen to have good contacts at VIA
60 ask them for me please -- Alan
61
62 This appears to be BIOS not version dependent. So presumably there is a
63 chipset level fix */
c30ca1db
AB		 64int isa_dma_bridge_buggy;
65EXPORT_SYMBOL(isa_dma_bridge_buggy);
1da177e4
LT		 66
67static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
68{
69 if (!isa_dma_bridge_buggy) {
70 isa_dma_bridge_buggy=1;
71 printk(KERN_INFO "Activating ISA DMA hang workarounds.\n");
72 }
73}
74 /*
75 * Its not totally clear which chipsets are the problematic ones
76 * We know 82C586 and 82C596 variants are affected.
77 */
78DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs );
79DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs );
80DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs );
81DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs );
82DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs );
83DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs );
84DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs );
85
86int pci_pci_problems;
c30ca1db 87EXPORT_SYMBOL(pci_pci_problems);
1da177e4
LT		 88
89/*
90 * Chipsets where PCI->PCI transfers vanish or hang
91 */
92static void __devinit quirk_nopcipci(struct pci_dev *dev)
93{
94 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
95 printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n");
96 pci_pci_problems |= PCIPCI_FAIL;
97 }
98}
c30ca1db
AB		 99DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci );
100DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci );
236561e5
AC		 101
102static void __devinit quirk_nopciamd(struct pci_dev *dev)
103{
104 u8 rev;
105 pci_read_config_byte(dev, 0x08, &rev);
106 if (rev == 0x13) {
107 /* Erratum 24 */
108 printk(KERN_INFO "Chipset erratum: Disabling direct PCI/AGP transfers.\n");
109 pci_pci_problems |= PCIAGP_FAIL;
110 }
111}
236561e5 112DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd );
1da177e4
LT		 113
114/*
115 * Triton requires workarounds to be used by the drivers
116 */
117static void __devinit quirk_triton(struct pci_dev *dev)
118{
119 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
120 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
121 pci_pci_problems |= PCIPCI_TRITON;
122 }
123}
124DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton );
125DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton );
126DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton );
127DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton );
128
129/*
130 * VIA Apollo KT133 needs PCI latency patch
131 * Made according to a windows driver based patch by George E. Breese
132 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
133 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
134 * the info on which Mr Breese based his work.
135 *
136 * Updated based on further information from the site and also on
137 * information provided by VIA
138 */
1597cacb 139static void quirk_vialatency(struct pci_dev *dev)
1da177e4
LT		 140{
141 struct pci_dev *p;
142 u8 rev;
143 u8 busarb;
144 /* Ok we have a potential problem chipset here. Now see if we have
145 a buggy southbridge */
146
147 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
148 if (p!=NULL) {
149 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
150 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
151 /* Check for buggy part revisions */
152 if (rev < 0x40 || rev > 0x42)
153 goto exit;
154 } else {
155 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
156 if (p==NULL) /* No problem parts */
157 goto exit;
158 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
159 /* Check for buggy part revisions */
160 if (rev < 0x10 || rev > 0x12)
161 goto exit;
162 }
163
164 /*
165 * Ok we have the problem. Now set the PCI master grant to
166 * occur every master grant. The apparent bug is that under high
167 * PCI load (quite common in Linux of course) you can get data
168 * loss when the CPU is held off the bus for 3 bus master requests
169 * This happens to include the IDE controllers....
170 *
171 * VIA only apply this fix when an SB Live! is present but under
172 * both Linux and Windows this isnt enough, and we have seen
173 * corruption without SB Live! but with things like 3 UDMA IDE
174 * controllers. So we ignore that bit of the VIA recommendation..
175 */
176
177 pci_read_config_byte(dev, 0x76, &busarb);
178 /* Set bit 4 and bi 5 of byte 76 to 0x01
179 "Master priority rotation on every PCI master grant */
180 busarb &= ~(1<<5);
181 busarb |= (1<<4);
182 pci_write_config_byte(dev, 0x76, busarb);
183 printk(KERN_INFO "Applying VIA southbridge workaround.\n");
184exit:
185 pci_dev_put(p);
186}
187DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency );
188DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency );
189DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency );
1597cacb
AC		 190/* Must restore this on a resume from RAM */
191DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency );
192DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency );
193DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency );
1da177e4
LT		 194
195/*
196 * VIA Apollo VP3 needs ETBF on BT848/878
197 */
198static void __devinit quirk_viaetbf(struct pci_dev *dev)
199{
200 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
201 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
202 pci_pci_problems |= PCIPCI_VIAETBF;
203 }
204}
205DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf );
206
207static void __devinit quirk_vsfx(struct pci_dev *dev)
208{
209 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
210 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
211 pci_pci_problems |= PCIPCI_VSFX;
212 }
213}
214DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx );
215
216/*
217 * Ali Magik requires workarounds to be used by the drivers
218 * that DMA to AGP space. Latency must be set to 0xA and triton
219 * workaround applied too
220 * [Info kindly provided by ALi]
221 */
222static void __init quirk_alimagik(struct pci_dev *dev)
223{
224 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
225 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
226 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
227 }
228}
229DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik );
230DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik );
231
232/*
233 * Natoma has some interesting boundary conditions with Zoran stuff
234 * at least
235 */
236static void __devinit quirk_natoma(struct pci_dev *dev)
237{
238 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
239 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
240 pci_pci_problems |= PCIPCI_NATOMA;
241 }
242}
243DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma );
244DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma );
245DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma );
246DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma );
247DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma );
248DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma );
249
250/*
251 * This chip can cause PCI parity errors if config register 0xA0 is read
252 * while DMAs are occurring.
253 */
254static void __devinit quirk_citrine(struct pci_dev *dev)
255{
256 dev->cfg_size = 0xA0;
257}
258DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine );
259
260/*
261 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
262 * If it's needed, re-allocate the region.
263 */
264static void __devinit quirk_s3_64M(struct pci_dev *dev)
265{
266 struct resource *r = &dev->resource[0];
267
268 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
269 r->start = 0;
270 r->end = 0x3ffffff;
271 }
272}
273DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M );
274DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M );
275
6693e74a
LT		 276static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
277 unsigned size, int nr, const char *name)
1da177e4
LT		 278{
279 region &= ~(size-1);
280 if (region) {
085ae41f 281 struct pci_bus_region bus_region;
1da177e4
LT		 282 struct resource *res = dev->resource + nr;
283
284 res->name = pci_name(dev);
285 res->start = region;
286 res->end = region + size - 1;
287 res->flags = IORESOURCE_IO;
085ae41f
DM		 288
289 /* Convert from PCI bus to resource space. */
290 bus_region.start = res->start;
291 bus_region.end = res->end;
292 pcibios_bus_to_resource(dev, res, &bus_region);
293
1da177e4 294 pci_claim_resource(dev, nr);
6693e74a 295 printk("PCI quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name);
1da177e4
LT		 296 }
297}
298
299/*
300 * ATI Northbridge setups MCE the processor if you even
301 * read somewhere between 0x3b0->0x3bb or read 0x3d3
302 */
303static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
304{
305 printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n");
306 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
307 request_region(0x3b0, 0x0C, "RadeonIGP");
308 request_region(0x3d3, 0x01, "RadeonIGP");
309}
310DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce );
311
312/*
313 * Let's make the southbridge information explicit instead
314 * of having to worry about people probing the ACPI areas,
315 * for example.. (Yes, it happens, and if you read the wrong
316 * ACPI register it will put the machine to sleep with no
317 * way of waking it up again. Bummer).
318 *
319 * ALI M7101: Two IO regions pointed to by words at
320 * 0xE0 (64 bytes of ACPI registers)
321 * 0xE2 (32 bytes of SMB registers)
322 */
323static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
324{
325 u16 region;
326
327 pci_read_config_word(dev, 0xE0, &region);
6693e74a 328 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
1da177e4 329 pci_read_config_word(dev, 0xE2, &region);
6693e74a 330 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
1da177e4
LT		 331}
332DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi );
333
6693e74a
LT		 334static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
335{
336 u32 devres;
337 u32 mask, size, base;
338
339 pci_read_config_dword(dev, port, &devres);
340 if ((devres & enable) != enable)
341 return;
342 mask = (devres >> 16) & 15;
343 base = devres & 0xffff;
344 size = 16;
345 for (;;) {
346 unsigned bit = size >> 1;
347 if ((bit & mask) == bit)
348 break;
349 size = bit;
350 }
351 /*
352 * For now we only print it out. Eventually we'll want to
353 * reserve it (at least if it's in the 0x1000+ range), but
354 * let's get enough confirmation reports first.
355 */
356 base &= -size;
357 printk("%s PIO at %04x-%04x\n", name, base, base + size - 1);
358}
359
360static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
361{
362 u32 devres;
363 u32 mask, size, base;
364
365 pci_read_config_dword(dev, port, &devres);
366 if ((devres & enable) != enable)
367 return;
368 base = devres & 0xffff0000;
369 mask = (devres & 0x3f) << 16;
370 size = 128 << 16;
371 for (;;) {
372 unsigned bit = size >> 1;
373 if ((bit & mask) == bit)
374 break;
375 size = bit;
376 }
377 /*
378 * For now we only print it out. Eventually we'll want to
379 * reserve it, but let's get enough confirmation reports first.
380 */
381 base &= -size;
382 printk("%s MMIO at %04x-%04x\n", name, base, base + size - 1);
383}
384
1da177e4
LT		 385/*
386 * PIIX4 ACPI: Two IO regions pointed to by longwords at
387 * 0x40 (64 bytes of ACPI registers)
08db2a70 388 * 0x90 (16 bytes of SMB registers)
6693e74a 389 * and a few strange programmable PIIX4 device resources.
1da177e4
LT		 390 */
391static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
392{
6693e74a 393 u32 region, res_a;
1da177e4
LT		 394
395 pci_read_config_dword(dev, 0x40, &region);
6693e74a 396 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
1da177e4 397 pci_read_config_dword(dev, 0x90, &region);
08db2a70 398 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
6693e74a
LT		 399
400 /* Device resource A has enables for some of the other ones */
401 pci_read_config_dword(dev, 0x5c, &res_a);
402
403 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
404 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
405
406 /* Device resource D is just bitfields for static resources */
407
408 /* Device 12 enabled? */
409 if (res_a & (1 << 29)) {
410 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
411 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
412 }
413 /* Device 13 enabled? */
414 if (res_a & (1 << 30)) {
415 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
416 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
417 }
418 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
419 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
1da177e4
LT		 420}
421DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi );
c6764664 422DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi );
1da177e4
LT		 423
424/*
425 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
426 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
427 * 0x58 (64 bytes of GPIO I/O space)
428 */
429static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
430{
431 u32 region;
432
433 pci_read_config_dword(dev, 0x40, &region);
6693e74a 434 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO");
1da177e4
LT		 435
436 pci_read_config_dword(dev, 0x58, &region);
6693e74a 437 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO");
1da177e4
LT		 438}
439DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi );
440DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi );
441DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi );
442DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi );
443DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi );
444DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi );
445DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi );
446DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi );
447DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi );
3aa8c4fe 448DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi );
1da177e4 449
2cea752f
RM		 450static void __devinit quirk_ich6_lpc_acpi(struct pci_dev *dev)
451{
452 u32 region;
453
454 pci_read_config_dword(dev, 0x40, &region);
455 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO");
456
457 pci_read_config_dword(dev, 0x48, &region);
458 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO");
459}
65ae4ddd 460DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc_acpi );
2cea752f 461DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc_acpi );
bacedce3
DR		 462DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich6_lpc_acpi );
463DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich6_lpc_acpi );
464DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich6_lpc_acpi );
465DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich6_lpc_acpi );
466DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich6_lpc_acpi );
467DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich6_lpc_acpi );
2cea752f 468
1da177e4
LT		 469/*
470 * VIA ACPI: One IO region pointed to by longword at
471 * 0x48 or 0x20 (256 bytes of ACPI registers)
472 */
473static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
474{
475 u8 rev;
476 u32 region;
477
478 pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
479 if (rev & 0x10) {
480 pci_read_config_dword(dev, 0x48, &region);
481 region &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 482 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
1da177e4
LT		 483 }
484}
485DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi );
486
487/*
488 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
489 * 0x48 (256 bytes of ACPI registers)
490 * 0x70 (128 bytes of hardware monitoring register)
491 * 0x90 (16 bytes of SMB registers)
492 */
493static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
494{
495 u16 hm;
496 u32 smb;
497
498 quirk_vt82c586_acpi(dev);
499
500 pci_read_config_word(dev, 0x70, &hm);
501 hm &= PCI_BASE_ADDRESS_IO_MASK;
02f313b2 502 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
1da177e4
LT		 503
504 pci_read_config_dword(dev, 0x90, &smb);
505 smb &= PCI_BASE_ADDRESS_IO_MASK;
02f313b2 506 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
1da177e4
LT		 507}
508DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi );
509
6d85f29b
IK		 510/*
511 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
512 * 0x88 (128 bytes of power management registers)
513 * 0xd0 (16 bytes of SMB registers)
514 */
515static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
516{
517 u16 pm, smb;
518
519 pci_read_config_word(dev, 0x88, &pm);
520 pm &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 521 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
6d85f29b
IK		 522
523 pci_read_config_word(dev, 0xd0, &smb);
524 smb &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 525 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
6d85f29b
IK		 526}
527DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
528
1da177e4
LT		 529
530#ifdef CONFIG_X86_IO_APIC
531
532#include <asm/io_apic.h>
533
534/*
535 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
536 * devices to the external APIC.
537 *
538 * TODO: When we have device-specific interrupt routers,
539 * this code will go away from quirks.
540 */
1597cacb 541static void quirk_via_ioapic(struct pci_dev *dev)
1da177e4
LT		 542{
543 u8 tmp;
544
545 if (nr_ioapics < 1)
546 tmp = 0; /* nothing routed to external APIC */
547 else
548 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
549
550 printk(KERN_INFO "PCI: %sbling Via external APIC routing\n",
551 tmp == 0 ? "Disa" : "Ena");
552
553 /* Offset 0x58: External APIC IRQ output control */
554 pci_write_config_byte (dev, 0x58, tmp);
555}
556DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic );
1597cacb 557DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic );
1da177e4 558
a1740913
KW		 559/*
560 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
561 * This leads to doubled level interrupt rates.
562 * Set this bit to get rid of cycle wastage.
563 * Otherwise uncritical.
564 */
1597cacb 565static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
a1740913
KW		 566{
567 u8 misc_control2;
568#define BYPASS_APIC_DEASSERT 8
569
570 pci_read_config_byte(dev, 0x5B, &misc_control2);
571 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
572 printk(KERN_INFO "PCI: Bypassing VIA 8237 APIC De-Assert Message\n");
573 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
574 }
575}
576DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
1597cacb 577DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
a1740913 578
1da177e4
LT		 579/*
580 * The AMD io apic can hang the box when an apic irq is masked.
581 * We check all revs >= B0 (yet not in the pre production!) as the bug
582 * is currently marked NoFix
583 *
584 * We have multiple reports of hangs with this chipset that went away with
236561e5 585 * noapic specified. For the moment we assume it's the erratum. We may be wrong
1da177e4
LT		 586 * of course. However the advice is demonstrably good even if so..
587 */
588static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
589{
590 u8 rev;
591
592 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
593 if (rev >= 0x02) {
236561e5 594 printk(KERN_WARNING "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
1da177e4
LT		 595 printk(KERN_WARNING " : booting with the \"noapic\" option.\n");
596 }
597}
598DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic );
599
600static void __init quirk_ioapic_rmw(struct pci_dev *dev)
601{
602 if (dev->devfn == 0 && dev->bus->number == 0)
603 sis_apic_bug = 1;
604}
605DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw );
606
1da177e4
LT		 607#define AMD8131_revA0 0x01
608#define AMD8131_revB0 0x11
609#define AMD8131_MISC 0x40
610#define AMD8131_NIOAMODE_BIT 0
1597cacb 611static void quirk_amd_8131_ioapic(struct pci_dev *dev)
1da177e4
LT		 612{
613 unsigned char revid, tmp;
614
1da177e4
LT		 615 if (nr_ioapics == 0)
616 return;
617
618 pci_read_config_byte(dev, PCI_REVISION_ID, &revid);
619 if (revid == AMD8131_revA0 || revid == AMD8131_revB0) {
620 printk(KERN_INFO "Fixing up AMD8131 IOAPIC mode\n");
621 pci_read_config_byte( dev, AMD8131_MISC, &tmp);
622 tmp &= ~(1 << AMD8131_NIOAMODE_BIT);
623 pci_write_config_byte( dev, AMD8131_MISC, tmp);
624 }
625}
5da594b1 626DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic);
1597cacb 627DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic);
1da177e4
LT		 628#endif /* CONFIG_X86_IO_APIC */
629
d556ad4b
PO		 630/*
631 * Some settings of MMRBC can lead to data corruption so block changes.
632 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
633 */
634static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev)
635{
636 unsigned char revid;
637
638 pci_read_config_byte(dev, PCI_REVISION_ID, &revid);
639 if (dev->subordinate && revid <= 0x12) {
640 printk(KERN_INFO "AMD8131 rev %x detected, disabling PCI-X MMRBC\n",
641 revid);
642 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
643 }
644}
645DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
1da177e4 646
1da177e4
LT		 647/*
648 * FIXME: it is questionable that quirk_via_acpi
649 * is needed. It shows up as an ISA bridge, and does not
650 * support the PCI_INTERRUPT_LINE register at all. Therefore
651 * it seems like setting the pci_dev's 'irq' to the
652 * value of the ACPI SCI interrupt is only done for convenience.
653 * -jgarzik
654 */
655static void __devinit quirk_via_acpi(struct pci_dev *d)
656{
657 /*
658 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
659 */
660 u8 irq;
661 pci_read_config_byte(d, 0x42, &irq);
662 irq &= 0xf;
663 if (irq && (irq != 2))
664 d->irq = irq;
665}
666DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi );
667DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi );
668
09d6029f
DD		 669
670/*
1597cacb 671 * VIA bridges which have VLink
09d6029f 672 */
1597cacb 673
c06bb5d4
JD		 674static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
675
676static void quirk_via_bridge(struct pci_dev *dev)
677{
678 /* See what bridge we have and find the device ranges */
679 switch (dev->device) {
680 case PCI_DEVICE_ID_VIA_82C686:
cb7468ef
JD		 681 /* The VT82C686 is special, it attaches to PCI and can have
682 any device number. All its subdevices are functions of
683 that single device. */
684 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
685 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
c06bb5d4
JD		 686 break;
687 case PCI_DEVICE_ID_VIA_8237:
688 case PCI_DEVICE_ID_VIA_8237A:
689 via_vlink_dev_lo = 15;
690 break;
691 case PCI_DEVICE_ID_VIA_8235:
692 via_vlink_dev_lo = 16;
693 break;
694 case PCI_DEVICE_ID_VIA_8231:
695 case PCI_DEVICE_ID_VIA_8233_0:
696 case PCI_DEVICE_ID_VIA_8233A:
697 case PCI_DEVICE_ID_VIA_8233C_0:
698 via_vlink_dev_lo = 17;
699 break;
700 }
701}
702DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
703DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
704DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
705DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
706DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
707DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
708DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
709DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
09d6029f 710
1597cacb
AC		 711/**
712 * quirk_via_vlink - VIA VLink IRQ number update
713 * @dev: PCI device
714 *
715 * If the device we are dealing with is on a PIC IRQ we need to
716 * ensure that the IRQ line register which usually is not relevant
717 * for PCI cards, is actually written so that interrupts get sent
c06bb5d4
JD		 718 * to the right place.
719 * We only do this on systems where a VIA south bridge was detected,
720 * and only for VIA devices on the motherboard (see quirk_via_bridge
721 * above).
1597cacb
AC		 722 */
723
724static void quirk_via_vlink(struct pci_dev *dev)
25be5e6c
LB		 725{
726 u8 irq, new_irq;
727
c06bb5d4
JD		 728 /* Check if we have VLink at all */
729 if (via_vlink_dev_lo == -1)
09d6029f
DD		 730 return;
731
732 new_irq = dev->irq;
733
734 /* Don't quirk interrupts outside the legacy IRQ range */
735 if (!new_irq || new_irq > 15)
736 return;
737
1597cacb 738 /* Internal device ? */
c06bb5d4
JD		 739 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
740 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
1597cacb
AC		 741 return;
742
743 /* This is an internal VLink device on a PIC interrupt. The BIOS
744 ought to have set this but may not have, so we redo it */
745
25be5e6c
LB		 746 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
747 if (new_irq != irq) {
1597cacb 748 printk(KERN_INFO "PCI: VIA VLink IRQ fixup for %s, from %d to %d\n",
25be5e6c
LB		 749 pci_name(dev), irq, new_irq);
750 udelay(15); /* unknown if delay really needed */
751 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
752 }
753}
1597cacb 754DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
25be5e6c 755
1da177e4
LT		 756/*
757 * VIA VT82C598 has its device ID settable and many BIOSes
758 * set it to the ID of VT82C597 for backward compatibility.
759 * We need to switch it off to be able to recognize the real
760 * type of the chip.
761 */
762static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
763{
764 pci_write_config_byte(dev, 0xfc, 0);
765 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
766}
767DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id );
768
769/*
770 * CardBus controllers have a legacy base address that enables them
771 * to respond as i82365 pcmcia controllers. We don't want them to
772 * do this even if the Linux CardBus driver is not loaded, because
773 * the Linux i82365 driver does not (and should not) handle CardBus.
774 */
1597cacb 775static void quirk_cardbus_legacy(struct pci_dev *dev)
1da177e4
LT		 776{
777 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
778 return;
779 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
780}
781DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
1597cacb 782DECLARE_PCI_FIXUP_RESUME(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
1da177e4
LT		 783
784/*
785 * Following the PCI ordering rules is optional on the AMD762. I'm not
786 * sure what the designers were smoking but let's not inhale...
787 *
788 * To be fair to AMD, it follows the spec by default, its BIOS people
789 * who turn it off!
790 */
1597cacb 791static void quirk_amd_ordering(struct pci_dev *dev)
1da177e4
LT		 792{
793 u32 pcic;
794 pci_read_config_dword(dev, 0x4C, &pcic);
795 if ((pcic&6)!=6) {
796 pcic |= 6;
797 printk(KERN_WARNING "BIOS failed to enable PCI standards compliance, fixing this error.\n");
798 pci_write_config_dword(dev, 0x4C, pcic);
799 pci_read_config_dword(dev, 0x84, &pcic);
800 pcic |= (1<<23); /* Required in this mode */
801 pci_write_config_dword(dev, 0x84, pcic);
802 }
803}
804DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering );
1597cacb 805DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering );
1da177e4
LT		 806
807/*
808 * DreamWorks provided workaround for Dunord I-3000 problem
809 *
810 * This card decodes and responds to addresses not apparently
811 * assigned to it. We force a larger allocation to ensure that
812 * nothing gets put too close to it.
813 */
814static void __devinit quirk_dunord ( struct pci_dev * dev )
815{
816 struct resource *r = &dev->resource [1];
817 r->start = 0;
818 r->end = 0xffffff;
819}
820DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord );
821
822/*
823 * i82380FB mobile docking controller: its PCI-to-PCI bridge
824 * is subtractive decoding (transparent), and does indicate this
825 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
826 * instead of 0x01.
827 */
828static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
829{
830 dev->transparent = 1;
831}
832DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge );
833DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge );
834
835/*
836 * Common misconfiguration of the MediaGX/Geode PCI master that will
837 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
838 * datasheets found at http://www.national.com/ds/GX for info on what
839 * these bits do. <christer@weinigel.se>
840 */
1597cacb 841static void quirk_mediagx_master(struct pci_dev *dev)
1da177e4
LT		 842{
843 u8 reg;
844 pci_read_config_byte(dev, 0x41, &reg);
845 if (reg & 2) {
846 reg &= ~2;
847 printk(KERN_INFO "PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
848 pci_write_config_byte(dev, 0x41, reg);
849 }
850}
851DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master );
1597cacb 852DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master );
1da177e4 853
1da177e4
LT		 854/*
855 * Ensure C0 rev restreaming is off. This is normally done by
856 * the BIOS but in the odd case it is not the results are corruption
857 * hence the presence of a Linux check
858 */
1597cacb 859static void quirk_disable_pxb(struct pci_dev *pdev)
1da177e4
LT		 860{
861 u16 config;
862 u8 rev;
863
864 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
865 if (rev != 0x04) /* Only C0 requires this */
866 return;
867 pci_read_config_word(pdev, 0x40, &config);
868 if (config & (1<<6)) {
869 config &= ~(1<<6);
870 pci_write_config_word(pdev, 0x40, config);
871 printk(KERN_INFO "PCI: C0 revision 450NX. Disabling PCI restreaming.\n");
872 }
873}
874DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb );
1597cacb 875DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb );
1da177e4 876
1da177e4 877
ab17443a
CH		 878static void __devinit quirk_sb600_sata(struct pci_dev *pdev)
879{
880 /* set sb600 sata to ahci mode */
881 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
882 u8 tmp;
883
884 pci_read_config_byte(pdev, 0x40, &tmp);
885 pci_write_config_byte(pdev, 0x40, tmp|1);
886 pci_write_config_byte(pdev, 0x9, 1);
887 pci_write_config_byte(pdev, 0xa, 6);
888 pci_write_config_byte(pdev, 0x40, tmp);
889
c9f89475 890 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
ab17443a
CH		 891 }
892}
893DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_sb600_sata);
82377718 894DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_sb600_sata);
ab17443a 895
1da177e4
LT		 896/*
897 * Serverworks CSB5 IDE does not fully support native mode
898 */
899static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
900{
901 u8 prog;
902 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
903 if (prog & 5) {
904 prog &= ~5;
905 pdev->class &= ~5;
906 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
368c73d4 907 /* PCI layer will sort out resources */
1da177e4
LT		 908 }
909}
368c73d4 910DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide );
1da177e4
LT		 911
912/*
913 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
914 */
915static void __init quirk_ide_samemode(struct pci_dev *pdev)
916{
917 u8 prog;
918
919 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
920
921 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
922 printk(KERN_INFO "PCI: IDE mode mismatch; forcing legacy mode\n");
923 prog &= ~5;
924 pdev->class &= ~5;
925 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1da177e4
LT		 926 }
927}
368c73d4 928DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1da177e4
LT		 929
930/* This was originally an Alpha specific thing, but it really fits here.
931 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
932 */
933static void __init quirk_eisa_bridge(struct pci_dev *dev)
934{
935 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
936}
937DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge );
938
7daa0c4f
JG		 939/*
940 * On the MSI-K8T-Neo2Fir Board, the internal Soundcard is disabled
941 * when a PCI-Soundcard is added. The BIOS only gives Options
942 * "Disabled" and "AUTO". This Quirk Sets the corresponding
943 * Register-Value to enable the Soundcard.
bd91fde9
CW		 944 *
945 * FIXME: Presently this quirk will run on anything that has an 8237
946 * which isn't correct, we need to check DMI tables or something in
947 * order to make sure it only runs on the MSI-K8T-Neo2Fir. Because it
948 * runs everywhere at present we suppress the printk output in most
949 * irrelevant cases.
7daa0c4f 950 */
1597cacb 951static void k8t_sound_hostbridge(struct pci_dev *dev)
7daa0c4f
JG		 952{
953 unsigned char val;
954
7daa0c4f
JG		 955 pci_read_config_byte(dev, 0x50, &val);
956 if (val == 0x88 || val == 0xc8) {
bd91fde9
CW		 957 /* Assume it's probably a MSI-K8T-Neo2Fir */
958 printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, attempting to turn soundcard ON\n");
7daa0c4f
JG		 959 pci_write_config_byte(dev, 0x50, val & (~0x40));
960
961 /* Verify the Change for Status output */
962 pci_read_config_byte(dev, 0x50, &val);
963 if (val & 0x40)
bd91fde9 964 printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, soundcard still off\n");
7daa0c4f 965 else
bd91fde9 966 printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, soundcard on\n");
7daa0c4f 967 }
7daa0c4f
JG		 968}
969DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, k8t_sound_hostbridge);
1597cacb 970DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, k8t_sound_hostbridge);
7daa0c4f 971
1da177e4
LT		 972/*
973 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
974 * is not activated. The myth is that Asus said that they do not want the
975 * users to be irritated by just another PCI Device in the Win98 device
976 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
977 * package 2.7.0 for details)
978 *
979 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
980 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
981 * becomes necessary to do this tweak in two steps -- I've chosen the Host
982 * bridge as trigger.
9208ee82
JD		 983 *
984 * Note that we used to unhide the SMBus that way on Toshiba laptops
985 * (Satellite A40 and Tecra M2) but then found that the thermal management
986 * was done by SMM code, which could cause unsynchronized concurrent
987 * accesses to the SMBus registers, with potentially bad effects. Thus you
988 * should be very careful when adding new entries: if SMM is accessing the
989 * Intel SMBus, this is a very good reason to leave it hidden.
1da177e4 990 */
9d24a81e 991static int asus_hides_smbus;
1da177e4
LT		 992
993static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
994{
995 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
996 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
997 switch(dev->subsystem_device) {
a00db371 998 case 0x8025: /* P4B-LX */
1da177e4
LT		 999 case 0x8070: /* P4B */
1000 case 0x8088: /* P4B533 */
1001 case 0x1626: /* L3C notebook */
1002 asus_hides_smbus = 1;
1003 }
2f2d39d2 1004 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1da177e4
LT		 1005 switch(dev->subsystem_device) {
1006 case 0x80b1: /* P4GE-V */
1007 case 0x80b2: /* P4PE */
1008 case 0x8093: /* P4B533-V */
1009 asus_hides_smbus = 1;
1010 }
2f2d39d2 1011 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1da177e4
LT		 1012 switch(dev->subsystem_device) {
1013 case 0x8030: /* P4T533 */
1014 asus_hides_smbus = 1;
1015 }
2f2d39d2 1016 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1da177e4
LT		 1017 switch (dev->subsystem_device) {
1018 case 0x8070: /* P4G8X Deluxe */
1019 asus_hides_smbus = 1;
1020 }
2f2d39d2 1021 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
321311af
JD		 1022 switch (dev->subsystem_device) {
1023 case 0x80c9: /* PU-DLS */
1024 asus_hides_smbus = 1;
1025 }
2f2d39d2 1026 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1da177e4
LT		 1027 switch (dev->subsystem_device) {
1028 case 0x1751: /* M2N notebook */
1029 case 0x1821: /* M5N notebook */
1030 asus_hides_smbus = 1;
1031 }
2f2d39d2 1032 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1da177e4
LT		 1033 switch (dev->subsystem_device) {
1034 case 0x184b: /* W1N notebook */
1035 case 0x186a: /* M6Ne notebook */
1036 asus_hides_smbus = 1;
1037 }
2f2d39d2 1038 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
2e45785c
JD		 1039 switch (dev->subsystem_device) {
1040 case 0x80f2: /* P4P800-X */
1041 asus_hides_smbus = 1;
1042 }
2f2d39d2 1043 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
acc06632
RM		 1044 switch (dev->subsystem_device) {
1045 case 0x1882: /* M6V notebook */
2d1e1c75 1046 case 0x1977: /* A6VA notebook */
acc06632
RM		 1047 asus_hides_smbus = 1;
1048 }
1da177e4
LT		 1049 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1050 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1051 switch(dev->subsystem_device) {
1052 case 0x088C: /* HP Compaq nc8000 */
1053 case 0x0890: /* HP Compaq nc6000 */
1054 asus_hides_smbus = 1;
1055 }
2f2d39d2 1056 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1da177e4
LT		 1057 switch (dev->subsystem_device) {
1058 case 0x12bc: /* HP D330L */
e3b1bd57 1059 case 0x12bd: /* HP D530 */
1da177e4
LT		 1060 asus_hides_smbus = 1;
1061 }
2f2d39d2 1062 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
3c0a654e 1063 switch (dev->subsystem_device) {
1064 case 0x099c: /* HP Compaq nx6110 */
1065 asus_hides_smbus = 1;
1066 }
1da177e4
LT		 1067 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1068 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1069 switch(dev->subsystem_device) {
1070 case 0xC00C: /* Samsung P35 notebook */
1071 asus_hides_smbus = 1;
1072 }
c87f883e
RIZ		 1073 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1074 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1075 switch(dev->subsystem_device) {
1076 case 0x0058: /* Compaq Evo N620c */
1077 asus_hides_smbus = 1;
1078 }
1da177e4
LT		 1079 }
1080}
1081DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge );
1082DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge );
1083DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge );
1084DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge );
1085DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge );
321311af 1086DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge );
1da177e4
LT		 1087DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge );
1088DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge );
acc06632 1089DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge );
1da177e4 1090
1597cacb 1091static void asus_hides_smbus_lpc(struct pci_dev *dev)
1da177e4
LT		 1092{
1093 u16 val;
1094
1095 if (likely(!asus_hides_smbus))
1096 return;
1097
1098 pci_read_config_word(dev, 0xF2, &val);
1099 if (val & 0x8) {
1100 pci_write_config_word(dev, 0xF2, val & (~0x8));
1101 pci_read_config_word(dev, 0xF2, &val);
1102 if (val & 0x8)
1103 printk(KERN_INFO "PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1104 else
1105 printk(KERN_INFO "PCI: Enabled i801 SMBus device\n");
1106 }
1107}
1108DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc );
1109DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc );
321311af 1110DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc );
1da177e4
LT		 1111DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc );
1112DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc );
1113DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc );
1597cacb
AC		 1114DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc );
1115DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc );
1116DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc );
1117DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc );
1118DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc );
1119DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc );
1120
1121static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
acc06632
RM		 1122{
1123 u32 val, rcba;
1124 void __iomem *base;
1125
1126 if (likely(!asus_hides_smbus))
1127 return;
1128 pci_read_config_dword(dev, 0xF0, &rcba);
1129 base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); /* use bits 31:14, 16 kB aligned */
1130 if (base == NULL) return;
1131 val=readl(base + 0x3418); /* read the Function Disable register, dword mode only */
1132 writel(val & 0xFFFFFFF7, base + 0x3418); /* enable the SMBus device */
1133 iounmap(base);
1134 printk(KERN_INFO "PCI: Enabled ICH6/i801 SMBus device\n");
1135}
1136DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6 );
1597cacb 1137DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6 );
ce007ea5 1138
1da177e4
LT		 1139/*
1140 * SiS 96x south bridge: BIOS typically hides SMBus device...
1141 */
1597cacb 1142static void quirk_sis_96x_smbus(struct pci_dev *dev)
1da177e4
LT		 1143{
1144 u8 val = 0;
1da177e4 1145 pci_read_config_byte(dev, 0x77, &val);
2f5c33b3
MH		 1146 if (val & 0x10) {
1147 printk(KERN_INFO "Enabling SiS 96x SMBus.\n");
1148 pci_write_config_byte(dev, 0x77, val & ~0x10);
1149 }
1da177e4 1150}
c30ca1db
AB		 1151DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus );
1152DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus );
1153DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus );
1154DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus );
1155DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus );
1156DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus );
1157DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus );
1158DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus );
1da177e4 1159
1da177e4
LT		 1160/*
1161 * ... This is further complicated by the fact that some SiS96x south
1162 * bridges pretend to be 85C503/5513 instead. In that case see if we
1163 * spotted a compatible north bridge to make sure.
1164 * (pci_find_device doesn't work yet)
1165 *
1166 * We can also enable the sis96x bit in the discovery register..
1167 */
1da177e4
LT		 1168#define SIS_DETECT_REGISTER 0x40
1169
1597cacb 1170static void quirk_sis_503(struct pci_dev *dev)
1da177e4
LT		 1171{
1172 u8 reg;
1173 u16 devid;
1174
1175 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1176 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1177 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1178 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1179 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1180 return;
1181 }
1182
1da177e4 1183 /*
2f5c33b3
MH		 1184 * Ok, it now shows up as a 96x.. run the 96x quirk by
1185 * hand in case it has already been processed.
1186 * (depends on link order, which is apparently not guaranteed)
1da177e4
LT		 1187 */
1188 dev->device = devid;
2f5c33b3 1189 quirk_sis_96x_smbus(dev);
1da177e4 1190}
c30ca1db
AB		 1191DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503 );
1192DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503 );
1da177e4 1193
1da177e4 1194
e5548e96
BJD		 1195/*
1196 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1197 * and MC97 modem controller are disabled when a second PCI soundcard is
1198 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1199 * -- bjd
1200 */
1597cacb 1201static void asus_hides_ac97_lpc(struct pci_dev *dev)
e5548e96
BJD		 1202{
1203 u8 val;
1204 int asus_hides_ac97 = 0;
1205
1206 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1207 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1208 asus_hides_ac97 = 1;
1209 }
1210
1211 if (!asus_hides_ac97)
1212 return;
1213
1214 pci_read_config_byte(dev, 0x50, &val);
1215 if (val & 0xc0) {
1216 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1217 pci_read_config_byte(dev, 0x50, &val);
1218 if (val & 0xc0)
1219 printk(KERN_INFO "PCI: onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
1220 else
1221 printk(KERN_INFO "PCI: enabled onboard AC97/MC97 devices\n");
1222 }
1223}
1224DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc );
1597cacb
AC		 1225DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc );
1226
77967052 1227#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
15e0c694
AC		 1228
1229/*
1230 * If we are using libata we can drive this chip properly but must
1231 * do this early on to make the additional device appear during
1232 * the PCI scanning.
1233 */
5ee2ae7f 1234static void quirk_jmicron_ata(struct pci_dev *pdev)
15e0c694 1235{
e34bb370 1236 u32 conf1, conf5, class;
15e0c694
AC		 1237 u8 hdr;
1238
1239 /* Only poke fn 0 */
1240 if (PCI_FUNC(pdev->devfn))
1241 return;
1242
5ee2ae7f
TH		 1243 pci_read_config_dword(pdev, 0x40, &conf1);
1244 pci_read_config_dword(pdev, 0x80, &conf5);
15e0c694 1245
5ee2ae7f
TH		 1246 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1247 conf5 &= ~(1 << 24); /* Clear bit 24 */
1248
1249 switch (pdev->device) {
1250 case PCI_DEVICE_ID_JMICRON_JMB360:
1251 /* The controller should be in single function ahci mode */
1252 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1253 break;
1254
1255 case PCI_DEVICE_ID_JMICRON_JMB365:
1256 case PCI_DEVICE_ID_JMICRON_JMB366:
1257 /* Redirect IDE second PATA port to the right spot */
1258 conf5 |= (1 << 24);
1259 /* Fall through */
1260 case PCI_DEVICE_ID_JMICRON_JMB361:
1261 case PCI_DEVICE_ID_JMICRON_JMB363:
1262 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1263 /* Set the class codes correctly and then direct IDE 0 */
1264 conf1 |= 0x00C2A102; /* Set 1, 8, 13, 15, 17, 22, 23 */
1265 break;
1266
1267 case PCI_DEVICE_ID_JMICRON_JMB368:
1268 /* The controller should be in single function IDE mode */
1269 conf1 |= 0x00C00000; /* Set 22, 23 */
1270 break;
15e0c694 1271 }
5ee2ae7f
TH		 1272
1273 pci_write_config_dword(pdev, 0x40, conf1);
1274 pci_write_config_dword(pdev, 0x80, conf5);
1275
1276 /* Update pdev accordingly */
1277 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1278 pdev->hdr_type = hdr & 0x7f;
1279 pdev->multifunction = !!(hdr & 0x80);
e34bb370
TH		 1280
1281 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1282 pdev->class = class >> 8;
15e0c694 1283}
5ee2ae7f
TH		 1284DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1285DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1286DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1287DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1288DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1289DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1290DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1291DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1292DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1293DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1294DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1295DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
15e0c694
AC		 1296
1297#endif
1298
1da177e4
LT		 1299#ifdef CONFIG_X86_IO_APIC
1300static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1301{
1302 int i;
1303
1304 if ((pdev->class >> 8) != 0xff00)
1305 return;
1306
1307 /* the first BAR is the location of the IO APIC...we must
1308 * not touch this (and it's already covered by the fixmap), so
1309 * forcibly insert it into the resource tree */
1310 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1311 insert_resource(&iomem_resource, &pdev->resource[0]);
1312
1313 /* The next five BARs all seem to be rubbish, so just clean
1314 * them out */
1315 for (i=1; i < 6; i++) {
1316 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1317 }
1318
1319}
1320DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic );
1321#endif
1322
1da177e4 1323int pcie_mch_quirk;
c30ca1db 1324EXPORT_SYMBOL(pcie_mch_quirk);
1da177e4
LT		 1325
1326static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1327{
1328 pcie_mch_quirk = 1;
1329}
1330DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch );
1331DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch );
1332DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch );
1333
4602b88d
KA		 1334
1335/*
1336 * It's possible for the MSI to get corrupted if shpc and acpi
1337 * are used together on certain PXH-based systems.
1338 */
1339static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1340{
f5f2b131
EB		 1341 pci_msi_off(dev);
1342
4602b88d
KA		 1343 dev->no_msi = 1;
1344
1345 printk(KERN_WARNING "PCI: PXH quirk detected, "
1346 "disabling MSI for SHPC device\n");
1347}
1348DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1349DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1350DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1351DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1352DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1353
ffadcc2f
KCA		 1354/*
1355 * Some Intel PCI Express chipsets have trouble with downstream
1356 * device power management.
1357 */
1358static void quirk_intel_pcie_pm(struct pci_dev * dev)
1359{
1360 pci_pm_d3_delay = 120;
1361 dev->no_d1d2 = 1;
1362}
1363
1364DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1365DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1366DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1367DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1368DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1369DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1370DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1371DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1372DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1373DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1374DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1375DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1376DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1377DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1378DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1379DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1380DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1381DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1382DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1383DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1384DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
4602b88d 1385
33dced2e
SS		 1386/*
1387 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1388 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1389 * Re-allocate the region if needed...
1390 */
1391static void __init quirk_tc86c001_ide(struct pci_dev *dev)
1392{
1393 struct resource *r = &dev->resource[0];
1394
1395 if (r->start & 0x8) {
1396 r->start = 0;
1397 r->end = 0xf;
1398 }
1399}
1400DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1401 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1402 quirk_tc86c001_ide);
1403
1da177e4
LT		 1404static void __devinit quirk_netmos(struct pci_dev *dev)
1405{
1406 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1407 unsigned int num_serial = dev->subsystem_device & 0xf;
1408
1409 /*
1410 * These Netmos parts are multiport serial devices with optional
1411 * parallel ports. Even when parallel ports are present, they
1412 * are identified as class SERIAL, which means the serial driver
1413 * will claim them. To prevent this, mark them as class OTHER.
1414 * These combo devices should be claimed by parport_serial.
1415 *
1416 * The subdevice ID is of the form 0x00PS, where <P> is the number
1417 * of parallel ports and <S> is the number of serial ports.
1418 */
1419 switch (dev->device) {
1420 case PCI_DEVICE_ID_NETMOS_9735:
1421 case PCI_DEVICE_ID_NETMOS_9745:
1422 case PCI_DEVICE_ID_NETMOS_9835:
1423 case PCI_DEVICE_ID_NETMOS_9845:
1424 case PCI_DEVICE_ID_NETMOS_9855:
1425 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1426 num_parallel) {
1427 printk(KERN_INFO "PCI: Netmos %04x (%u parallel, "
1428 "%u serial); changing class SERIAL to OTHER "
1429 "(use parport_serial)\n",
1430 dev->device, num_parallel, num_serial);
1431 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1432 (dev->class & 0xff);
1433 }
1434 }
1435}
1436DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1437
16a74744
BH		 1438static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1439{
1440 u16 command;
1441 u32 bar;
1442 u8 __iomem *csr;
1443 u8 cmd_hi;
1444
1445 switch (dev->device) {
1446 /* PCI IDs taken from drivers/net/e100.c */
1447 case 0x1029:
1448 case 0x1030 ... 0x1034:
1449 case 0x1038 ... 0x103E:
1450 case 0x1050 ... 0x1057:
1451 case 0x1059:
1452 case 0x1064 ... 0x106B:
1453 case 0x1091 ... 0x1095:
1454 case 0x1209:
1455 case 0x1229:
1456 case 0x2449:
1457 case 0x2459:
1458 case 0x245D:
1459 case 0x27DC:
1460 break;
1461 default:
1462 return;
1463 }
1464
1465 /*
1466 * Some firmware hands off the e100 with interrupts enabled,
1467 * which can cause a flood of interrupts if packets are
1468 * received before the driver attaches to the device. So
1469 * disable all e100 interrupts here. The driver will
1470 * re-enable them when it's ready.
1471 */
1472 pci_read_config_word(dev, PCI_COMMAND, &command);
1473 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar);
1474
1475 if (!(command & PCI_COMMAND_MEMORY) || !bar)
1476 return;
1477
1478 csr = ioremap(bar, 8);
1479 if (!csr) {
1480 printk(KERN_WARNING "PCI: Can't map %s e100 registers\n",
1481 pci_name(dev));
1482 return;
1483 }
1484
1485 cmd_hi = readb(csr + 3);
1486 if (cmd_hi == 0) {
1487 printk(KERN_WARNING "PCI: Firmware left %s e100 interrupts "
1488 "enabled, disabling\n", pci_name(dev));
1489 writeb(1, csr + 3);
1490 }
1491
1492 iounmap(csr);
1493}
1494DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt);
a5312e28
IK		 1495
1496static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1497{
1498 /* rev 1 ncr53c810 chips don't set the class at all which means
1499 * they don't get their resources remapped. Fix that here.
1500 */
1501
1502 if (dev->class == PCI_CLASS_NOT_DEFINED) {
1503 printk(KERN_INFO "NCR 53c810 rev 1 detected, setting PCI class.\n");
1504 dev->class = PCI_CLASS_STORAGE_SCSI;
1505 }
1506}
1507DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1508
1da177e4
LT		 1509static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end)
1510{
1511 while (f < end) {
1512 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
1513 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
1514 pr_debug("PCI: Calling quirk %p for %s\n", f->hook, pci_name(dev));
1515 f->hook(dev);
1516 }
1517 f++;
1518 }
1519}
1520
1521extern struct pci_fixup __start_pci_fixups_early[];
1522extern struct pci_fixup __end_pci_fixups_early[];
1523extern struct pci_fixup __start_pci_fixups_header[];
1524extern struct pci_fixup __end_pci_fixups_header[];
1525extern struct pci_fixup __start_pci_fixups_final[];
1526extern struct pci_fixup __end_pci_fixups_final[];
1527extern struct pci_fixup __start_pci_fixups_enable[];
1528extern struct pci_fixup __end_pci_fixups_enable[];
1597cacb
AC		 1529extern struct pci_fixup __start_pci_fixups_resume[];
1530extern struct pci_fixup __end_pci_fixups_resume[];
1da177e4
LT		 1531
1532
1533void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
1534{
1535 struct pci_fixup *start, *end;
1536
1537 switch(pass) {
1538 case pci_fixup_early:
1539 start = __start_pci_fixups_early;
1540 end = __end_pci_fixups_early;
1541 break;
1542
1543 case pci_fixup_header:
1544 start = __start_pci_fixups_header;
1545 end = __end_pci_fixups_header;
1546 break;
1547
1548 case pci_fixup_final:
1549 start = __start_pci_fixups_final;
1550 end = __end_pci_fixups_final;
1551 break;
1552
1553 case pci_fixup_enable:
1554 start = __start_pci_fixups_enable;
1555 end = __end_pci_fixups_enable;
1556 break;
1557
1597cacb
AC		 1558 case pci_fixup_resume:
1559 start = __start_pci_fixups_resume;
1560 end = __end_pci_fixups_resume;
1561 break;
1562
1da177e4
LT		 1563 default:
1564 /* stupid compiler warning, you would think with an enum... */
1565 return;
1566 }
1567 pci_do_fixups(dev, start, end);
1568}
c30ca1db 1569EXPORT_SYMBOL(pci_fixup_device);
1da177e4 1570
9d265124
DY		 1571/* Enable 1k I/O space granularity on the Intel P64H2 */
1572static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1573{
1574 u16 en1k;
1575 u8 io_base_lo, io_limit_lo;
1576 unsigned long base, limit;
1577 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1578
1579 pci_read_config_word(dev, 0x40, &en1k);
1580
1581 if (en1k & 0x200) {
1582 printk(KERN_INFO "PCI: Enable I/O Space to 1 KB Granularity\n");
1583
1584 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
1585 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
1586 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1587 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1588
1589 if (base <= limit) {
1590 res->start = base;
1591 res->end = limit + 0x3ff;
1592 }
1593 }
1594}
1595DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
1596
15a260d5
DY		 1597/* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2
1598 * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge()
1599 * in drivers/pci/setup-bus.c
1600 */
1601static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev)
1602{
1603 u16 en1k, iobl_adr, iobl_adr_1k;
1604 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1605
1606 pci_read_config_word(dev, 0x40, &en1k);
1607
1608 if (en1k & 0x200) {
1609 pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr);
1610
1611 iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00);
1612
1613 if (iobl_adr != iobl_adr_1k) {
1614 printk(KERN_INFO "PCI: Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1 KB Granularity\n",
1615 iobl_adr,iobl_adr_1k);
1616 pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k);
1617 }
1618 }
1619}
1620DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl);
1621
cf34a8e0
BG		 1622/* Under some circumstances, AER is not linked with extended capabilities.
1623 * Force it to be linked by setting the corresponding control bit in the
1624 * config space.
1625 */
1597cacb 1626static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
cf34a8e0
BG		 1627{
1628 uint8_t b;
1629 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
1630 if (!(b & 0x20)) {
1631 pci_write_config_byte(dev, 0xf41, b | 0x20);
1632 printk(KERN_INFO
1633 "PCI: Linking AER extended capability on %s\n",
1634 pci_name(dev));
1635 }
1636 }
1637}
1638DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1639 quirk_nvidia_ck804_pcie_aer_ext_cap);
1597cacb
AC		 1640DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1641 quirk_nvidia_ck804_pcie_aer_ext_cap);
cf34a8e0 1642
3f79e107 1643#ifdef CONFIG_PCI_MSI
ebdf7d39
TH		 1644/* Some chipsets do not support MSI. We cannot easily rely on setting
1645 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
1646 * some other busses controlled by the chipset even if Linux is not
1647 * aware of it. Instead of setting the flag on all busses in the
1648 * machine, simply disable MSI globally.
3f79e107 1649 */
ebdf7d39 1650static void __init quirk_disable_all_msi(struct pci_dev *dev)
3f79e107 1651{
88187dfa
ME		 1652 pci_no_msi();
1653 printk(KERN_WARNING "PCI: MSI quirk detected. MSI deactivated.\n");
3f79e107 1654}
ebdf7d39 1655DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
e3008ded 1656DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000_PCIX, quirk_disable_all_msi);
ebdf7d39
TH		 1657DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
1658DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
184b812f 1659DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
3f79e107
BG		 1660
1661/* Disable MSI on chipsets that are known to not support it */
1662static void __devinit quirk_disable_msi(struct pci_dev *dev)
1663{
1664 if (dev->subordinate) {
1665 printk(KERN_WARNING "PCI: MSI quirk detected. "
1666 "PCI_BUS_FLAGS_NO_MSI set for %s subordinate bus.\n",
1667 pci_name(dev));
1668 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1669 }
1670}
1671DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
6397c75c
BG		 1672
1673/* Go through the list of Hypertransport capabilities and
1674 * return 1 if a HT MSI capability is found and enabled */
1675static int __devinit msi_ht_cap_enabled(struct pci_dev *dev)
1676{
7a380507
ME		 1677 int pos, ttl = 48;
1678
1679 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
1680 while (pos && ttl--) {
1681 u8 flags;
1682
1683 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
1684 &flags) == 0)
1685 {
1686 printk(KERN_INFO "PCI: Found %s HT MSI Mapping on %s\n",
1687 flags & HT_MSI_FLAGS_ENABLE ?
1688 "enabled" : "disabled", pci_name(dev));
1689 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
6397c75c 1690 }
7a380507
ME		 1691
1692 pos = pci_find_next_ht_capability(dev, pos,
1693 HT_CAPTYPE_MSI_MAPPING);
6397c75c
BG		 1694 }
1695 return 0;
1696}
1697
1698/* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
1699static void __devinit quirk_msi_ht_cap(struct pci_dev *dev)
1700{
1701 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
1702 printk(KERN_WARNING "PCI: MSI quirk detected. "
1703 "MSI disabled on chipset %s.\n",
1704 pci_name(dev));
1705 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1706 }
1707}
1708DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
1709 quirk_msi_ht_cap);
1710
1711/* The nVidia CK804 chipset may have 2 HT MSI mappings.
1712 * MSI are supported if the MSI capability set in any of these mappings.
1713 */
1714static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
1715{
1716 struct pci_dev *pdev;
1717
1718 if (!dev->subordinate)
1719 return;
1720
1721 /* check HT MSI cap on this chipset and the root one.
1722 * a single one having MSI is enough to be sure that MSI are supported.
1723 */
11f242f0 1724 pdev = pci_get_slot(dev->bus, 0);
9ac0ce85
JJ		 1725 if (!pdev)
1726 return;
0c875c28 1727 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
6397c75c
BG		 1728 printk(KERN_WARNING "PCI: MSI quirk detected. "
1729 "MSI disabled on chipset %s.\n",
1730 pci_name(dev));
1731 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1732 }
11f242f0 1733 pci_dev_put(pdev);
6397c75c
BG		 1734}
1735DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1736 quirk_nvidia_ck804_msi_ht_cap);
3f79e107 1737#endif /* CONFIG_PCI_MSI */
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