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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * drivers/pci/rom.c | |
3 | * | |
4 | * (C) Copyright 2004 Jon Smirl <jonsmirl@yahoo.com> | |
5 | * (C) Copyright 2004 Silicon Graphics, Inc. Jesse Barnes <jbarnes@sgi.com> | |
6 | * | |
7 | * PCI ROM access routines | |
8 | */ | |
1da177e4 | 9 | #include <linux/kernel.h> |
363c75db | 10 | #include <linux/export.h> |
1da177e4 | 11 | #include <linux/pci.h> |
4e57b681 | 12 | #include <linux/slab.h> |
1da177e4 LT |
13 | |
14 | #include "pci.h" | |
15 | ||
16 | /** | |
17 | * pci_enable_rom - enable ROM decoding for a PCI device | |
67be2dd1 | 18 | * @pdev: PCI device to enable |
1da177e4 LT |
19 | * |
20 | * Enable ROM decoding on @dev. This involves simply turning on the last | |
21 | * bit of the PCI ROM BAR. Note that some cards may share address decoders | |
22 | * between the ROM and other resources, so enabling it may disable access | |
23 | * to MMIO registers or other card memory. | |
24 | */ | |
e416de5e | 25 | int pci_enable_rom(struct pci_dev *pdev) |
1da177e4 | 26 | { |
8085ce08 BH |
27 | struct resource *res = pdev->resource + PCI_ROM_RESOURCE; |
28 | struct pci_bus_region region; | |
1da177e4 LT |
29 | u32 rom_addr; |
30 | ||
8085ce08 BH |
31 | if (!res->flags) |
32 | return -1; | |
33 | ||
b09fcafe BH |
34 | /* |
35 | * Ideally pci_update_resource() would update the ROM BAR address, | |
36 | * and we would only set the enable bit here. But apparently some | |
37 | * devices have buggy ROM BARs that read as zero when disabled. | |
38 | */ | |
fc279850 | 39 | pcibios_resource_to_bus(pdev->bus, ®ion, res); |
1da177e4 | 40 | pci_read_config_dword(pdev, pdev->rom_base_reg, &rom_addr); |
8085ce08 BH |
41 | rom_addr &= ~PCI_ROM_ADDRESS_MASK; |
42 | rom_addr |= region.start | PCI_ROM_ADDRESS_ENABLE; | |
1da177e4 | 43 | pci_write_config_dword(pdev, pdev->rom_base_reg, rom_addr); |
8085ce08 | 44 | return 0; |
1da177e4 | 45 | } |
b7fe9434 | 46 | EXPORT_SYMBOL_GPL(pci_enable_rom); |
1da177e4 LT |
47 | |
48 | /** | |
49 | * pci_disable_rom - disable ROM decoding for a PCI device | |
67be2dd1 | 50 | * @pdev: PCI device to disable |
1da177e4 LT |
51 | * |
52 | * Disable ROM decoding on a PCI device by turning off the last bit in the | |
53 | * ROM BAR. | |
54 | */ | |
e416de5e | 55 | void pci_disable_rom(struct pci_dev *pdev) |
1da177e4 LT |
56 | { |
57 | u32 rom_addr; | |
58 | pci_read_config_dword(pdev, pdev->rom_base_reg, &rom_addr); | |
59 | rom_addr &= ~PCI_ROM_ADDRESS_ENABLE; | |
60 | pci_write_config_dword(pdev, pdev->rom_base_reg, rom_addr); | |
61 | } | |
b7fe9434 | 62 | EXPORT_SYMBOL_GPL(pci_disable_rom); |
1da177e4 | 63 | |
d7ad2254 JK |
64 | /** |
65 | * pci_get_rom_size - obtain the actual size of the ROM image | |
4cc59c72 | 66 | * @pdev: target PCI device |
d7ad2254 JK |
67 | * @rom: kernel virtual pointer to image of ROM |
68 | * @size: size of PCI window | |
69 | * return: size of actual ROM image | |
70 | * | |
71 | * Determine the actual length of the ROM image. | |
72 | * The PCI window size could be much larger than the | |
73 | * actual image size. | |
74 | */ | |
97c44836 | 75 | size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size) |
d7ad2254 JK |
76 | { |
77 | void __iomem *image; | |
78 | int last_image; | |
16b036af | 79 | unsigned length; |
d7ad2254 JK |
80 | |
81 | image = rom; | |
82 | do { | |
83 | void __iomem *pds; | |
84 | /* Standard PCI ROMs start out with these bytes 55 AA */ | |
97c44836 TN |
85 | if (readb(image) != 0x55) { |
86 | dev_err(&pdev->dev, "Invalid ROM contents\n"); | |
d7ad2254 | 87 | break; |
97c44836 | 88 | } |
d7ad2254 JK |
89 | if (readb(image + 1) != 0xAA) |
90 | break; | |
91 | /* get the PCI data structure and check its signature */ | |
92 | pds = image + readw(image + 24); | |
93 | if (readb(pds) != 'P') | |
94 | break; | |
95 | if (readb(pds + 1) != 'C') | |
96 | break; | |
97 | if (readb(pds + 2) != 'I') | |
98 | break; | |
99 | if (readb(pds + 3) != 'R') | |
100 | break; | |
101 | last_image = readb(pds + 21) & 0x80; | |
16b036af MD |
102 | length = readw(pds + 16); |
103 | image += length * 512; | |
104 | } while (length && !last_image); | |
d7ad2254 JK |
105 | |
106 | /* never return a size larger than the PCI resource window */ | |
107 | /* there are known ROMs that get the size wrong */ | |
108 | return min((size_t)(image - rom), size); | |
109 | } | |
110 | ||
1da177e4 LT |
111 | /** |
112 | * pci_map_rom - map a PCI ROM to kernel space | |
67be2dd1 | 113 | * @pdev: pointer to pci device struct |
1da177e4 | 114 | * @size: pointer to receive size of pci window over ROM |
f5dafca5 RD |
115 | * |
116 | * Return: kernel virtual pointer to image of ROM | |
1da177e4 LT |
117 | * |
118 | * Map a PCI ROM into kernel space. If ROM is boot video ROM, | |
119 | * the shadow BIOS copy will be returned instead of the | |
120 | * actual ROM. | |
121 | */ | |
122 | void __iomem *pci_map_rom(struct pci_dev *pdev, size_t *size) | |
123 | { | |
124 | struct resource *res = &pdev->resource[PCI_ROM_RESOURCE]; | |
fffe01f7 | 125 | loff_t start; |
1da177e4 | 126 | void __iomem *rom; |
1da177e4 | 127 | |
b5e4efe7 | 128 | /* |
6b5c76b8 EO |
129 | * IORESOURCE_ROM_SHADOW set on x86, x86_64 and IA64 supports legacy |
130 | * memory map if the VGA enable bit of the Bridge Control register is | |
131 | * set for embedded VGA. | |
b5e4efe7 | 132 | */ |
547b5246 | 133 | if (res->flags & IORESOURCE_ROM_SHADOW) { |
1da177e4 LT |
134 | /* primary video rom always starts here */ |
135 | start = (loff_t)0xC0000; | |
136 | *size = 0x20000; /* cover C000:0 through E000:0 */ | |
137 | } else { | |
a2302c68 JK |
138 | if (res->flags & |
139 | (IORESOURCE_ROM_COPY | IORESOURCE_ROM_BIOS_COPY)) { | |
1da177e4 | 140 | *size = pci_resource_len(pdev, PCI_ROM_RESOURCE); |
e31dd6e4 GKH |
141 | return (void __iomem *)(unsigned long) |
142 | pci_resource_start(pdev, PCI_ROM_RESOURCE); | |
1da177e4 | 143 | } else { |
fffe01f7 MG |
144 | /* assign the ROM an address if it doesn't have one */ |
145 | if (res->parent == NULL && | |
3c78bc61 | 146 | pci_assign_resource(pdev, PCI_ROM_RESOURCE)) |
fffe01f7 MG |
147 | return NULL; |
148 | start = pci_resource_start(pdev, PCI_ROM_RESOURCE); | |
149 | *size = pci_resource_len(pdev, PCI_ROM_RESOURCE); | |
150 | if (*size == 0) | |
151 | return NULL; | |
1da177e4 | 152 | |
fffe01f7 MG |
153 | /* Enable ROM space decodes */ |
154 | if (pci_enable_rom(pdev)) | |
155 | return NULL; | |
156 | } | |
547b5246 MG |
157 | } |
158 | ||
1da177e4 LT |
159 | rom = ioremap(start, *size); |
160 | if (!rom) { | |
161 | /* restore enable if ioremap fails */ | |
162 | if (!(res->flags & (IORESOURCE_ROM_ENABLE | | |
163 | IORESOURCE_ROM_SHADOW | | |
164 | IORESOURCE_ROM_COPY))) | |
165 | pci_disable_rom(pdev); | |
166 | return NULL; | |
167 | } | |
168 | ||
169 | /* | |
170 | * Try to find the true size of the ROM since sometimes the PCI window | |
171 | * size is much larger than the actual size of the ROM. | |
172 | * True size is important if the ROM is going to be copied. | |
173 | */ | |
97c44836 | 174 | *size = pci_get_rom_size(pdev, rom, *size); |
1da177e4 LT |
175 | return rom; |
176 | } | |
b7fe9434 | 177 | EXPORT_SYMBOL(pci_map_rom); |
1da177e4 | 178 | |
1da177e4 LT |
179 | /** |
180 | * pci_unmap_rom - unmap the ROM from kernel space | |
67be2dd1 | 181 | * @pdev: pointer to pci device struct |
1da177e4 LT |
182 | * @rom: virtual address of the previous mapping |
183 | * | |
184 | * Remove a mapping of a previously mapped ROM | |
185 | */ | |
186 | void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom) | |
187 | { | |
188 | struct resource *res = &pdev->resource[PCI_ROM_RESOURCE]; | |
189 | ||
a2302c68 | 190 | if (res->flags & (IORESOURCE_ROM_COPY | IORESOURCE_ROM_BIOS_COPY)) |
1da177e4 LT |
191 | return; |
192 | ||
fffe01f7 | 193 | iounmap(rom); |
1da177e4 LT |
194 | |
195 | /* Disable again before continuing, leave enabled if pci=rom */ | |
196 | if (!(res->flags & (IORESOURCE_ROM_ENABLE | IORESOURCE_ROM_SHADOW))) | |
197 | pci_disable_rom(pdev); | |
198 | } | |
b7fe9434 | 199 | EXPORT_SYMBOL(pci_unmap_rom); |
1da177e4 | 200 | |
1da177e4 | 201 | /** |
0643245f | 202 | * pci_cleanup_rom - free the ROM copy created by pci_map_rom_copy |
67be2dd1 | 203 | * @pdev: pointer to pci device struct |
1da177e4 LT |
204 | * |
205 | * Free the copied ROM if we allocated one. | |
206 | */ | |
207 | void pci_cleanup_rom(struct pci_dev *pdev) | |
208 | { | |
209 | struct resource *res = &pdev->resource[PCI_ROM_RESOURCE]; | |
bd064f0a | 210 | |
1da177e4 | 211 | if (res->flags & IORESOURCE_ROM_COPY) { |
3c78bc61 | 212 | kfree((void *)(unsigned long)res->start); |
bd064f0a | 213 | res->flags |= IORESOURCE_UNSET; |
1da177e4 LT |
214 | res->flags &= ~IORESOURCE_ROM_COPY; |
215 | res->start = 0; | |
216 | res->end = 0; | |
217 | } | |
218 | } | |
219 | ||
fffe01f7 MG |
220 | /** |
221 | * pci_platform_rom - provides a pointer to any ROM image provided by the | |
222 | * platform | |
223 | * @pdev: pointer to pci device struct | |
224 | * @size: pointer to receive size of pci window over ROM | |
225 | */ | |
226 | void __iomem *pci_platform_rom(struct pci_dev *pdev, size_t *size) | |
227 | { | |
228 | if (pdev->rom && pdev->romlen) { | |
229 | *size = pdev->romlen; | |
230 | return phys_to_virt((phys_addr_t)pdev->rom); | |
231 | } | |
232 | ||
233 | return NULL; | |
234 | } | |
fffe01f7 | 235 | EXPORT_SYMBOL(pci_platform_rom); |