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Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * drivers/pci/setup-bus.c | |
3 | * | |
4 | * Extruded from code written by | |
5 | * Dave Rusling (david.rusling@reo.mts.dec.com) | |
6 | * David Mosberger (davidm@cs.arizona.edu) | |
7 | * David Miller (davem@redhat.com) | |
8 | * | |
9 | * Support routines for initializing a PCI subsystem. | |
10 | */ | |
11 | ||
12 | /* | |
13 | * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> | |
14 | * PCI-PCI bridges cleanup, sorted resource allocation. | |
15 | * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru> | |
16 | * Converted to allocation in 3 passes, which gives | |
17 | * tighter packing. Prefetchable range support. | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/pci.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/ioport.h> | |
26 | #include <linux/cache.h> | |
27 | #include <linux/slab.h> | |
6faf17f6 | 28 | #include "pci.h" |
1da177e4 | 29 | |
ea741551 | 30 | static void pbus_assign_resources_sorted(const struct pci_bus *bus) |
1da177e4 LT |
31 | { |
32 | struct pci_dev *dev; | |
33 | struct resource *res; | |
34 | struct resource_list head, *list, *tmp; | |
35 | int idx; | |
36 | ||
1da177e4 LT |
37 | head.next = NULL; |
38 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
39 | u16 class = dev->class >> 8; | |
40 | ||
9bded00b | 41 | /* Don't touch classless devices or host bridges or ioapics. */ |
1da177e4 | 42 | if (class == PCI_CLASS_NOT_DEFINED || |
23186279 | 43 | class == PCI_CLASS_BRIDGE_HOST) |
1da177e4 LT |
44 | continue; |
45 | ||
9bded00b | 46 | /* Don't touch ioapic devices already enabled by firmware */ |
23186279 | 47 | if (class == PCI_CLASS_SYSTEM_PIC) { |
9bded00b KK |
48 | u16 command; |
49 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
50 | if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | |
23186279 ST |
51 | continue; |
52 | } | |
53 | ||
1da177e4 LT |
54 | pdev_sort_resources(dev, &head); |
55 | } | |
56 | ||
57 | for (list = head.next; list;) { | |
58 | res = list->res; | |
59 | idx = res - &list->dev->resource[0]; | |
542df5de RS |
60 | if (pci_assign_resource(list->dev, idx)) { |
61 | res->start = 0; | |
960b8466 | 62 | res->end = 0; |
542df5de RS |
63 | res->flags = 0; |
64 | } | |
1da177e4 LT |
65 | tmp = list; |
66 | list = list->next; | |
67 | kfree(tmp); | |
68 | } | |
69 | } | |
70 | ||
b3743fa4 | 71 | void pci_setup_cardbus(struct pci_bus *bus) |
1da177e4 LT |
72 | { |
73 | struct pci_dev *bridge = bus->self; | |
c7dabef8 | 74 | struct resource *res; |
1da177e4 LT |
75 | struct pci_bus_region region; |
76 | ||
865df576 BH |
77 | dev_info(&bridge->dev, "CardBus bridge to [bus %02x-%02x]\n", |
78 | bus->secondary, bus->subordinate); | |
1da177e4 | 79 | |
c7dabef8 BH |
80 | res = bus->resource[0]; |
81 | pcibios_resource_to_bus(bridge, ®ion, res); | |
82 | if (res->flags & IORESOURCE_IO) { | |
1da177e4 LT |
83 | /* |
84 | * The IO resource is allocated a range twice as large as it | |
85 | * would normally need. This allows us to set both IO regs. | |
86 | */ | |
c7dabef8 | 87 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
1da177e4 LT |
88 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, |
89 | region.start); | |
90 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0, | |
91 | region.end); | |
92 | } | |
93 | ||
c7dabef8 BH |
94 | res = bus->resource[1]; |
95 | pcibios_resource_to_bus(bridge, ®ion, res); | |
96 | if (res->flags & IORESOURCE_IO) { | |
97 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
98 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, |
99 | region.start); | |
100 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1, | |
101 | region.end); | |
102 | } | |
103 | ||
c7dabef8 BH |
104 | res = bus->resource[2]; |
105 | pcibios_resource_to_bus(bridge, ®ion, res); | |
106 | if (res->flags & IORESOURCE_MEM) { | |
107 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
108 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, |
109 | region.start); | |
110 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0, | |
111 | region.end); | |
112 | } | |
113 | ||
c7dabef8 BH |
114 | res = bus->resource[3]; |
115 | pcibios_resource_to_bus(bridge, ®ion, res); | |
116 | if (res->flags & IORESOURCE_MEM) { | |
117 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
118 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, |
119 | region.start); | |
120 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1, | |
121 | region.end); | |
122 | } | |
123 | } | |
b3743fa4 | 124 | EXPORT_SYMBOL(pci_setup_cardbus); |
1da177e4 LT |
125 | |
126 | /* Initialize bridges with base/limit values we have collected. | |
127 | PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998) | |
128 | requires that if there is no I/O ports or memory behind the | |
129 | bridge, corresponding range must be turned off by writing base | |
130 | value greater than limit to the bridge's base/limit registers. | |
131 | ||
132 | Note: care must be taken when updating I/O base/limit registers | |
133 | of bridges which support 32-bit I/O. This update requires two | |
134 | config space writes, so it's quite possible that an I/O window of | |
135 | the bridge will have some undesirable address (e.g. 0) after the | |
136 | first write. Ditto 64-bit prefetchable MMIO. */ | |
a391f197 | 137 | static void pci_setup_bridge(struct pci_bus *bus) |
1da177e4 LT |
138 | { |
139 | struct pci_dev *bridge = bus->self; | |
c7dabef8 | 140 | struct resource *res; |
1da177e4 | 141 | struct pci_bus_region region; |
c40a22e0 | 142 | u32 l, bu, lu, io_upper16; |
1f82de10 | 143 | int pref_mem64; |
1da177e4 | 144 | |
296ccb08 | 145 | if (pci_is_enabled(bridge)) |
b73e97d9 AC |
146 | return; |
147 | ||
865df576 BH |
148 | dev_info(&bridge->dev, "PCI bridge to [bus %02x-%02x]\n", |
149 | bus->secondary, bus->subordinate); | |
1da177e4 LT |
150 | |
151 | /* Set up the top and bottom of the PCI I/O segment for this bus. */ | |
c7dabef8 BH |
152 | res = bus->resource[0]; |
153 | pcibios_resource_to_bus(bridge, ®ion, res); | |
154 | if (res->flags & IORESOURCE_IO) { | |
1da177e4 LT |
155 | pci_read_config_dword(bridge, PCI_IO_BASE, &l); |
156 | l &= 0xffff0000; | |
157 | l |= (region.start >> 8) & 0x00f0; | |
158 | l |= region.end & 0xf000; | |
159 | /* Set up upper 16 bits of I/O base/limit. */ | |
160 | io_upper16 = (region.end & 0xffff0000) | (region.start >> 16); | |
c7dabef8 | 161 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
1da177e4 LT |
162 | } |
163 | else { | |
164 | /* Clear upper 16 bits of I/O base/limit. */ | |
165 | io_upper16 = 0; | |
166 | l = 0x00f0; | |
c7dabef8 | 167 | dev_info(&bridge->dev, " bridge window [io disabled]\n"); |
1da177e4 LT |
168 | } |
169 | /* Temporarily disable the I/O range before updating PCI_IO_BASE. */ | |
170 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff); | |
171 | /* Update lower 16 bits of I/O base/limit. */ | |
172 | pci_write_config_dword(bridge, PCI_IO_BASE, l); | |
173 | /* Update upper 16 bits of I/O base/limit. */ | |
174 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16); | |
175 | ||
176 | /* Set up the top and bottom of the PCI Memory segment | |
177 | for this bus. */ | |
c7dabef8 BH |
178 | res = bus->resource[1]; |
179 | pcibios_resource_to_bus(bridge, ®ion, res); | |
180 | if (res->flags & IORESOURCE_MEM) { | |
1da177e4 LT |
181 | l = (region.start >> 16) & 0xfff0; |
182 | l |= region.end & 0xfff00000; | |
c7dabef8 | 183 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
1da177e4 LT |
184 | } |
185 | else { | |
186 | l = 0x0000fff0; | |
c7dabef8 | 187 | dev_info(&bridge->dev, " bridge window [mem disabled]\n"); |
1da177e4 LT |
188 | } |
189 | pci_write_config_dword(bridge, PCI_MEMORY_BASE, l); | |
190 | ||
191 | /* Clear out the upper 32 bits of PREF limit. | |
192 | If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily | |
193 | disables PREF range, which is ok. */ | |
194 | pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0); | |
195 | ||
196 | /* Set up PREF base/limit. */ | |
1f82de10 | 197 | pref_mem64 = 0; |
c40a22e0 | 198 | bu = lu = 0; |
c7dabef8 BH |
199 | res = bus->resource[2]; |
200 | pcibios_resource_to_bus(bridge, ®ion, res); | |
201 | if (res->flags & IORESOURCE_PREFETCH) { | |
1da177e4 LT |
202 | l = (region.start >> 16) & 0xfff0; |
203 | l |= region.end & 0xfff00000; | |
c7dabef8 | 204 | if (res->flags & IORESOURCE_MEM_64) { |
1f82de10 YL |
205 | pref_mem64 = 1; |
206 | bu = upper_32_bits(region.start); | |
207 | lu = upper_32_bits(region.end); | |
1f82de10 | 208 | } |
c7dabef8 | 209 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
1da177e4 LT |
210 | } |
211 | else { | |
212 | l = 0x0000fff0; | |
c7dabef8 | 213 | dev_info(&bridge->dev, " bridge window [mem pref disabled]\n"); |
1da177e4 LT |
214 | } |
215 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l); | |
216 | ||
1f82de10 YL |
217 | if (pref_mem64) { |
218 | /* Set the upper 32 bits of PREF base & limit. */ | |
219 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu); | |
220 | pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu); | |
221 | } | |
1da177e4 LT |
222 | |
223 | pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl); | |
224 | } | |
225 | ||
226 | /* Check whether the bridge supports optional I/O and | |
227 | prefetchable memory ranges. If not, the respective | |
228 | base/limit registers must be read-only and read as 0. */ | |
96bde06a | 229 | static void pci_bridge_check_ranges(struct pci_bus *bus) |
1da177e4 LT |
230 | { |
231 | u16 io; | |
232 | u32 pmem; | |
233 | struct pci_dev *bridge = bus->self; | |
234 | struct resource *b_res; | |
235 | ||
236 | b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; | |
237 | b_res[1].flags |= IORESOURCE_MEM; | |
238 | ||
239 | pci_read_config_word(bridge, PCI_IO_BASE, &io); | |
240 | if (!io) { | |
241 | pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0); | |
242 | pci_read_config_word(bridge, PCI_IO_BASE, &io); | |
243 | pci_write_config_word(bridge, PCI_IO_BASE, 0x0); | |
244 | } | |
245 | if (io) | |
246 | b_res[0].flags |= IORESOURCE_IO; | |
247 | /* DECchip 21050 pass 2 errata: the bridge may miss an address | |
248 | disconnect boundary by one PCI data phase. | |
249 | Workaround: do not use prefetching on this device. */ | |
250 | if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) | |
251 | return; | |
252 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); | |
253 | if (!pmem) { | |
254 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, | |
255 | 0xfff0fff0); | |
256 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); | |
257 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); | |
258 | } | |
1f82de10 | 259 | if (pmem) { |
1da177e4 | 260 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; |
1f82de10 YL |
261 | if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) |
262 | b_res[2].flags |= IORESOURCE_MEM_64; | |
263 | } | |
264 | ||
265 | /* double check if bridge does support 64 bit pref */ | |
266 | if (b_res[2].flags & IORESOURCE_MEM_64) { | |
267 | u32 mem_base_hi, tmp; | |
268 | pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
269 | &mem_base_hi); | |
270 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
271 | 0xffffffff); | |
272 | pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp); | |
273 | if (!tmp) | |
274 | b_res[2].flags &= ~IORESOURCE_MEM_64; | |
275 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
276 | mem_base_hi); | |
277 | } | |
1da177e4 LT |
278 | } |
279 | ||
280 | /* Helper function for sizing routines: find first available | |
281 | bus resource of a given type. Note: we intentionally skip | |
282 | the bus resources which have already been assigned (that is, | |
283 | have non-NULL parent resource). */ | |
96bde06a | 284 | static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type) |
1da177e4 LT |
285 | { |
286 | int i; | |
287 | struct resource *r; | |
288 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | | |
289 | IORESOURCE_PREFETCH; | |
290 | ||
291 | for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) { | |
292 | r = bus->resource[i]; | |
299de034 IK |
293 | if (r == &ioport_resource || r == &iomem_resource) |
294 | continue; | |
55a10984 JB |
295 | if (r && (r->flags & type_mask) == type && !r->parent) |
296 | return r; | |
1da177e4 LT |
297 | } |
298 | return NULL; | |
299 | } | |
300 | ||
301 | /* Sizing the IO windows of the PCI-PCI bridge is trivial, | |
302 | since these windows have 4K granularity and the IO ranges | |
303 | of non-bridge PCI devices are limited to 256 bytes. | |
304 | We must be careful with the ISA aliasing though. */ | |
28760489 | 305 | static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size) |
1da177e4 LT |
306 | { |
307 | struct pci_dev *dev; | |
308 | struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO); | |
309 | unsigned long size = 0, size1 = 0; | |
310 | ||
311 | if (!b_res) | |
312 | return; | |
313 | ||
314 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
315 | int i; | |
316 | ||
317 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
318 | struct resource *r = &dev->resource[i]; | |
319 | unsigned long r_size; | |
320 | ||
321 | if (r->parent || !(r->flags & IORESOURCE_IO)) | |
322 | continue; | |
022edd86 | 323 | r_size = resource_size(r); |
1da177e4 LT |
324 | |
325 | if (r_size < 0x400) | |
326 | /* Might be re-aligned for ISA */ | |
327 | size += r_size; | |
328 | else | |
329 | size1 += r_size; | |
330 | } | |
331 | } | |
28760489 EB |
332 | if (size < min_size) |
333 | size = min_size; | |
1da177e4 LT |
334 | /* To be fixed in 2.5: we should have sort of HAVE_ISA |
335 | flag in the struct pci_bus. */ | |
336 | #if defined(CONFIG_ISA) || defined(CONFIG_EISA) | |
337 | size = (size & 0xff) + ((size & ~0xffUL) << 2); | |
338 | #endif | |
6f6f8c2f | 339 | size = ALIGN(size + size1, 4096); |
1da177e4 | 340 | if (!size) { |
865df576 BH |
341 | if (b_res->start || b_res->end) |
342 | dev_info(&bus->self->dev, "disabling bridge window " | |
343 | "%pR to [bus %02x-%02x] (unused)\n", b_res, | |
344 | bus->secondary, bus->subordinate); | |
1da177e4 LT |
345 | b_res->flags = 0; |
346 | return; | |
347 | } | |
348 | /* Alignment of the IO window is always 4K */ | |
349 | b_res->start = 4096; | |
350 | b_res->end = b_res->start + size - 1; | |
88452565 | 351 | b_res->flags |= IORESOURCE_STARTALIGN; |
1da177e4 LT |
352 | } |
353 | ||
354 | /* Calculate the size of the bus and minimal alignment which | |
355 | guarantees that all child resources fit in this size. */ | |
28760489 EB |
356 | static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, |
357 | unsigned long type, resource_size_t min_size) | |
1da177e4 LT |
358 | { |
359 | struct pci_dev *dev; | |
c40a22e0 BH |
360 | resource_size_t min_align, align, size; |
361 | resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */ | |
1da177e4 LT |
362 | int order, max_order; |
363 | struct resource *b_res = find_free_bus_resource(bus, type); | |
1f82de10 | 364 | unsigned int mem64_mask = 0; |
1da177e4 LT |
365 | |
366 | if (!b_res) | |
367 | return 0; | |
368 | ||
369 | memset(aligns, 0, sizeof(aligns)); | |
370 | max_order = 0; | |
371 | size = 0; | |
372 | ||
1f82de10 YL |
373 | mem64_mask = b_res->flags & IORESOURCE_MEM_64; |
374 | b_res->flags &= ~IORESOURCE_MEM_64; | |
375 | ||
1da177e4 LT |
376 | list_for_each_entry(dev, &bus->devices, bus_list) { |
377 | int i; | |
1f82de10 | 378 | |
1da177e4 LT |
379 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { |
380 | struct resource *r = &dev->resource[i]; | |
c40a22e0 | 381 | resource_size_t r_size; |
1da177e4 LT |
382 | |
383 | if (r->parent || (r->flags & mask) != type) | |
384 | continue; | |
022edd86 | 385 | r_size = resource_size(r); |
1da177e4 | 386 | /* For bridges size != alignment */ |
6faf17f6 | 387 | align = pci_resource_alignment(dev, r); |
1da177e4 LT |
388 | order = __ffs(align) - 20; |
389 | if (order > 11) { | |
865df576 BH |
390 | dev_warn(&dev->dev, "disabling BAR %d: %pR " |
391 | "(bad alignment %#llx)\n", i, r, | |
392 | (unsigned long long) align); | |
1da177e4 LT |
393 | r->flags = 0; |
394 | continue; | |
395 | } | |
396 | size += r_size; | |
397 | if (order < 0) | |
398 | order = 0; | |
399 | /* Exclude ranges with size > align from | |
400 | calculation of the alignment. */ | |
401 | if (r_size == align) | |
402 | aligns[order] += align; | |
403 | if (order > max_order) | |
404 | max_order = order; | |
1f82de10 | 405 | mem64_mask &= r->flags & IORESOURCE_MEM_64; |
1da177e4 LT |
406 | } |
407 | } | |
28760489 EB |
408 | if (size < min_size) |
409 | size = min_size; | |
1da177e4 LT |
410 | |
411 | align = 0; | |
412 | min_align = 0; | |
413 | for (order = 0; order <= max_order; order++) { | |
8308c54d JF |
414 | resource_size_t align1 = 1; |
415 | ||
416 | align1 <<= (order + 20); | |
417 | ||
1da177e4 LT |
418 | if (!align) |
419 | min_align = align1; | |
6f6f8c2f | 420 | else if (ALIGN(align + min_align, min_align) < align1) |
1da177e4 LT |
421 | min_align = align1 >> 1; |
422 | align += aligns[order]; | |
423 | } | |
6f6f8c2f | 424 | size = ALIGN(size, min_align); |
1da177e4 | 425 | if (!size) { |
865df576 BH |
426 | if (b_res->start || b_res->end) |
427 | dev_info(&bus->self->dev, "disabling bridge window " | |
428 | "%pR to [bus %02x-%02x] (unused)\n", b_res, | |
429 | bus->secondary, bus->subordinate); | |
1da177e4 LT |
430 | b_res->flags = 0; |
431 | return 1; | |
432 | } | |
433 | b_res->start = min_align; | |
434 | b_res->end = size + min_align - 1; | |
88452565 | 435 | b_res->flags |= IORESOURCE_STARTALIGN; |
1f82de10 | 436 | b_res->flags |= mem64_mask; |
1da177e4 LT |
437 | return 1; |
438 | } | |
439 | ||
5468ae61 | 440 | static void pci_bus_size_cardbus(struct pci_bus *bus) |
1da177e4 LT |
441 | { |
442 | struct pci_dev *bridge = bus->self; | |
443 | struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; | |
444 | u16 ctrl; | |
445 | ||
446 | /* | |
447 | * Reserve some resources for CardBus. We reserve | |
448 | * a fixed amount of bus space for CardBus bridges. | |
449 | */ | |
934b7024 LT |
450 | b_res[0].start = 0; |
451 | b_res[0].end = pci_cardbus_io_size - 1; | |
452 | b_res[0].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN; | |
1da177e4 | 453 | |
934b7024 LT |
454 | b_res[1].start = 0; |
455 | b_res[1].end = pci_cardbus_io_size - 1; | |
456 | b_res[1].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN; | |
1da177e4 LT |
457 | |
458 | /* | |
459 | * Check whether prefetchable memory is supported | |
460 | * by this bridge. | |
461 | */ | |
462 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
463 | if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) { | |
464 | ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; | |
465 | pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); | |
466 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
467 | } | |
468 | ||
469 | /* | |
470 | * If we have prefetchable memory support, allocate | |
471 | * two regions. Otherwise, allocate one region of | |
472 | * twice the size. | |
473 | */ | |
474 | if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) { | |
934b7024 LT |
475 | b_res[2].start = 0; |
476 | b_res[2].end = pci_cardbus_mem_size - 1; | |
477 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_SIZEALIGN; | |
1da177e4 | 478 | |
934b7024 LT |
479 | b_res[3].start = 0; |
480 | b_res[3].end = pci_cardbus_mem_size - 1; | |
481 | b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN; | |
1da177e4 | 482 | } else { |
934b7024 LT |
483 | b_res[3].start = 0; |
484 | b_res[3].end = pci_cardbus_mem_size * 2 - 1; | |
485 | b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN; | |
1da177e4 LT |
486 | } |
487 | } | |
488 | ||
451124a7 | 489 | void __ref pci_bus_size_bridges(struct pci_bus *bus) |
1da177e4 LT |
490 | { |
491 | struct pci_dev *dev; | |
492 | unsigned long mask, prefmask; | |
28760489 | 493 | resource_size_t min_mem_size = 0, min_io_size = 0; |
1da177e4 LT |
494 | |
495 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
496 | struct pci_bus *b = dev->subordinate; | |
497 | if (!b) | |
498 | continue; | |
499 | ||
500 | switch (dev->class >> 8) { | |
501 | case PCI_CLASS_BRIDGE_CARDBUS: | |
502 | pci_bus_size_cardbus(b); | |
503 | break; | |
504 | ||
505 | case PCI_CLASS_BRIDGE_PCI: | |
506 | default: | |
507 | pci_bus_size_bridges(b); | |
508 | break; | |
509 | } | |
510 | } | |
511 | ||
512 | /* The root bus? */ | |
513 | if (!bus->self) | |
514 | return; | |
515 | ||
516 | switch (bus->self->class >> 8) { | |
517 | case PCI_CLASS_BRIDGE_CARDBUS: | |
518 | /* don't size cardbuses yet. */ | |
519 | break; | |
520 | ||
521 | case PCI_CLASS_BRIDGE_PCI: | |
522 | pci_bridge_check_ranges(bus); | |
28760489 EB |
523 | if (bus->self->is_hotplug_bridge) { |
524 | min_io_size = pci_hotplug_io_size; | |
525 | min_mem_size = pci_hotplug_mem_size; | |
526 | } | |
1da177e4 | 527 | default: |
28760489 | 528 | pbus_size_io(bus, min_io_size); |
1da177e4 LT |
529 | /* If the bridge supports prefetchable range, size it |
530 | separately. If it doesn't, or its prefetchable window | |
531 | has already been allocated by arch code, try | |
532 | non-prefetchable range for both types of PCI memory | |
533 | resources. */ | |
534 | mask = IORESOURCE_MEM; | |
535 | prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
28760489 | 536 | if (pbus_size_mem(bus, prefmask, prefmask, min_mem_size)) |
1da177e4 | 537 | mask = prefmask; /* Success, size non-prefetch only. */ |
28760489 EB |
538 | else |
539 | min_mem_size += min_mem_size; | |
540 | pbus_size_mem(bus, mask, IORESOURCE_MEM, min_mem_size); | |
1da177e4 LT |
541 | break; |
542 | } | |
543 | } | |
544 | EXPORT_SYMBOL(pci_bus_size_bridges); | |
545 | ||
ea741551 | 546 | void __ref pci_bus_assign_resources(const struct pci_bus *bus) |
1da177e4 LT |
547 | { |
548 | struct pci_bus *b; | |
549 | struct pci_dev *dev; | |
550 | ||
551 | pbus_assign_resources_sorted(bus); | |
552 | ||
1da177e4 LT |
553 | list_for_each_entry(dev, &bus->devices, bus_list) { |
554 | b = dev->subordinate; | |
555 | if (!b) | |
556 | continue; | |
557 | ||
558 | pci_bus_assign_resources(b); | |
559 | ||
560 | switch (dev->class >> 8) { | |
561 | case PCI_CLASS_BRIDGE_PCI: | |
562 | pci_setup_bridge(b); | |
563 | break; | |
564 | ||
565 | case PCI_CLASS_BRIDGE_CARDBUS: | |
566 | pci_setup_cardbus(b); | |
567 | break; | |
568 | ||
569 | default: | |
80ccba11 BH |
570 | dev_info(&dev->dev, "not setting up bridge for bus " |
571 | "%04x:%02x\n", pci_domain_nr(b), b->number); | |
1da177e4 LT |
572 | break; |
573 | } | |
574 | } | |
575 | } | |
576 | EXPORT_SYMBOL(pci_bus_assign_resources); | |
577 | ||
76fbc263 YL |
578 | static void pci_bus_dump_res(struct pci_bus *bus) |
579 | { | |
580 | int i; | |
581 | ||
582 | for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) { | |
583 | struct resource *res = bus->resource[i]; | |
681bf597 | 584 | if (!res || !res->end) |
76fbc263 YL |
585 | continue; |
586 | ||
c7dabef8 | 587 | dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res); |
76fbc263 YL |
588 | } |
589 | } | |
590 | ||
591 | static void pci_bus_dump_resources(struct pci_bus *bus) | |
592 | { | |
593 | struct pci_bus *b; | |
594 | struct pci_dev *dev; | |
595 | ||
596 | ||
597 | pci_bus_dump_res(bus); | |
598 | ||
599 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
600 | b = dev->subordinate; | |
601 | if (!b) | |
602 | continue; | |
603 | ||
604 | pci_bus_dump_resources(b); | |
605 | } | |
606 | } | |
607 | ||
1da177e4 LT |
608 | void __init |
609 | pci_assign_unassigned_resources(void) | |
610 | { | |
611 | struct pci_bus *bus; | |
612 | ||
613 | /* Depth first, calculate sizes and alignments of all | |
614 | subordinate buses. */ | |
615 | list_for_each_entry(bus, &pci_root_buses, node) { | |
616 | pci_bus_size_bridges(bus); | |
617 | } | |
618 | /* Depth last, allocate resources and update the hardware. */ | |
619 | list_for_each_entry(bus, &pci_root_buses, node) { | |
620 | pci_bus_assign_resources(bus); | |
621 | pci_enable_bridges(bus); | |
622 | } | |
76fbc263 YL |
623 | |
624 | /* dump the resource on buses */ | |
625 | list_for_each_entry(bus, &pci_root_buses, node) { | |
626 | pci_bus_dump_resources(bus); | |
627 | } | |
1da177e4 | 628 | } |