]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * drivers/pci/setup-bus.c | |
3 | * | |
4 | * Extruded from code written by | |
5 | * Dave Rusling (david.rusling@reo.mts.dec.com) | |
6 | * David Mosberger (davidm@cs.arizona.edu) | |
7 | * David Miller (davem@redhat.com) | |
8 | * | |
9 | * Support routines for initializing a PCI subsystem. | |
10 | */ | |
11 | ||
12 | /* | |
13 | * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> | |
14 | * PCI-PCI bridges cleanup, sorted resource allocation. | |
15 | * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru> | |
16 | * Converted to allocation in 3 passes, which gives | |
17 | * tighter packing. Prefetchable range support. | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/pci.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/ioport.h> | |
26 | #include <linux/cache.h> | |
27 | #include <linux/slab.h> | |
6faf17f6 | 28 | #include "pci.h" |
1da177e4 | 29 | |
bdc4abec YL |
30 | struct pci_dev_resource { |
31 | struct list_head list; | |
2934a0de YL |
32 | struct resource *res; |
33 | struct pci_dev *dev; | |
568ddef8 YL |
34 | resource_size_t start; |
35 | resource_size_t end; | |
c8adf9a3 | 36 | resource_size_t add_size; |
2bbc6942 | 37 | resource_size_t min_align; |
568ddef8 YL |
38 | unsigned long flags; |
39 | }; | |
40 | ||
bffc56d4 YL |
41 | static void free_list(struct list_head *head) |
42 | { | |
43 | struct pci_dev_resource *dev_res, *tmp; | |
44 | ||
45 | list_for_each_entry_safe(dev_res, tmp, head, list) { | |
46 | list_del(&dev_res->list); | |
47 | kfree(dev_res); | |
48 | } | |
49 | } | |
094732a5 | 50 | |
f483d392 RP |
51 | int pci_realloc_enable = 0; |
52 | #define pci_realloc_enabled() pci_realloc_enable | |
53 | void pci_realloc(void) | |
54 | { | |
55 | pci_realloc_enable = 1; | |
56 | } | |
57 | ||
c8adf9a3 RP |
58 | /** |
59 | * add_to_list() - add a new resource tracker to the list | |
60 | * @head: Head of the list | |
61 | * @dev: device corresponding to which the resource | |
62 | * belongs | |
63 | * @res: The resource to be tracked | |
64 | * @add_size: additional size to be optionally added | |
65 | * to the resource | |
66 | */ | |
bdc4abec | 67 | static int add_to_list(struct list_head *head, |
c8adf9a3 | 68 | struct pci_dev *dev, struct resource *res, |
2bbc6942 | 69 | resource_size_t add_size, resource_size_t min_align) |
568ddef8 | 70 | { |
764242a0 | 71 | struct pci_dev_resource *tmp; |
568ddef8 | 72 | |
bdc4abec | 73 | tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); |
568ddef8 | 74 | if (!tmp) { |
c8adf9a3 | 75 | pr_warning("add_to_list: kmalloc() failed!\n"); |
ef62dfef | 76 | return -ENOMEM; |
568ddef8 YL |
77 | } |
78 | ||
568ddef8 YL |
79 | tmp->res = res; |
80 | tmp->dev = dev; | |
81 | tmp->start = res->start; | |
82 | tmp->end = res->end; | |
83 | tmp->flags = res->flags; | |
c8adf9a3 | 84 | tmp->add_size = add_size; |
2bbc6942 | 85 | tmp->min_align = min_align; |
bdc4abec YL |
86 | |
87 | list_add(&tmp->list, head); | |
ef62dfef YL |
88 | |
89 | return 0; | |
568ddef8 YL |
90 | } |
91 | ||
b9b0bba9 | 92 | static void remove_from_list(struct list_head *head, |
3e6e0d80 YL |
93 | struct resource *res) |
94 | { | |
b9b0bba9 | 95 | struct pci_dev_resource *dev_res, *tmp; |
3e6e0d80 | 96 | |
b9b0bba9 YL |
97 | list_for_each_entry_safe(dev_res, tmp, head, list) { |
98 | if (dev_res->res == res) { | |
99 | list_del(&dev_res->list); | |
100 | kfree(dev_res); | |
bdc4abec | 101 | break; |
3e6e0d80 | 102 | } |
3e6e0d80 YL |
103 | } |
104 | } | |
105 | ||
b9b0bba9 | 106 | static resource_size_t get_res_add_size(struct list_head *head, |
1c372353 YL |
107 | struct resource *res) |
108 | { | |
b9b0bba9 | 109 | struct pci_dev_resource *dev_res; |
bdc4abec | 110 | |
b9b0bba9 YL |
111 | list_for_each_entry(dev_res, head, list) { |
112 | if (dev_res->res == res) { | |
b592443d YL |
113 | int idx = res - &dev_res->dev->resource[0]; |
114 | ||
b9b0bba9 | 115 | dev_printk(KERN_DEBUG, &dev_res->dev->dev, |
b592443d YL |
116 | "res[%d]=%pR get_res_add_size add_size %llx\n", |
117 | idx, dev_res->res, | |
b9b0bba9 | 118 | (unsigned long long)dev_res->add_size); |
b592443d | 119 | |
b9b0bba9 | 120 | return dev_res->add_size; |
bdc4abec | 121 | } |
3e6e0d80 | 122 | } |
1c372353 YL |
123 | |
124 | return 0; | |
125 | } | |
126 | ||
78c3b329 | 127 | /* Sort resources by alignment */ |
bdc4abec | 128 | static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head) |
78c3b329 YL |
129 | { |
130 | int i; | |
131 | ||
132 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
133 | struct resource *r; | |
bdc4abec | 134 | struct pci_dev_resource *dev_res, *tmp; |
78c3b329 | 135 | resource_size_t r_align; |
bdc4abec | 136 | struct list_head *n; |
78c3b329 YL |
137 | |
138 | r = &dev->resource[i]; | |
139 | ||
140 | if (r->flags & IORESOURCE_PCI_FIXED) | |
141 | continue; | |
142 | ||
143 | if (!(r->flags) || r->parent) | |
144 | continue; | |
145 | ||
146 | r_align = pci_resource_alignment(dev, r); | |
147 | if (!r_align) { | |
148 | dev_warn(&dev->dev, "BAR %d: %pR has bogus alignment\n", | |
149 | i, r); | |
150 | continue; | |
151 | } | |
78c3b329 | 152 | |
bdc4abec YL |
153 | tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); |
154 | if (!tmp) | |
155 | panic("pdev_sort_resources(): " | |
156 | "kmalloc() failed!\n"); | |
157 | tmp->res = r; | |
158 | tmp->dev = dev; | |
159 | ||
160 | /* fallback is smallest one or list is empty*/ | |
161 | n = head; | |
162 | list_for_each_entry(dev_res, head, list) { | |
163 | resource_size_t align; | |
164 | ||
165 | align = pci_resource_alignment(dev_res->dev, | |
166 | dev_res->res); | |
78c3b329 YL |
167 | |
168 | if (r_align > align) { | |
bdc4abec | 169 | n = &dev_res->list; |
78c3b329 YL |
170 | break; |
171 | } | |
172 | } | |
bdc4abec YL |
173 | /* Insert it just before n*/ |
174 | list_add_tail(&tmp->list, n); | |
78c3b329 YL |
175 | } |
176 | } | |
177 | ||
6841ec68 | 178 | static void __dev_sort_resources(struct pci_dev *dev, |
bdc4abec | 179 | struct list_head *head) |
1da177e4 | 180 | { |
6841ec68 | 181 | u16 class = dev->class >> 8; |
1da177e4 | 182 | |
6841ec68 YL |
183 | /* Don't touch classless devices or host bridges or ioapics. */ |
184 | if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST) | |
185 | return; | |
1da177e4 | 186 | |
6841ec68 YL |
187 | /* Don't touch ioapic devices already enabled by firmware */ |
188 | if (class == PCI_CLASS_SYSTEM_PIC) { | |
189 | u16 command; | |
190 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
191 | if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | |
192 | return; | |
193 | } | |
1da177e4 | 194 | |
6841ec68 YL |
195 | pdev_sort_resources(dev, head); |
196 | } | |
23186279 | 197 | |
fc075e1d RP |
198 | static inline void reset_resource(struct resource *res) |
199 | { | |
200 | res->start = 0; | |
201 | res->end = 0; | |
202 | res->flags = 0; | |
203 | } | |
204 | ||
c8adf9a3 | 205 | /** |
9e8bf93a | 206 | * reassign_resources_sorted() - satisfy any additional resource requests |
c8adf9a3 | 207 | * |
9e8bf93a | 208 | * @realloc_head : head of the list tracking requests requiring additional |
c8adf9a3 RP |
209 | * resources |
210 | * @head : head of the list tracking requests with allocated | |
211 | * resources | |
212 | * | |
9e8bf93a | 213 | * Walk through each element of the realloc_head and try to procure |
c8adf9a3 RP |
214 | * additional resources for the element, provided the element |
215 | * is in the head list. | |
216 | */ | |
bdc4abec YL |
217 | static void reassign_resources_sorted(struct list_head *realloc_head, |
218 | struct list_head *head) | |
6841ec68 YL |
219 | { |
220 | struct resource *res; | |
b9b0bba9 | 221 | struct pci_dev_resource *add_res, *tmp; |
bdc4abec | 222 | struct pci_dev_resource *dev_res; |
c8adf9a3 | 223 | resource_size_t add_size; |
6841ec68 | 224 | int idx; |
1da177e4 | 225 | |
b9b0bba9 | 226 | list_for_each_entry_safe(add_res, tmp, realloc_head, list) { |
bdc4abec YL |
227 | bool found_match = false; |
228 | ||
b9b0bba9 | 229 | res = add_res->res; |
c8adf9a3 RP |
230 | /* skip resource that has been reset */ |
231 | if (!res->flags) | |
232 | goto out; | |
233 | ||
234 | /* skip this resource if not found in head list */ | |
bdc4abec YL |
235 | list_for_each_entry(dev_res, head, list) { |
236 | if (dev_res->res == res) { | |
237 | found_match = true; | |
238 | break; | |
239 | } | |
c8adf9a3 | 240 | } |
bdc4abec YL |
241 | if (!found_match)/* just skip */ |
242 | continue; | |
c8adf9a3 | 243 | |
b9b0bba9 YL |
244 | idx = res - &add_res->dev->resource[0]; |
245 | add_size = add_res->add_size; | |
2bbc6942 | 246 | if (!resource_size(res)) { |
b9b0bba9 | 247 | res->start = add_res->start; |
2bbc6942 | 248 | res->end = res->start + add_size - 1; |
b9b0bba9 | 249 | if (pci_assign_resource(add_res->dev, idx)) |
c8adf9a3 | 250 | reset_resource(res); |
2bbc6942 | 251 | } else { |
b9b0bba9 YL |
252 | resource_size_t align = add_res->min_align; |
253 | res->flags |= add_res->flags & | |
bdc4abec | 254 | (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN); |
b9b0bba9 | 255 | if (pci_reassign_resource(add_res->dev, idx, |
bdc4abec | 256 | add_size, align)) |
b9b0bba9 | 257 | dev_printk(KERN_DEBUG, &add_res->dev->dev, |
b592443d YL |
258 | "failed to add %llx res[%d]=%pR\n", |
259 | (unsigned long long)add_size, | |
260 | idx, res); | |
c8adf9a3 RP |
261 | } |
262 | out: | |
b9b0bba9 YL |
263 | list_del(&add_res->list); |
264 | kfree(add_res); | |
c8adf9a3 RP |
265 | } |
266 | } | |
267 | ||
268 | /** | |
269 | * assign_requested_resources_sorted() - satisfy resource requests | |
270 | * | |
271 | * @head : head of the list tracking requests for resources | |
272 | * @failed_list : head of the list tracking requests that could | |
273 | * not be allocated | |
274 | * | |
275 | * Satisfy resource requests of each element in the list. Add | |
276 | * requests that could not satisfied to the failed_list. | |
277 | */ | |
bdc4abec YL |
278 | static void assign_requested_resources_sorted(struct list_head *head, |
279 | struct list_head *fail_head) | |
c8adf9a3 RP |
280 | { |
281 | struct resource *res; | |
bdc4abec | 282 | struct pci_dev_resource *dev_res; |
c8adf9a3 | 283 | int idx; |
9a928660 | 284 | |
bdc4abec YL |
285 | list_for_each_entry(dev_res, head, list) { |
286 | res = dev_res->res; | |
287 | idx = res - &dev_res->dev->resource[0]; | |
288 | if (resource_size(res) && | |
289 | pci_assign_resource(dev_res->dev, idx)) { | |
290 | if (fail_head && !pci_is_root_bus(dev_res->dev->bus)) { | |
9a928660 YL |
291 | /* |
292 | * if the failed res is for ROM BAR, and it will | |
293 | * be enabled later, don't add it to the list | |
294 | */ | |
295 | if (!((idx == PCI_ROM_RESOURCE) && | |
296 | (!(res->flags & IORESOURCE_ROM_ENABLE)))) | |
67cc7e26 YL |
297 | add_to_list(fail_head, |
298 | dev_res->dev, res, | |
299 | 0 /* dont care */, | |
300 | 0 /* dont care */); | |
9a928660 | 301 | } |
fc075e1d | 302 | reset_resource(res); |
542df5de | 303 | } |
1da177e4 LT |
304 | } |
305 | } | |
306 | ||
bdc4abec YL |
307 | static void __assign_resources_sorted(struct list_head *head, |
308 | struct list_head *realloc_head, | |
309 | struct list_head *fail_head) | |
c8adf9a3 | 310 | { |
3e6e0d80 YL |
311 | /* |
312 | * Should not assign requested resources at first. | |
313 | * they could be adjacent, so later reassign can not reallocate | |
314 | * them one by one in parent resource window. | |
315 | * Try to assign requested + add_size at begining | |
316 | * if could do that, could get out early. | |
317 | * if could not do that, we still try to assign requested at first, | |
318 | * then try to reassign add_size for some resources. | |
319 | */ | |
bdc4abec YL |
320 | LIST_HEAD(save_head); |
321 | LIST_HEAD(local_fail_head); | |
b9b0bba9 | 322 | struct pci_dev_resource *save_res; |
bdc4abec | 323 | struct pci_dev_resource *dev_res; |
3e6e0d80 YL |
324 | |
325 | /* Check if optional add_size is there */ | |
bdc4abec | 326 | if (!realloc_head || list_empty(realloc_head)) |
3e6e0d80 YL |
327 | goto requested_and_reassign; |
328 | ||
329 | /* Save original start, end, flags etc at first */ | |
bdc4abec YL |
330 | list_for_each_entry(dev_res, head, list) { |
331 | if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) { | |
bffc56d4 | 332 | free_list(&save_head); |
3e6e0d80 YL |
333 | goto requested_and_reassign; |
334 | } | |
bdc4abec | 335 | } |
3e6e0d80 YL |
336 | |
337 | /* Update res in head list with add_size in realloc_head list */ | |
bdc4abec YL |
338 | list_for_each_entry(dev_res, head, list) |
339 | dev_res->res->end += get_res_add_size(realloc_head, | |
340 | dev_res->res); | |
3e6e0d80 YL |
341 | |
342 | /* Try updated head list with add_size added */ | |
3e6e0d80 YL |
343 | assign_requested_resources_sorted(head, &local_fail_head); |
344 | ||
345 | /* all assigned with add_size ? */ | |
bdc4abec | 346 | if (list_empty(&local_fail_head)) { |
3e6e0d80 | 347 | /* Remove head list from realloc_head list */ |
bdc4abec YL |
348 | list_for_each_entry(dev_res, head, list) |
349 | remove_from_list(realloc_head, dev_res->res); | |
bffc56d4 YL |
350 | free_list(&save_head); |
351 | free_list(head); | |
3e6e0d80 YL |
352 | return; |
353 | } | |
354 | ||
bffc56d4 | 355 | free_list(&local_fail_head); |
3e6e0d80 | 356 | /* Release assigned resource */ |
bdc4abec YL |
357 | list_for_each_entry(dev_res, head, list) |
358 | if (dev_res->res->parent) | |
359 | release_resource(dev_res->res); | |
3e6e0d80 | 360 | /* Restore start/end/flags from saved list */ |
b9b0bba9 YL |
361 | list_for_each_entry(save_res, &save_head, list) { |
362 | struct resource *res = save_res->res; | |
3e6e0d80 | 363 | |
b9b0bba9 YL |
364 | res->start = save_res->start; |
365 | res->end = save_res->end; | |
366 | res->flags = save_res->flags; | |
3e6e0d80 | 367 | } |
bffc56d4 | 368 | free_list(&save_head); |
3e6e0d80 YL |
369 | |
370 | requested_and_reassign: | |
c8adf9a3 RP |
371 | /* Satisfy the must-have resource requests */ |
372 | assign_requested_resources_sorted(head, fail_head); | |
373 | ||
0a2daa1c | 374 | /* Try to satisfy any additional optional resource |
c8adf9a3 | 375 | requests */ |
9e8bf93a RP |
376 | if (realloc_head) |
377 | reassign_resources_sorted(realloc_head, head); | |
bffc56d4 | 378 | free_list(head); |
c8adf9a3 RP |
379 | } |
380 | ||
6841ec68 | 381 | static void pdev_assign_resources_sorted(struct pci_dev *dev, |
bdc4abec YL |
382 | struct list_head *add_head, |
383 | struct list_head *fail_head) | |
6841ec68 | 384 | { |
bdc4abec | 385 | LIST_HEAD(head); |
6841ec68 | 386 | |
6841ec68 | 387 | __dev_sort_resources(dev, &head); |
8424d759 | 388 | __assign_resources_sorted(&head, add_head, fail_head); |
6841ec68 YL |
389 | |
390 | } | |
391 | ||
392 | static void pbus_assign_resources_sorted(const struct pci_bus *bus, | |
bdc4abec YL |
393 | struct list_head *realloc_head, |
394 | struct list_head *fail_head) | |
6841ec68 YL |
395 | { |
396 | struct pci_dev *dev; | |
bdc4abec | 397 | LIST_HEAD(head); |
6841ec68 | 398 | |
6841ec68 YL |
399 | list_for_each_entry(dev, &bus->devices, bus_list) |
400 | __dev_sort_resources(dev, &head); | |
401 | ||
9e8bf93a | 402 | __assign_resources_sorted(&head, realloc_head, fail_head); |
6841ec68 YL |
403 | } |
404 | ||
b3743fa4 | 405 | void pci_setup_cardbus(struct pci_bus *bus) |
1da177e4 LT |
406 | { |
407 | struct pci_dev *bridge = bus->self; | |
c7dabef8 | 408 | struct resource *res; |
1da177e4 LT |
409 | struct pci_bus_region region; |
410 | ||
865df576 BH |
411 | dev_info(&bridge->dev, "CardBus bridge to [bus %02x-%02x]\n", |
412 | bus->secondary, bus->subordinate); | |
1da177e4 | 413 | |
c7dabef8 BH |
414 | res = bus->resource[0]; |
415 | pcibios_resource_to_bus(bridge, ®ion, res); | |
416 | if (res->flags & IORESOURCE_IO) { | |
1da177e4 LT |
417 | /* |
418 | * The IO resource is allocated a range twice as large as it | |
419 | * would normally need. This allows us to set both IO regs. | |
420 | */ | |
c7dabef8 | 421 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
1da177e4 LT |
422 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, |
423 | region.start); | |
424 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0, | |
425 | region.end); | |
426 | } | |
427 | ||
c7dabef8 BH |
428 | res = bus->resource[1]; |
429 | pcibios_resource_to_bus(bridge, ®ion, res); | |
430 | if (res->flags & IORESOURCE_IO) { | |
431 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
432 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, |
433 | region.start); | |
434 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1, | |
435 | region.end); | |
436 | } | |
437 | ||
c7dabef8 BH |
438 | res = bus->resource[2]; |
439 | pcibios_resource_to_bus(bridge, ®ion, res); | |
440 | if (res->flags & IORESOURCE_MEM) { | |
441 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
442 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, |
443 | region.start); | |
444 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0, | |
445 | region.end); | |
446 | } | |
447 | ||
c7dabef8 BH |
448 | res = bus->resource[3]; |
449 | pcibios_resource_to_bus(bridge, ®ion, res); | |
450 | if (res->flags & IORESOURCE_MEM) { | |
451 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
452 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, |
453 | region.start); | |
454 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1, | |
455 | region.end); | |
456 | } | |
457 | } | |
b3743fa4 | 458 | EXPORT_SYMBOL(pci_setup_cardbus); |
1da177e4 LT |
459 | |
460 | /* Initialize bridges with base/limit values we have collected. | |
461 | PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998) | |
462 | requires that if there is no I/O ports or memory behind the | |
463 | bridge, corresponding range must be turned off by writing base | |
464 | value greater than limit to the bridge's base/limit registers. | |
465 | ||
466 | Note: care must be taken when updating I/O base/limit registers | |
467 | of bridges which support 32-bit I/O. This update requires two | |
468 | config space writes, so it's quite possible that an I/O window of | |
469 | the bridge will have some undesirable address (e.g. 0) after the | |
470 | first write. Ditto 64-bit prefetchable MMIO. */ | |
7cc5997d | 471 | static void pci_setup_bridge_io(struct pci_bus *bus) |
1da177e4 LT |
472 | { |
473 | struct pci_dev *bridge = bus->self; | |
c7dabef8 | 474 | struct resource *res; |
1da177e4 | 475 | struct pci_bus_region region; |
7cc5997d | 476 | u32 l, io_upper16; |
1da177e4 LT |
477 | |
478 | /* Set up the top and bottom of the PCI I/O segment for this bus. */ | |
c7dabef8 BH |
479 | res = bus->resource[0]; |
480 | pcibios_resource_to_bus(bridge, ®ion, res); | |
481 | if (res->flags & IORESOURCE_IO) { | |
1da177e4 LT |
482 | pci_read_config_dword(bridge, PCI_IO_BASE, &l); |
483 | l &= 0xffff0000; | |
484 | l |= (region.start >> 8) & 0x00f0; | |
485 | l |= region.end & 0xf000; | |
486 | /* Set up upper 16 bits of I/O base/limit. */ | |
487 | io_upper16 = (region.end & 0xffff0000) | (region.start >> 16); | |
c7dabef8 | 488 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 489 | } else { |
1da177e4 LT |
490 | /* Clear upper 16 bits of I/O base/limit. */ |
491 | io_upper16 = 0; | |
492 | l = 0x00f0; | |
1da177e4 LT |
493 | } |
494 | /* Temporarily disable the I/O range before updating PCI_IO_BASE. */ | |
495 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff); | |
496 | /* Update lower 16 bits of I/O base/limit. */ | |
497 | pci_write_config_dword(bridge, PCI_IO_BASE, l); | |
498 | /* Update upper 16 bits of I/O base/limit. */ | |
499 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16); | |
7cc5997d YL |
500 | } |
501 | ||
502 | static void pci_setup_bridge_mmio(struct pci_bus *bus) | |
503 | { | |
504 | struct pci_dev *bridge = bus->self; | |
505 | struct resource *res; | |
506 | struct pci_bus_region region; | |
507 | u32 l; | |
1da177e4 | 508 | |
7cc5997d | 509 | /* Set up the top and bottom of the PCI Memory segment for this bus. */ |
c7dabef8 BH |
510 | res = bus->resource[1]; |
511 | pcibios_resource_to_bus(bridge, ®ion, res); | |
512 | if (res->flags & IORESOURCE_MEM) { | |
1da177e4 LT |
513 | l = (region.start >> 16) & 0xfff0; |
514 | l |= region.end & 0xfff00000; | |
c7dabef8 | 515 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 516 | } else { |
1da177e4 | 517 | l = 0x0000fff0; |
1da177e4 LT |
518 | } |
519 | pci_write_config_dword(bridge, PCI_MEMORY_BASE, l); | |
7cc5997d YL |
520 | } |
521 | ||
522 | static void pci_setup_bridge_mmio_pref(struct pci_bus *bus) | |
523 | { | |
524 | struct pci_dev *bridge = bus->self; | |
525 | struct resource *res; | |
526 | struct pci_bus_region region; | |
527 | u32 l, bu, lu; | |
1da177e4 LT |
528 | |
529 | /* Clear out the upper 32 bits of PREF limit. | |
530 | If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily | |
531 | disables PREF range, which is ok. */ | |
532 | pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0); | |
533 | ||
534 | /* Set up PREF base/limit. */ | |
c40a22e0 | 535 | bu = lu = 0; |
c7dabef8 BH |
536 | res = bus->resource[2]; |
537 | pcibios_resource_to_bus(bridge, ®ion, res); | |
538 | if (res->flags & IORESOURCE_PREFETCH) { | |
1da177e4 LT |
539 | l = (region.start >> 16) & 0xfff0; |
540 | l |= region.end & 0xfff00000; | |
c7dabef8 | 541 | if (res->flags & IORESOURCE_MEM_64) { |
1f82de10 YL |
542 | bu = upper_32_bits(region.start); |
543 | lu = upper_32_bits(region.end); | |
1f82de10 | 544 | } |
c7dabef8 | 545 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 546 | } else { |
1da177e4 | 547 | l = 0x0000fff0; |
1da177e4 LT |
548 | } |
549 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l); | |
550 | ||
59353ea3 AW |
551 | /* Set the upper 32 bits of PREF base & limit. */ |
552 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu); | |
553 | pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu); | |
7cc5997d YL |
554 | } |
555 | ||
556 | static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type) | |
557 | { | |
558 | struct pci_dev *bridge = bus->self; | |
559 | ||
7cc5997d YL |
560 | dev_info(&bridge->dev, "PCI bridge to [bus %02x-%02x]\n", |
561 | bus->secondary, bus->subordinate); | |
562 | ||
563 | if (type & IORESOURCE_IO) | |
564 | pci_setup_bridge_io(bus); | |
565 | ||
566 | if (type & IORESOURCE_MEM) | |
567 | pci_setup_bridge_mmio(bus); | |
568 | ||
569 | if (type & IORESOURCE_PREFETCH) | |
570 | pci_setup_bridge_mmio_pref(bus); | |
1da177e4 LT |
571 | |
572 | pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl); | |
573 | } | |
574 | ||
e2444273 | 575 | void pci_setup_bridge(struct pci_bus *bus) |
7cc5997d YL |
576 | { |
577 | unsigned long type = IORESOURCE_IO | IORESOURCE_MEM | | |
578 | IORESOURCE_PREFETCH; | |
579 | ||
580 | __pci_setup_bridge(bus, type); | |
581 | } | |
582 | ||
1da177e4 LT |
583 | /* Check whether the bridge supports optional I/O and |
584 | prefetchable memory ranges. If not, the respective | |
585 | base/limit registers must be read-only and read as 0. */ | |
96bde06a | 586 | static void pci_bridge_check_ranges(struct pci_bus *bus) |
1da177e4 LT |
587 | { |
588 | u16 io; | |
589 | u32 pmem; | |
590 | struct pci_dev *bridge = bus->self; | |
591 | struct resource *b_res; | |
592 | ||
593 | b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; | |
594 | b_res[1].flags |= IORESOURCE_MEM; | |
595 | ||
596 | pci_read_config_word(bridge, PCI_IO_BASE, &io); | |
597 | if (!io) { | |
598 | pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0); | |
599 | pci_read_config_word(bridge, PCI_IO_BASE, &io); | |
600 | pci_write_config_word(bridge, PCI_IO_BASE, 0x0); | |
601 | } | |
602 | if (io) | |
603 | b_res[0].flags |= IORESOURCE_IO; | |
604 | /* DECchip 21050 pass 2 errata: the bridge may miss an address | |
605 | disconnect boundary by one PCI data phase. | |
606 | Workaround: do not use prefetching on this device. */ | |
607 | if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) | |
608 | return; | |
609 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); | |
610 | if (!pmem) { | |
611 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, | |
612 | 0xfff0fff0); | |
613 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); | |
614 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); | |
615 | } | |
1f82de10 | 616 | if (pmem) { |
1da177e4 | 617 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; |
99586105 YL |
618 | if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == |
619 | PCI_PREF_RANGE_TYPE_64) { | |
1f82de10 | 620 | b_res[2].flags |= IORESOURCE_MEM_64; |
99586105 YL |
621 | b_res[2].flags |= PCI_PREF_RANGE_TYPE_64; |
622 | } | |
1f82de10 YL |
623 | } |
624 | ||
625 | /* double check if bridge does support 64 bit pref */ | |
626 | if (b_res[2].flags & IORESOURCE_MEM_64) { | |
627 | u32 mem_base_hi, tmp; | |
628 | pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
629 | &mem_base_hi); | |
630 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
631 | 0xffffffff); | |
632 | pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp); | |
633 | if (!tmp) | |
634 | b_res[2].flags &= ~IORESOURCE_MEM_64; | |
635 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
636 | mem_base_hi); | |
637 | } | |
1da177e4 LT |
638 | } |
639 | ||
640 | /* Helper function for sizing routines: find first available | |
641 | bus resource of a given type. Note: we intentionally skip | |
642 | the bus resources which have already been assigned (that is, | |
643 | have non-NULL parent resource). */ | |
96bde06a | 644 | static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type) |
1da177e4 LT |
645 | { |
646 | int i; | |
647 | struct resource *r; | |
648 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | | |
649 | IORESOURCE_PREFETCH; | |
650 | ||
89a74ecc | 651 | pci_bus_for_each_resource(bus, r, i) { |
299de034 IK |
652 | if (r == &ioport_resource || r == &iomem_resource) |
653 | continue; | |
55a10984 JB |
654 | if (r && (r->flags & type_mask) == type && !r->parent) |
655 | return r; | |
1da177e4 LT |
656 | } |
657 | return NULL; | |
658 | } | |
659 | ||
13583b16 RP |
660 | static resource_size_t calculate_iosize(resource_size_t size, |
661 | resource_size_t min_size, | |
662 | resource_size_t size1, | |
663 | resource_size_t old_size, | |
664 | resource_size_t align) | |
665 | { | |
666 | if (size < min_size) | |
667 | size = min_size; | |
668 | if (old_size == 1 ) | |
669 | old_size = 0; | |
670 | /* To be fixed in 2.5: we should have sort of HAVE_ISA | |
671 | flag in the struct pci_bus. */ | |
672 | #if defined(CONFIG_ISA) || defined(CONFIG_EISA) | |
673 | size = (size & 0xff) + ((size & ~0xffUL) << 2); | |
674 | #endif | |
675 | size = ALIGN(size + size1, align); | |
676 | if (size < old_size) | |
677 | size = old_size; | |
678 | return size; | |
679 | } | |
680 | ||
681 | static resource_size_t calculate_memsize(resource_size_t size, | |
682 | resource_size_t min_size, | |
683 | resource_size_t size1, | |
684 | resource_size_t old_size, | |
685 | resource_size_t align) | |
686 | { | |
687 | if (size < min_size) | |
688 | size = min_size; | |
689 | if (old_size == 1 ) | |
690 | old_size = 0; | |
691 | if (size < old_size) | |
692 | size = old_size; | |
693 | size = ALIGN(size + size1, align); | |
694 | return size; | |
695 | } | |
696 | ||
c8adf9a3 RP |
697 | /** |
698 | * pbus_size_io() - size the io window of a given bus | |
699 | * | |
700 | * @bus : the bus | |
701 | * @min_size : the minimum io window that must to be allocated | |
702 | * @add_size : additional optional io window | |
9e8bf93a | 703 | * @realloc_head : track the additional io window on this list |
c8adf9a3 RP |
704 | * |
705 | * Sizing the IO windows of the PCI-PCI bridge is trivial, | |
706 | * since these windows have 4K granularity and the IO ranges | |
707 | * of non-bridge PCI devices are limited to 256 bytes. | |
708 | * We must be careful with the ISA aliasing though. | |
709 | */ | |
710 | static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size, | |
bdc4abec | 711 | resource_size_t add_size, struct list_head *realloc_head) |
1da177e4 LT |
712 | { |
713 | struct pci_dev *dev; | |
714 | struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO); | |
c8adf9a3 | 715 | unsigned long size = 0, size0 = 0, size1 = 0; |
be768912 | 716 | resource_size_t children_add_size = 0; |
1da177e4 LT |
717 | |
718 | if (!b_res) | |
719 | return; | |
720 | ||
721 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
722 | int i; | |
723 | ||
724 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
725 | struct resource *r = &dev->resource[i]; | |
726 | unsigned long r_size; | |
727 | ||
728 | if (r->parent || !(r->flags & IORESOURCE_IO)) | |
729 | continue; | |
022edd86 | 730 | r_size = resource_size(r); |
1da177e4 LT |
731 | |
732 | if (r_size < 0x400) | |
733 | /* Might be re-aligned for ISA */ | |
734 | size += r_size; | |
735 | else | |
736 | size1 += r_size; | |
be768912 | 737 | |
9e8bf93a RP |
738 | if (realloc_head) |
739 | children_add_size += get_res_add_size(realloc_head, r); | |
1da177e4 LT |
740 | } |
741 | } | |
c8adf9a3 RP |
742 | size0 = calculate_iosize(size, min_size, size1, |
743 | resource_size(b_res), 4096); | |
be768912 YL |
744 | if (children_add_size > add_size) |
745 | add_size = children_add_size; | |
9e8bf93a | 746 | size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 : |
a4ac9fea | 747 | calculate_iosize(size, min_size, add_size + size1, |
13583b16 | 748 | resource_size(b_res), 4096); |
c8adf9a3 | 749 | if (!size0 && !size1) { |
865df576 BH |
750 | if (b_res->start || b_res->end) |
751 | dev_info(&bus->self->dev, "disabling bridge window " | |
752 | "%pR to [bus %02x-%02x] (unused)\n", b_res, | |
753 | bus->secondary, bus->subordinate); | |
1da177e4 LT |
754 | b_res->flags = 0; |
755 | return; | |
756 | } | |
757 | /* Alignment of the IO window is always 4K */ | |
758 | b_res->start = 4096; | |
c8adf9a3 | 759 | b_res->end = b_res->start + size0 - 1; |
88452565 | 760 | b_res->flags |= IORESOURCE_STARTALIGN; |
b592443d | 761 | if (size1 > size0 && realloc_head) { |
9e8bf93a | 762 | add_to_list(realloc_head, bus->self, b_res, size1-size0, 4096); |
b592443d YL |
763 | dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window " |
764 | "%pR to [bus %02x-%02x] add_size %lx\n", b_res, | |
765 | bus->secondary, bus->subordinate, size1-size0); | |
766 | } | |
1da177e4 LT |
767 | } |
768 | ||
c8adf9a3 RP |
769 | /** |
770 | * pbus_size_mem() - size the memory window of a given bus | |
771 | * | |
772 | * @bus : the bus | |
773 | * @min_size : the minimum memory window that must to be allocated | |
774 | * @add_size : additional optional memory window | |
9e8bf93a | 775 | * @realloc_head : track the additional memory window on this list |
c8adf9a3 RP |
776 | * |
777 | * Calculate the size of the bus and minimal alignment which | |
778 | * guarantees that all child resources fit in this size. | |
779 | */ | |
28760489 | 780 | static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, |
c8adf9a3 RP |
781 | unsigned long type, resource_size_t min_size, |
782 | resource_size_t add_size, | |
bdc4abec | 783 | struct list_head *realloc_head) |
1da177e4 LT |
784 | { |
785 | struct pci_dev *dev; | |
c8adf9a3 | 786 | resource_size_t min_align, align, size, size0, size1; |
c40a22e0 | 787 | resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */ |
1da177e4 LT |
788 | int order, max_order; |
789 | struct resource *b_res = find_free_bus_resource(bus, type); | |
1f82de10 | 790 | unsigned int mem64_mask = 0; |
be768912 | 791 | resource_size_t children_add_size = 0; |
1da177e4 LT |
792 | |
793 | if (!b_res) | |
794 | return 0; | |
795 | ||
796 | memset(aligns, 0, sizeof(aligns)); | |
797 | max_order = 0; | |
798 | size = 0; | |
799 | ||
1f82de10 YL |
800 | mem64_mask = b_res->flags & IORESOURCE_MEM_64; |
801 | b_res->flags &= ~IORESOURCE_MEM_64; | |
802 | ||
1da177e4 LT |
803 | list_for_each_entry(dev, &bus->devices, bus_list) { |
804 | int i; | |
1f82de10 | 805 | |
1da177e4 LT |
806 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { |
807 | struct resource *r = &dev->resource[i]; | |
c40a22e0 | 808 | resource_size_t r_size; |
1da177e4 LT |
809 | |
810 | if (r->parent || (r->flags & mask) != type) | |
811 | continue; | |
022edd86 | 812 | r_size = resource_size(r); |
2aceefcb YL |
813 | #ifdef CONFIG_PCI_IOV |
814 | /* put SRIOV requested res to the optional list */ | |
9e8bf93a | 815 | if (realloc_head && i >= PCI_IOV_RESOURCES && |
2aceefcb YL |
816 | i <= PCI_IOV_RESOURCE_END) { |
817 | r->end = r->start - 1; | |
9e8bf93a | 818 | add_to_list(realloc_head, dev, r, r_size, 0/* dont' care */); |
2aceefcb YL |
819 | children_add_size += r_size; |
820 | continue; | |
821 | } | |
822 | #endif | |
1da177e4 | 823 | /* For bridges size != alignment */ |
6faf17f6 | 824 | align = pci_resource_alignment(dev, r); |
1da177e4 LT |
825 | order = __ffs(align) - 20; |
826 | if (order > 11) { | |
865df576 BH |
827 | dev_warn(&dev->dev, "disabling BAR %d: %pR " |
828 | "(bad alignment %#llx)\n", i, r, | |
829 | (unsigned long long) align); | |
1da177e4 LT |
830 | r->flags = 0; |
831 | continue; | |
832 | } | |
833 | size += r_size; | |
834 | if (order < 0) | |
835 | order = 0; | |
836 | /* Exclude ranges with size > align from | |
837 | calculation of the alignment. */ | |
838 | if (r_size == align) | |
839 | aligns[order] += align; | |
840 | if (order > max_order) | |
841 | max_order = order; | |
1f82de10 | 842 | mem64_mask &= r->flags & IORESOURCE_MEM_64; |
be768912 | 843 | |
9e8bf93a RP |
844 | if (realloc_head) |
845 | children_add_size += get_res_add_size(realloc_head, r); | |
1da177e4 LT |
846 | } |
847 | } | |
1da177e4 LT |
848 | align = 0; |
849 | min_align = 0; | |
850 | for (order = 0; order <= max_order; order++) { | |
8308c54d JF |
851 | resource_size_t align1 = 1; |
852 | ||
853 | align1 <<= (order + 20); | |
854 | ||
1da177e4 LT |
855 | if (!align) |
856 | min_align = align1; | |
6f6f8c2f | 857 | else if (ALIGN(align + min_align, min_align) < align1) |
1da177e4 LT |
858 | min_align = align1 >> 1; |
859 | align += aligns[order]; | |
860 | } | |
b42282e5 | 861 | size0 = calculate_memsize(size, min_size, 0, resource_size(b_res), min_align); |
be768912 YL |
862 | if (children_add_size > add_size) |
863 | add_size = children_add_size; | |
9e8bf93a | 864 | size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 : |
a4ac9fea | 865 | calculate_memsize(size, min_size, add_size, |
b42282e5 | 866 | resource_size(b_res), min_align); |
c8adf9a3 | 867 | if (!size0 && !size1) { |
865df576 BH |
868 | if (b_res->start || b_res->end) |
869 | dev_info(&bus->self->dev, "disabling bridge window " | |
870 | "%pR to [bus %02x-%02x] (unused)\n", b_res, | |
871 | bus->secondary, bus->subordinate); | |
1da177e4 LT |
872 | b_res->flags = 0; |
873 | return 1; | |
874 | } | |
875 | b_res->start = min_align; | |
c8adf9a3 RP |
876 | b_res->end = size0 + min_align - 1; |
877 | b_res->flags |= IORESOURCE_STARTALIGN | mem64_mask; | |
b592443d | 878 | if (size1 > size0 && realloc_head) { |
9e8bf93a | 879 | add_to_list(realloc_head, bus->self, b_res, size1-size0, min_align); |
b592443d YL |
880 | dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window " |
881 | "%pR to [bus %02x-%02x] add_size %llx\n", b_res, | |
882 | bus->secondary, bus->subordinate, (unsigned long long)size1-size0); | |
883 | } | |
1da177e4 LT |
884 | return 1; |
885 | } | |
886 | ||
0a2daa1c RP |
887 | unsigned long pci_cardbus_resource_alignment(struct resource *res) |
888 | { | |
889 | if (res->flags & IORESOURCE_IO) | |
890 | return pci_cardbus_io_size; | |
891 | if (res->flags & IORESOURCE_MEM) | |
892 | return pci_cardbus_mem_size; | |
893 | return 0; | |
894 | } | |
895 | ||
896 | static void pci_bus_size_cardbus(struct pci_bus *bus, | |
bdc4abec | 897 | struct list_head *realloc_head) |
1da177e4 LT |
898 | { |
899 | struct pci_dev *bridge = bus->self; | |
900 | struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; | |
11848934 | 901 | resource_size_t b_res_3_size = pci_cardbus_mem_size * 2; |
1da177e4 LT |
902 | u16 ctrl; |
903 | ||
904 | /* | |
905 | * Reserve some resources for CardBus. We reserve | |
906 | * a fixed amount of bus space for CardBus bridges. | |
907 | */ | |
11848934 YL |
908 | b_res[0].start = pci_cardbus_io_size; |
909 | b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1; | |
910 | b_res[0].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN; | |
911 | if (realloc_head) { | |
912 | b_res[0].end -= pci_cardbus_io_size; | |
913 | add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size, | |
914 | pci_cardbus_io_size); | |
915 | } | |
1da177e4 | 916 | |
11848934 YL |
917 | b_res[1].start = pci_cardbus_io_size; |
918 | b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1; | |
919 | b_res[1].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN; | |
920 | if (realloc_head) { | |
921 | b_res[1].end -= pci_cardbus_io_size; | |
922 | add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size, | |
923 | pci_cardbus_io_size); | |
924 | } | |
1da177e4 | 925 | |
dcef0d06 YL |
926 | /* MEM1 must not be pref mmio */ |
927 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
928 | if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) { | |
929 | ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1; | |
930 | pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); | |
931 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
932 | } | |
933 | ||
1da177e4 LT |
934 | /* |
935 | * Check whether prefetchable memory is supported | |
936 | * by this bridge. | |
937 | */ | |
938 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
939 | if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) { | |
940 | ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; | |
941 | pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); | |
942 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
943 | } | |
944 | ||
945 | /* | |
946 | * If we have prefetchable memory support, allocate | |
947 | * two regions. Otherwise, allocate one region of | |
948 | * twice the size. | |
949 | */ | |
950 | if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) { | |
11848934 YL |
951 | b_res[2].start = pci_cardbus_mem_size; |
952 | b_res[2].end = b_res[2].start + pci_cardbus_mem_size - 1; | |
953 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | | |
954 | IORESOURCE_STARTALIGN; | |
955 | if (realloc_head) { | |
956 | b_res[2].end -= pci_cardbus_mem_size; | |
957 | add_to_list(realloc_head, bridge, b_res+2, | |
958 | pci_cardbus_mem_size, pci_cardbus_mem_size); | |
959 | } | |
960 | ||
961 | /* reduce that to half */ | |
962 | b_res_3_size = pci_cardbus_mem_size; | |
963 | } | |
964 | ||
965 | b_res[3].start = pci_cardbus_mem_size; | |
966 | b_res[3].end = b_res[3].start + b_res_3_size - 1; | |
967 | b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN; | |
968 | if (realloc_head) { | |
969 | b_res[3].end -= b_res_3_size; | |
970 | add_to_list(realloc_head, bridge, b_res+3, b_res_3_size, | |
971 | pci_cardbus_mem_size); | |
972 | } | |
1da177e4 LT |
973 | } |
974 | ||
c8adf9a3 | 975 | void __ref __pci_bus_size_bridges(struct pci_bus *bus, |
bdc4abec | 976 | struct list_head *realloc_head) |
1da177e4 LT |
977 | { |
978 | struct pci_dev *dev; | |
979 | unsigned long mask, prefmask; | |
c8adf9a3 | 980 | resource_size_t additional_mem_size = 0, additional_io_size = 0; |
1da177e4 LT |
981 | |
982 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
983 | struct pci_bus *b = dev->subordinate; | |
984 | if (!b) | |
985 | continue; | |
986 | ||
987 | switch (dev->class >> 8) { | |
988 | case PCI_CLASS_BRIDGE_CARDBUS: | |
9e8bf93a | 989 | pci_bus_size_cardbus(b, realloc_head); |
1da177e4 LT |
990 | break; |
991 | ||
992 | case PCI_CLASS_BRIDGE_PCI: | |
993 | default: | |
9e8bf93a | 994 | __pci_bus_size_bridges(b, realloc_head); |
1da177e4 LT |
995 | break; |
996 | } | |
997 | } | |
998 | ||
999 | /* The root bus? */ | |
1000 | if (!bus->self) | |
1001 | return; | |
1002 | ||
1003 | switch (bus->self->class >> 8) { | |
1004 | case PCI_CLASS_BRIDGE_CARDBUS: | |
1005 | /* don't size cardbuses yet. */ | |
1006 | break; | |
1007 | ||
1008 | case PCI_CLASS_BRIDGE_PCI: | |
1009 | pci_bridge_check_ranges(bus); | |
28760489 | 1010 | if (bus->self->is_hotplug_bridge) { |
c8adf9a3 RP |
1011 | additional_io_size = pci_hotplug_io_size; |
1012 | additional_mem_size = pci_hotplug_mem_size; | |
28760489 | 1013 | } |
c8adf9a3 RP |
1014 | /* |
1015 | * Follow thru | |
1016 | */ | |
1da177e4 | 1017 | default: |
19aa7ee4 YL |
1018 | pbus_size_io(bus, realloc_head ? 0 : additional_io_size, |
1019 | additional_io_size, realloc_head); | |
1da177e4 LT |
1020 | /* If the bridge supports prefetchable range, size it |
1021 | separately. If it doesn't, or its prefetchable window | |
1022 | has already been allocated by arch code, try | |
1023 | non-prefetchable range for both types of PCI memory | |
1024 | resources. */ | |
1025 | mask = IORESOURCE_MEM; | |
1026 | prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
19aa7ee4 YL |
1027 | if (pbus_size_mem(bus, prefmask, prefmask, |
1028 | realloc_head ? 0 : additional_mem_size, | |
1029 | additional_mem_size, realloc_head)) | |
1da177e4 | 1030 | mask = prefmask; /* Success, size non-prefetch only. */ |
28760489 | 1031 | else |
c8adf9a3 | 1032 | additional_mem_size += additional_mem_size; |
19aa7ee4 YL |
1033 | pbus_size_mem(bus, mask, IORESOURCE_MEM, |
1034 | realloc_head ? 0 : additional_mem_size, | |
1035 | additional_mem_size, realloc_head); | |
1da177e4 LT |
1036 | break; |
1037 | } | |
1038 | } | |
c8adf9a3 RP |
1039 | |
1040 | void __ref pci_bus_size_bridges(struct pci_bus *bus) | |
1041 | { | |
1042 | __pci_bus_size_bridges(bus, NULL); | |
1043 | } | |
1da177e4 LT |
1044 | EXPORT_SYMBOL(pci_bus_size_bridges); |
1045 | ||
568ddef8 | 1046 | static void __ref __pci_bus_assign_resources(const struct pci_bus *bus, |
bdc4abec YL |
1047 | struct list_head *realloc_head, |
1048 | struct list_head *fail_head) | |
1da177e4 LT |
1049 | { |
1050 | struct pci_bus *b; | |
1051 | struct pci_dev *dev; | |
1052 | ||
9e8bf93a | 1053 | pbus_assign_resources_sorted(bus, realloc_head, fail_head); |
1da177e4 | 1054 | |
1da177e4 LT |
1055 | list_for_each_entry(dev, &bus->devices, bus_list) { |
1056 | b = dev->subordinate; | |
1057 | if (!b) | |
1058 | continue; | |
1059 | ||
9e8bf93a | 1060 | __pci_bus_assign_resources(b, realloc_head, fail_head); |
1da177e4 LT |
1061 | |
1062 | switch (dev->class >> 8) { | |
1063 | case PCI_CLASS_BRIDGE_PCI: | |
6841ec68 YL |
1064 | if (!pci_is_enabled(dev)) |
1065 | pci_setup_bridge(b); | |
1da177e4 LT |
1066 | break; |
1067 | ||
1068 | case PCI_CLASS_BRIDGE_CARDBUS: | |
1069 | pci_setup_cardbus(b); | |
1070 | break; | |
1071 | ||
1072 | default: | |
80ccba11 BH |
1073 | dev_info(&dev->dev, "not setting up bridge for bus " |
1074 | "%04x:%02x\n", pci_domain_nr(b), b->number); | |
1da177e4 LT |
1075 | break; |
1076 | } | |
1077 | } | |
1078 | } | |
568ddef8 YL |
1079 | |
1080 | void __ref pci_bus_assign_resources(const struct pci_bus *bus) | |
1081 | { | |
c8adf9a3 | 1082 | __pci_bus_assign_resources(bus, NULL, NULL); |
568ddef8 | 1083 | } |
1da177e4 LT |
1084 | EXPORT_SYMBOL(pci_bus_assign_resources); |
1085 | ||
6841ec68 | 1086 | static void __ref __pci_bridge_assign_resources(const struct pci_dev *bridge, |
bdc4abec YL |
1087 | struct list_head *add_head, |
1088 | struct list_head *fail_head) | |
6841ec68 YL |
1089 | { |
1090 | struct pci_bus *b; | |
1091 | ||
8424d759 YL |
1092 | pdev_assign_resources_sorted((struct pci_dev *)bridge, |
1093 | add_head, fail_head); | |
6841ec68 YL |
1094 | |
1095 | b = bridge->subordinate; | |
1096 | if (!b) | |
1097 | return; | |
1098 | ||
8424d759 | 1099 | __pci_bus_assign_resources(b, add_head, fail_head); |
6841ec68 YL |
1100 | |
1101 | switch (bridge->class >> 8) { | |
1102 | case PCI_CLASS_BRIDGE_PCI: | |
1103 | pci_setup_bridge(b); | |
1104 | break; | |
1105 | ||
1106 | case PCI_CLASS_BRIDGE_CARDBUS: | |
1107 | pci_setup_cardbus(b); | |
1108 | break; | |
1109 | ||
1110 | default: | |
1111 | dev_info(&bridge->dev, "not setting up bridge for bus " | |
1112 | "%04x:%02x\n", pci_domain_nr(b), b->number); | |
1113 | break; | |
1114 | } | |
1115 | } | |
5009b460 YL |
1116 | static void pci_bridge_release_resources(struct pci_bus *bus, |
1117 | unsigned long type) | |
1118 | { | |
1119 | int idx; | |
1120 | bool changed = false; | |
1121 | struct pci_dev *dev; | |
1122 | struct resource *r; | |
1123 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | | |
1124 | IORESOURCE_PREFETCH; | |
1125 | ||
1126 | dev = bus->self; | |
1127 | for (idx = PCI_BRIDGE_RESOURCES; idx <= PCI_BRIDGE_RESOURCE_END; | |
1128 | idx++) { | |
1129 | r = &dev->resource[idx]; | |
1130 | if ((r->flags & type_mask) != type) | |
1131 | continue; | |
1132 | if (!r->parent) | |
1133 | continue; | |
1134 | /* | |
1135 | * if there are children under that, we should release them | |
1136 | * all | |
1137 | */ | |
1138 | release_child_resources(r); | |
1139 | if (!release_resource(r)) { | |
1140 | dev_printk(KERN_DEBUG, &dev->dev, | |
1141 | "resource %d %pR released\n", idx, r); | |
1142 | /* keep the old size */ | |
1143 | r->end = resource_size(r) - 1; | |
1144 | r->start = 0; | |
1145 | r->flags = 0; | |
1146 | changed = true; | |
1147 | } | |
1148 | } | |
1149 | ||
1150 | if (changed) { | |
1151 | /* avoiding touch the one without PREF */ | |
1152 | if (type & IORESOURCE_PREFETCH) | |
1153 | type = IORESOURCE_PREFETCH; | |
1154 | __pci_setup_bridge(bus, type); | |
1155 | } | |
1156 | } | |
1157 | ||
1158 | enum release_type { | |
1159 | leaf_only, | |
1160 | whole_subtree, | |
1161 | }; | |
1162 | /* | |
1163 | * try to release pci bridge resources that is from leaf bridge, | |
1164 | * so we can allocate big new one later | |
1165 | */ | |
1166 | static void __ref pci_bus_release_bridge_resources(struct pci_bus *bus, | |
1167 | unsigned long type, | |
1168 | enum release_type rel_type) | |
1169 | { | |
1170 | struct pci_dev *dev; | |
1171 | bool is_leaf_bridge = true; | |
1172 | ||
1173 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1174 | struct pci_bus *b = dev->subordinate; | |
1175 | if (!b) | |
1176 | continue; | |
1177 | ||
1178 | is_leaf_bridge = false; | |
1179 | ||
1180 | if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) | |
1181 | continue; | |
1182 | ||
1183 | if (rel_type == whole_subtree) | |
1184 | pci_bus_release_bridge_resources(b, type, | |
1185 | whole_subtree); | |
1186 | } | |
1187 | ||
1188 | if (pci_is_root_bus(bus)) | |
1189 | return; | |
1190 | ||
1191 | if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI) | |
1192 | return; | |
1193 | ||
1194 | if ((rel_type == whole_subtree) || is_leaf_bridge) | |
1195 | pci_bridge_release_resources(bus, type); | |
1196 | } | |
1197 | ||
76fbc263 YL |
1198 | static void pci_bus_dump_res(struct pci_bus *bus) |
1199 | { | |
89a74ecc BH |
1200 | struct resource *res; |
1201 | int i; | |
7c9342b8 | 1202 | |
89a74ecc | 1203 | pci_bus_for_each_resource(bus, res, i) { |
7c9342b8 | 1204 | if (!res || !res->end || !res->flags) |
76fbc263 YL |
1205 | continue; |
1206 | ||
c7dabef8 | 1207 | dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res); |
76fbc263 YL |
1208 | } |
1209 | } | |
1210 | ||
1211 | static void pci_bus_dump_resources(struct pci_bus *bus) | |
1212 | { | |
1213 | struct pci_bus *b; | |
1214 | struct pci_dev *dev; | |
1215 | ||
1216 | ||
1217 | pci_bus_dump_res(bus); | |
1218 | ||
1219 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1220 | b = dev->subordinate; | |
1221 | if (!b) | |
1222 | continue; | |
1223 | ||
1224 | pci_bus_dump_resources(b); | |
1225 | } | |
1226 | } | |
1227 | ||
da7822e5 YL |
1228 | static int __init pci_bus_get_depth(struct pci_bus *bus) |
1229 | { | |
1230 | int depth = 0; | |
1231 | struct pci_dev *dev; | |
1232 | ||
1233 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1234 | int ret; | |
1235 | struct pci_bus *b = dev->subordinate; | |
1236 | if (!b) | |
1237 | continue; | |
1238 | ||
1239 | ret = pci_bus_get_depth(b); | |
1240 | if (ret + 1 > depth) | |
1241 | depth = ret + 1; | |
1242 | } | |
1243 | ||
1244 | return depth; | |
1245 | } | |
1246 | static int __init pci_get_max_depth(void) | |
1247 | { | |
1248 | int depth = 0; | |
1249 | struct pci_bus *bus; | |
1250 | ||
1251 | list_for_each_entry(bus, &pci_root_buses, node) { | |
1252 | int ret; | |
1253 | ||
1254 | ret = pci_bus_get_depth(bus); | |
1255 | if (ret > depth) | |
1256 | depth = ret; | |
1257 | } | |
1258 | ||
1259 | return depth; | |
1260 | } | |
1261 | ||
f483d392 | 1262 | |
da7822e5 YL |
1263 | /* |
1264 | * first try will not touch pci bridge res | |
1265 | * second and later try will clear small leaf bridge res | |
1266 | * will stop till to the max deepth if can not find good one | |
1267 | */ | |
1da177e4 LT |
1268 | void __init |
1269 | pci_assign_unassigned_resources(void) | |
1270 | { | |
1271 | struct pci_bus *bus; | |
bdc4abec | 1272 | LIST_HEAD(realloc_head); /* list of resources that |
c8adf9a3 | 1273 | want additional resources */ |
bdc4abec | 1274 | struct list_head *add_list = NULL; |
da7822e5 YL |
1275 | int tried_times = 0; |
1276 | enum release_type rel_type = leaf_only; | |
bdc4abec | 1277 | LIST_HEAD(fail_head); |
b9b0bba9 | 1278 | struct pci_dev_resource *fail_res; |
da7822e5 YL |
1279 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | |
1280 | IORESOURCE_PREFETCH; | |
1281 | unsigned long failed_type; | |
19aa7ee4 | 1282 | int pci_try_num = 1; |
da7822e5 | 1283 | |
19aa7ee4 YL |
1284 | /* don't realloc if asked to do so */ |
1285 | if (pci_realloc_enabled()) { | |
1286 | int max_depth = pci_get_max_depth(); | |
1287 | ||
1288 | pci_try_num = max_depth + 1; | |
1289 | printk(KERN_DEBUG "PCI: max bus depth: %d pci_try_num: %d\n", | |
1290 | max_depth, pci_try_num); | |
1291 | } | |
da7822e5 YL |
1292 | |
1293 | again: | |
19aa7ee4 YL |
1294 | /* |
1295 | * last try will use add_list, otherwise will try good to have as | |
1296 | * must have, so can realloc parent bridge resource | |
1297 | */ | |
1298 | if (tried_times + 1 == pci_try_num) | |
bdc4abec | 1299 | add_list = &realloc_head; |
1da177e4 LT |
1300 | /* Depth first, calculate sizes and alignments of all |
1301 | subordinate buses. */ | |
da7822e5 | 1302 | list_for_each_entry(bus, &pci_root_buses, node) |
19aa7ee4 | 1303 | __pci_bus_size_bridges(bus, add_list); |
c8adf9a3 | 1304 | |
1da177e4 | 1305 | /* Depth last, allocate resources and update the hardware. */ |
da7822e5 | 1306 | list_for_each_entry(bus, &pci_root_buses, node) |
bdc4abec | 1307 | __pci_bus_assign_resources(bus, add_list, &fail_head); |
19aa7ee4 | 1308 | if (add_list) |
bdc4abec | 1309 | BUG_ON(!list_empty(add_list)); |
da7822e5 YL |
1310 | tried_times++; |
1311 | ||
1312 | /* any device complain? */ | |
bdc4abec | 1313 | if (list_empty(&fail_head)) |
da7822e5 | 1314 | goto enable_and_dump; |
f483d392 | 1315 | |
da7822e5 | 1316 | failed_type = 0; |
b9b0bba9 YL |
1317 | list_for_each_entry(fail_res, &fail_head, list) |
1318 | failed_type |= fail_res->flags; | |
bdc4abec | 1319 | |
da7822e5 YL |
1320 | /* |
1321 | * io port are tight, don't try extra | |
1322 | * or if reach the limit, don't want to try more | |
1323 | */ | |
1324 | failed_type &= type_mask; | |
1325 | if ((failed_type == IORESOURCE_IO) || (tried_times >= pci_try_num)) { | |
bffc56d4 | 1326 | free_list(&fail_head); |
da7822e5 YL |
1327 | goto enable_and_dump; |
1328 | } | |
1329 | ||
1330 | printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n", | |
1331 | tried_times + 1); | |
1332 | ||
1333 | /* third times and later will not check if it is leaf */ | |
1334 | if ((tried_times + 1) > 2) | |
1335 | rel_type = whole_subtree; | |
1336 | ||
1337 | /* | |
1338 | * Try to release leaf bridge's resources that doesn't fit resource of | |
1339 | * child device under that bridge | |
1340 | */ | |
b9b0bba9 YL |
1341 | list_for_each_entry(fail_res, &fail_head, list) { |
1342 | bus = fail_res->dev->bus; | |
bdc4abec | 1343 | pci_bus_release_bridge_resources(bus, |
b9b0bba9 | 1344 | fail_res->flags & type_mask, |
bdc4abec | 1345 | rel_type); |
da7822e5 YL |
1346 | } |
1347 | /* restore size and flags */ | |
b9b0bba9 YL |
1348 | list_for_each_entry(fail_res, &fail_head, list) { |
1349 | struct resource *res = fail_res->res; | |
da7822e5 | 1350 | |
b9b0bba9 YL |
1351 | res->start = fail_res->start; |
1352 | res->end = fail_res->end; | |
1353 | res->flags = fail_res->flags; | |
1354 | if (fail_res->dev->subordinate) | |
da7822e5 | 1355 | res->flags = 0; |
da7822e5 | 1356 | } |
bffc56d4 | 1357 | free_list(&fail_head); |
da7822e5 YL |
1358 | |
1359 | goto again; | |
1360 | ||
1361 | enable_and_dump: | |
1362 | /* Depth last, update the hardware. */ | |
1363 | list_for_each_entry(bus, &pci_root_buses, node) | |
1364 | pci_enable_bridges(bus); | |
76fbc263 YL |
1365 | |
1366 | /* dump the resource on buses */ | |
da7822e5 | 1367 | list_for_each_entry(bus, &pci_root_buses, node) |
76fbc263 | 1368 | pci_bus_dump_resources(bus); |
1da177e4 | 1369 | } |
6841ec68 YL |
1370 | |
1371 | void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge) | |
1372 | { | |
1373 | struct pci_bus *parent = bridge->subordinate; | |
bdc4abec | 1374 | LIST_HEAD(add_list); /* list of resources that |
8424d759 | 1375 | want additional resources */ |
32180e40 | 1376 | int tried_times = 0; |
bdc4abec | 1377 | LIST_HEAD(fail_head); |
b9b0bba9 | 1378 | struct pci_dev_resource *fail_res; |
6841ec68 | 1379 | int retval; |
32180e40 YL |
1380 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | |
1381 | IORESOURCE_PREFETCH; | |
1382 | ||
32180e40 | 1383 | again: |
8424d759 | 1384 | __pci_bus_size_bridges(parent, &add_list); |
bdc4abec YL |
1385 | __pci_bridge_assign_resources(bridge, &add_list, &fail_head); |
1386 | BUG_ON(!list_empty(&add_list)); | |
32180e40 YL |
1387 | tried_times++; |
1388 | ||
bdc4abec | 1389 | if (list_empty(&fail_head)) |
3f579c34 | 1390 | goto enable_all; |
32180e40 YL |
1391 | |
1392 | if (tried_times >= 2) { | |
1393 | /* still fail, don't need to try more */ | |
bffc56d4 | 1394 | free_list(&fail_head); |
3f579c34 | 1395 | goto enable_all; |
32180e40 YL |
1396 | } |
1397 | ||
1398 | printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n", | |
1399 | tried_times + 1); | |
1400 | ||
1401 | /* | |
1402 | * Try to release leaf bridge's resources that doesn't fit resource of | |
1403 | * child device under that bridge | |
1404 | */ | |
b9b0bba9 YL |
1405 | list_for_each_entry(fail_res, &fail_head, list) { |
1406 | struct pci_bus *bus = fail_res->dev->bus; | |
1407 | unsigned long flags = fail_res->flags; | |
32180e40 YL |
1408 | |
1409 | pci_bus_release_bridge_resources(bus, flags & type_mask, | |
1410 | whole_subtree); | |
32180e40 YL |
1411 | } |
1412 | /* restore size and flags */ | |
b9b0bba9 YL |
1413 | list_for_each_entry(fail_res, &fail_head, list) { |
1414 | struct resource *res = fail_res->res; | |
32180e40 | 1415 | |
b9b0bba9 YL |
1416 | res->start = fail_res->start; |
1417 | res->end = fail_res->end; | |
1418 | res->flags = fail_res->flags; | |
1419 | if (fail_res->dev->subordinate) | |
32180e40 | 1420 | res->flags = 0; |
32180e40 | 1421 | } |
bffc56d4 | 1422 | free_list(&fail_head); |
32180e40 YL |
1423 | |
1424 | goto again; | |
3f579c34 YL |
1425 | |
1426 | enable_all: | |
1427 | retval = pci_reenable_device(bridge); | |
1428 | pci_set_master(bridge); | |
1429 | pci_enable_bridges(parent); | |
6841ec68 YL |
1430 | } |
1431 | EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources); | |
9b03088f YL |
1432 | |
1433 | #ifdef CONFIG_HOTPLUG | |
1434 | /** | |
1435 | * pci_rescan_bus - scan a PCI bus for devices. | |
1436 | * @bus: PCI bus to scan | |
1437 | * | |
1438 | * Scan a PCI bus and child buses for new devices, adds them, | |
1439 | * and enables them. | |
1440 | * | |
1441 | * Returns the max number of subordinate bus discovered. | |
1442 | */ | |
1443 | unsigned int __ref pci_rescan_bus(struct pci_bus *bus) | |
1444 | { | |
1445 | unsigned int max; | |
1446 | struct pci_dev *dev; | |
bdc4abec | 1447 | LIST_HEAD(add_list); /* list of resources that |
9b03088f YL |
1448 | want additional resources */ |
1449 | ||
1450 | max = pci_scan_child_bus(bus); | |
1451 | ||
9b03088f YL |
1452 | down_read(&pci_bus_sem); |
1453 | list_for_each_entry(dev, &bus->devices, bus_list) | |
1454 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || | |
1455 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) | |
1456 | if (dev->subordinate) | |
1457 | __pci_bus_size_bridges(dev->subordinate, | |
1458 | &add_list); | |
1459 | up_read(&pci_bus_sem); | |
1460 | __pci_bus_assign_resources(bus, &add_list, NULL); | |
bdc4abec | 1461 | BUG_ON(!list_empty(&add_list)); |
9b03088f YL |
1462 | |
1463 | pci_enable_bridges(bus); | |
1464 | pci_bus_add_devices(bus); | |
1465 | ||
1466 | return max; | |
1467 | } | |
1468 | EXPORT_SYMBOL_GPL(pci_rescan_bus); | |
1469 | #endif |