]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * drivers/pci/setup-bus.c | |
3 | * | |
4 | * Extruded from code written by | |
5 | * Dave Rusling (david.rusling@reo.mts.dec.com) | |
6 | * David Mosberger (davidm@cs.arizona.edu) | |
7 | * David Miller (davem@redhat.com) | |
8 | * | |
9 | * Support routines for initializing a PCI subsystem. | |
10 | */ | |
11 | ||
12 | /* | |
13 | * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> | |
14 | * PCI-PCI bridges cleanup, sorted resource allocation. | |
15 | * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru> | |
16 | * Converted to allocation in 3 passes, which gives | |
17 | * tighter packing. Prefetchable range support. | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/pci.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/ioport.h> | |
26 | #include <linux/cache.h> | |
27 | #include <linux/slab.h> | |
47087700 | 28 | #include <asm-generic/pci-bridge.h> |
6faf17f6 | 29 | #include "pci.h" |
1da177e4 | 30 | |
844393f4 | 31 | unsigned int pci_flags; |
47087700 | 32 | |
bdc4abec YL |
33 | struct pci_dev_resource { |
34 | struct list_head list; | |
2934a0de YL |
35 | struct resource *res; |
36 | struct pci_dev *dev; | |
568ddef8 YL |
37 | resource_size_t start; |
38 | resource_size_t end; | |
c8adf9a3 | 39 | resource_size_t add_size; |
2bbc6942 | 40 | resource_size_t min_align; |
568ddef8 YL |
41 | unsigned long flags; |
42 | }; | |
43 | ||
bffc56d4 YL |
44 | static void free_list(struct list_head *head) |
45 | { | |
46 | struct pci_dev_resource *dev_res, *tmp; | |
47 | ||
48 | list_for_each_entry_safe(dev_res, tmp, head, list) { | |
49 | list_del(&dev_res->list); | |
50 | kfree(dev_res); | |
51 | } | |
52 | } | |
094732a5 | 53 | |
c8adf9a3 RP |
54 | /** |
55 | * add_to_list() - add a new resource tracker to the list | |
56 | * @head: Head of the list | |
57 | * @dev: device corresponding to which the resource | |
58 | * belongs | |
59 | * @res: The resource to be tracked | |
60 | * @add_size: additional size to be optionally added | |
61 | * to the resource | |
62 | */ | |
bdc4abec | 63 | static int add_to_list(struct list_head *head, |
c8adf9a3 | 64 | struct pci_dev *dev, struct resource *res, |
2bbc6942 | 65 | resource_size_t add_size, resource_size_t min_align) |
568ddef8 | 66 | { |
764242a0 | 67 | struct pci_dev_resource *tmp; |
568ddef8 | 68 | |
bdc4abec | 69 | tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); |
568ddef8 | 70 | if (!tmp) { |
c8adf9a3 | 71 | pr_warning("add_to_list: kmalloc() failed!\n"); |
ef62dfef | 72 | return -ENOMEM; |
568ddef8 YL |
73 | } |
74 | ||
568ddef8 YL |
75 | tmp->res = res; |
76 | tmp->dev = dev; | |
77 | tmp->start = res->start; | |
78 | tmp->end = res->end; | |
79 | tmp->flags = res->flags; | |
c8adf9a3 | 80 | tmp->add_size = add_size; |
2bbc6942 | 81 | tmp->min_align = min_align; |
bdc4abec YL |
82 | |
83 | list_add(&tmp->list, head); | |
ef62dfef YL |
84 | |
85 | return 0; | |
568ddef8 YL |
86 | } |
87 | ||
b9b0bba9 | 88 | static void remove_from_list(struct list_head *head, |
3e6e0d80 YL |
89 | struct resource *res) |
90 | { | |
b9b0bba9 | 91 | struct pci_dev_resource *dev_res, *tmp; |
3e6e0d80 | 92 | |
b9b0bba9 YL |
93 | list_for_each_entry_safe(dev_res, tmp, head, list) { |
94 | if (dev_res->res == res) { | |
95 | list_del(&dev_res->list); | |
96 | kfree(dev_res); | |
bdc4abec | 97 | break; |
3e6e0d80 | 98 | } |
3e6e0d80 YL |
99 | } |
100 | } | |
101 | ||
b9b0bba9 | 102 | static resource_size_t get_res_add_size(struct list_head *head, |
1c372353 YL |
103 | struct resource *res) |
104 | { | |
b9b0bba9 | 105 | struct pci_dev_resource *dev_res; |
bdc4abec | 106 | |
b9b0bba9 YL |
107 | list_for_each_entry(dev_res, head, list) { |
108 | if (dev_res->res == res) { | |
b592443d YL |
109 | int idx = res - &dev_res->dev->resource[0]; |
110 | ||
b9b0bba9 | 111 | dev_printk(KERN_DEBUG, &dev_res->dev->dev, |
b592443d YL |
112 | "res[%d]=%pR get_res_add_size add_size %llx\n", |
113 | idx, dev_res->res, | |
b9b0bba9 | 114 | (unsigned long long)dev_res->add_size); |
b592443d | 115 | |
b9b0bba9 | 116 | return dev_res->add_size; |
bdc4abec | 117 | } |
3e6e0d80 | 118 | } |
1c372353 YL |
119 | |
120 | return 0; | |
121 | } | |
122 | ||
78c3b329 | 123 | /* Sort resources by alignment */ |
bdc4abec | 124 | static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head) |
78c3b329 YL |
125 | { |
126 | int i; | |
127 | ||
128 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
129 | struct resource *r; | |
bdc4abec | 130 | struct pci_dev_resource *dev_res, *tmp; |
78c3b329 | 131 | resource_size_t r_align; |
bdc4abec | 132 | struct list_head *n; |
78c3b329 YL |
133 | |
134 | r = &dev->resource[i]; | |
135 | ||
136 | if (r->flags & IORESOURCE_PCI_FIXED) | |
137 | continue; | |
138 | ||
139 | if (!(r->flags) || r->parent) | |
140 | continue; | |
141 | ||
142 | r_align = pci_resource_alignment(dev, r); | |
143 | if (!r_align) { | |
144 | dev_warn(&dev->dev, "BAR %d: %pR has bogus alignment\n", | |
145 | i, r); | |
146 | continue; | |
147 | } | |
78c3b329 | 148 | |
bdc4abec YL |
149 | tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); |
150 | if (!tmp) | |
151 | panic("pdev_sort_resources(): " | |
152 | "kmalloc() failed!\n"); | |
153 | tmp->res = r; | |
154 | tmp->dev = dev; | |
155 | ||
156 | /* fallback is smallest one or list is empty*/ | |
157 | n = head; | |
158 | list_for_each_entry(dev_res, head, list) { | |
159 | resource_size_t align; | |
160 | ||
161 | align = pci_resource_alignment(dev_res->dev, | |
162 | dev_res->res); | |
78c3b329 YL |
163 | |
164 | if (r_align > align) { | |
bdc4abec | 165 | n = &dev_res->list; |
78c3b329 YL |
166 | break; |
167 | } | |
168 | } | |
bdc4abec YL |
169 | /* Insert it just before n*/ |
170 | list_add_tail(&tmp->list, n); | |
78c3b329 YL |
171 | } |
172 | } | |
173 | ||
6841ec68 | 174 | static void __dev_sort_resources(struct pci_dev *dev, |
bdc4abec | 175 | struct list_head *head) |
1da177e4 | 176 | { |
6841ec68 | 177 | u16 class = dev->class >> 8; |
1da177e4 | 178 | |
6841ec68 YL |
179 | /* Don't touch classless devices or host bridges or ioapics. */ |
180 | if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST) | |
181 | return; | |
1da177e4 | 182 | |
6841ec68 YL |
183 | /* Don't touch ioapic devices already enabled by firmware */ |
184 | if (class == PCI_CLASS_SYSTEM_PIC) { | |
185 | u16 command; | |
186 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
187 | if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | |
188 | return; | |
189 | } | |
1da177e4 | 190 | |
6841ec68 YL |
191 | pdev_sort_resources(dev, head); |
192 | } | |
23186279 | 193 | |
fc075e1d RP |
194 | static inline void reset_resource(struct resource *res) |
195 | { | |
196 | res->start = 0; | |
197 | res->end = 0; | |
198 | res->flags = 0; | |
199 | } | |
200 | ||
c8adf9a3 | 201 | /** |
9e8bf93a | 202 | * reassign_resources_sorted() - satisfy any additional resource requests |
c8adf9a3 | 203 | * |
9e8bf93a | 204 | * @realloc_head : head of the list tracking requests requiring additional |
c8adf9a3 RP |
205 | * resources |
206 | * @head : head of the list tracking requests with allocated | |
207 | * resources | |
208 | * | |
9e8bf93a | 209 | * Walk through each element of the realloc_head and try to procure |
c8adf9a3 RP |
210 | * additional resources for the element, provided the element |
211 | * is in the head list. | |
212 | */ | |
bdc4abec YL |
213 | static void reassign_resources_sorted(struct list_head *realloc_head, |
214 | struct list_head *head) | |
6841ec68 YL |
215 | { |
216 | struct resource *res; | |
b9b0bba9 | 217 | struct pci_dev_resource *add_res, *tmp; |
bdc4abec | 218 | struct pci_dev_resource *dev_res; |
c8adf9a3 | 219 | resource_size_t add_size; |
6841ec68 | 220 | int idx; |
1da177e4 | 221 | |
b9b0bba9 | 222 | list_for_each_entry_safe(add_res, tmp, realloc_head, list) { |
bdc4abec YL |
223 | bool found_match = false; |
224 | ||
b9b0bba9 | 225 | res = add_res->res; |
c8adf9a3 RP |
226 | /* skip resource that has been reset */ |
227 | if (!res->flags) | |
228 | goto out; | |
229 | ||
230 | /* skip this resource if not found in head list */ | |
bdc4abec YL |
231 | list_for_each_entry(dev_res, head, list) { |
232 | if (dev_res->res == res) { | |
233 | found_match = true; | |
234 | break; | |
235 | } | |
c8adf9a3 | 236 | } |
bdc4abec YL |
237 | if (!found_match)/* just skip */ |
238 | continue; | |
c8adf9a3 | 239 | |
b9b0bba9 YL |
240 | idx = res - &add_res->dev->resource[0]; |
241 | add_size = add_res->add_size; | |
2bbc6942 | 242 | if (!resource_size(res)) { |
b9b0bba9 | 243 | res->start = add_res->start; |
2bbc6942 | 244 | res->end = res->start + add_size - 1; |
b9b0bba9 | 245 | if (pci_assign_resource(add_res->dev, idx)) |
c8adf9a3 | 246 | reset_resource(res); |
2bbc6942 | 247 | } else { |
b9b0bba9 YL |
248 | resource_size_t align = add_res->min_align; |
249 | res->flags |= add_res->flags & | |
bdc4abec | 250 | (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN); |
b9b0bba9 | 251 | if (pci_reassign_resource(add_res->dev, idx, |
bdc4abec | 252 | add_size, align)) |
b9b0bba9 | 253 | dev_printk(KERN_DEBUG, &add_res->dev->dev, |
b592443d YL |
254 | "failed to add %llx res[%d]=%pR\n", |
255 | (unsigned long long)add_size, | |
256 | idx, res); | |
c8adf9a3 RP |
257 | } |
258 | out: | |
b9b0bba9 YL |
259 | list_del(&add_res->list); |
260 | kfree(add_res); | |
c8adf9a3 RP |
261 | } |
262 | } | |
263 | ||
264 | /** | |
265 | * assign_requested_resources_sorted() - satisfy resource requests | |
266 | * | |
267 | * @head : head of the list tracking requests for resources | |
8356aad4 | 268 | * @fail_head : head of the list tracking requests that could |
c8adf9a3 RP |
269 | * not be allocated |
270 | * | |
271 | * Satisfy resource requests of each element in the list. Add | |
272 | * requests that could not satisfied to the failed_list. | |
273 | */ | |
bdc4abec YL |
274 | static void assign_requested_resources_sorted(struct list_head *head, |
275 | struct list_head *fail_head) | |
c8adf9a3 RP |
276 | { |
277 | struct resource *res; | |
bdc4abec | 278 | struct pci_dev_resource *dev_res; |
c8adf9a3 | 279 | int idx; |
9a928660 | 280 | |
bdc4abec YL |
281 | list_for_each_entry(dev_res, head, list) { |
282 | res = dev_res->res; | |
283 | idx = res - &dev_res->dev->resource[0]; | |
284 | if (resource_size(res) && | |
285 | pci_assign_resource(dev_res->dev, idx)) { | |
a3cb999d | 286 | if (fail_head) { |
9a928660 YL |
287 | /* |
288 | * if the failed res is for ROM BAR, and it will | |
289 | * be enabled later, don't add it to the list | |
290 | */ | |
291 | if (!((idx == PCI_ROM_RESOURCE) && | |
292 | (!(res->flags & IORESOURCE_ROM_ENABLE)))) | |
67cc7e26 YL |
293 | add_to_list(fail_head, |
294 | dev_res->dev, res, | |
f7625980 BH |
295 | 0 /* don't care */, |
296 | 0 /* don't care */); | |
9a928660 | 297 | } |
fc075e1d | 298 | reset_resource(res); |
542df5de | 299 | } |
1da177e4 LT |
300 | } |
301 | } | |
302 | ||
aa914f5e YL |
303 | static unsigned long pci_fail_res_type_mask(struct list_head *fail_head) |
304 | { | |
305 | struct pci_dev_resource *fail_res; | |
306 | unsigned long mask = 0; | |
307 | ||
308 | /* check failed type */ | |
309 | list_for_each_entry(fail_res, fail_head, list) | |
310 | mask |= fail_res->flags; | |
311 | ||
312 | /* | |
313 | * one pref failed resource will set IORESOURCE_MEM, | |
314 | * as we can allocate pref in non-pref range. | |
315 | * Will release all assigned non-pref sibling resources | |
316 | * according to that bit. | |
317 | */ | |
318 | return mask & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH); | |
319 | } | |
320 | ||
321 | static bool pci_need_to_release(unsigned long mask, struct resource *res) | |
322 | { | |
323 | if (res->flags & IORESOURCE_IO) | |
324 | return !!(mask & IORESOURCE_IO); | |
325 | ||
326 | /* check pref at first */ | |
327 | if (res->flags & IORESOURCE_PREFETCH) { | |
328 | if (mask & IORESOURCE_PREFETCH) | |
329 | return true; | |
330 | /* count pref if its parent is non-pref */ | |
331 | else if ((mask & IORESOURCE_MEM) && | |
332 | !(res->parent->flags & IORESOURCE_PREFETCH)) | |
333 | return true; | |
334 | else | |
335 | return false; | |
336 | } | |
337 | ||
338 | if (res->flags & IORESOURCE_MEM) | |
339 | return !!(mask & IORESOURCE_MEM); | |
340 | ||
341 | return false; /* should not get here */ | |
342 | } | |
343 | ||
bdc4abec YL |
344 | static void __assign_resources_sorted(struct list_head *head, |
345 | struct list_head *realloc_head, | |
346 | struct list_head *fail_head) | |
c8adf9a3 | 347 | { |
3e6e0d80 YL |
348 | /* |
349 | * Should not assign requested resources at first. | |
350 | * they could be adjacent, so later reassign can not reallocate | |
351 | * them one by one in parent resource window. | |
367fa982 | 352 | * Try to assign requested + add_size at beginning |
3e6e0d80 YL |
353 | * if could do that, could get out early. |
354 | * if could not do that, we still try to assign requested at first, | |
355 | * then try to reassign add_size for some resources. | |
aa914f5e YL |
356 | * |
357 | * Separate three resource type checking if we need to release | |
358 | * assigned resource after requested + add_size try. | |
359 | * 1. if there is io port assign fail, will release assigned | |
360 | * io port. | |
361 | * 2. if there is pref mmio assign fail, release assigned | |
362 | * pref mmio. | |
363 | * if assigned pref mmio's parent is non-pref mmio and there | |
364 | * is non-pref mmio assign fail, will release that assigned | |
365 | * pref mmio. | |
366 | * 3. if there is non-pref mmio assign fail or pref mmio | |
367 | * assigned fail, will release assigned non-pref mmio. | |
3e6e0d80 | 368 | */ |
bdc4abec YL |
369 | LIST_HEAD(save_head); |
370 | LIST_HEAD(local_fail_head); | |
b9b0bba9 | 371 | struct pci_dev_resource *save_res; |
aa914f5e YL |
372 | struct pci_dev_resource *dev_res, *tmp_res; |
373 | unsigned long fail_type; | |
3e6e0d80 YL |
374 | |
375 | /* Check if optional add_size is there */ | |
bdc4abec | 376 | if (!realloc_head || list_empty(realloc_head)) |
3e6e0d80 YL |
377 | goto requested_and_reassign; |
378 | ||
379 | /* Save original start, end, flags etc at first */ | |
bdc4abec YL |
380 | list_for_each_entry(dev_res, head, list) { |
381 | if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) { | |
bffc56d4 | 382 | free_list(&save_head); |
3e6e0d80 YL |
383 | goto requested_and_reassign; |
384 | } | |
bdc4abec | 385 | } |
3e6e0d80 YL |
386 | |
387 | /* Update res in head list with add_size in realloc_head list */ | |
bdc4abec YL |
388 | list_for_each_entry(dev_res, head, list) |
389 | dev_res->res->end += get_res_add_size(realloc_head, | |
390 | dev_res->res); | |
3e6e0d80 YL |
391 | |
392 | /* Try updated head list with add_size added */ | |
3e6e0d80 YL |
393 | assign_requested_resources_sorted(head, &local_fail_head); |
394 | ||
395 | /* all assigned with add_size ? */ | |
bdc4abec | 396 | if (list_empty(&local_fail_head)) { |
3e6e0d80 | 397 | /* Remove head list from realloc_head list */ |
bdc4abec YL |
398 | list_for_each_entry(dev_res, head, list) |
399 | remove_from_list(realloc_head, dev_res->res); | |
bffc56d4 YL |
400 | free_list(&save_head); |
401 | free_list(head); | |
3e6e0d80 YL |
402 | return; |
403 | } | |
404 | ||
aa914f5e YL |
405 | /* check failed type */ |
406 | fail_type = pci_fail_res_type_mask(&local_fail_head); | |
407 | /* remove not need to be released assigned res from head list etc */ | |
408 | list_for_each_entry_safe(dev_res, tmp_res, head, list) | |
409 | if (dev_res->res->parent && | |
410 | !pci_need_to_release(fail_type, dev_res->res)) { | |
411 | /* remove it from realloc_head list */ | |
412 | remove_from_list(realloc_head, dev_res->res); | |
413 | remove_from_list(&save_head, dev_res->res); | |
414 | list_del(&dev_res->list); | |
415 | kfree(dev_res); | |
416 | } | |
417 | ||
bffc56d4 | 418 | free_list(&local_fail_head); |
3e6e0d80 | 419 | /* Release assigned resource */ |
bdc4abec YL |
420 | list_for_each_entry(dev_res, head, list) |
421 | if (dev_res->res->parent) | |
422 | release_resource(dev_res->res); | |
3e6e0d80 | 423 | /* Restore start/end/flags from saved list */ |
b9b0bba9 YL |
424 | list_for_each_entry(save_res, &save_head, list) { |
425 | struct resource *res = save_res->res; | |
3e6e0d80 | 426 | |
b9b0bba9 YL |
427 | res->start = save_res->start; |
428 | res->end = save_res->end; | |
429 | res->flags = save_res->flags; | |
3e6e0d80 | 430 | } |
bffc56d4 | 431 | free_list(&save_head); |
3e6e0d80 YL |
432 | |
433 | requested_and_reassign: | |
c8adf9a3 RP |
434 | /* Satisfy the must-have resource requests */ |
435 | assign_requested_resources_sorted(head, fail_head); | |
436 | ||
0a2daa1c | 437 | /* Try to satisfy any additional optional resource |
c8adf9a3 | 438 | requests */ |
9e8bf93a RP |
439 | if (realloc_head) |
440 | reassign_resources_sorted(realloc_head, head); | |
bffc56d4 | 441 | free_list(head); |
c8adf9a3 RP |
442 | } |
443 | ||
6841ec68 | 444 | static void pdev_assign_resources_sorted(struct pci_dev *dev, |
bdc4abec YL |
445 | struct list_head *add_head, |
446 | struct list_head *fail_head) | |
6841ec68 | 447 | { |
bdc4abec | 448 | LIST_HEAD(head); |
6841ec68 | 449 | |
6841ec68 | 450 | __dev_sort_resources(dev, &head); |
8424d759 | 451 | __assign_resources_sorted(&head, add_head, fail_head); |
6841ec68 YL |
452 | |
453 | } | |
454 | ||
455 | static void pbus_assign_resources_sorted(const struct pci_bus *bus, | |
bdc4abec YL |
456 | struct list_head *realloc_head, |
457 | struct list_head *fail_head) | |
6841ec68 YL |
458 | { |
459 | struct pci_dev *dev; | |
bdc4abec | 460 | LIST_HEAD(head); |
6841ec68 | 461 | |
6841ec68 YL |
462 | list_for_each_entry(dev, &bus->devices, bus_list) |
463 | __dev_sort_resources(dev, &head); | |
464 | ||
9e8bf93a | 465 | __assign_resources_sorted(&head, realloc_head, fail_head); |
6841ec68 YL |
466 | } |
467 | ||
b3743fa4 | 468 | void pci_setup_cardbus(struct pci_bus *bus) |
1da177e4 LT |
469 | { |
470 | struct pci_dev *bridge = bus->self; | |
c7dabef8 | 471 | struct resource *res; |
1da177e4 LT |
472 | struct pci_bus_region region; |
473 | ||
b918c62e YL |
474 | dev_info(&bridge->dev, "CardBus bridge to %pR\n", |
475 | &bus->busn_res); | |
1da177e4 | 476 | |
c7dabef8 | 477 | res = bus->resource[0]; |
fc279850 | 478 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 | 479 | if (res->flags & IORESOURCE_IO) { |
1da177e4 LT |
480 | /* |
481 | * The IO resource is allocated a range twice as large as it | |
482 | * would normally need. This allows us to set both IO regs. | |
483 | */ | |
c7dabef8 | 484 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
1da177e4 LT |
485 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, |
486 | region.start); | |
487 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0, | |
488 | region.end); | |
489 | } | |
490 | ||
c7dabef8 | 491 | res = bus->resource[1]; |
fc279850 | 492 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 BH |
493 | if (res->flags & IORESOURCE_IO) { |
494 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
495 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, |
496 | region.start); | |
497 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1, | |
498 | region.end); | |
499 | } | |
500 | ||
c7dabef8 | 501 | res = bus->resource[2]; |
fc279850 | 502 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 BH |
503 | if (res->flags & IORESOURCE_MEM) { |
504 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
505 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, |
506 | region.start); | |
507 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0, | |
508 | region.end); | |
509 | } | |
510 | ||
c7dabef8 | 511 | res = bus->resource[3]; |
fc279850 | 512 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 BH |
513 | if (res->flags & IORESOURCE_MEM) { |
514 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
515 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, |
516 | region.start); | |
517 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1, | |
518 | region.end); | |
519 | } | |
520 | } | |
b3743fa4 | 521 | EXPORT_SYMBOL(pci_setup_cardbus); |
1da177e4 LT |
522 | |
523 | /* Initialize bridges with base/limit values we have collected. | |
524 | PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998) | |
525 | requires that if there is no I/O ports or memory behind the | |
526 | bridge, corresponding range must be turned off by writing base | |
527 | value greater than limit to the bridge's base/limit registers. | |
528 | ||
529 | Note: care must be taken when updating I/O base/limit registers | |
530 | of bridges which support 32-bit I/O. This update requires two | |
531 | config space writes, so it's quite possible that an I/O window of | |
532 | the bridge will have some undesirable address (e.g. 0) after the | |
533 | first write. Ditto 64-bit prefetchable MMIO. */ | |
7cc5997d | 534 | static void pci_setup_bridge_io(struct pci_bus *bus) |
1da177e4 LT |
535 | { |
536 | struct pci_dev *bridge = bus->self; | |
c7dabef8 | 537 | struct resource *res; |
1da177e4 | 538 | struct pci_bus_region region; |
2b28ae19 BH |
539 | unsigned long io_mask; |
540 | u8 io_base_lo, io_limit_lo; | |
5b764b83 BH |
541 | u16 l; |
542 | u32 io_upper16; | |
1da177e4 | 543 | |
2b28ae19 BH |
544 | io_mask = PCI_IO_RANGE_MASK; |
545 | if (bridge->io_window_1k) | |
546 | io_mask = PCI_IO_1K_RANGE_MASK; | |
547 | ||
1da177e4 | 548 | /* Set up the top and bottom of the PCI I/O segment for this bus. */ |
c7dabef8 | 549 | res = bus->resource[0]; |
fc279850 | 550 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 | 551 | if (res->flags & IORESOURCE_IO) { |
5b764b83 | 552 | pci_read_config_word(bridge, PCI_IO_BASE, &l); |
2b28ae19 BH |
553 | io_base_lo = (region.start >> 8) & io_mask; |
554 | io_limit_lo = (region.end >> 8) & io_mask; | |
5b764b83 | 555 | l = ((u16) io_limit_lo << 8) | io_base_lo; |
1da177e4 LT |
556 | /* Set up upper 16 bits of I/O base/limit. */ |
557 | io_upper16 = (region.end & 0xffff0000) | (region.start >> 16); | |
c7dabef8 | 558 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 559 | } else { |
1da177e4 LT |
560 | /* Clear upper 16 bits of I/O base/limit. */ |
561 | io_upper16 = 0; | |
562 | l = 0x00f0; | |
1da177e4 LT |
563 | } |
564 | /* Temporarily disable the I/O range before updating PCI_IO_BASE. */ | |
565 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff); | |
566 | /* Update lower 16 bits of I/O base/limit. */ | |
5b764b83 | 567 | pci_write_config_word(bridge, PCI_IO_BASE, l); |
1da177e4 LT |
568 | /* Update upper 16 bits of I/O base/limit. */ |
569 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16); | |
7cc5997d YL |
570 | } |
571 | ||
572 | static void pci_setup_bridge_mmio(struct pci_bus *bus) | |
573 | { | |
574 | struct pci_dev *bridge = bus->self; | |
575 | struct resource *res; | |
576 | struct pci_bus_region region; | |
577 | u32 l; | |
1da177e4 | 578 | |
7cc5997d | 579 | /* Set up the top and bottom of the PCI Memory segment for this bus. */ |
c7dabef8 | 580 | res = bus->resource[1]; |
fc279850 | 581 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 | 582 | if (res->flags & IORESOURCE_MEM) { |
1da177e4 LT |
583 | l = (region.start >> 16) & 0xfff0; |
584 | l |= region.end & 0xfff00000; | |
c7dabef8 | 585 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 586 | } else { |
1da177e4 | 587 | l = 0x0000fff0; |
1da177e4 LT |
588 | } |
589 | pci_write_config_dword(bridge, PCI_MEMORY_BASE, l); | |
7cc5997d YL |
590 | } |
591 | ||
592 | static void pci_setup_bridge_mmio_pref(struct pci_bus *bus) | |
593 | { | |
594 | struct pci_dev *bridge = bus->self; | |
595 | struct resource *res; | |
596 | struct pci_bus_region region; | |
597 | u32 l, bu, lu; | |
1da177e4 LT |
598 | |
599 | /* Clear out the upper 32 bits of PREF limit. | |
600 | If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily | |
601 | disables PREF range, which is ok. */ | |
602 | pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0); | |
603 | ||
604 | /* Set up PREF base/limit. */ | |
c40a22e0 | 605 | bu = lu = 0; |
c7dabef8 | 606 | res = bus->resource[2]; |
fc279850 | 607 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 | 608 | if (res->flags & IORESOURCE_PREFETCH) { |
1da177e4 LT |
609 | l = (region.start >> 16) & 0xfff0; |
610 | l |= region.end & 0xfff00000; | |
c7dabef8 | 611 | if (res->flags & IORESOURCE_MEM_64) { |
1f82de10 YL |
612 | bu = upper_32_bits(region.start); |
613 | lu = upper_32_bits(region.end); | |
1f82de10 | 614 | } |
c7dabef8 | 615 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 616 | } else { |
1da177e4 | 617 | l = 0x0000fff0; |
1da177e4 LT |
618 | } |
619 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l); | |
620 | ||
59353ea3 AW |
621 | /* Set the upper 32 bits of PREF base & limit. */ |
622 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu); | |
623 | pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu); | |
7cc5997d YL |
624 | } |
625 | ||
626 | static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type) | |
627 | { | |
628 | struct pci_dev *bridge = bus->self; | |
629 | ||
b918c62e YL |
630 | dev_info(&bridge->dev, "PCI bridge to %pR\n", |
631 | &bus->busn_res); | |
7cc5997d YL |
632 | |
633 | if (type & IORESOURCE_IO) | |
634 | pci_setup_bridge_io(bus); | |
635 | ||
636 | if (type & IORESOURCE_MEM) | |
637 | pci_setup_bridge_mmio(bus); | |
638 | ||
639 | if (type & IORESOURCE_PREFETCH) | |
640 | pci_setup_bridge_mmio_pref(bus); | |
1da177e4 LT |
641 | |
642 | pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl); | |
643 | } | |
644 | ||
e2444273 | 645 | void pci_setup_bridge(struct pci_bus *bus) |
7cc5997d YL |
646 | { |
647 | unsigned long type = IORESOURCE_IO | IORESOURCE_MEM | | |
648 | IORESOURCE_PREFETCH; | |
649 | ||
650 | __pci_setup_bridge(bus, type); | |
651 | } | |
652 | ||
1da177e4 LT |
653 | /* Check whether the bridge supports optional I/O and |
654 | prefetchable memory ranges. If not, the respective | |
655 | base/limit registers must be read-only and read as 0. */ | |
96bde06a | 656 | static void pci_bridge_check_ranges(struct pci_bus *bus) |
1da177e4 LT |
657 | { |
658 | u16 io; | |
659 | u32 pmem; | |
660 | struct pci_dev *bridge = bus->self; | |
661 | struct resource *b_res; | |
662 | ||
663 | b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; | |
664 | b_res[1].flags |= IORESOURCE_MEM; | |
665 | ||
666 | pci_read_config_word(bridge, PCI_IO_BASE, &io); | |
667 | if (!io) { | |
d2f54d9b | 668 | pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0); |
1da177e4 | 669 | pci_read_config_word(bridge, PCI_IO_BASE, &io); |
f7625980 BH |
670 | pci_write_config_word(bridge, PCI_IO_BASE, 0x0); |
671 | } | |
672 | if (io) | |
1da177e4 | 673 | b_res[0].flags |= IORESOURCE_IO; |
d2f54d9b | 674 | |
1da177e4 LT |
675 | /* DECchip 21050 pass 2 errata: the bridge may miss an address |
676 | disconnect boundary by one PCI data phase. | |
677 | Workaround: do not use prefetching on this device. */ | |
678 | if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) | |
679 | return; | |
d2f54d9b | 680 | |
1da177e4 LT |
681 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); |
682 | if (!pmem) { | |
683 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, | |
d2f54d9b | 684 | 0xffe0fff0); |
1da177e4 LT |
685 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); |
686 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); | |
687 | } | |
1f82de10 | 688 | if (pmem) { |
1da177e4 | 689 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; |
99586105 YL |
690 | if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == |
691 | PCI_PREF_RANGE_TYPE_64) { | |
1f82de10 | 692 | b_res[2].flags |= IORESOURCE_MEM_64; |
99586105 YL |
693 | b_res[2].flags |= PCI_PREF_RANGE_TYPE_64; |
694 | } | |
1f82de10 YL |
695 | } |
696 | ||
697 | /* double check if bridge does support 64 bit pref */ | |
698 | if (b_res[2].flags & IORESOURCE_MEM_64) { | |
699 | u32 mem_base_hi, tmp; | |
700 | pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
701 | &mem_base_hi); | |
702 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
703 | 0xffffffff); | |
704 | pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp); | |
705 | if (!tmp) | |
706 | b_res[2].flags &= ~IORESOURCE_MEM_64; | |
707 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
708 | mem_base_hi); | |
709 | } | |
1da177e4 LT |
710 | } |
711 | ||
712 | /* Helper function for sizing routines: find first available | |
713 | bus resource of a given type. Note: we intentionally skip | |
714 | the bus resources which have already been assigned (that is, | |
715 | have non-NULL parent resource). */ | |
96bde06a | 716 | static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type) |
1da177e4 LT |
717 | { |
718 | int i; | |
719 | struct resource *r; | |
720 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | | |
721 | IORESOURCE_PREFETCH; | |
722 | ||
89a74ecc | 723 | pci_bus_for_each_resource(bus, r, i) { |
299de034 IK |
724 | if (r == &ioport_resource || r == &iomem_resource) |
725 | continue; | |
55a10984 JB |
726 | if (r && (r->flags & type_mask) == type && !r->parent) |
727 | return r; | |
1da177e4 LT |
728 | } |
729 | return NULL; | |
730 | } | |
731 | ||
13583b16 RP |
732 | static resource_size_t calculate_iosize(resource_size_t size, |
733 | resource_size_t min_size, | |
734 | resource_size_t size1, | |
735 | resource_size_t old_size, | |
736 | resource_size_t align) | |
737 | { | |
738 | if (size < min_size) | |
739 | size = min_size; | |
740 | if (old_size == 1 ) | |
741 | old_size = 0; | |
742 | /* To be fixed in 2.5: we should have sort of HAVE_ISA | |
743 | flag in the struct pci_bus. */ | |
744 | #if defined(CONFIG_ISA) || defined(CONFIG_EISA) | |
745 | size = (size & 0xff) + ((size & ~0xffUL) << 2); | |
746 | #endif | |
747 | size = ALIGN(size + size1, align); | |
748 | if (size < old_size) | |
749 | size = old_size; | |
750 | return size; | |
751 | } | |
752 | ||
753 | static resource_size_t calculate_memsize(resource_size_t size, | |
754 | resource_size_t min_size, | |
755 | resource_size_t size1, | |
756 | resource_size_t old_size, | |
757 | resource_size_t align) | |
758 | { | |
759 | if (size < min_size) | |
760 | size = min_size; | |
761 | if (old_size == 1 ) | |
762 | old_size = 0; | |
763 | if (size < old_size) | |
764 | size = old_size; | |
765 | size = ALIGN(size + size1, align); | |
766 | return size; | |
767 | } | |
768 | ||
ac5ad93e GS |
769 | resource_size_t __weak pcibios_window_alignment(struct pci_bus *bus, |
770 | unsigned long type) | |
771 | { | |
772 | return 1; | |
773 | } | |
774 | ||
775 | #define PCI_P2P_DEFAULT_MEM_ALIGN 0x100000 /* 1MiB */ | |
776 | #define PCI_P2P_DEFAULT_IO_ALIGN 0x1000 /* 4KiB */ | |
777 | #define PCI_P2P_DEFAULT_IO_ALIGN_1K 0x400 /* 1KiB */ | |
778 | ||
779 | static resource_size_t window_alignment(struct pci_bus *bus, | |
780 | unsigned long type) | |
781 | { | |
782 | resource_size_t align = 1, arch_align; | |
783 | ||
784 | if (type & IORESOURCE_MEM) | |
785 | align = PCI_P2P_DEFAULT_MEM_ALIGN; | |
786 | else if (type & IORESOURCE_IO) { | |
787 | /* | |
788 | * Per spec, I/O windows are 4K-aligned, but some | |
789 | * bridges have an extension to support 1K alignment. | |
790 | */ | |
791 | if (bus->self->io_window_1k) | |
792 | align = PCI_P2P_DEFAULT_IO_ALIGN_1K; | |
793 | else | |
794 | align = PCI_P2P_DEFAULT_IO_ALIGN; | |
795 | } | |
796 | ||
797 | arch_align = pcibios_window_alignment(bus, type); | |
798 | return max(align, arch_align); | |
799 | } | |
800 | ||
c8adf9a3 RP |
801 | /** |
802 | * pbus_size_io() - size the io window of a given bus | |
803 | * | |
804 | * @bus : the bus | |
805 | * @min_size : the minimum io window that must to be allocated | |
806 | * @add_size : additional optional io window | |
9e8bf93a | 807 | * @realloc_head : track the additional io window on this list |
c8adf9a3 RP |
808 | * |
809 | * Sizing the IO windows of the PCI-PCI bridge is trivial, | |
fd591341 | 810 | * since these windows have 1K or 4K granularity and the IO ranges |
c8adf9a3 RP |
811 | * of non-bridge PCI devices are limited to 256 bytes. |
812 | * We must be careful with the ISA aliasing though. | |
813 | */ | |
814 | static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size, | |
bdc4abec | 815 | resource_size_t add_size, struct list_head *realloc_head) |
1da177e4 LT |
816 | { |
817 | struct pci_dev *dev; | |
818 | struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO); | |
11251a86 | 819 | resource_size_t size = 0, size0 = 0, size1 = 0; |
be768912 | 820 | resource_size_t children_add_size = 0; |
2d1d6678 | 821 | resource_size_t min_align, align; |
1da177e4 LT |
822 | |
823 | if (!b_res) | |
f7625980 | 824 | return; |
1da177e4 | 825 | |
2d1d6678 | 826 | min_align = window_alignment(bus, IORESOURCE_IO); |
1da177e4 LT |
827 | list_for_each_entry(dev, &bus->devices, bus_list) { |
828 | int i; | |
829 | ||
830 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
831 | struct resource *r = &dev->resource[i]; | |
832 | unsigned long r_size; | |
833 | ||
834 | if (r->parent || !(r->flags & IORESOURCE_IO)) | |
835 | continue; | |
022edd86 | 836 | r_size = resource_size(r); |
1da177e4 LT |
837 | |
838 | if (r_size < 0x400) | |
839 | /* Might be re-aligned for ISA */ | |
840 | size += r_size; | |
841 | else | |
842 | size1 += r_size; | |
be768912 | 843 | |
fd591341 YL |
844 | align = pci_resource_alignment(dev, r); |
845 | if (align > min_align) | |
846 | min_align = align; | |
847 | ||
9e8bf93a RP |
848 | if (realloc_head) |
849 | children_add_size += get_res_add_size(realloc_head, r); | |
1da177e4 LT |
850 | } |
851 | } | |
fd591341 | 852 | |
c8adf9a3 | 853 | size0 = calculate_iosize(size, min_size, size1, |
fd591341 | 854 | resource_size(b_res), min_align); |
be768912 YL |
855 | if (children_add_size > add_size) |
856 | add_size = children_add_size; | |
9e8bf93a | 857 | size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 : |
a4ac9fea | 858 | calculate_iosize(size, min_size, add_size + size1, |
fd591341 | 859 | resource_size(b_res), min_align); |
c8adf9a3 | 860 | if (!size0 && !size1) { |
865df576 BH |
861 | if (b_res->start || b_res->end) |
862 | dev_info(&bus->self->dev, "disabling bridge window " | |
b918c62e YL |
863 | "%pR to %pR (unused)\n", b_res, |
864 | &bus->busn_res); | |
1da177e4 LT |
865 | b_res->flags = 0; |
866 | return; | |
867 | } | |
fd591341 YL |
868 | |
869 | b_res->start = min_align; | |
c8adf9a3 | 870 | b_res->end = b_res->start + size0 - 1; |
88452565 | 871 | b_res->flags |= IORESOURCE_STARTALIGN; |
b592443d | 872 | if (size1 > size0 && realloc_head) { |
fd591341 YL |
873 | add_to_list(realloc_head, bus->self, b_res, size1-size0, |
874 | min_align); | |
b592443d | 875 | dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window " |
11251a86 WY |
876 | "%pR to %pR add_size %llx\n", b_res, |
877 | &bus->busn_res, | |
878 | (unsigned long long)size1-size0); | |
b592443d | 879 | } |
1da177e4 LT |
880 | } |
881 | ||
c121504e GS |
882 | static inline resource_size_t calculate_mem_align(resource_size_t *aligns, |
883 | int max_order) | |
884 | { | |
885 | resource_size_t align = 0; | |
886 | resource_size_t min_align = 0; | |
887 | int order; | |
888 | ||
889 | for (order = 0; order <= max_order; order++) { | |
890 | resource_size_t align1 = 1; | |
891 | ||
892 | align1 <<= (order + 20); | |
893 | ||
894 | if (!align) | |
895 | min_align = align1; | |
896 | else if (ALIGN(align + min_align, min_align) < align1) | |
897 | min_align = align1 >> 1; | |
898 | align += aligns[order]; | |
899 | } | |
900 | ||
901 | return min_align; | |
902 | } | |
903 | ||
c8adf9a3 RP |
904 | /** |
905 | * pbus_size_mem() - size the memory window of a given bus | |
906 | * | |
907 | * @bus : the bus | |
496f70cf WY |
908 | * @mask: mask the resource flag, then compare it with type |
909 | * @type: the type of free resource from bridge | |
c8adf9a3 RP |
910 | * @min_size : the minimum memory window that must to be allocated |
911 | * @add_size : additional optional memory window | |
9e8bf93a | 912 | * @realloc_head : track the additional memory window on this list |
c8adf9a3 RP |
913 | * |
914 | * Calculate the size of the bus and minimal alignment which | |
915 | * guarantees that all child resources fit in this size. | |
916 | */ | |
28760489 | 917 | static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, |
c8adf9a3 RP |
918 | unsigned long type, resource_size_t min_size, |
919 | resource_size_t add_size, | |
bdc4abec | 920 | struct list_head *realloc_head) |
1da177e4 LT |
921 | { |
922 | struct pci_dev *dev; | |
c8adf9a3 | 923 | resource_size_t min_align, align, size, size0, size1; |
c40a22e0 | 924 | resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */ |
1da177e4 LT |
925 | int order, max_order; |
926 | struct resource *b_res = find_free_bus_resource(bus, type); | |
1f82de10 | 927 | unsigned int mem64_mask = 0; |
be768912 | 928 | resource_size_t children_add_size = 0; |
1da177e4 LT |
929 | |
930 | if (!b_res) | |
931 | return 0; | |
932 | ||
933 | memset(aligns, 0, sizeof(aligns)); | |
934 | max_order = 0; | |
935 | size = 0; | |
936 | ||
1f82de10 YL |
937 | mem64_mask = b_res->flags & IORESOURCE_MEM_64; |
938 | b_res->flags &= ~IORESOURCE_MEM_64; | |
939 | ||
1da177e4 LT |
940 | list_for_each_entry(dev, &bus->devices, bus_list) { |
941 | int i; | |
1f82de10 | 942 | |
1da177e4 LT |
943 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { |
944 | struct resource *r = &dev->resource[i]; | |
c40a22e0 | 945 | resource_size_t r_size; |
1da177e4 LT |
946 | |
947 | if (r->parent || (r->flags & mask) != type) | |
948 | continue; | |
022edd86 | 949 | r_size = resource_size(r); |
2aceefcb YL |
950 | #ifdef CONFIG_PCI_IOV |
951 | /* put SRIOV requested res to the optional list */ | |
9e8bf93a | 952 | if (realloc_head && i >= PCI_IOV_RESOURCES && |
2aceefcb YL |
953 | i <= PCI_IOV_RESOURCE_END) { |
954 | r->end = r->start - 1; | |
f7625980 | 955 | add_to_list(realloc_head, dev, r, r_size, 0/* don't care */); |
2aceefcb YL |
956 | children_add_size += r_size; |
957 | continue; | |
958 | } | |
959 | #endif | |
1da177e4 | 960 | /* For bridges size != alignment */ |
6faf17f6 | 961 | align = pci_resource_alignment(dev, r); |
1da177e4 LT |
962 | order = __ffs(align) - 20; |
963 | if (order > 11) { | |
865df576 BH |
964 | dev_warn(&dev->dev, "disabling BAR %d: %pR " |
965 | "(bad alignment %#llx)\n", i, r, | |
966 | (unsigned long long) align); | |
1da177e4 LT |
967 | r->flags = 0; |
968 | continue; | |
969 | } | |
970 | size += r_size; | |
971 | if (order < 0) | |
972 | order = 0; | |
973 | /* Exclude ranges with size > align from | |
974 | calculation of the alignment. */ | |
975 | if (r_size == align) | |
976 | aligns[order] += align; | |
977 | if (order > max_order) | |
978 | max_order = order; | |
1f82de10 | 979 | mem64_mask &= r->flags & IORESOURCE_MEM_64; |
be768912 | 980 | |
9e8bf93a RP |
981 | if (realloc_head) |
982 | children_add_size += get_res_add_size(realloc_head, r); | |
1da177e4 LT |
983 | } |
984 | } | |
462d9303 | 985 | |
c121504e | 986 | min_align = calculate_mem_align(aligns, max_order); |
3ad94b0d | 987 | min_align = max(min_align, window_alignment(bus, b_res->flags)); |
b42282e5 | 988 | size0 = calculate_memsize(size, min_size, 0, resource_size(b_res), min_align); |
be768912 YL |
989 | if (children_add_size > add_size) |
990 | add_size = children_add_size; | |
9e8bf93a | 991 | size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 : |
a4ac9fea | 992 | calculate_memsize(size, min_size, add_size, |
b42282e5 | 993 | resource_size(b_res), min_align); |
c8adf9a3 | 994 | if (!size0 && !size1) { |
865df576 BH |
995 | if (b_res->start || b_res->end) |
996 | dev_info(&bus->self->dev, "disabling bridge window " | |
b918c62e YL |
997 | "%pR to %pR (unused)\n", b_res, |
998 | &bus->busn_res); | |
1da177e4 LT |
999 | b_res->flags = 0; |
1000 | return 1; | |
1001 | } | |
1002 | b_res->start = min_align; | |
c8adf9a3 RP |
1003 | b_res->end = size0 + min_align - 1; |
1004 | b_res->flags |= IORESOURCE_STARTALIGN | mem64_mask; | |
b592443d | 1005 | if (size1 > size0 && realloc_head) { |
9e8bf93a | 1006 | add_to_list(realloc_head, bus->self, b_res, size1-size0, min_align); |
b592443d | 1007 | dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window " |
b918c62e YL |
1008 | "%pR to %pR add_size %llx\n", b_res, |
1009 | &bus->busn_res, (unsigned long long)size1-size0); | |
b592443d | 1010 | } |
1da177e4 LT |
1011 | return 1; |
1012 | } | |
1013 | ||
0a2daa1c RP |
1014 | unsigned long pci_cardbus_resource_alignment(struct resource *res) |
1015 | { | |
1016 | if (res->flags & IORESOURCE_IO) | |
1017 | return pci_cardbus_io_size; | |
1018 | if (res->flags & IORESOURCE_MEM) | |
1019 | return pci_cardbus_mem_size; | |
1020 | return 0; | |
1021 | } | |
1022 | ||
1023 | static void pci_bus_size_cardbus(struct pci_bus *bus, | |
bdc4abec | 1024 | struct list_head *realloc_head) |
1da177e4 LT |
1025 | { |
1026 | struct pci_dev *bridge = bus->self; | |
1027 | struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; | |
11848934 | 1028 | resource_size_t b_res_3_size = pci_cardbus_mem_size * 2; |
1da177e4 LT |
1029 | u16 ctrl; |
1030 | ||
3796f1e2 YL |
1031 | if (b_res[0].parent) |
1032 | goto handle_b_res_1; | |
1da177e4 LT |
1033 | /* |
1034 | * Reserve some resources for CardBus. We reserve | |
1035 | * a fixed amount of bus space for CardBus bridges. | |
1036 | */ | |
11848934 YL |
1037 | b_res[0].start = pci_cardbus_io_size; |
1038 | b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1; | |
1039 | b_res[0].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN; | |
1040 | if (realloc_head) { | |
1041 | b_res[0].end -= pci_cardbus_io_size; | |
1042 | add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size, | |
1043 | pci_cardbus_io_size); | |
1044 | } | |
1da177e4 | 1045 | |
3796f1e2 YL |
1046 | handle_b_res_1: |
1047 | if (b_res[1].parent) | |
1048 | goto handle_b_res_2; | |
11848934 YL |
1049 | b_res[1].start = pci_cardbus_io_size; |
1050 | b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1; | |
1051 | b_res[1].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN; | |
1052 | if (realloc_head) { | |
1053 | b_res[1].end -= pci_cardbus_io_size; | |
1054 | add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size, | |
1055 | pci_cardbus_io_size); | |
1056 | } | |
1da177e4 | 1057 | |
3796f1e2 | 1058 | handle_b_res_2: |
dcef0d06 YL |
1059 | /* MEM1 must not be pref mmio */ |
1060 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
1061 | if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) { | |
1062 | ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1; | |
1063 | pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); | |
1064 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
1065 | } | |
1066 | ||
1da177e4 LT |
1067 | /* |
1068 | * Check whether prefetchable memory is supported | |
1069 | * by this bridge. | |
1070 | */ | |
1071 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
1072 | if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) { | |
1073 | ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; | |
1074 | pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); | |
1075 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
1076 | } | |
1077 | ||
3796f1e2 YL |
1078 | if (b_res[2].parent) |
1079 | goto handle_b_res_3; | |
1da177e4 LT |
1080 | /* |
1081 | * If we have prefetchable memory support, allocate | |
1082 | * two regions. Otherwise, allocate one region of | |
1083 | * twice the size. | |
1084 | */ | |
1085 | if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) { | |
11848934 YL |
1086 | b_res[2].start = pci_cardbus_mem_size; |
1087 | b_res[2].end = b_res[2].start + pci_cardbus_mem_size - 1; | |
1088 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | | |
1089 | IORESOURCE_STARTALIGN; | |
1090 | if (realloc_head) { | |
1091 | b_res[2].end -= pci_cardbus_mem_size; | |
1092 | add_to_list(realloc_head, bridge, b_res+2, | |
1093 | pci_cardbus_mem_size, pci_cardbus_mem_size); | |
1094 | } | |
1095 | ||
1096 | /* reduce that to half */ | |
1097 | b_res_3_size = pci_cardbus_mem_size; | |
1098 | } | |
1099 | ||
3796f1e2 YL |
1100 | handle_b_res_3: |
1101 | if (b_res[3].parent) | |
1102 | goto handle_done; | |
11848934 YL |
1103 | b_res[3].start = pci_cardbus_mem_size; |
1104 | b_res[3].end = b_res[3].start + b_res_3_size - 1; | |
1105 | b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN; | |
1106 | if (realloc_head) { | |
1107 | b_res[3].end -= b_res_3_size; | |
1108 | add_to_list(realloc_head, bridge, b_res+3, b_res_3_size, | |
1109 | pci_cardbus_mem_size); | |
1110 | } | |
3796f1e2 YL |
1111 | |
1112 | handle_done: | |
1113 | ; | |
1da177e4 LT |
1114 | } |
1115 | ||
d66ecb72 | 1116 | void __ref __pci_bus_size_bridges(struct pci_bus *bus, |
bdc4abec | 1117 | struct list_head *realloc_head) |
1da177e4 LT |
1118 | { |
1119 | struct pci_dev *dev; | |
1120 | unsigned long mask, prefmask; | |
c8adf9a3 | 1121 | resource_size_t additional_mem_size = 0, additional_io_size = 0; |
1da177e4 LT |
1122 | |
1123 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1124 | struct pci_bus *b = dev->subordinate; | |
1125 | if (!b) | |
1126 | continue; | |
1127 | ||
1128 | switch (dev->class >> 8) { | |
1129 | case PCI_CLASS_BRIDGE_CARDBUS: | |
9e8bf93a | 1130 | pci_bus_size_cardbus(b, realloc_head); |
1da177e4 LT |
1131 | break; |
1132 | ||
1133 | case PCI_CLASS_BRIDGE_PCI: | |
1134 | default: | |
9e8bf93a | 1135 | __pci_bus_size_bridges(b, realloc_head); |
1da177e4 LT |
1136 | break; |
1137 | } | |
1138 | } | |
1139 | ||
1140 | /* The root bus? */ | |
2ba29e27 | 1141 | if (pci_is_root_bus(bus)) |
1da177e4 LT |
1142 | return; |
1143 | ||
1144 | switch (bus->self->class >> 8) { | |
1145 | case PCI_CLASS_BRIDGE_CARDBUS: | |
1146 | /* don't size cardbuses yet. */ | |
1147 | break; | |
1148 | ||
1149 | case PCI_CLASS_BRIDGE_PCI: | |
1150 | pci_bridge_check_ranges(bus); | |
28760489 | 1151 | if (bus->self->is_hotplug_bridge) { |
c8adf9a3 RP |
1152 | additional_io_size = pci_hotplug_io_size; |
1153 | additional_mem_size = pci_hotplug_mem_size; | |
28760489 | 1154 | } |
c8adf9a3 RP |
1155 | /* |
1156 | * Follow thru | |
1157 | */ | |
1da177e4 | 1158 | default: |
19aa7ee4 YL |
1159 | pbus_size_io(bus, realloc_head ? 0 : additional_io_size, |
1160 | additional_io_size, realloc_head); | |
1da177e4 LT |
1161 | /* If the bridge supports prefetchable range, size it |
1162 | separately. If it doesn't, or its prefetchable window | |
1163 | has already been allocated by arch code, try | |
1164 | non-prefetchable range for both types of PCI memory | |
1165 | resources. */ | |
1166 | mask = IORESOURCE_MEM; | |
1167 | prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
19aa7ee4 YL |
1168 | if (pbus_size_mem(bus, prefmask, prefmask, |
1169 | realloc_head ? 0 : additional_mem_size, | |
1170 | additional_mem_size, realloc_head)) | |
1da177e4 | 1171 | mask = prefmask; /* Success, size non-prefetch only. */ |
28760489 | 1172 | else |
c8adf9a3 | 1173 | additional_mem_size += additional_mem_size; |
19aa7ee4 YL |
1174 | pbus_size_mem(bus, mask, IORESOURCE_MEM, |
1175 | realloc_head ? 0 : additional_mem_size, | |
1176 | additional_mem_size, realloc_head); | |
1da177e4 LT |
1177 | break; |
1178 | } | |
1179 | } | |
c8adf9a3 RP |
1180 | |
1181 | void __ref pci_bus_size_bridges(struct pci_bus *bus) | |
1182 | { | |
1183 | __pci_bus_size_bridges(bus, NULL); | |
1184 | } | |
1da177e4 LT |
1185 | EXPORT_SYMBOL(pci_bus_size_bridges); |
1186 | ||
d66ecb72 JL |
1187 | void __ref __pci_bus_assign_resources(const struct pci_bus *bus, |
1188 | struct list_head *realloc_head, | |
1189 | struct list_head *fail_head) | |
1da177e4 LT |
1190 | { |
1191 | struct pci_bus *b; | |
1192 | struct pci_dev *dev; | |
1193 | ||
9e8bf93a | 1194 | pbus_assign_resources_sorted(bus, realloc_head, fail_head); |
1da177e4 | 1195 | |
1da177e4 LT |
1196 | list_for_each_entry(dev, &bus->devices, bus_list) { |
1197 | b = dev->subordinate; | |
1198 | if (!b) | |
1199 | continue; | |
1200 | ||
9e8bf93a | 1201 | __pci_bus_assign_resources(b, realloc_head, fail_head); |
1da177e4 LT |
1202 | |
1203 | switch (dev->class >> 8) { | |
1204 | case PCI_CLASS_BRIDGE_PCI: | |
6841ec68 YL |
1205 | if (!pci_is_enabled(dev)) |
1206 | pci_setup_bridge(b); | |
1da177e4 LT |
1207 | break; |
1208 | ||
1209 | case PCI_CLASS_BRIDGE_CARDBUS: | |
1210 | pci_setup_cardbus(b); | |
1211 | break; | |
1212 | ||
1213 | default: | |
80ccba11 BH |
1214 | dev_info(&dev->dev, "not setting up bridge for bus " |
1215 | "%04x:%02x\n", pci_domain_nr(b), b->number); | |
1da177e4 LT |
1216 | break; |
1217 | } | |
1218 | } | |
1219 | } | |
568ddef8 YL |
1220 | |
1221 | void __ref pci_bus_assign_resources(const struct pci_bus *bus) | |
1222 | { | |
c8adf9a3 | 1223 | __pci_bus_assign_resources(bus, NULL, NULL); |
568ddef8 | 1224 | } |
1da177e4 LT |
1225 | EXPORT_SYMBOL(pci_bus_assign_resources); |
1226 | ||
6841ec68 | 1227 | static void __ref __pci_bridge_assign_resources(const struct pci_dev *bridge, |
bdc4abec YL |
1228 | struct list_head *add_head, |
1229 | struct list_head *fail_head) | |
6841ec68 YL |
1230 | { |
1231 | struct pci_bus *b; | |
1232 | ||
8424d759 YL |
1233 | pdev_assign_resources_sorted((struct pci_dev *)bridge, |
1234 | add_head, fail_head); | |
6841ec68 YL |
1235 | |
1236 | b = bridge->subordinate; | |
1237 | if (!b) | |
1238 | return; | |
1239 | ||
8424d759 | 1240 | __pci_bus_assign_resources(b, add_head, fail_head); |
6841ec68 YL |
1241 | |
1242 | switch (bridge->class >> 8) { | |
1243 | case PCI_CLASS_BRIDGE_PCI: | |
1244 | pci_setup_bridge(b); | |
1245 | break; | |
1246 | ||
1247 | case PCI_CLASS_BRIDGE_CARDBUS: | |
1248 | pci_setup_cardbus(b); | |
1249 | break; | |
1250 | ||
1251 | default: | |
1252 | dev_info(&bridge->dev, "not setting up bridge for bus " | |
1253 | "%04x:%02x\n", pci_domain_nr(b), b->number); | |
1254 | break; | |
1255 | } | |
1256 | } | |
5009b460 YL |
1257 | static void pci_bridge_release_resources(struct pci_bus *bus, |
1258 | unsigned long type) | |
1259 | { | |
1260 | int idx; | |
1261 | bool changed = false; | |
1262 | struct pci_dev *dev; | |
1263 | struct resource *r; | |
1264 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | | |
1265 | IORESOURCE_PREFETCH; | |
1266 | ||
1267 | dev = bus->self; | |
1268 | for (idx = PCI_BRIDGE_RESOURCES; idx <= PCI_BRIDGE_RESOURCE_END; | |
1269 | idx++) { | |
1270 | r = &dev->resource[idx]; | |
1271 | if ((r->flags & type_mask) != type) | |
1272 | continue; | |
1273 | if (!r->parent) | |
1274 | continue; | |
1275 | /* | |
1276 | * if there are children under that, we should release them | |
1277 | * all | |
1278 | */ | |
1279 | release_child_resources(r); | |
1280 | if (!release_resource(r)) { | |
1281 | dev_printk(KERN_DEBUG, &dev->dev, | |
1282 | "resource %d %pR released\n", idx, r); | |
1283 | /* keep the old size */ | |
1284 | r->end = resource_size(r) - 1; | |
1285 | r->start = 0; | |
1286 | r->flags = 0; | |
1287 | changed = true; | |
1288 | } | |
1289 | } | |
1290 | ||
1291 | if (changed) { | |
1292 | /* avoiding touch the one without PREF */ | |
1293 | if (type & IORESOURCE_PREFETCH) | |
1294 | type = IORESOURCE_PREFETCH; | |
1295 | __pci_setup_bridge(bus, type); | |
1296 | } | |
1297 | } | |
1298 | ||
1299 | enum release_type { | |
1300 | leaf_only, | |
1301 | whole_subtree, | |
1302 | }; | |
1303 | /* | |
1304 | * try to release pci bridge resources that is from leaf bridge, | |
1305 | * so we can allocate big new one later | |
1306 | */ | |
1307 | static void __ref pci_bus_release_bridge_resources(struct pci_bus *bus, | |
1308 | unsigned long type, | |
1309 | enum release_type rel_type) | |
1310 | { | |
1311 | struct pci_dev *dev; | |
1312 | bool is_leaf_bridge = true; | |
1313 | ||
1314 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1315 | struct pci_bus *b = dev->subordinate; | |
1316 | if (!b) | |
1317 | continue; | |
1318 | ||
1319 | is_leaf_bridge = false; | |
1320 | ||
1321 | if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) | |
1322 | continue; | |
1323 | ||
1324 | if (rel_type == whole_subtree) | |
1325 | pci_bus_release_bridge_resources(b, type, | |
1326 | whole_subtree); | |
1327 | } | |
1328 | ||
1329 | if (pci_is_root_bus(bus)) | |
1330 | return; | |
1331 | ||
1332 | if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI) | |
1333 | return; | |
1334 | ||
1335 | if ((rel_type == whole_subtree) || is_leaf_bridge) | |
1336 | pci_bridge_release_resources(bus, type); | |
1337 | } | |
1338 | ||
76fbc263 YL |
1339 | static void pci_bus_dump_res(struct pci_bus *bus) |
1340 | { | |
89a74ecc BH |
1341 | struct resource *res; |
1342 | int i; | |
7c9342b8 | 1343 | |
89a74ecc | 1344 | pci_bus_for_each_resource(bus, res, i) { |
7c9342b8 | 1345 | if (!res || !res->end || !res->flags) |
76fbc263 YL |
1346 | continue; |
1347 | ||
c7dabef8 | 1348 | dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res); |
76fbc263 YL |
1349 | } |
1350 | } | |
1351 | ||
1352 | static void pci_bus_dump_resources(struct pci_bus *bus) | |
1353 | { | |
1354 | struct pci_bus *b; | |
1355 | struct pci_dev *dev; | |
1356 | ||
1357 | ||
1358 | pci_bus_dump_res(bus); | |
1359 | ||
1360 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1361 | b = dev->subordinate; | |
1362 | if (!b) | |
1363 | continue; | |
1364 | ||
1365 | pci_bus_dump_resources(b); | |
1366 | } | |
1367 | } | |
1368 | ||
ff35147c | 1369 | static int pci_bus_get_depth(struct pci_bus *bus) |
da7822e5 YL |
1370 | { |
1371 | int depth = 0; | |
f2a230bd | 1372 | struct pci_bus *child_bus; |
da7822e5 | 1373 | |
f2a230bd | 1374 | list_for_each_entry(child_bus, &bus->children, node){ |
da7822e5 | 1375 | int ret; |
da7822e5 | 1376 | |
f2a230bd | 1377 | ret = pci_bus_get_depth(child_bus); |
da7822e5 YL |
1378 | if (ret + 1 > depth) |
1379 | depth = ret + 1; | |
1380 | } | |
1381 | ||
1382 | return depth; | |
1383 | } | |
da7822e5 | 1384 | |
b55438fd YL |
1385 | /* |
1386 | * -1: undefined, will auto detect later | |
1387 | * 0: disabled by user | |
1388 | * 1: disabled by auto detect | |
1389 | * 2: enabled by user | |
1390 | * 3: enabled by auto detect | |
1391 | */ | |
1392 | enum enable_type { | |
1393 | undefined = -1, | |
1394 | user_disabled, | |
1395 | auto_disabled, | |
1396 | user_enabled, | |
1397 | auto_enabled, | |
1398 | }; | |
1399 | ||
ff35147c | 1400 | static enum enable_type pci_realloc_enable = undefined; |
b55438fd YL |
1401 | void __init pci_realloc_get_opt(char *str) |
1402 | { | |
1403 | if (!strncmp(str, "off", 3)) | |
1404 | pci_realloc_enable = user_disabled; | |
1405 | else if (!strncmp(str, "on", 2)) | |
1406 | pci_realloc_enable = user_enabled; | |
1407 | } | |
ff35147c | 1408 | static bool pci_realloc_enabled(enum enable_type enable) |
b55438fd | 1409 | { |
967260cd | 1410 | return enable >= user_enabled; |
b55438fd | 1411 | } |
f483d392 | 1412 | |
b07f2ebc | 1413 | #if defined(CONFIG_PCI_IOV) && defined(CONFIG_PCI_REALLOC_ENABLE_AUTO) |
ff35147c | 1414 | static int iov_resources_unassigned(struct pci_dev *dev, void *data) |
223d96fc YL |
1415 | { |
1416 | int i; | |
1417 | bool *unassigned = data; | |
b07f2ebc | 1418 | |
223d96fc YL |
1419 | for (i = PCI_IOV_RESOURCES; i <= PCI_IOV_RESOURCE_END; i++) { |
1420 | struct resource *r = &dev->resource[i]; | |
fa216bf4 | 1421 | struct pci_bus_region region; |
b07f2ebc | 1422 | |
223d96fc | 1423 | /* Not assigned or rejected by kernel? */ |
fa216bf4 YL |
1424 | if (!r->flags) |
1425 | continue; | |
b07f2ebc | 1426 | |
fc279850 | 1427 | pcibios_resource_to_bus(dev->bus, ®ion, r); |
fa216bf4 | 1428 | if (!region.start) { |
223d96fc YL |
1429 | *unassigned = true; |
1430 | return 1; /* return early from pci_walk_bus() */ | |
b07f2ebc YL |
1431 | } |
1432 | } | |
b07f2ebc | 1433 | |
223d96fc | 1434 | return 0; |
b07f2ebc YL |
1435 | } |
1436 | ||
ff35147c | 1437 | static enum enable_type pci_realloc_detect(struct pci_bus *bus, |
967260cd | 1438 | enum enable_type enable_local) |
223d96fc YL |
1439 | { |
1440 | bool unassigned = false; | |
b07f2ebc | 1441 | |
967260cd YL |
1442 | if (enable_local != undefined) |
1443 | return enable_local; | |
223d96fc | 1444 | |
967260cd YL |
1445 | pci_walk_bus(bus, iov_resources_unassigned, &unassigned); |
1446 | if (unassigned) | |
1447 | return auto_enabled; | |
1448 | ||
1449 | return enable_local; | |
b07f2ebc | 1450 | } |
223d96fc | 1451 | #else |
ff35147c | 1452 | static enum enable_type pci_realloc_detect(struct pci_bus *bus, |
967260cd YL |
1453 | enum enable_type enable_local) |
1454 | { | |
1455 | return enable_local; | |
b07f2ebc | 1456 | } |
223d96fc | 1457 | #endif |
b07f2ebc | 1458 | |
da7822e5 YL |
1459 | /* |
1460 | * first try will not touch pci bridge res | |
f7625980 BH |
1461 | * second and later try will clear small leaf bridge res |
1462 | * will stop till to the max depth if can not find good one | |
da7822e5 | 1463 | */ |
39772038 | 1464 | void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus) |
1da177e4 | 1465 | { |
bdc4abec | 1466 | LIST_HEAD(realloc_head); /* list of resources that |
c8adf9a3 | 1467 | want additional resources */ |
bdc4abec | 1468 | struct list_head *add_list = NULL; |
da7822e5 YL |
1469 | int tried_times = 0; |
1470 | enum release_type rel_type = leaf_only; | |
bdc4abec | 1471 | LIST_HEAD(fail_head); |
b9b0bba9 | 1472 | struct pci_dev_resource *fail_res; |
da7822e5 YL |
1473 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | |
1474 | IORESOURCE_PREFETCH; | |
19aa7ee4 | 1475 | int pci_try_num = 1; |
55ed83a6 | 1476 | enum enable_type enable_local; |
da7822e5 | 1477 | |
19aa7ee4 | 1478 | /* don't realloc if asked to do so */ |
55ed83a6 | 1479 | enable_local = pci_realloc_detect(bus, pci_realloc_enable); |
967260cd | 1480 | if (pci_realloc_enabled(enable_local)) { |
55ed83a6 | 1481 | int max_depth = pci_bus_get_depth(bus); |
19aa7ee4 YL |
1482 | |
1483 | pci_try_num = max_depth + 1; | |
55ed83a6 YL |
1484 | dev_printk(KERN_DEBUG, &bus->dev, |
1485 | "max bus depth: %d pci_try_num: %d\n", | |
1486 | max_depth, pci_try_num); | |
19aa7ee4 | 1487 | } |
da7822e5 YL |
1488 | |
1489 | again: | |
19aa7ee4 YL |
1490 | /* |
1491 | * last try will use add_list, otherwise will try good to have as | |
1492 | * must have, so can realloc parent bridge resource | |
1493 | */ | |
1494 | if (tried_times + 1 == pci_try_num) | |
bdc4abec | 1495 | add_list = &realloc_head; |
1da177e4 LT |
1496 | /* Depth first, calculate sizes and alignments of all |
1497 | subordinate buses. */ | |
55ed83a6 | 1498 | __pci_bus_size_bridges(bus, add_list); |
c8adf9a3 | 1499 | |
1da177e4 | 1500 | /* Depth last, allocate resources and update the hardware. */ |
55ed83a6 | 1501 | __pci_bus_assign_resources(bus, add_list, &fail_head); |
19aa7ee4 | 1502 | if (add_list) |
bdc4abec | 1503 | BUG_ON(!list_empty(add_list)); |
da7822e5 YL |
1504 | tried_times++; |
1505 | ||
1506 | /* any device complain? */ | |
bdc4abec | 1507 | if (list_empty(&fail_head)) |
928bea96 | 1508 | goto dump; |
f483d392 | 1509 | |
0c5be0cb | 1510 | if (tried_times >= pci_try_num) { |
967260cd | 1511 | if (enable_local == undefined) |
55ed83a6 | 1512 | dev_info(&bus->dev, "Some PCI device resources are unassigned, try booting with pci=realloc\n"); |
967260cd | 1513 | else if (enable_local == auto_enabled) |
55ed83a6 | 1514 | dev_info(&bus->dev, "Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n"); |
eb572e7c | 1515 | |
bffc56d4 | 1516 | free_list(&fail_head); |
928bea96 | 1517 | goto dump; |
da7822e5 YL |
1518 | } |
1519 | ||
55ed83a6 YL |
1520 | dev_printk(KERN_DEBUG, &bus->dev, |
1521 | "No. %d try to assign unassigned res\n", tried_times + 1); | |
da7822e5 YL |
1522 | |
1523 | /* third times and later will not check if it is leaf */ | |
1524 | if ((tried_times + 1) > 2) | |
1525 | rel_type = whole_subtree; | |
1526 | ||
1527 | /* | |
1528 | * Try to release leaf bridge's resources that doesn't fit resource of | |
1529 | * child device under that bridge | |
1530 | */ | |
61e83cdd YL |
1531 | list_for_each_entry(fail_res, &fail_head, list) |
1532 | pci_bus_release_bridge_resources(fail_res->dev->bus, | |
b9b0bba9 | 1533 | fail_res->flags & type_mask, |
bdc4abec | 1534 | rel_type); |
61e83cdd | 1535 | |
da7822e5 | 1536 | /* restore size and flags */ |
b9b0bba9 YL |
1537 | list_for_each_entry(fail_res, &fail_head, list) { |
1538 | struct resource *res = fail_res->res; | |
da7822e5 | 1539 | |
b9b0bba9 YL |
1540 | res->start = fail_res->start; |
1541 | res->end = fail_res->end; | |
1542 | res->flags = fail_res->flags; | |
1543 | if (fail_res->dev->subordinate) | |
da7822e5 | 1544 | res->flags = 0; |
da7822e5 | 1545 | } |
bffc56d4 | 1546 | free_list(&fail_head); |
da7822e5 YL |
1547 | |
1548 | goto again; | |
1549 | ||
928bea96 | 1550 | dump: |
76fbc263 | 1551 | /* dump the resource on buses */ |
55ed83a6 YL |
1552 | pci_bus_dump_resources(bus); |
1553 | } | |
1554 | ||
1555 | void __init pci_assign_unassigned_resources(void) | |
1556 | { | |
1557 | struct pci_bus *root_bus; | |
1558 | ||
1559 | list_for_each_entry(root_bus, &pci_root_buses, node) | |
1560 | pci_assign_unassigned_root_bus_resources(root_bus); | |
1da177e4 | 1561 | } |
6841ec68 YL |
1562 | |
1563 | void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge) | |
1564 | { | |
1565 | struct pci_bus *parent = bridge->subordinate; | |
bdc4abec | 1566 | LIST_HEAD(add_list); /* list of resources that |
8424d759 | 1567 | want additional resources */ |
32180e40 | 1568 | int tried_times = 0; |
bdc4abec | 1569 | LIST_HEAD(fail_head); |
b9b0bba9 | 1570 | struct pci_dev_resource *fail_res; |
6841ec68 | 1571 | int retval; |
32180e40 YL |
1572 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | |
1573 | IORESOURCE_PREFETCH; | |
1574 | ||
32180e40 | 1575 | again: |
8424d759 | 1576 | __pci_bus_size_bridges(parent, &add_list); |
bdc4abec YL |
1577 | __pci_bridge_assign_resources(bridge, &add_list, &fail_head); |
1578 | BUG_ON(!list_empty(&add_list)); | |
32180e40 YL |
1579 | tried_times++; |
1580 | ||
bdc4abec | 1581 | if (list_empty(&fail_head)) |
3f579c34 | 1582 | goto enable_all; |
32180e40 YL |
1583 | |
1584 | if (tried_times >= 2) { | |
1585 | /* still fail, don't need to try more */ | |
bffc56d4 | 1586 | free_list(&fail_head); |
3f579c34 | 1587 | goto enable_all; |
32180e40 YL |
1588 | } |
1589 | ||
1590 | printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n", | |
1591 | tried_times + 1); | |
1592 | ||
1593 | /* | |
1594 | * Try to release leaf bridge's resources that doesn't fit resource of | |
1595 | * child device under that bridge | |
1596 | */ | |
61e83cdd YL |
1597 | list_for_each_entry(fail_res, &fail_head, list) |
1598 | pci_bus_release_bridge_resources(fail_res->dev->bus, | |
1599 | fail_res->flags & type_mask, | |
32180e40 | 1600 | whole_subtree); |
61e83cdd | 1601 | |
32180e40 | 1602 | /* restore size and flags */ |
b9b0bba9 YL |
1603 | list_for_each_entry(fail_res, &fail_head, list) { |
1604 | struct resource *res = fail_res->res; | |
32180e40 | 1605 | |
b9b0bba9 YL |
1606 | res->start = fail_res->start; |
1607 | res->end = fail_res->end; | |
1608 | res->flags = fail_res->flags; | |
1609 | if (fail_res->dev->subordinate) | |
32180e40 | 1610 | res->flags = 0; |
32180e40 | 1611 | } |
bffc56d4 | 1612 | free_list(&fail_head); |
32180e40 YL |
1613 | |
1614 | goto again; | |
3f579c34 YL |
1615 | |
1616 | enable_all: | |
1617 | retval = pci_reenable_device(bridge); | |
9fc9eea0 BH |
1618 | if (retval) |
1619 | dev_err(&bridge->dev, "Error reenabling bridge (%d)\n", retval); | |
3f579c34 | 1620 | pci_set_master(bridge); |
6841ec68 YL |
1621 | } |
1622 | EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources); | |
9b03088f | 1623 | |
17787940 | 1624 | void pci_assign_unassigned_bus_resources(struct pci_bus *bus) |
9b03088f | 1625 | { |
9b03088f | 1626 | struct pci_dev *dev; |
bdc4abec | 1627 | LIST_HEAD(add_list); /* list of resources that |
9b03088f YL |
1628 | want additional resources */ |
1629 | ||
9b03088f YL |
1630 | down_read(&pci_bus_sem); |
1631 | list_for_each_entry(dev, &bus->devices, bus_list) | |
1632 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || | |
1633 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) | |
1634 | if (dev->subordinate) | |
1635 | __pci_bus_size_bridges(dev->subordinate, | |
1636 | &add_list); | |
1637 | up_read(&pci_bus_sem); | |
1638 | __pci_bus_assign_resources(bus, &add_list, NULL); | |
bdc4abec | 1639 | BUG_ON(!list_empty(&add_list)); |
17787940 | 1640 | } |