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Commit | Line | Data |
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7328c8f4 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1da177e4 | 2 | /* |
df62ab5e | 3 | * Support routines for initializing a PCI subsystem |
1da177e4 LT |
4 | * |
5 | * Extruded from code written by | |
6 | * Dave Rusling (david.rusling@reo.mts.dec.com) | |
7 | * David Mosberger (davidm@cs.arizona.edu) | |
8 | * David Miller (davem@redhat.com) | |
9 | * | |
1da177e4 LT |
10 | * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> |
11 | * PCI-PCI bridges cleanup, sorted resource allocation. | |
12 | * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru> | |
13 | * Converted to allocation in 3 passes, which gives | |
14 | * tighter packing. Prefetchable range support. | |
15 | */ | |
16 | ||
17 | #include <linux/init.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/pci.h> | |
21 | #include <linux/errno.h> | |
22 | #include <linux/ioport.h> | |
23 | #include <linux/cache.h> | |
24 | #include <linux/slab.h> | |
584c5c42 | 25 | #include <linux/acpi.h> |
6faf17f6 | 26 | #include "pci.h" |
1da177e4 | 27 | |
844393f4 | 28 | unsigned int pci_flags; |
47087700 | 29 | |
bdc4abec YL |
30 | struct pci_dev_resource { |
31 | struct list_head list; | |
2934a0de YL |
32 | struct resource *res; |
33 | struct pci_dev *dev; | |
568ddef8 YL |
34 | resource_size_t start; |
35 | resource_size_t end; | |
c8adf9a3 | 36 | resource_size_t add_size; |
2bbc6942 | 37 | resource_size_t min_align; |
568ddef8 YL |
38 | unsigned long flags; |
39 | }; | |
40 | ||
bffc56d4 YL |
41 | static void free_list(struct list_head *head) |
42 | { | |
43 | struct pci_dev_resource *dev_res, *tmp; | |
44 | ||
45 | list_for_each_entry_safe(dev_res, tmp, head, list) { | |
46 | list_del(&dev_res->list); | |
47 | kfree(dev_res); | |
48 | } | |
49 | } | |
094732a5 | 50 | |
c8adf9a3 RP |
51 | /** |
52 | * add_to_list() - add a new resource tracker to the list | |
53 | * @head: Head of the list | |
54 | * @dev: device corresponding to which the resource | |
55 | * belongs | |
56 | * @res: The resource to be tracked | |
57 | * @add_size: additional size to be optionally added | |
58 | * to the resource | |
59 | */ | |
bdc4abec | 60 | static int add_to_list(struct list_head *head, |
c8adf9a3 | 61 | struct pci_dev *dev, struct resource *res, |
2bbc6942 | 62 | resource_size_t add_size, resource_size_t min_align) |
568ddef8 | 63 | { |
764242a0 | 64 | struct pci_dev_resource *tmp; |
568ddef8 | 65 | |
bdc4abec | 66 | tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); |
c7abb235 | 67 | if (!tmp) |
ef62dfef | 68 | return -ENOMEM; |
568ddef8 | 69 | |
568ddef8 YL |
70 | tmp->res = res; |
71 | tmp->dev = dev; | |
72 | tmp->start = res->start; | |
73 | tmp->end = res->end; | |
74 | tmp->flags = res->flags; | |
c8adf9a3 | 75 | tmp->add_size = add_size; |
2bbc6942 | 76 | tmp->min_align = min_align; |
bdc4abec YL |
77 | |
78 | list_add(&tmp->list, head); | |
ef62dfef YL |
79 | |
80 | return 0; | |
568ddef8 YL |
81 | } |
82 | ||
b9b0bba9 | 83 | static void remove_from_list(struct list_head *head, |
3e6e0d80 YL |
84 | struct resource *res) |
85 | { | |
b9b0bba9 | 86 | struct pci_dev_resource *dev_res, *tmp; |
3e6e0d80 | 87 | |
b9b0bba9 YL |
88 | list_for_each_entry_safe(dev_res, tmp, head, list) { |
89 | if (dev_res->res == res) { | |
90 | list_del(&dev_res->list); | |
91 | kfree(dev_res); | |
bdc4abec | 92 | break; |
3e6e0d80 | 93 | } |
3e6e0d80 YL |
94 | } |
95 | } | |
96 | ||
d74b9027 WY |
97 | static struct pci_dev_resource *res_to_dev_res(struct list_head *head, |
98 | struct resource *res) | |
1c372353 | 99 | { |
b9b0bba9 | 100 | struct pci_dev_resource *dev_res; |
bdc4abec | 101 | |
b9b0bba9 | 102 | list_for_each_entry(dev_res, head, list) { |
25e77388 | 103 | if (dev_res->res == res) |
d74b9027 | 104 | return dev_res; |
3e6e0d80 | 105 | } |
1c372353 | 106 | |
d74b9027 | 107 | return NULL; |
1c372353 YL |
108 | } |
109 | ||
d74b9027 WY |
110 | static resource_size_t get_res_add_size(struct list_head *head, |
111 | struct resource *res) | |
112 | { | |
113 | struct pci_dev_resource *dev_res; | |
114 | ||
115 | dev_res = res_to_dev_res(head, res); | |
116 | return dev_res ? dev_res->add_size : 0; | |
117 | } | |
118 | ||
119 | static resource_size_t get_res_add_align(struct list_head *head, | |
120 | struct resource *res) | |
121 | { | |
122 | struct pci_dev_resource *dev_res; | |
123 | ||
124 | dev_res = res_to_dev_res(head, res); | |
125 | return dev_res ? dev_res->min_align : 0; | |
126 | } | |
127 | ||
128 | ||
78c3b329 | 129 | /* Sort resources by alignment */ |
bdc4abec | 130 | static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head) |
78c3b329 YL |
131 | { |
132 | int i; | |
133 | ||
134 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
135 | struct resource *r; | |
bdc4abec | 136 | struct pci_dev_resource *dev_res, *tmp; |
78c3b329 | 137 | resource_size_t r_align; |
bdc4abec | 138 | struct list_head *n; |
78c3b329 YL |
139 | |
140 | r = &dev->resource[i]; | |
141 | ||
142 | if (r->flags & IORESOURCE_PCI_FIXED) | |
143 | continue; | |
144 | ||
145 | if (!(r->flags) || r->parent) | |
146 | continue; | |
147 | ||
148 | r_align = pci_resource_alignment(dev, r); | |
149 | if (!r_align) { | |
7506dc79 | 150 | pci_warn(dev, "BAR %d: %pR has bogus alignment\n", |
78c3b329 YL |
151 | i, r); |
152 | continue; | |
153 | } | |
78c3b329 | 154 | |
bdc4abec YL |
155 | tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); |
156 | if (!tmp) | |
227f0647 | 157 | panic("pdev_sort_resources(): kmalloc() failed!\n"); |
bdc4abec YL |
158 | tmp->res = r; |
159 | tmp->dev = dev; | |
160 | ||
161 | /* fallback is smallest one or list is empty*/ | |
162 | n = head; | |
163 | list_for_each_entry(dev_res, head, list) { | |
164 | resource_size_t align; | |
165 | ||
166 | align = pci_resource_alignment(dev_res->dev, | |
167 | dev_res->res); | |
78c3b329 YL |
168 | |
169 | if (r_align > align) { | |
bdc4abec | 170 | n = &dev_res->list; |
78c3b329 YL |
171 | break; |
172 | } | |
173 | } | |
bdc4abec YL |
174 | /* Insert it just before n*/ |
175 | list_add_tail(&tmp->list, n); | |
78c3b329 YL |
176 | } |
177 | } | |
178 | ||
6841ec68 | 179 | static void __dev_sort_resources(struct pci_dev *dev, |
bdc4abec | 180 | struct list_head *head) |
1da177e4 | 181 | { |
6841ec68 | 182 | u16 class = dev->class >> 8; |
1da177e4 | 183 | |
6841ec68 YL |
184 | /* Don't touch classless devices or host bridges or ioapics. */ |
185 | if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST) | |
186 | return; | |
1da177e4 | 187 | |
6841ec68 YL |
188 | /* Don't touch ioapic devices already enabled by firmware */ |
189 | if (class == PCI_CLASS_SYSTEM_PIC) { | |
190 | u16 command; | |
191 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
192 | if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | |
193 | return; | |
194 | } | |
1da177e4 | 195 | |
6841ec68 YL |
196 | pdev_sort_resources(dev, head); |
197 | } | |
23186279 | 198 | |
fc075e1d RP |
199 | static inline void reset_resource(struct resource *res) |
200 | { | |
201 | res->start = 0; | |
202 | res->end = 0; | |
203 | res->flags = 0; | |
204 | } | |
205 | ||
c8adf9a3 | 206 | /** |
9e8bf93a | 207 | * reassign_resources_sorted() - satisfy any additional resource requests |
c8adf9a3 | 208 | * |
9e8bf93a | 209 | * @realloc_head : head of the list tracking requests requiring additional |
c8adf9a3 RP |
210 | * resources |
211 | * @head : head of the list tracking requests with allocated | |
212 | * resources | |
213 | * | |
9e8bf93a | 214 | * Walk through each element of the realloc_head and try to procure |
c8adf9a3 RP |
215 | * additional resources for the element, provided the element |
216 | * is in the head list. | |
217 | */ | |
bdc4abec YL |
218 | static void reassign_resources_sorted(struct list_head *realloc_head, |
219 | struct list_head *head) | |
6841ec68 YL |
220 | { |
221 | struct resource *res; | |
b9b0bba9 | 222 | struct pci_dev_resource *add_res, *tmp; |
bdc4abec | 223 | struct pci_dev_resource *dev_res; |
d74b9027 | 224 | resource_size_t add_size, align; |
6841ec68 | 225 | int idx; |
1da177e4 | 226 | |
b9b0bba9 | 227 | list_for_each_entry_safe(add_res, tmp, realloc_head, list) { |
bdc4abec YL |
228 | bool found_match = false; |
229 | ||
b9b0bba9 | 230 | res = add_res->res; |
c8adf9a3 RP |
231 | /* skip resource that has been reset */ |
232 | if (!res->flags) | |
233 | goto out; | |
234 | ||
235 | /* skip this resource if not found in head list */ | |
bdc4abec YL |
236 | list_for_each_entry(dev_res, head, list) { |
237 | if (dev_res->res == res) { | |
238 | found_match = true; | |
239 | break; | |
240 | } | |
c8adf9a3 | 241 | } |
bdc4abec YL |
242 | if (!found_match)/* just skip */ |
243 | continue; | |
c8adf9a3 | 244 | |
b9b0bba9 YL |
245 | idx = res - &add_res->dev->resource[0]; |
246 | add_size = add_res->add_size; | |
d74b9027 | 247 | align = add_res->min_align; |
2bbc6942 | 248 | if (!resource_size(res)) { |
d74b9027 | 249 | res->start = align; |
2bbc6942 | 250 | res->end = res->start + add_size - 1; |
b9b0bba9 | 251 | if (pci_assign_resource(add_res->dev, idx)) |
c8adf9a3 | 252 | reset_resource(res); |
2bbc6942 | 253 | } else { |
b9b0bba9 | 254 | res->flags |= add_res->flags & |
bdc4abec | 255 | (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN); |
b9b0bba9 | 256 | if (pci_reassign_resource(add_res->dev, idx, |
bdc4abec | 257 | add_size, align)) |
7506dc79 | 258 | pci_printk(KERN_DEBUG, add_res->dev, |
b592443d YL |
259 | "failed to add %llx res[%d]=%pR\n", |
260 | (unsigned long long)add_size, | |
261 | idx, res); | |
c8adf9a3 RP |
262 | } |
263 | out: | |
b9b0bba9 YL |
264 | list_del(&add_res->list); |
265 | kfree(add_res); | |
c8adf9a3 RP |
266 | } |
267 | } | |
268 | ||
269 | /** | |
270 | * assign_requested_resources_sorted() - satisfy resource requests | |
271 | * | |
272 | * @head : head of the list tracking requests for resources | |
8356aad4 | 273 | * @fail_head : head of the list tracking requests that could |
c8adf9a3 RP |
274 | * not be allocated |
275 | * | |
276 | * Satisfy resource requests of each element in the list. Add | |
277 | * requests that could not satisfied to the failed_list. | |
278 | */ | |
bdc4abec YL |
279 | static void assign_requested_resources_sorted(struct list_head *head, |
280 | struct list_head *fail_head) | |
c8adf9a3 RP |
281 | { |
282 | struct resource *res; | |
bdc4abec | 283 | struct pci_dev_resource *dev_res; |
c8adf9a3 | 284 | int idx; |
9a928660 | 285 | |
bdc4abec YL |
286 | list_for_each_entry(dev_res, head, list) { |
287 | res = dev_res->res; | |
288 | idx = res - &dev_res->dev->resource[0]; | |
289 | if (resource_size(res) && | |
290 | pci_assign_resource(dev_res->dev, idx)) { | |
a3cb999d | 291 | if (fail_head) { |
9a928660 YL |
292 | /* |
293 | * if the failed res is for ROM BAR, and it will | |
294 | * be enabled later, don't add it to the list | |
295 | */ | |
296 | if (!((idx == PCI_ROM_RESOURCE) && | |
297 | (!(res->flags & IORESOURCE_ROM_ENABLE)))) | |
67cc7e26 YL |
298 | add_to_list(fail_head, |
299 | dev_res->dev, res, | |
f7625980 BH |
300 | 0 /* don't care */, |
301 | 0 /* don't care */); | |
9a928660 | 302 | } |
fc075e1d | 303 | reset_resource(res); |
542df5de | 304 | } |
1da177e4 LT |
305 | } |
306 | } | |
307 | ||
aa914f5e YL |
308 | static unsigned long pci_fail_res_type_mask(struct list_head *fail_head) |
309 | { | |
310 | struct pci_dev_resource *fail_res; | |
311 | unsigned long mask = 0; | |
312 | ||
313 | /* check failed type */ | |
314 | list_for_each_entry(fail_res, fail_head, list) | |
315 | mask |= fail_res->flags; | |
316 | ||
317 | /* | |
318 | * one pref failed resource will set IORESOURCE_MEM, | |
319 | * as we can allocate pref in non-pref range. | |
320 | * Will release all assigned non-pref sibling resources | |
321 | * according to that bit. | |
322 | */ | |
323 | return mask & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH); | |
324 | } | |
325 | ||
326 | static bool pci_need_to_release(unsigned long mask, struct resource *res) | |
327 | { | |
328 | if (res->flags & IORESOURCE_IO) | |
329 | return !!(mask & IORESOURCE_IO); | |
330 | ||
331 | /* check pref at first */ | |
332 | if (res->flags & IORESOURCE_PREFETCH) { | |
333 | if (mask & IORESOURCE_PREFETCH) | |
334 | return true; | |
335 | /* count pref if its parent is non-pref */ | |
336 | else if ((mask & IORESOURCE_MEM) && | |
337 | !(res->parent->flags & IORESOURCE_PREFETCH)) | |
338 | return true; | |
339 | else | |
340 | return false; | |
341 | } | |
342 | ||
343 | if (res->flags & IORESOURCE_MEM) | |
344 | return !!(mask & IORESOURCE_MEM); | |
345 | ||
346 | return false; /* should not get here */ | |
347 | } | |
348 | ||
bdc4abec YL |
349 | static void __assign_resources_sorted(struct list_head *head, |
350 | struct list_head *realloc_head, | |
351 | struct list_head *fail_head) | |
c8adf9a3 | 352 | { |
3e6e0d80 YL |
353 | /* |
354 | * Should not assign requested resources at first. | |
355 | * they could be adjacent, so later reassign can not reallocate | |
356 | * them one by one in parent resource window. | |
367fa982 | 357 | * Try to assign requested + add_size at beginning |
3e6e0d80 YL |
358 | * if could do that, could get out early. |
359 | * if could not do that, we still try to assign requested at first, | |
360 | * then try to reassign add_size for some resources. | |
aa914f5e YL |
361 | * |
362 | * Separate three resource type checking if we need to release | |
363 | * assigned resource after requested + add_size try. | |
364 | * 1. if there is io port assign fail, will release assigned | |
365 | * io port. | |
366 | * 2. if there is pref mmio assign fail, release assigned | |
367 | * pref mmio. | |
368 | * if assigned pref mmio's parent is non-pref mmio and there | |
369 | * is non-pref mmio assign fail, will release that assigned | |
370 | * pref mmio. | |
371 | * 3. if there is non-pref mmio assign fail or pref mmio | |
372 | * assigned fail, will release assigned non-pref mmio. | |
3e6e0d80 | 373 | */ |
bdc4abec YL |
374 | LIST_HEAD(save_head); |
375 | LIST_HEAD(local_fail_head); | |
b9b0bba9 | 376 | struct pci_dev_resource *save_res; |
d74b9027 | 377 | struct pci_dev_resource *dev_res, *tmp_res, *dev_res2; |
aa914f5e | 378 | unsigned long fail_type; |
d74b9027 | 379 | resource_size_t add_align, align; |
3e6e0d80 YL |
380 | |
381 | /* Check if optional add_size is there */ | |
bdc4abec | 382 | if (!realloc_head || list_empty(realloc_head)) |
3e6e0d80 YL |
383 | goto requested_and_reassign; |
384 | ||
385 | /* Save original start, end, flags etc at first */ | |
bdc4abec YL |
386 | list_for_each_entry(dev_res, head, list) { |
387 | if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) { | |
bffc56d4 | 388 | free_list(&save_head); |
3e6e0d80 YL |
389 | goto requested_and_reassign; |
390 | } | |
bdc4abec | 391 | } |
3e6e0d80 YL |
392 | |
393 | /* Update res in head list with add_size in realloc_head list */ | |
d74b9027 | 394 | list_for_each_entry_safe(dev_res, tmp_res, head, list) { |
bdc4abec YL |
395 | dev_res->res->end += get_res_add_size(realloc_head, |
396 | dev_res->res); | |
3e6e0d80 | 397 | |
d74b9027 WY |
398 | /* |
399 | * There are two kinds of additional resources in the list: | |
400 | * 1. bridge resource -- IORESOURCE_STARTALIGN | |
401 | * 2. SR-IOV resource -- IORESOURCE_SIZEALIGN | |
402 | * Here just fix the additional alignment for bridge | |
403 | */ | |
404 | if (!(dev_res->res->flags & IORESOURCE_STARTALIGN)) | |
405 | continue; | |
406 | ||
407 | add_align = get_res_add_align(realloc_head, dev_res->res); | |
408 | ||
409 | /* | |
410 | * The "head" list is sorted by the alignment to make sure | |
411 | * resources with bigger alignment will be assigned first. | |
412 | * After we change the alignment of a dev_res in "head" list, | |
413 | * we need to reorder the list by alignment to make it | |
414 | * consistent. | |
415 | */ | |
416 | if (add_align > dev_res->res->start) { | |
552bc94e YL |
417 | resource_size_t r_size = resource_size(dev_res->res); |
418 | ||
d74b9027 | 419 | dev_res->res->start = add_align; |
552bc94e | 420 | dev_res->res->end = add_align + r_size - 1; |
d74b9027 WY |
421 | |
422 | list_for_each_entry(dev_res2, head, list) { | |
423 | align = pci_resource_alignment(dev_res2->dev, | |
424 | dev_res2->res); | |
a6b65983 | 425 | if (add_align > align) { |
d74b9027 WY |
426 | list_move_tail(&dev_res->list, |
427 | &dev_res2->list); | |
a6b65983 WY |
428 | break; |
429 | } | |
d74b9027 | 430 | } |
ff3ce480 | 431 | } |
d74b9027 WY |
432 | |
433 | } | |
434 | ||
3e6e0d80 | 435 | /* Try updated head list with add_size added */ |
3e6e0d80 YL |
436 | assign_requested_resources_sorted(head, &local_fail_head); |
437 | ||
438 | /* all assigned with add_size ? */ | |
bdc4abec | 439 | if (list_empty(&local_fail_head)) { |
3e6e0d80 | 440 | /* Remove head list from realloc_head list */ |
bdc4abec YL |
441 | list_for_each_entry(dev_res, head, list) |
442 | remove_from_list(realloc_head, dev_res->res); | |
bffc56d4 YL |
443 | free_list(&save_head); |
444 | free_list(head); | |
3e6e0d80 YL |
445 | return; |
446 | } | |
447 | ||
aa914f5e YL |
448 | /* check failed type */ |
449 | fail_type = pci_fail_res_type_mask(&local_fail_head); | |
450 | /* remove not need to be released assigned res from head list etc */ | |
451 | list_for_each_entry_safe(dev_res, tmp_res, head, list) | |
452 | if (dev_res->res->parent && | |
453 | !pci_need_to_release(fail_type, dev_res->res)) { | |
454 | /* remove it from realloc_head list */ | |
455 | remove_from_list(realloc_head, dev_res->res); | |
456 | remove_from_list(&save_head, dev_res->res); | |
457 | list_del(&dev_res->list); | |
458 | kfree(dev_res); | |
459 | } | |
460 | ||
bffc56d4 | 461 | free_list(&local_fail_head); |
3e6e0d80 | 462 | /* Release assigned resource */ |
bdc4abec YL |
463 | list_for_each_entry(dev_res, head, list) |
464 | if (dev_res->res->parent) | |
465 | release_resource(dev_res->res); | |
3e6e0d80 | 466 | /* Restore start/end/flags from saved list */ |
b9b0bba9 YL |
467 | list_for_each_entry(save_res, &save_head, list) { |
468 | struct resource *res = save_res->res; | |
3e6e0d80 | 469 | |
b9b0bba9 YL |
470 | res->start = save_res->start; |
471 | res->end = save_res->end; | |
472 | res->flags = save_res->flags; | |
3e6e0d80 | 473 | } |
bffc56d4 | 474 | free_list(&save_head); |
3e6e0d80 YL |
475 | |
476 | requested_and_reassign: | |
c8adf9a3 RP |
477 | /* Satisfy the must-have resource requests */ |
478 | assign_requested_resources_sorted(head, fail_head); | |
479 | ||
0a2daa1c | 480 | /* Try to satisfy any additional optional resource |
c8adf9a3 | 481 | requests */ |
9e8bf93a RP |
482 | if (realloc_head) |
483 | reassign_resources_sorted(realloc_head, head); | |
bffc56d4 | 484 | free_list(head); |
c8adf9a3 RP |
485 | } |
486 | ||
6841ec68 | 487 | static void pdev_assign_resources_sorted(struct pci_dev *dev, |
bdc4abec YL |
488 | struct list_head *add_head, |
489 | struct list_head *fail_head) | |
6841ec68 | 490 | { |
bdc4abec | 491 | LIST_HEAD(head); |
6841ec68 | 492 | |
6841ec68 | 493 | __dev_sort_resources(dev, &head); |
8424d759 | 494 | __assign_resources_sorted(&head, add_head, fail_head); |
6841ec68 YL |
495 | |
496 | } | |
497 | ||
498 | static void pbus_assign_resources_sorted(const struct pci_bus *bus, | |
bdc4abec YL |
499 | struct list_head *realloc_head, |
500 | struct list_head *fail_head) | |
6841ec68 YL |
501 | { |
502 | struct pci_dev *dev; | |
bdc4abec | 503 | LIST_HEAD(head); |
6841ec68 | 504 | |
6841ec68 YL |
505 | list_for_each_entry(dev, &bus->devices, bus_list) |
506 | __dev_sort_resources(dev, &head); | |
507 | ||
9e8bf93a | 508 | __assign_resources_sorted(&head, realloc_head, fail_head); |
6841ec68 YL |
509 | } |
510 | ||
b3743fa4 | 511 | void pci_setup_cardbus(struct pci_bus *bus) |
1da177e4 LT |
512 | { |
513 | struct pci_dev *bridge = bus->self; | |
c7dabef8 | 514 | struct resource *res; |
1da177e4 LT |
515 | struct pci_bus_region region; |
516 | ||
7506dc79 | 517 | pci_info(bridge, "CardBus bridge to %pR\n", |
b918c62e | 518 | &bus->busn_res); |
1da177e4 | 519 | |
c7dabef8 | 520 | res = bus->resource[0]; |
fc279850 | 521 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 | 522 | if (res->flags & IORESOURCE_IO) { |
1da177e4 LT |
523 | /* |
524 | * The IO resource is allocated a range twice as large as it | |
525 | * would normally need. This allows us to set both IO regs. | |
526 | */ | |
7506dc79 | 527 | pci_info(bridge, " bridge window %pR\n", res); |
1da177e4 LT |
528 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, |
529 | region.start); | |
530 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0, | |
531 | region.end); | |
532 | } | |
533 | ||
c7dabef8 | 534 | res = bus->resource[1]; |
fc279850 | 535 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 | 536 | if (res->flags & IORESOURCE_IO) { |
7506dc79 | 537 | pci_info(bridge, " bridge window %pR\n", res); |
1da177e4 LT |
538 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, |
539 | region.start); | |
540 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1, | |
541 | region.end); | |
542 | } | |
543 | ||
c7dabef8 | 544 | res = bus->resource[2]; |
fc279850 | 545 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 | 546 | if (res->flags & IORESOURCE_MEM) { |
7506dc79 | 547 | pci_info(bridge, " bridge window %pR\n", res); |
1da177e4 LT |
548 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, |
549 | region.start); | |
550 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0, | |
551 | region.end); | |
552 | } | |
553 | ||
c7dabef8 | 554 | res = bus->resource[3]; |
fc279850 | 555 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 | 556 | if (res->flags & IORESOURCE_MEM) { |
7506dc79 | 557 | pci_info(bridge, " bridge window %pR\n", res); |
1da177e4 LT |
558 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, |
559 | region.start); | |
560 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1, | |
561 | region.end); | |
562 | } | |
563 | } | |
b3743fa4 | 564 | EXPORT_SYMBOL(pci_setup_cardbus); |
1da177e4 LT |
565 | |
566 | /* Initialize bridges with base/limit values we have collected. | |
567 | PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998) | |
568 | requires that if there is no I/O ports or memory behind the | |
569 | bridge, corresponding range must be turned off by writing base | |
570 | value greater than limit to the bridge's base/limit registers. | |
571 | ||
572 | Note: care must be taken when updating I/O base/limit registers | |
573 | of bridges which support 32-bit I/O. This update requires two | |
574 | config space writes, so it's quite possible that an I/O window of | |
575 | the bridge will have some undesirable address (e.g. 0) after the | |
576 | first write. Ditto 64-bit prefetchable MMIO. */ | |
3f2f4dc4 | 577 | static void pci_setup_bridge_io(struct pci_dev *bridge) |
1da177e4 | 578 | { |
c7dabef8 | 579 | struct resource *res; |
1da177e4 | 580 | struct pci_bus_region region; |
2b28ae19 BH |
581 | unsigned long io_mask; |
582 | u8 io_base_lo, io_limit_lo; | |
5b764b83 BH |
583 | u16 l; |
584 | u32 io_upper16; | |
1da177e4 | 585 | |
2b28ae19 BH |
586 | io_mask = PCI_IO_RANGE_MASK; |
587 | if (bridge->io_window_1k) | |
588 | io_mask = PCI_IO_1K_RANGE_MASK; | |
589 | ||
1da177e4 | 590 | /* Set up the top and bottom of the PCI I/O segment for this bus. */ |
3f2f4dc4 | 591 | res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0]; |
fc279850 | 592 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 | 593 | if (res->flags & IORESOURCE_IO) { |
5b764b83 | 594 | pci_read_config_word(bridge, PCI_IO_BASE, &l); |
2b28ae19 BH |
595 | io_base_lo = (region.start >> 8) & io_mask; |
596 | io_limit_lo = (region.end >> 8) & io_mask; | |
5b764b83 | 597 | l = ((u16) io_limit_lo << 8) | io_base_lo; |
1da177e4 LT |
598 | /* Set up upper 16 bits of I/O base/limit. */ |
599 | io_upper16 = (region.end & 0xffff0000) | (region.start >> 16); | |
7506dc79 | 600 | pci_info(bridge, " bridge window %pR\n", res); |
7cc5997d | 601 | } else { |
1da177e4 LT |
602 | /* Clear upper 16 bits of I/O base/limit. */ |
603 | io_upper16 = 0; | |
604 | l = 0x00f0; | |
1da177e4 LT |
605 | } |
606 | /* Temporarily disable the I/O range before updating PCI_IO_BASE. */ | |
607 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff); | |
608 | /* Update lower 16 bits of I/O base/limit. */ | |
5b764b83 | 609 | pci_write_config_word(bridge, PCI_IO_BASE, l); |
1da177e4 LT |
610 | /* Update upper 16 bits of I/O base/limit. */ |
611 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16); | |
7cc5997d YL |
612 | } |
613 | ||
3f2f4dc4 | 614 | static void pci_setup_bridge_mmio(struct pci_dev *bridge) |
7cc5997d | 615 | { |
7cc5997d YL |
616 | struct resource *res; |
617 | struct pci_bus_region region; | |
618 | u32 l; | |
1da177e4 | 619 | |
7cc5997d | 620 | /* Set up the top and bottom of the PCI Memory segment for this bus. */ |
3f2f4dc4 | 621 | res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1]; |
fc279850 | 622 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 | 623 | if (res->flags & IORESOURCE_MEM) { |
1da177e4 LT |
624 | l = (region.start >> 16) & 0xfff0; |
625 | l |= region.end & 0xfff00000; | |
7506dc79 | 626 | pci_info(bridge, " bridge window %pR\n", res); |
7cc5997d | 627 | } else { |
1da177e4 | 628 | l = 0x0000fff0; |
1da177e4 LT |
629 | } |
630 | pci_write_config_dword(bridge, PCI_MEMORY_BASE, l); | |
7cc5997d YL |
631 | } |
632 | ||
3f2f4dc4 | 633 | static void pci_setup_bridge_mmio_pref(struct pci_dev *bridge) |
7cc5997d | 634 | { |
7cc5997d YL |
635 | struct resource *res; |
636 | struct pci_bus_region region; | |
637 | u32 l, bu, lu; | |
1da177e4 LT |
638 | |
639 | /* Clear out the upper 32 bits of PREF limit. | |
640 | If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily | |
641 | disables PREF range, which is ok. */ | |
642 | pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0); | |
643 | ||
644 | /* Set up PREF base/limit. */ | |
c40a22e0 | 645 | bu = lu = 0; |
3f2f4dc4 | 646 | res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2]; |
fc279850 | 647 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 | 648 | if (res->flags & IORESOURCE_PREFETCH) { |
1da177e4 LT |
649 | l = (region.start >> 16) & 0xfff0; |
650 | l |= region.end & 0xfff00000; | |
c7dabef8 | 651 | if (res->flags & IORESOURCE_MEM_64) { |
1f82de10 YL |
652 | bu = upper_32_bits(region.start); |
653 | lu = upper_32_bits(region.end); | |
1f82de10 | 654 | } |
7506dc79 | 655 | pci_info(bridge, " bridge window %pR\n", res); |
7cc5997d | 656 | } else { |
1da177e4 | 657 | l = 0x0000fff0; |
1da177e4 LT |
658 | } |
659 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l); | |
660 | ||
59353ea3 AW |
661 | /* Set the upper 32 bits of PREF base & limit. */ |
662 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu); | |
663 | pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu); | |
7cc5997d YL |
664 | } |
665 | ||
666 | static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type) | |
667 | { | |
668 | struct pci_dev *bridge = bus->self; | |
669 | ||
7506dc79 | 670 | pci_info(bridge, "PCI bridge to %pR\n", |
b918c62e | 671 | &bus->busn_res); |
7cc5997d YL |
672 | |
673 | if (type & IORESOURCE_IO) | |
3f2f4dc4 | 674 | pci_setup_bridge_io(bridge); |
7cc5997d YL |
675 | |
676 | if (type & IORESOURCE_MEM) | |
3f2f4dc4 | 677 | pci_setup_bridge_mmio(bridge); |
7cc5997d YL |
678 | |
679 | if (type & IORESOURCE_PREFETCH) | |
3f2f4dc4 | 680 | pci_setup_bridge_mmio_pref(bridge); |
1da177e4 LT |
681 | |
682 | pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl); | |
683 | } | |
684 | ||
d366d28c GS |
685 | void __weak pcibios_setup_bridge(struct pci_bus *bus, unsigned long type) |
686 | { | |
687 | } | |
688 | ||
e2444273 | 689 | void pci_setup_bridge(struct pci_bus *bus) |
7cc5997d YL |
690 | { |
691 | unsigned long type = IORESOURCE_IO | IORESOURCE_MEM | | |
692 | IORESOURCE_PREFETCH; | |
693 | ||
d366d28c | 694 | pcibios_setup_bridge(bus, type); |
7cc5997d YL |
695 | __pci_setup_bridge(bus, type); |
696 | } | |
697 | ||
8505e729 YL |
698 | |
699 | int pci_claim_bridge_resource(struct pci_dev *bridge, int i) | |
700 | { | |
701 | if (i < PCI_BRIDGE_RESOURCES || i > PCI_BRIDGE_RESOURCE_END) | |
702 | return 0; | |
703 | ||
704 | if (pci_claim_resource(bridge, i) == 0) | |
705 | return 0; /* claimed the window */ | |
706 | ||
707 | if ((bridge->class >> 8) != PCI_CLASS_BRIDGE_PCI) | |
708 | return 0; | |
709 | ||
710 | if (!pci_bus_clip_resource(bridge, i)) | |
711 | return -EINVAL; /* clipping didn't change anything */ | |
712 | ||
713 | switch (i - PCI_BRIDGE_RESOURCES) { | |
714 | case 0: | |
715 | pci_setup_bridge_io(bridge); | |
716 | break; | |
717 | case 1: | |
718 | pci_setup_bridge_mmio(bridge); | |
719 | break; | |
720 | case 2: | |
721 | pci_setup_bridge_mmio_pref(bridge); | |
722 | break; | |
723 | default: | |
724 | return -EINVAL; | |
725 | } | |
726 | ||
727 | if (pci_claim_resource(bridge, i) == 0) | |
728 | return 0; /* claimed a smaller window */ | |
729 | ||
730 | return -EINVAL; | |
731 | } | |
732 | ||
1da177e4 LT |
733 | /* Check whether the bridge supports optional I/O and |
734 | prefetchable memory ranges. If not, the respective | |
735 | base/limit registers must be read-only and read as 0. */ | |
96bde06a | 736 | static void pci_bridge_check_ranges(struct pci_bus *bus) |
1da177e4 | 737 | { |
1da177e4 | 738 | struct pci_dev *bridge = bus->self; |
51c48b31 | 739 | struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; |
1da177e4 | 740 | |
1da177e4 LT |
741 | b_res[1].flags |= IORESOURCE_MEM; |
742 | ||
51c48b31 | 743 | if (bridge->io_window) |
1da177e4 | 744 | b_res[0].flags |= IORESOURCE_IO; |
d2f54d9b | 745 | |
51c48b31 | 746 | if (bridge->pref_window) { |
1da177e4 | 747 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; |
51c48b31 | 748 | if (bridge->pref_64_window) { |
1f82de10 | 749 | b_res[2].flags |= IORESOURCE_MEM_64; |
99586105 YL |
750 | b_res[2].flags |= PCI_PREF_RANGE_TYPE_64; |
751 | } | |
1f82de10 | 752 | } |
1da177e4 LT |
753 | } |
754 | ||
755 | /* Helper function for sizing routines: find first available | |
756 | bus resource of a given type. Note: we intentionally skip | |
757 | the bus resources which have already been assigned (that is, | |
758 | have non-NULL parent resource). */ | |
5b285415 YL |
759 | static struct resource *find_free_bus_resource(struct pci_bus *bus, |
760 | unsigned long type_mask, unsigned long type) | |
1da177e4 LT |
761 | { |
762 | int i; | |
763 | struct resource *r; | |
1da177e4 | 764 | |
89a74ecc | 765 | pci_bus_for_each_resource(bus, r, i) { |
299de034 IK |
766 | if (r == &ioport_resource || r == &iomem_resource) |
767 | continue; | |
55a10984 JB |
768 | if (r && (r->flags & type_mask) == type && !r->parent) |
769 | return r; | |
1da177e4 LT |
770 | } |
771 | return NULL; | |
772 | } | |
773 | ||
13583b16 RP |
774 | static resource_size_t calculate_iosize(resource_size_t size, |
775 | resource_size_t min_size, | |
776 | resource_size_t size1, | |
de3ffa30 JD |
777 | resource_size_t add_size, |
778 | resource_size_t children_add_size, | |
13583b16 RP |
779 | resource_size_t old_size, |
780 | resource_size_t align) | |
781 | { | |
782 | if (size < min_size) | |
783 | size = min_size; | |
3c78bc61 | 784 | if (old_size == 1) |
13583b16 RP |
785 | old_size = 0; |
786 | /* To be fixed in 2.5: we should have sort of HAVE_ISA | |
787 | flag in the struct pci_bus. */ | |
788 | #if defined(CONFIG_ISA) || defined(CONFIG_EISA) | |
789 | size = (size & 0xff) + ((size & ~0xffUL) << 2); | |
790 | #endif | |
de3ffa30 | 791 | size = size + size1; |
13583b16 RP |
792 | if (size < old_size) |
793 | size = old_size; | |
de3ffa30 JD |
794 | |
795 | size = ALIGN(max(size, add_size) + children_add_size, align); | |
13583b16 RP |
796 | return size; |
797 | } | |
798 | ||
799 | static resource_size_t calculate_memsize(resource_size_t size, | |
800 | resource_size_t min_size, | |
de3ffa30 JD |
801 | resource_size_t add_size, |
802 | resource_size_t children_add_size, | |
13583b16 RP |
803 | resource_size_t old_size, |
804 | resource_size_t align) | |
805 | { | |
806 | if (size < min_size) | |
807 | size = min_size; | |
3c78bc61 | 808 | if (old_size == 1) |
13583b16 RP |
809 | old_size = 0; |
810 | if (size < old_size) | |
811 | size = old_size; | |
de3ffa30 JD |
812 | |
813 | size = ALIGN(max(size, add_size) + children_add_size, align); | |
13583b16 RP |
814 | return size; |
815 | } | |
816 | ||
ac5ad93e GS |
817 | resource_size_t __weak pcibios_window_alignment(struct pci_bus *bus, |
818 | unsigned long type) | |
819 | { | |
820 | return 1; | |
821 | } | |
822 | ||
823 | #define PCI_P2P_DEFAULT_MEM_ALIGN 0x100000 /* 1MiB */ | |
824 | #define PCI_P2P_DEFAULT_IO_ALIGN 0x1000 /* 4KiB */ | |
825 | #define PCI_P2P_DEFAULT_IO_ALIGN_1K 0x400 /* 1KiB */ | |
826 | ||
827 | static resource_size_t window_alignment(struct pci_bus *bus, | |
828 | unsigned long type) | |
829 | { | |
830 | resource_size_t align = 1, arch_align; | |
831 | ||
832 | if (type & IORESOURCE_MEM) | |
833 | align = PCI_P2P_DEFAULT_MEM_ALIGN; | |
834 | else if (type & IORESOURCE_IO) { | |
835 | /* | |
836 | * Per spec, I/O windows are 4K-aligned, but some | |
837 | * bridges have an extension to support 1K alignment. | |
838 | */ | |
839 | if (bus->self->io_window_1k) | |
840 | align = PCI_P2P_DEFAULT_IO_ALIGN_1K; | |
841 | else | |
842 | align = PCI_P2P_DEFAULT_IO_ALIGN; | |
843 | } | |
844 | ||
845 | arch_align = pcibios_window_alignment(bus, type); | |
846 | return max(align, arch_align); | |
847 | } | |
848 | ||
c8adf9a3 RP |
849 | /** |
850 | * pbus_size_io() - size the io window of a given bus | |
851 | * | |
852 | * @bus : the bus | |
853 | * @min_size : the minimum io window that must to be allocated | |
854 | * @add_size : additional optional io window | |
9e8bf93a | 855 | * @realloc_head : track the additional io window on this list |
c8adf9a3 RP |
856 | * |
857 | * Sizing the IO windows of the PCI-PCI bridge is trivial, | |
fd591341 | 858 | * since these windows have 1K or 4K granularity and the IO ranges |
c8adf9a3 RP |
859 | * of non-bridge PCI devices are limited to 256 bytes. |
860 | * We must be careful with the ISA aliasing though. | |
861 | */ | |
862 | static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size, | |
bdc4abec | 863 | resource_size_t add_size, struct list_head *realloc_head) |
1da177e4 LT |
864 | { |
865 | struct pci_dev *dev; | |
5b285415 YL |
866 | struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO, |
867 | IORESOURCE_IO); | |
11251a86 | 868 | resource_size_t size = 0, size0 = 0, size1 = 0; |
be768912 | 869 | resource_size_t children_add_size = 0; |
2d1d6678 | 870 | resource_size_t min_align, align; |
1da177e4 LT |
871 | |
872 | if (!b_res) | |
f7625980 | 873 | return; |
1da177e4 | 874 | |
2d1d6678 | 875 | min_align = window_alignment(bus, IORESOURCE_IO); |
1da177e4 LT |
876 | list_for_each_entry(dev, &bus->devices, bus_list) { |
877 | int i; | |
878 | ||
879 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
880 | struct resource *r = &dev->resource[i]; | |
881 | unsigned long r_size; | |
882 | ||
883 | if (r->parent || !(r->flags & IORESOURCE_IO)) | |
884 | continue; | |
022edd86 | 885 | r_size = resource_size(r); |
1da177e4 LT |
886 | |
887 | if (r_size < 0x400) | |
888 | /* Might be re-aligned for ISA */ | |
889 | size += r_size; | |
890 | else | |
891 | size1 += r_size; | |
be768912 | 892 | |
fd591341 YL |
893 | align = pci_resource_alignment(dev, r); |
894 | if (align > min_align) | |
895 | min_align = align; | |
896 | ||
9e8bf93a RP |
897 | if (realloc_head) |
898 | children_add_size += get_res_add_size(realloc_head, r); | |
1da177e4 LT |
899 | } |
900 | } | |
fd591341 | 901 | |
de3ffa30 | 902 | size0 = calculate_iosize(size, min_size, size1, 0, 0, |
fd591341 | 903 | resource_size(b_res), min_align); |
de3ffa30 JD |
904 | size1 = (!realloc_head || (realloc_head && !add_size && !children_add_size)) ? size0 : |
905 | calculate_iosize(size, min_size, size1, add_size, children_add_size, | |
fd591341 | 906 | resource_size(b_res), min_align); |
c8adf9a3 | 907 | if (!size0 && !size1) { |
865df576 | 908 | if (b_res->start || b_res->end) |
7506dc79 | 909 | pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n", |
227f0647 | 910 | b_res, &bus->busn_res); |
1da177e4 LT |
911 | b_res->flags = 0; |
912 | return; | |
913 | } | |
fd591341 YL |
914 | |
915 | b_res->start = min_align; | |
c8adf9a3 | 916 | b_res->end = b_res->start + size0 - 1; |
88452565 | 917 | b_res->flags |= IORESOURCE_STARTALIGN; |
b592443d | 918 | if (size1 > size0 && realloc_head) { |
fd591341 YL |
919 | add_to_list(realloc_head, bus->self, b_res, size1-size0, |
920 | min_align); | |
7506dc79 | 921 | pci_printk(KERN_DEBUG, bus->self, "bridge window %pR to %pR add_size %llx\n", |
227f0647 RD |
922 | b_res, &bus->busn_res, |
923 | (unsigned long long)size1-size0); | |
b592443d | 924 | } |
1da177e4 LT |
925 | } |
926 | ||
c121504e GS |
927 | static inline resource_size_t calculate_mem_align(resource_size_t *aligns, |
928 | int max_order) | |
929 | { | |
930 | resource_size_t align = 0; | |
931 | resource_size_t min_align = 0; | |
932 | int order; | |
933 | ||
934 | for (order = 0; order <= max_order; order++) { | |
935 | resource_size_t align1 = 1; | |
936 | ||
937 | align1 <<= (order + 20); | |
938 | ||
939 | if (!align) | |
940 | min_align = align1; | |
941 | else if (ALIGN(align + min_align, min_align) < align1) | |
942 | min_align = align1 >> 1; | |
943 | align += aligns[order]; | |
944 | } | |
945 | ||
946 | return min_align; | |
947 | } | |
948 | ||
c8adf9a3 RP |
949 | /** |
950 | * pbus_size_mem() - size the memory window of a given bus | |
951 | * | |
952 | * @bus : the bus | |
496f70cf WY |
953 | * @mask: mask the resource flag, then compare it with type |
954 | * @type: the type of free resource from bridge | |
5b285415 YL |
955 | * @type2: second match type |
956 | * @type3: third match type | |
c8adf9a3 RP |
957 | * @min_size : the minimum memory window that must to be allocated |
958 | * @add_size : additional optional memory window | |
9e8bf93a | 959 | * @realloc_head : track the additional memory window on this list |
c8adf9a3 RP |
960 | * |
961 | * Calculate the size of the bus and minimal alignment which | |
962 | * guarantees that all child resources fit in this size. | |
30afe8d0 BH |
963 | * |
964 | * Returns -ENOSPC if there's no available bus resource of the desired type. | |
965 | * Otherwise, sets the bus resource start/end to indicate the required | |
966 | * size, adds things to realloc_head (if supplied), and returns 0. | |
c8adf9a3 | 967 | */ |
28760489 | 968 | static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, |
5b285415 YL |
969 | unsigned long type, unsigned long type2, |
970 | unsigned long type3, | |
971 | resource_size_t min_size, resource_size_t add_size, | |
972 | struct list_head *realloc_head) | |
1da177e4 LT |
973 | { |
974 | struct pci_dev *dev; | |
c8adf9a3 | 975 | resource_size_t min_align, align, size, size0, size1; |
096d4221 | 976 | resource_size_t aligns[18]; /* Alignments from 1Mb to 128Gb */ |
1da177e4 | 977 | int order, max_order; |
5b285415 YL |
978 | struct resource *b_res = find_free_bus_resource(bus, |
979 | mask | IORESOURCE_PREFETCH, type); | |
be768912 | 980 | resource_size_t children_add_size = 0; |
d74b9027 WY |
981 | resource_size_t children_add_align = 0; |
982 | resource_size_t add_align = 0; | |
1da177e4 LT |
983 | |
984 | if (!b_res) | |
30afe8d0 | 985 | return -ENOSPC; |
1da177e4 LT |
986 | |
987 | memset(aligns, 0, sizeof(aligns)); | |
988 | max_order = 0; | |
989 | size = 0; | |
990 | ||
991 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
992 | int i; | |
1f82de10 | 993 | |
1da177e4 LT |
994 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { |
995 | struct resource *r = &dev->resource[i]; | |
c40a22e0 | 996 | resource_size_t r_size; |
1da177e4 | 997 | |
a2220d80 DD |
998 | if (r->parent || (r->flags & IORESOURCE_PCI_FIXED) || |
999 | ((r->flags & mask) != type && | |
1000 | (r->flags & mask) != type2 && | |
1001 | (r->flags & mask) != type3)) | |
1da177e4 | 1002 | continue; |
022edd86 | 1003 | r_size = resource_size(r); |
2aceefcb YL |
1004 | #ifdef CONFIG_PCI_IOV |
1005 | /* put SRIOV requested res to the optional list */ | |
9e8bf93a | 1006 | if (realloc_head && i >= PCI_IOV_RESOURCES && |
2aceefcb | 1007 | i <= PCI_IOV_RESOURCE_END) { |
d74b9027 | 1008 | add_align = max(pci_resource_alignment(dev, r), add_align); |
2aceefcb | 1009 | r->end = r->start - 1; |
f7625980 | 1010 | add_to_list(realloc_head, dev, r, r_size, 0/* don't care */); |
2aceefcb YL |
1011 | children_add_size += r_size; |
1012 | continue; | |
1013 | } | |
1014 | #endif | |
14c8530d A |
1015 | /* |
1016 | * aligns[0] is for 1MB (since bridge memory | |
1017 | * windows are always at least 1MB aligned), so | |
1018 | * keep "order" from being negative for smaller | |
1019 | * resources. | |
1020 | */ | |
6faf17f6 | 1021 | align = pci_resource_alignment(dev, r); |
1da177e4 | 1022 | order = __ffs(align) - 20; |
14c8530d A |
1023 | if (order < 0) |
1024 | order = 0; | |
1025 | if (order >= ARRAY_SIZE(aligns)) { | |
7506dc79 | 1026 | pci_warn(dev, "disabling BAR %d: %pR (bad alignment %#llx)\n", |
227f0647 | 1027 | i, r, (unsigned long long) align); |
1da177e4 LT |
1028 | r->flags = 0; |
1029 | continue; | |
1030 | } | |
c9c75143 | 1031 | size += max(r_size, align); |
1da177e4 LT |
1032 | /* Exclude ranges with size > align from |
1033 | calculation of the alignment. */ | |
c9c75143 | 1034 | if (r_size <= align) |
1da177e4 LT |
1035 | aligns[order] += align; |
1036 | if (order > max_order) | |
1037 | max_order = order; | |
be768912 | 1038 | |
d74b9027 | 1039 | if (realloc_head) { |
9e8bf93a | 1040 | children_add_size += get_res_add_size(realloc_head, r); |
d74b9027 WY |
1041 | children_add_align = get_res_add_align(realloc_head, r); |
1042 | add_align = max(add_align, children_add_align); | |
1043 | } | |
1da177e4 LT |
1044 | } |
1045 | } | |
462d9303 | 1046 | |
c121504e | 1047 | min_align = calculate_mem_align(aligns, max_order); |
3ad94b0d | 1048 | min_align = max(min_align, window_alignment(bus, b_res->flags)); |
de3ffa30 | 1049 | size0 = calculate_memsize(size, min_size, 0, 0, resource_size(b_res), min_align); |
d74b9027 | 1050 | add_align = max(min_align, add_align); |
de3ffa30 JD |
1051 | size1 = (!realloc_head || (realloc_head && !add_size && !children_add_size)) ? size0 : |
1052 | calculate_memsize(size, min_size, add_size, children_add_size, | |
d74b9027 | 1053 | resource_size(b_res), add_align); |
c8adf9a3 | 1054 | if (!size0 && !size1) { |
865df576 | 1055 | if (b_res->start || b_res->end) |
7506dc79 | 1056 | pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n", |
227f0647 | 1057 | b_res, &bus->busn_res); |
1da177e4 | 1058 | b_res->flags = 0; |
30afe8d0 | 1059 | return 0; |
1da177e4 LT |
1060 | } |
1061 | b_res->start = min_align; | |
c8adf9a3 | 1062 | b_res->end = size0 + min_align - 1; |
5b285415 | 1063 | b_res->flags |= IORESOURCE_STARTALIGN; |
b592443d | 1064 | if (size1 > size0 && realloc_head) { |
d74b9027 | 1065 | add_to_list(realloc_head, bus->self, b_res, size1-size0, add_align); |
7506dc79 | 1066 | pci_printk(KERN_DEBUG, bus->self, "bridge window %pR to %pR add_size %llx add_align %llx\n", |
227f0647 | 1067 | b_res, &bus->busn_res, |
d74b9027 WY |
1068 | (unsigned long long) (size1 - size0), |
1069 | (unsigned long long) add_align); | |
b592443d | 1070 | } |
30afe8d0 | 1071 | return 0; |
1da177e4 LT |
1072 | } |
1073 | ||
0a2daa1c RP |
1074 | unsigned long pci_cardbus_resource_alignment(struct resource *res) |
1075 | { | |
1076 | if (res->flags & IORESOURCE_IO) | |
1077 | return pci_cardbus_io_size; | |
1078 | if (res->flags & IORESOURCE_MEM) | |
1079 | return pci_cardbus_mem_size; | |
1080 | return 0; | |
1081 | } | |
1082 | ||
1083 | static void pci_bus_size_cardbus(struct pci_bus *bus, | |
bdc4abec | 1084 | struct list_head *realloc_head) |
1da177e4 LT |
1085 | { |
1086 | struct pci_dev *bridge = bus->self; | |
1087 | struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; | |
11848934 | 1088 | resource_size_t b_res_3_size = pci_cardbus_mem_size * 2; |
1da177e4 LT |
1089 | u16 ctrl; |
1090 | ||
3796f1e2 YL |
1091 | if (b_res[0].parent) |
1092 | goto handle_b_res_1; | |
1da177e4 LT |
1093 | /* |
1094 | * Reserve some resources for CardBus. We reserve | |
1095 | * a fixed amount of bus space for CardBus bridges. | |
1096 | */ | |
11848934 YL |
1097 | b_res[0].start = pci_cardbus_io_size; |
1098 | b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1; | |
1099 | b_res[0].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN; | |
1100 | if (realloc_head) { | |
1101 | b_res[0].end -= pci_cardbus_io_size; | |
1102 | add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size, | |
1103 | pci_cardbus_io_size); | |
1104 | } | |
1da177e4 | 1105 | |
3796f1e2 YL |
1106 | handle_b_res_1: |
1107 | if (b_res[1].parent) | |
1108 | goto handle_b_res_2; | |
11848934 YL |
1109 | b_res[1].start = pci_cardbus_io_size; |
1110 | b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1; | |
1111 | b_res[1].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN; | |
1112 | if (realloc_head) { | |
1113 | b_res[1].end -= pci_cardbus_io_size; | |
1114 | add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size, | |
1115 | pci_cardbus_io_size); | |
1116 | } | |
1da177e4 | 1117 | |
3796f1e2 | 1118 | handle_b_res_2: |
dcef0d06 YL |
1119 | /* MEM1 must not be pref mmio */ |
1120 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
1121 | if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) { | |
1122 | ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1; | |
1123 | pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); | |
1124 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
1125 | } | |
1126 | ||
1da177e4 LT |
1127 | /* |
1128 | * Check whether prefetchable memory is supported | |
1129 | * by this bridge. | |
1130 | */ | |
1131 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
1132 | if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) { | |
1133 | ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; | |
1134 | pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); | |
1135 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
1136 | } | |
1137 | ||
3796f1e2 YL |
1138 | if (b_res[2].parent) |
1139 | goto handle_b_res_3; | |
1da177e4 LT |
1140 | /* |
1141 | * If we have prefetchable memory support, allocate | |
1142 | * two regions. Otherwise, allocate one region of | |
1143 | * twice the size. | |
1144 | */ | |
1145 | if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) { | |
11848934 YL |
1146 | b_res[2].start = pci_cardbus_mem_size; |
1147 | b_res[2].end = b_res[2].start + pci_cardbus_mem_size - 1; | |
1148 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | | |
1149 | IORESOURCE_STARTALIGN; | |
1150 | if (realloc_head) { | |
1151 | b_res[2].end -= pci_cardbus_mem_size; | |
1152 | add_to_list(realloc_head, bridge, b_res+2, | |
1153 | pci_cardbus_mem_size, pci_cardbus_mem_size); | |
1154 | } | |
1155 | ||
1156 | /* reduce that to half */ | |
1157 | b_res_3_size = pci_cardbus_mem_size; | |
1158 | } | |
1159 | ||
3796f1e2 YL |
1160 | handle_b_res_3: |
1161 | if (b_res[3].parent) | |
1162 | goto handle_done; | |
11848934 YL |
1163 | b_res[3].start = pci_cardbus_mem_size; |
1164 | b_res[3].end = b_res[3].start + b_res_3_size - 1; | |
1165 | b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN; | |
1166 | if (realloc_head) { | |
1167 | b_res[3].end -= b_res_3_size; | |
1168 | add_to_list(realloc_head, bridge, b_res+3, b_res_3_size, | |
1169 | pci_cardbus_mem_size); | |
1170 | } | |
3796f1e2 YL |
1171 | |
1172 | handle_done: | |
1173 | ; | |
1da177e4 LT |
1174 | } |
1175 | ||
10874f5a | 1176 | void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head) |
1da177e4 LT |
1177 | { |
1178 | struct pci_dev *dev; | |
5b285415 | 1179 | unsigned long mask, prefmask, type2 = 0, type3 = 0; |
c8adf9a3 | 1180 | resource_size_t additional_mem_size = 0, additional_io_size = 0; |
5b285415 | 1181 | struct resource *b_res; |
30afe8d0 | 1182 | int ret; |
1da177e4 LT |
1183 | |
1184 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1185 | struct pci_bus *b = dev->subordinate; | |
1186 | if (!b) | |
1187 | continue; | |
1188 | ||
b2fb5cc5 HZ |
1189 | switch (dev->hdr_type) { |
1190 | case PCI_HEADER_TYPE_CARDBUS: | |
9e8bf93a | 1191 | pci_bus_size_cardbus(b, realloc_head); |
1da177e4 LT |
1192 | break; |
1193 | ||
b2fb5cc5 | 1194 | case PCI_HEADER_TYPE_BRIDGE: |
1da177e4 | 1195 | default: |
9e8bf93a | 1196 | __pci_bus_size_bridges(b, realloc_head); |
1da177e4 LT |
1197 | break; |
1198 | } | |
1199 | } | |
1200 | ||
1201 | /* The root bus? */ | |
2ba29e27 | 1202 | if (pci_is_root_bus(bus)) |
1da177e4 LT |
1203 | return; |
1204 | ||
b2fb5cc5 HZ |
1205 | switch (bus->self->hdr_type) { |
1206 | case PCI_HEADER_TYPE_CARDBUS: | |
1da177e4 LT |
1207 | /* don't size cardbuses yet. */ |
1208 | break; | |
1209 | ||
b2fb5cc5 | 1210 | case PCI_HEADER_TYPE_BRIDGE: |
1da177e4 | 1211 | pci_bridge_check_ranges(bus); |
28760489 | 1212 | if (bus->self->is_hotplug_bridge) { |
c8adf9a3 RP |
1213 | additional_io_size = pci_hotplug_io_size; |
1214 | additional_mem_size = pci_hotplug_mem_size; | |
28760489 | 1215 | } |
67d29b5c | 1216 | /* Fall through */ |
1da177e4 | 1217 | default: |
19aa7ee4 YL |
1218 | pbus_size_io(bus, realloc_head ? 0 : additional_io_size, |
1219 | additional_io_size, realloc_head); | |
67d29b5c BH |
1220 | |
1221 | /* | |
1222 | * If there's a 64-bit prefetchable MMIO window, compute | |
1223 | * the size required to put all 64-bit prefetchable | |
1224 | * resources in it. | |
1225 | */ | |
5b285415 | 1226 | b_res = &bus->self->resource[PCI_BRIDGE_RESOURCES]; |
1da177e4 LT |
1227 | mask = IORESOURCE_MEM; |
1228 | prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
5b285415 YL |
1229 | if (b_res[2].flags & IORESOURCE_MEM_64) { |
1230 | prefmask |= IORESOURCE_MEM_64; | |
30afe8d0 | 1231 | ret = pbus_size_mem(bus, prefmask, prefmask, |
5b285415 | 1232 | prefmask, prefmask, |
19aa7ee4 | 1233 | realloc_head ? 0 : additional_mem_size, |
30afe8d0 | 1234 | additional_mem_size, realloc_head); |
67d29b5c BH |
1235 | |
1236 | /* | |
1237 | * If successful, all non-prefetchable resources | |
1238 | * and any 32-bit prefetchable resources will go in | |
1239 | * the non-prefetchable window. | |
1240 | */ | |
30afe8d0 | 1241 | if (ret == 0) { |
30afe8d0 BH |
1242 | mask = prefmask; |
1243 | type2 = prefmask & ~IORESOURCE_MEM_64; | |
1244 | type3 = prefmask & ~IORESOURCE_PREFETCH; | |
5b285415 YL |
1245 | } |
1246 | } | |
67d29b5c BH |
1247 | |
1248 | /* | |
1249 | * If there is no 64-bit prefetchable window, compute the | |
1250 | * size required to put all prefetchable resources in the | |
1251 | * 32-bit prefetchable window (if there is one). | |
1252 | */ | |
5b285415 YL |
1253 | if (!type2) { |
1254 | prefmask &= ~IORESOURCE_MEM_64; | |
30afe8d0 | 1255 | ret = pbus_size_mem(bus, prefmask, prefmask, |
5b285415 YL |
1256 | prefmask, prefmask, |
1257 | realloc_head ? 0 : additional_mem_size, | |
30afe8d0 | 1258 | additional_mem_size, realloc_head); |
67d29b5c BH |
1259 | |
1260 | /* | |
1261 | * If successful, only non-prefetchable resources | |
1262 | * will go in the non-prefetchable window. | |
1263 | */ | |
1264 | if (ret == 0) | |
5b285415 | 1265 | mask = prefmask; |
67d29b5c | 1266 | else |
5b285415 | 1267 | additional_mem_size += additional_mem_size; |
67d29b5c | 1268 | |
5b285415 YL |
1269 | type2 = type3 = IORESOURCE_MEM; |
1270 | } | |
67d29b5c BH |
1271 | |
1272 | /* | |
1273 | * Compute the size required to put everything else in the | |
1274 | * non-prefetchable window. This includes: | |
1275 | * | |
1276 | * - all non-prefetchable resources | |
1277 | * - 32-bit prefetchable resources if there's a 64-bit | |
1278 | * prefetchable window or no prefetchable window at all | |
1279 | * - 64-bit prefetchable resources if there's no | |
1280 | * prefetchable window at all | |
1281 | * | |
1282 | * Note that the strategy in __pci_assign_resource() must | |
1283 | * match that used here. Specifically, we cannot put a | |
1284 | * 32-bit prefetchable resource in a 64-bit prefetchable | |
1285 | * window. | |
1286 | */ | |
5b285415 | 1287 | pbus_size_mem(bus, mask, IORESOURCE_MEM, type2, type3, |
19aa7ee4 YL |
1288 | realloc_head ? 0 : additional_mem_size, |
1289 | additional_mem_size, realloc_head); | |
1da177e4 LT |
1290 | break; |
1291 | } | |
1292 | } | |
c8adf9a3 | 1293 | |
10874f5a | 1294 | void pci_bus_size_bridges(struct pci_bus *bus) |
c8adf9a3 RP |
1295 | { |
1296 | __pci_bus_size_bridges(bus, NULL); | |
1297 | } | |
1da177e4 LT |
1298 | EXPORT_SYMBOL(pci_bus_size_bridges); |
1299 | ||
d04d0111 DD |
1300 | static void assign_fixed_resource_on_bus(struct pci_bus *b, struct resource *r) |
1301 | { | |
1302 | int i; | |
1303 | struct resource *parent_r; | |
1304 | unsigned long mask = IORESOURCE_IO | IORESOURCE_MEM | | |
1305 | IORESOURCE_PREFETCH; | |
1306 | ||
1307 | pci_bus_for_each_resource(b, parent_r, i) { | |
1308 | if (!parent_r) | |
1309 | continue; | |
1310 | ||
1311 | if ((r->flags & mask) == (parent_r->flags & mask) && | |
1312 | resource_contains(parent_r, r)) | |
1313 | request_resource(parent_r, r); | |
1314 | } | |
1315 | } | |
1316 | ||
1317 | /* | |
1318 | * Try to assign any resources marked as IORESOURCE_PCI_FIXED, as they | |
1319 | * are skipped by pbus_assign_resources_sorted(). | |
1320 | */ | |
1321 | static void pdev_assign_fixed_resources(struct pci_dev *dev) | |
1322 | { | |
1323 | int i; | |
1324 | ||
1325 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
1326 | struct pci_bus *b; | |
1327 | struct resource *r = &dev->resource[i]; | |
1328 | ||
1329 | if (r->parent || !(r->flags & IORESOURCE_PCI_FIXED) || | |
1330 | !(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) | |
1331 | continue; | |
1332 | ||
1333 | b = dev->bus; | |
1334 | while (b && !r->parent) { | |
1335 | assign_fixed_resource_on_bus(b, r); | |
1336 | b = b->parent; | |
1337 | } | |
1338 | } | |
1339 | } | |
1340 | ||
10874f5a BH |
1341 | void __pci_bus_assign_resources(const struct pci_bus *bus, |
1342 | struct list_head *realloc_head, | |
1343 | struct list_head *fail_head) | |
1da177e4 LT |
1344 | { |
1345 | struct pci_bus *b; | |
1346 | struct pci_dev *dev; | |
1347 | ||
9e8bf93a | 1348 | pbus_assign_resources_sorted(bus, realloc_head, fail_head); |
1da177e4 | 1349 | |
1da177e4 | 1350 | list_for_each_entry(dev, &bus->devices, bus_list) { |
d04d0111 DD |
1351 | pdev_assign_fixed_resources(dev); |
1352 | ||
1da177e4 LT |
1353 | b = dev->subordinate; |
1354 | if (!b) | |
1355 | continue; | |
1356 | ||
9e8bf93a | 1357 | __pci_bus_assign_resources(b, realloc_head, fail_head); |
1da177e4 | 1358 | |
b2fb5cc5 HZ |
1359 | switch (dev->hdr_type) { |
1360 | case PCI_HEADER_TYPE_BRIDGE: | |
6841ec68 YL |
1361 | if (!pci_is_enabled(dev)) |
1362 | pci_setup_bridge(b); | |
1da177e4 LT |
1363 | break; |
1364 | ||
b2fb5cc5 | 1365 | case PCI_HEADER_TYPE_CARDBUS: |
1da177e4 LT |
1366 | pci_setup_cardbus(b); |
1367 | break; | |
1368 | ||
1369 | default: | |
7506dc79 | 1370 | pci_info(dev, "not setting up bridge for bus %04x:%02x\n", |
227f0647 | 1371 | pci_domain_nr(b), b->number); |
1da177e4 LT |
1372 | break; |
1373 | } | |
1374 | } | |
1375 | } | |
568ddef8 | 1376 | |
10874f5a | 1377 | void pci_bus_assign_resources(const struct pci_bus *bus) |
568ddef8 | 1378 | { |
c8adf9a3 | 1379 | __pci_bus_assign_resources(bus, NULL, NULL); |
568ddef8 | 1380 | } |
1da177e4 LT |
1381 | EXPORT_SYMBOL(pci_bus_assign_resources); |
1382 | ||
765bf9b7 LP |
1383 | static void pci_claim_device_resources(struct pci_dev *dev) |
1384 | { | |
1385 | int i; | |
1386 | ||
1387 | for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) { | |
1388 | struct resource *r = &dev->resource[i]; | |
1389 | ||
1390 | if (!r->flags || r->parent) | |
1391 | continue; | |
1392 | ||
1393 | pci_claim_resource(dev, i); | |
1394 | } | |
1395 | } | |
1396 | ||
1397 | static void pci_claim_bridge_resources(struct pci_dev *dev) | |
1398 | { | |
1399 | int i; | |
1400 | ||
1401 | for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) { | |
1402 | struct resource *r = &dev->resource[i]; | |
1403 | ||
1404 | if (!r->flags || r->parent) | |
1405 | continue; | |
1406 | ||
1407 | pci_claim_bridge_resource(dev, i); | |
1408 | } | |
1409 | } | |
1410 | ||
1411 | static void pci_bus_allocate_dev_resources(struct pci_bus *b) | |
1412 | { | |
1413 | struct pci_dev *dev; | |
1414 | struct pci_bus *child; | |
1415 | ||
1416 | list_for_each_entry(dev, &b->devices, bus_list) { | |
1417 | pci_claim_device_resources(dev); | |
1418 | ||
1419 | child = dev->subordinate; | |
1420 | if (child) | |
1421 | pci_bus_allocate_dev_resources(child); | |
1422 | } | |
1423 | } | |
1424 | ||
1425 | static void pci_bus_allocate_resources(struct pci_bus *b) | |
1426 | { | |
1427 | struct pci_bus *child; | |
1428 | ||
1429 | /* | |
1430 | * Carry out a depth-first search on the PCI bus | |
1431 | * tree to allocate bridge apertures. Read the | |
1432 | * programmed bridge bases and recursively claim | |
1433 | * the respective bridge resources. | |
1434 | */ | |
1435 | if (b->self) { | |
1436 | pci_read_bridge_bases(b); | |
1437 | pci_claim_bridge_resources(b->self); | |
1438 | } | |
1439 | ||
1440 | list_for_each_entry(child, &b->children, node) | |
1441 | pci_bus_allocate_resources(child); | |
1442 | } | |
1443 | ||
1444 | void pci_bus_claim_resources(struct pci_bus *b) | |
1445 | { | |
1446 | pci_bus_allocate_resources(b); | |
1447 | pci_bus_allocate_dev_resources(b); | |
1448 | } | |
1449 | EXPORT_SYMBOL(pci_bus_claim_resources); | |
1450 | ||
10874f5a BH |
1451 | static void __pci_bridge_assign_resources(const struct pci_dev *bridge, |
1452 | struct list_head *add_head, | |
1453 | struct list_head *fail_head) | |
6841ec68 YL |
1454 | { |
1455 | struct pci_bus *b; | |
1456 | ||
8424d759 YL |
1457 | pdev_assign_resources_sorted((struct pci_dev *)bridge, |
1458 | add_head, fail_head); | |
6841ec68 YL |
1459 | |
1460 | b = bridge->subordinate; | |
1461 | if (!b) | |
1462 | return; | |
1463 | ||
8424d759 | 1464 | __pci_bus_assign_resources(b, add_head, fail_head); |
6841ec68 YL |
1465 | |
1466 | switch (bridge->class >> 8) { | |
1467 | case PCI_CLASS_BRIDGE_PCI: | |
1468 | pci_setup_bridge(b); | |
1469 | break; | |
1470 | ||
1471 | case PCI_CLASS_BRIDGE_CARDBUS: | |
1472 | pci_setup_cardbus(b); | |
1473 | break; | |
1474 | ||
1475 | default: | |
7506dc79 | 1476 | pci_info(bridge, "not setting up bridge for bus %04x:%02x\n", |
227f0647 | 1477 | pci_domain_nr(b), b->number); |
6841ec68 YL |
1478 | break; |
1479 | } | |
1480 | } | |
cb21bc94 CK |
1481 | |
1482 | #define PCI_RES_TYPE_MASK \ | |
1483 | (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH |\ | |
1484 | IORESOURCE_MEM_64) | |
1485 | ||
5009b460 YL |
1486 | static void pci_bridge_release_resources(struct pci_bus *bus, |
1487 | unsigned long type) | |
1488 | { | |
5b285415 | 1489 | struct pci_dev *dev = bus->self; |
5009b460 | 1490 | struct resource *r; |
5b285415 YL |
1491 | unsigned old_flags = 0; |
1492 | struct resource *b_res; | |
1493 | int idx = 1; | |
5009b460 | 1494 | |
5b285415 YL |
1495 | b_res = &dev->resource[PCI_BRIDGE_RESOURCES]; |
1496 | ||
1497 | /* | |
1498 | * 1. if there is io port assign fail, will release bridge | |
1499 | * io port. | |
1500 | * 2. if there is non pref mmio assign fail, release bridge | |
1501 | * nonpref mmio. | |
1502 | * 3. if there is 64bit pref mmio assign fail, and bridge pref | |
1503 | * is 64bit, release bridge pref mmio. | |
1504 | * 4. if there is pref mmio assign fail, and bridge pref is | |
1505 | * 32bit mmio, release bridge pref mmio | |
1506 | * 5. if there is pref mmio assign fail, and bridge pref is not | |
1507 | * assigned, release bridge nonpref mmio. | |
1508 | */ | |
1509 | if (type & IORESOURCE_IO) | |
1510 | idx = 0; | |
1511 | else if (!(type & IORESOURCE_PREFETCH)) | |
1512 | idx = 1; | |
1513 | else if ((type & IORESOURCE_MEM_64) && | |
1514 | (b_res[2].flags & IORESOURCE_MEM_64)) | |
1515 | idx = 2; | |
1516 | else if (!(b_res[2].flags & IORESOURCE_MEM_64) && | |
1517 | (b_res[2].flags & IORESOURCE_PREFETCH)) | |
1518 | idx = 2; | |
1519 | else | |
1520 | idx = 1; | |
1521 | ||
1522 | r = &b_res[idx]; | |
1523 | ||
1524 | if (!r->parent) | |
1525 | return; | |
1526 | ||
1527 | /* | |
1528 | * if there are children under that, we should release them | |
1529 | * all | |
1530 | */ | |
1531 | release_child_resources(r); | |
1532 | if (!release_resource(r)) { | |
cb21bc94 | 1533 | type = old_flags = r->flags & PCI_RES_TYPE_MASK; |
7506dc79 | 1534 | pci_printk(KERN_DEBUG, dev, "resource %d %pR released\n", |
5b285415 YL |
1535 | PCI_BRIDGE_RESOURCES + idx, r); |
1536 | /* keep the old size */ | |
1537 | r->end = resource_size(r) - 1; | |
1538 | r->start = 0; | |
1539 | r->flags = 0; | |
5009b460 | 1540 | |
5009b460 YL |
1541 | /* avoiding touch the one without PREF */ |
1542 | if (type & IORESOURCE_PREFETCH) | |
1543 | type = IORESOURCE_PREFETCH; | |
1544 | __pci_setup_bridge(bus, type); | |
5b285415 YL |
1545 | /* for next child res under same bridge */ |
1546 | r->flags = old_flags; | |
5009b460 YL |
1547 | } |
1548 | } | |
1549 | ||
1550 | enum release_type { | |
1551 | leaf_only, | |
1552 | whole_subtree, | |
1553 | }; | |
1554 | /* | |
1555 | * try to release pci bridge resources that is from leaf bridge, | |
1556 | * so we can allocate big new one later | |
1557 | */ | |
10874f5a BH |
1558 | static void pci_bus_release_bridge_resources(struct pci_bus *bus, |
1559 | unsigned long type, | |
1560 | enum release_type rel_type) | |
5009b460 YL |
1561 | { |
1562 | struct pci_dev *dev; | |
1563 | bool is_leaf_bridge = true; | |
1564 | ||
1565 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1566 | struct pci_bus *b = dev->subordinate; | |
1567 | if (!b) | |
1568 | continue; | |
1569 | ||
1570 | is_leaf_bridge = false; | |
1571 | ||
1572 | if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) | |
1573 | continue; | |
1574 | ||
1575 | if (rel_type == whole_subtree) | |
1576 | pci_bus_release_bridge_resources(b, type, | |
1577 | whole_subtree); | |
1578 | } | |
1579 | ||
1580 | if (pci_is_root_bus(bus)) | |
1581 | return; | |
1582 | ||
1583 | if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI) | |
1584 | return; | |
1585 | ||
1586 | if ((rel_type == whole_subtree) || is_leaf_bridge) | |
1587 | pci_bridge_release_resources(bus, type); | |
1588 | } | |
1589 | ||
76fbc263 YL |
1590 | static void pci_bus_dump_res(struct pci_bus *bus) |
1591 | { | |
89a74ecc BH |
1592 | struct resource *res; |
1593 | int i; | |
7c9342b8 | 1594 | |
89a74ecc | 1595 | pci_bus_for_each_resource(bus, res, i) { |
7c9342b8 | 1596 | if (!res || !res->end || !res->flags) |
3c78bc61 | 1597 | continue; |
76fbc263 | 1598 | |
c7dabef8 | 1599 | dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res); |
3c78bc61 | 1600 | } |
76fbc263 YL |
1601 | } |
1602 | ||
1603 | static void pci_bus_dump_resources(struct pci_bus *bus) | |
1604 | { | |
1605 | struct pci_bus *b; | |
1606 | struct pci_dev *dev; | |
1607 | ||
1608 | ||
1609 | pci_bus_dump_res(bus); | |
1610 | ||
1611 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1612 | b = dev->subordinate; | |
1613 | if (!b) | |
1614 | continue; | |
1615 | ||
1616 | pci_bus_dump_resources(b); | |
1617 | } | |
1618 | } | |
1619 | ||
ff35147c | 1620 | static int pci_bus_get_depth(struct pci_bus *bus) |
da7822e5 YL |
1621 | { |
1622 | int depth = 0; | |
f2a230bd | 1623 | struct pci_bus *child_bus; |
da7822e5 | 1624 | |
3c78bc61 | 1625 | list_for_each_entry(child_bus, &bus->children, node) { |
da7822e5 | 1626 | int ret; |
da7822e5 | 1627 | |
f2a230bd | 1628 | ret = pci_bus_get_depth(child_bus); |
da7822e5 YL |
1629 | if (ret + 1 > depth) |
1630 | depth = ret + 1; | |
1631 | } | |
1632 | ||
1633 | return depth; | |
1634 | } | |
da7822e5 | 1635 | |
b55438fd YL |
1636 | /* |
1637 | * -1: undefined, will auto detect later | |
1638 | * 0: disabled by user | |
1639 | * 1: disabled by auto detect | |
1640 | * 2: enabled by user | |
1641 | * 3: enabled by auto detect | |
1642 | */ | |
1643 | enum enable_type { | |
1644 | undefined = -1, | |
1645 | user_disabled, | |
1646 | auto_disabled, | |
1647 | user_enabled, | |
1648 | auto_enabled, | |
1649 | }; | |
1650 | ||
ff35147c | 1651 | static enum enable_type pci_realloc_enable = undefined; |
b55438fd YL |
1652 | void __init pci_realloc_get_opt(char *str) |
1653 | { | |
1654 | if (!strncmp(str, "off", 3)) | |
1655 | pci_realloc_enable = user_disabled; | |
1656 | else if (!strncmp(str, "on", 2)) | |
1657 | pci_realloc_enable = user_enabled; | |
1658 | } | |
ff35147c | 1659 | static bool pci_realloc_enabled(enum enable_type enable) |
b55438fd | 1660 | { |
967260cd | 1661 | return enable >= user_enabled; |
b55438fd | 1662 | } |
f483d392 | 1663 | |
b07f2ebc | 1664 | #if defined(CONFIG_PCI_IOV) && defined(CONFIG_PCI_REALLOC_ENABLE_AUTO) |
ff35147c | 1665 | static int iov_resources_unassigned(struct pci_dev *dev, void *data) |
223d96fc YL |
1666 | { |
1667 | int i; | |
1668 | bool *unassigned = data; | |
b07f2ebc | 1669 | |
223d96fc YL |
1670 | for (i = PCI_IOV_RESOURCES; i <= PCI_IOV_RESOURCE_END; i++) { |
1671 | struct resource *r = &dev->resource[i]; | |
fa216bf4 | 1672 | struct pci_bus_region region; |
b07f2ebc | 1673 | |
223d96fc | 1674 | /* Not assigned or rejected by kernel? */ |
fa216bf4 YL |
1675 | if (!r->flags) |
1676 | continue; | |
b07f2ebc | 1677 | |
fc279850 | 1678 | pcibios_resource_to_bus(dev->bus, ®ion, r); |
fa216bf4 | 1679 | if (!region.start) { |
223d96fc YL |
1680 | *unassigned = true; |
1681 | return 1; /* return early from pci_walk_bus() */ | |
b07f2ebc YL |
1682 | } |
1683 | } | |
b07f2ebc | 1684 | |
223d96fc | 1685 | return 0; |
b07f2ebc YL |
1686 | } |
1687 | ||
ff35147c | 1688 | static enum enable_type pci_realloc_detect(struct pci_bus *bus, |
967260cd | 1689 | enum enable_type enable_local) |
223d96fc YL |
1690 | { |
1691 | bool unassigned = false; | |
b07f2ebc | 1692 | |
967260cd YL |
1693 | if (enable_local != undefined) |
1694 | return enable_local; | |
223d96fc | 1695 | |
967260cd YL |
1696 | pci_walk_bus(bus, iov_resources_unassigned, &unassigned); |
1697 | if (unassigned) | |
1698 | return auto_enabled; | |
1699 | ||
1700 | return enable_local; | |
b07f2ebc | 1701 | } |
223d96fc | 1702 | #else |
ff35147c | 1703 | static enum enable_type pci_realloc_detect(struct pci_bus *bus, |
967260cd YL |
1704 | enum enable_type enable_local) |
1705 | { | |
1706 | return enable_local; | |
b07f2ebc | 1707 | } |
223d96fc | 1708 | #endif |
b07f2ebc | 1709 | |
da7822e5 YL |
1710 | /* |
1711 | * first try will not touch pci bridge res | |
f7625980 BH |
1712 | * second and later try will clear small leaf bridge res |
1713 | * will stop till to the max depth if can not find good one | |
da7822e5 | 1714 | */ |
39772038 | 1715 | void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus) |
1da177e4 | 1716 | { |
bdc4abec | 1717 | LIST_HEAD(realloc_head); /* list of resources that |
c8adf9a3 | 1718 | want additional resources */ |
bdc4abec | 1719 | struct list_head *add_list = NULL; |
da7822e5 YL |
1720 | int tried_times = 0; |
1721 | enum release_type rel_type = leaf_only; | |
bdc4abec | 1722 | LIST_HEAD(fail_head); |
b9b0bba9 | 1723 | struct pci_dev_resource *fail_res; |
19aa7ee4 | 1724 | int pci_try_num = 1; |
55ed83a6 | 1725 | enum enable_type enable_local; |
da7822e5 | 1726 | |
19aa7ee4 | 1727 | /* don't realloc if asked to do so */ |
55ed83a6 | 1728 | enable_local = pci_realloc_detect(bus, pci_realloc_enable); |
967260cd | 1729 | if (pci_realloc_enabled(enable_local)) { |
55ed83a6 | 1730 | int max_depth = pci_bus_get_depth(bus); |
19aa7ee4 YL |
1731 | |
1732 | pci_try_num = max_depth + 1; | |
55ed83a6 YL |
1733 | dev_printk(KERN_DEBUG, &bus->dev, |
1734 | "max bus depth: %d pci_try_num: %d\n", | |
1735 | max_depth, pci_try_num); | |
19aa7ee4 | 1736 | } |
da7822e5 YL |
1737 | |
1738 | again: | |
19aa7ee4 YL |
1739 | /* |
1740 | * last try will use add_list, otherwise will try good to have as | |
1741 | * must have, so can realloc parent bridge resource | |
1742 | */ | |
1743 | if (tried_times + 1 == pci_try_num) | |
bdc4abec | 1744 | add_list = &realloc_head; |
1da177e4 LT |
1745 | /* Depth first, calculate sizes and alignments of all |
1746 | subordinate buses. */ | |
55ed83a6 | 1747 | __pci_bus_size_bridges(bus, add_list); |
c8adf9a3 | 1748 | |
1da177e4 | 1749 | /* Depth last, allocate resources and update the hardware. */ |
55ed83a6 | 1750 | __pci_bus_assign_resources(bus, add_list, &fail_head); |
19aa7ee4 | 1751 | if (add_list) |
bdc4abec | 1752 | BUG_ON(!list_empty(add_list)); |
da7822e5 YL |
1753 | tried_times++; |
1754 | ||
1755 | /* any device complain? */ | |
bdc4abec | 1756 | if (list_empty(&fail_head)) |
928bea96 | 1757 | goto dump; |
f483d392 | 1758 | |
0c5be0cb | 1759 | if (tried_times >= pci_try_num) { |
967260cd | 1760 | if (enable_local == undefined) |
55ed83a6 | 1761 | dev_info(&bus->dev, "Some PCI device resources are unassigned, try booting with pci=realloc\n"); |
967260cd | 1762 | else if (enable_local == auto_enabled) |
55ed83a6 | 1763 | dev_info(&bus->dev, "Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n"); |
eb572e7c | 1764 | |
bffc56d4 | 1765 | free_list(&fail_head); |
928bea96 | 1766 | goto dump; |
da7822e5 YL |
1767 | } |
1768 | ||
55ed83a6 YL |
1769 | dev_printk(KERN_DEBUG, &bus->dev, |
1770 | "No. %d try to assign unassigned res\n", tried_times + 1); | |
da7822e5 YL |
1771 | |
1772 | /* third times and later will not check if it is leaf */ | |
1773 | if ((tried_times + 1) > 2) | |
1774 | rel_type = whole_subtree; | |
1775 | ||
1776 | /* | |
1777 | * Try to release leaf bridge's resources that doesn't fit resource of | |
1778 | * child device under that bridge | |
1779 | */ | |
61e83cdd YL |
1780 | list_for_each_entry(fail_res, &fail_head, list) |
1781 | pci_bus_release_bridge_resources(fail_res->dev->bus, | |
cb21bc94 | 1782 | fail_res->flags & PCI_RES_TYPE_MASK, |
bdc4abec | 1783 | rel_type); |
61e83cdd | 1784 | |
da7822e5 | 1785 | /* restore size and flags */ |
b9b0bba9 YL |
1786 | list_for_each_entry(fail_res, &fail_head, list) { |
1787 | struct resource *res = fail_res->res; | |
da7822e5 | 1788 | |
b9b0bba9 YL |
1789 | res->start = fail_res->start; |
1790 | res->end = fail_res->end; | |
1791 | res->flags = fail_res->flags; | |
1792 | if (fail_res->dev->subordinate) | |
da7822e5 | 1793 | res->flags = 0; |
da7822e5 | 1794 | } |
bffc56d4 | 1795 | free_list(&fail_head); |
da7822e5 YL |
1796 | |
1797 | goto again; | |
1798 | ||
928bea96 | 1799 | dump: |
76fbc263 | 1800 | /* dump the resource on buses */ |
55ed83a6 YL |
1801 | pci_bus_dump_resources(bus); |
1802 | } | |
1803 | ||
1804 | void __init pci_assign_unassigned_resources(void) | |
1805 | { | |
1806 | struct pci_bus *root_bus; | |
1807 | ||
584c5c42 | 1808 | list_for_each_entry(root_bus, &pci_root_buses, node) { |
55ed83a6 | 1809 | pci_assign_unassigned_root_bus_resources(root_bus); |
d9c149d6 RW |
1810 | |
1811 | /* Make sure the root bridge has a companion ACPI device: */ | |
1812 | if (ACPI_HANDLE(root_bus->bridge)) | |
1813 | acpi_ioapic_add(ACPI_HANDLE(root_bus->bridge)); | |
584c5c42 | 1814 | } |
1da177e4 | 1815 | } |
6841ec68 | 1816 | |
1a576772 MW |
1817 | static void extend_bridge_window(struct pci_dev *bridge, struct resource *res, |
1818 | struct list_head *add_list, resource_size_t available) | |
1819 | { | |
1820 | struct pci_dev_resource *dev_res; | |
1821 | ||
1822 | if (res->parent) | |
1823 | return; | |
1824 | ||
1825 | if (resource_size(res) >= available) | |
1826 | return; | |
1827 | ||
1828 | dev_res = res_to_dev_res(add_list, res); | |
1829 | if (!dev_res) | |
1830 | return; | |
1831 | ||
1832 | /* Is there room to extend the window? */ | |
1833 | if (available - resource_size(res) <= dev_res->add_size) | |
1834 | return; | |
1835 | ||
1836 | dev_res->add_size = available - resource_size(res); | |
7506dc79 | 1837 | pci_dbg(bridge, "bridge window %pR extended by %pa\n", res, |
1a576772 MW |
1838 | &dev_res->add_size); |
1839 | } | |
1840 | ||
1841 | static void pci_bus_distribute_available_resources(struct pci_bus *bus, | |
1842 | struct list_head *add_list, resource_size_t available_io, | |
1843 | resource_size_t available_mmio, resource_size_t available_mmio_pref) | |
1844 | { | |
1845 | resource_size_t remaining_io, remaining_mmio, remaining_mmio_pref; | |
1846 | unsigned int normal_bridges = 0, hotplug_bridges = 0; | |
1847 | struct resource *io_res, *mmio_res, *mmio_pref_res; | |
1848 | struct pci_dev *dev, *bridge = bus->self; | |
1849 | ||
1850 | io_res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0]; | |
1851 | mmio_res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1]; | |
1852 | mmio_pref_res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2]; | |
1853 | ||
1854 | /* | |
1855 | * Update additional resource list (add_list) to fill all the | |
1856 | * extra resource space available for this port except the space | |
1857 | * calculated in __pci_bus_size_bridges() which covers all the | |
1858 | * devices currently connected to the port and below. | |
1859 | */ | |
1860 | extend_bridge_window(bridge, io_res, add_list, available_io); | |
1861 | extend_bridge_window(bridge, mmio_res, add_list, available_mmio); | |
1862 | extend_bridge_window(bridge, mmio_pref_res, add_list, | |
1863 | available_mmio_pref); | |
1864 | ||
1865 | /* | |
1866 | * Calculate the total amount of extra resource space we can | |
1867 | * pass to bridges below this one. This is basically the | |
1868 | * extra space reduced by the minimal required space for the | |
1869 | * non-hotplug bridges. | |
1870 | */ | |
1871 | remaining_io = available_io; | |
1872 | remaining_mmio = available_mmio; | |
1873 | remaining_mmio_pref = available_mmio_pref; | |
1874 | ||
1875 | /* | |
1876 | * Calculate how many hotplug bridges and normal bridges there | |
1877 | * are on this bus. We will distribute the additional available | |
1878 | * resources between hotplug bridges. | |
1879 | */ | |
1880 | for_each_pci_bridge(dev, bus) { | |
1881 | if (dev->is_hotplug_bridge) | |
1882 | hotplug_bridges++; | |
1883 | else | |
1884 | normal_bridges++; | |
1885 | } | |
1886 | ||
1887 | for_each_pci_bridge(dev, bus) { | |
1888 | const struct resource *res; | |
1889 | ||
1890 | if (dev->is_hotplug_bridge) | |
1891 | continue; | |
1892 | ||
1893 | /* | |
1894 | * Reduce the available resource space by what the | |
1895 | * bridge and devices below it occupy. | |
1896 | */ | |
1897 | res = &dev->resource[PCI_BRIDGE_RESOURCES + 0]; | |
1898 | if (!res->parent && available_io > resource_size(res)) | |
1899 | remaining_io -= resource_size(res); | |
1900 | ||
1901 | res = &dev->resource[PCI_BRIDGE_RESOURCES + 1]; | |
1902 | if (!res->parent && available_mmio > resource_size(res)) | |
1903 | remaining_mmio -= resource_size(res); | |
1904 | ||
1905 | res = &dev->resource[PCI_BRIDGE_RESOURCES + 2]; | |
1906 | if (!res->parent && available_mmio_pref > resource_size(res)) | |
1907 | remaining_mmio_pref -= resource_size(res); | |
1908 | } | |
1909 | ||
14fe5951 MW |
1910 | /* |
1911 | * There is only one bridge on the bus so it gets all available | |
1912 | * resources which it can then distribute to the possible | |
1913 | * hotplug bridges below. | |
1914 | */ | |
1915 | if (hotplug_bridges + normal_bridges == 1) { | |
1916 | dev = list_first_entry(&bus->devices, struct pci_dev, bus_list); | |
1917 | if (dev->subordinate) { | |
1918 | pci_bus_distribute_available_resources(dev->subordinate, | |
1919 | add_list, available_io, available_mmio, | |
1920 | available_mmio_pref); | |
1921 | } | |
1922 | return; | |
1923 | } | |
1924 | ||
1a576772 MW |
1925 | /* |
1926 | * Go over devices on this bus and distribute the remaining | |
1927 | * resource space between hotplug bridges. | |
1928 | */ | |
1929 | for_each_pci_bridge(dev, bus) { | |
14fe5951 | 1930 | resource_size_t align, io, mmio, mmio_pref; |
1a576772 MW |
1931 | struct pci_bus *b; |
1932 | ||
1933 | b = dev->subordinate; | |
14fe5951 | 1934 | if (!b || !dev->is_hotplug_bridge) |
1a576772 MW |
1935 | continue; |
1936 | ||
14fe5951 MW |
1937 | /* |
1938 | * Distribute available extra resources equally between | |
1939 | * hotplug-capable downstream ports taking alignment into | |
1940 | * account. | |
1941 | * | |
1942 | * Here hotplug_bridges is always != 0. | |
1943 | */ | |
1944 | align = pci_resource_alignment(bridge, io_res); | |
1945 | io = div64_ul(available_io, hotplug_bridges); | |
1946 | io = min(ALIGN(io, align), remaining_io); | |
1947 | remaining_io -= io; | |
1948 | ||
1949 | align = pci_resource_alignment(bridge, mmio_res); | |
1950 | mmio = div64_ul(available_mmio, hotplug_bridges); | |
1951 | mmio = min(ALIGN(mmio, align), remaining_mmio); | |
1952 | remaining_mmio -= mmio; | |
1953 | ||
1954 | align = pci_resource_alignment(bridge, mmio_pref_res); | |
1955 | mmio_pref = div64_ul(available_mmio_pref, hotplug_bridges); | |
1956 | mmio_pref = min(ALIGN(mmio_pref, align), remaining_mmio_pref); | |
1957 | remaining_mmio_pref -= mmio_pref; | |
1958 | ||
1959 | pci_bus_distribute_available_resources(b, add_list, io, mmio, | |
1960 | mmio_pref); | |
1a576772 MW |
1961 | } |
1962 | } | |
1963 | ||
1964 | static void | |
1965 | pci_bridge_distribute_available_resources(struct pci_dev *bridge, | |
1966 | struct list_head *add_list) | |
1967 | { | |
1968 | resource_size_t available_io, available_mmio, available_mmio_pref; | |
1969 | const struct resource *res; | |
1970 | ||
1971 | if (!bridge->is_hotplug_bridge) | |
1972 | return; | |
1973 | ||
1974 | /* Take the initial extra resources from the hotplug port */ | |
1975 | res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0]; | |
1976 | available_io = resource_size(res); | |
1977 | res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1]; | |
1978 | available_mmio = resource_size(res); | |
1979 | res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2]; | |
1980 | available_mmio_pref = resource_size(res); | |
1981 | ||
1982 | pci_bus_distribute_available_resources(bridge->subordinate, | |
1983 | add_list, available_io, available_mmio, available_mmio_pref); | |
1984 | } | |
1985 | ||
6841ec68 YL |
1986 | void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge) |
1987 | { | |
1988 | struct pci_bus *parent = bridge->subordinate; | |
bdc4abec | 1989 | LIST_HEAD(add_list); /* list of resources that |
8424d759 | 1990 | want additional resources */ |
32180e40 | 1991 | int tried_times = 0; |
bdc4abec | 1992 | LIST_HEAD(fail_head); |
b9b0bba9 | 1993 | struct pci_dev_resource *fail_res; |
6841ec68 | 1994 | int retval; |
32180e40 | 1995 | |
32180e40 | 1996 | again: |
8424d759 | 1997 | __pci_bus_size_bridges(parent, &add_list); |
1a576772 MW |
1998 | |
1999 | /* | |
2000 | * Distribute remaining resources (if any) equally between | |
2001 | * hotplug bridges below. This makes it possible to extend the | |
2002 | * hierarchy later without running out of resources. | |
2003 | */ | |
2004 | pci_bridge_distribute_available_resources(bridge, &add_list); | |
2005 | ||
bdc4abec YL |
2006 | __pci_bridge_assign_resources(bridge, &add_list, &fail_head); |
2007 | BUG_ON(!list_empty(&add_list)); | |
32180e40 YL |
2008 | tried_times++; |
2009 | ||
bdc4abec | 2010 | if (list_empty(&fail_head)) |
3f579c34 | 2011 | goto enable_all; |
32180e40 YL |
2012 | |
2013 | if (tried_times >= 2) { | |
2014 | /* still fail, don't need to try more */ | |
bffc56d4 | 2015 | free_list(&fail_head); |
3f579c34 | 2016 | goto enable_all; |
32180e40 YL |
2017 | } |
2018 | ||
2019 | printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n", | |
2020 | tried_times + 1); | |
2021 | ||
2022 | /* | |
2023 | * Try to release leaf bridge's resources that doesn't fit resource of | |
2024 | * child device under that bridge | |
2025 | */ | |
61e83cdd YL |
2026 | list_for_each_entry(fail_res, &fail_head, list) |
2027 | pci_bus_release_bridge_resources(fail_res->dev->bus, | |
cb21bc94 | 2028 | fail_res->flags & PCI_RES_TYPE_MASK, |
32180e40 | 2029 | whole_subtree); |
61e83cdd | 2030 | |
32180e40 | 2031 | /* restore size and flags */ |
b9b0bba9 YL |
2032 | list_for_each_entry(fail_res, &fail_head, list) { |
2033 | struct resource *res = fail_res->res; | |
32180e40 | 2034 | |
b9b0bba9 YL |
2035 | res->start = fail_res->start; |
2036 | res->end = fail_res->end; | |
2037 | res->flags = fail_res->flags; | |
2038 | if (fail_res->dev->subordinate) | |
32180e40 | 2039 | res->flags = 0; |
32180e40 | 2040 | } |
bffc56d4 | 2041 | free_list(&fail_head); |
32180e40 YL |
2042 | |
2043 | goto again; | |
3f579c34 YL |
2044 | |
2045 | enable_all: | |
2046 | retval = pci_reenable_device(bridge); | |
9fc9eea0 | 2047 | if (retval) |
7506dc79 | 2048 | pci_err(bridge, "Error reenabling bridge (%d)\n", retval); |
3f579c34 | 2049 | pci_set_master(bridge); |
6841ec68 YL |
2050 | } |
2051 | EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources); | |
9b03088f | 2052 | |
8bb705e3 CK |
2053 | int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type) |
2054 | { | |
2055 | struct pci_dev_resource *dev_res; | |
2056 | struct pci_dev *next; | |
2057 | LIST_HEAD(saved); | |
2058 | LIST_HEAD(added); | |
2059 | LIST_HEAD(failed); | |
2060 | unsigned int i; | |
2061 | int ret; | |
2062 | ||
2063 | /* Walk to the root hub, releasing bridge BARs when possible */ | |
2064 | next = bridge; | |
2065 | do { | |
2066 | bridge = next; | |
2067 | for (i = PCI_BRIDGE_RESOURCES; i < PCI_BRIDGE_RESOURCE_END; | |
2068 | i++) { | |
2069 | struct resource *res = &bridge->resource[i]; | |
2070 | ||
2071 | if ((res->flags ^ type) & PCI_RES_TYPE_MASK) | |
2072 | continue; | |
2073 | ||
2074 | /* Ignore BARs which are still in use */ | |
2075 | if (res->child) | |
2076 | continue; | |
2077 | ||
2078 | ret = add_to_list(&saved, bridge, res, 0, 0); | |
2079 | if (ret) | |
2080 | goto cleanup; | |
2081 | ||
7506dc79 | 2082 | pci_info(bridge, "BAR %d: releasing %pR\n", |
8bb705e3 CK |
2083 | i, res); |
2084 | ||
2085 | if (res->parent) | |
2086 | release_resource(res); | |
2087 | res->start = 0; | |
2088 | res->end = 0; | |
2089 | break; | |
2090 | } | |
2091 | if (i == PCI_BRIDGE_RESOURCE_END) | |
2092 | break; | |
2093 | ||
2094 | next = bridge->bus ? bridge->bus->self : NULL; | |
2095 | } while (next); | |
2096 | ||
2097 | if (list_empty(&saved)) | |
2098 | return -ENOENT; | |
2099 | ||
2100 | __pci_bus_size_bridges(bridge->subordinate, &added); | |
2101 | __pci_bridge_assign_resources(bridge, &added, &failed); | |
2102 | BUG_ON(!list_empty(&added)); | |
2103 | ||
2104 | if (!list_empty(&failed)) { | |
2105 | ret = -ENOSPC; | |
2106 | goto cleanup; | |
2107 | } | |
2108 | ||
2109 | list_for_each_entry(dev_res, &saved, list) { | |
2110 | /* Skip the bridge we just assigned resources for. */ | |
2111 | if (bridge == dev_res->dev) | |
2112 | continue; | |
2113 | ||
2114 | bridge = dev_res->dev; | |
2115 | pci_setup_bridge(bridge->subordinate); | |
2116 | } | |
2117 | ||
2118 | free_list(&saved); | |
2119 | return 0; | |
2120 | ||
2121 | cleanup: | |
2122 | /* restore size and flags */ | |
2123 | list_for_each_entry(dev_res, &failed, list) { | |
2124 | struct resource *res = dev_res->res; | |
2125 | ||
2126 | res->start = dev_res->start; | |
2127 | res->end = dev_res->end; | |
2128 | res->flags = dev_res->flags; | |
2129 | } | |
2130 | free_list(&failed); | |
2131 | ||
2132 | /* Revert to the old configuration */ | |
2133 | list_for_each_entry(dev_res, &saved, list) { | |
2134 | struct resource *res = dev_res->res; | |
2135 | ||
2136 | bridge = dev_res->dev; | |
2137 | i = res - bridge->resource; | |
2138 | ||
2139 | res->start = dev_res->start; | |
2140 | res->end = dev_res->end; | |
2141 | res->flags = dev_res->flags; | |
2142 | ||
2143 | pci_claim_resource(bridge, i); | |
2144 | pci_setup_bridge(bridge->subordinate); | |
2145 | } | |
2146 | free_list(&saved); | |
2147 | ||
2148 | return ret; | |
2149 | } | |
2150 | ||
17787940 | 2151 | void pci_assign_unassigned_bus_resources(struct pci_bus *bus) |
9b03088f | 2152 | { |
9b03088f | 2153 | struct pci_dev *dev; |
bdc4abec | 2154 | LIST_HEAD(add_list); /* list of resources that |
9b03088f YL |
2155 | want additional resources */ |
2156 | ||
9b03088f | 2157 | down_read(&pci_bus_sem); |
24a0c654 AS |
2158 | for_each_pci_bridge(dev, bus) |
2159 | if (pci_has_subordinate(dev)) | |
2160 | __pci_bus_size_bridges(dev->subordinate, &add_list); | |
9b03088f YL |
2161 | up_read(&pci_bus_sem); |
2162 | __pci_bus_assign_resources(bus, &add_list, NULL); | |
bdc4abec | 2163 | BUG_ON(!list_empty(&add_list)); |
17787940 | 2164 | } |
e6b29dea | 2165 | EXPORT_SYMBOL_GPL(pci_assign_unassigned_bus_resources); |