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Commit | Line | Data |
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7328c8f4 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1da177e4 | 2 | /* |
df62ab5e | 3 | * Support routines for initializing a PCI subsystem |
1da177e4 LT |
4 | * |
5 | * Extruded from code written by | |
6 | * Dave Rusling (david.rusling@reo.mts.dec.com) | |
7 | * David Mosberger (davidm@cs.arizona.edu) | |
8 | * David Miller (davem@redhat.com) | |
9 | * | |
1da177e4 LT |
10 | * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> |
11 | * PCI-PCI bridges cleanup, sorted resource allocation. | |
12 | * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru> | |
13 | * Converted to allocation in 3 passes, which gives | |
14 | * tighter packing. Prefetchable range support. | |
15 | */ | |
16 | ||
17 | #include <linux/init.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/pci.h> | |
21 | #include <linux/errno.h> | |
22 | #include <linux/ioport.h> | |
23 | #include <linux/cache.h> | |
24 | #include <linux/slab.h> | |
584c5c42 | 25 | #include <linux/acpi.h> |
6faf17f6 | 26 | #include "pci.h" |
1da177e4 | 27 | |
844393f4 | 28 | unsigned int pci_flags; |
47087700 | 29 | |
bdc4abec YL |
30 | struct pci_dev_resource { |
31 | struct list_head list; | |
2934a0de YL |
32 | struct resource *res; |
33 | struct pci_dev *dev; | |
568ddef8 YL |
34 | resource_size_t start; |
35 | resource_size_t end; | |
c8adf9a3 | 36 | resource_size_t add_size; |
2bbc6942 | 37 | resource_size_t min_align; |
568ddef8 YL |
38 | unsigned long flags; |
39 | }; | |
40 | ||
bffc56d4 YL |
41 | static void free_list(struct list_head *head) |
42 | { | |
43 | struct pci_dev_resource *dev_res, *tmp; | |
44 | ||
45 | list_for_each_entry_safe(dev_res, tmp, head, list) { | |
46 | list_del(&dev_res->list); | |
47 | kfree(dev_res); | |
48 | } | |
49 | } | |
094732a5 | 50 | |
c8adf9a3 | 51 | /** |
0d607618 | 52 | * add_to_list() - Add a new resource tracker to the list |
c8adf9a3 | 53 | * @head: Head of the list |
0d607618 NJ |
54 | * @dev: Device to which the resource belongs |
55 | * @res: Resource to be tracked | |
56 | * @add_size: Additional size to be optionally added to the resource | |
c8adf9a3 | 57 | */ |
0d607618 NJ |
58 | static int add_to_list(struct list_head *head, struct pci_dev *dev, |
59 | struct resource *res, resource_size_t add_size, | |
60 | resource_size_t min_align) | |
568ddef8 | 61 | { |
764242a0 | 62 | struct pci_dev_resource *tmp; |
568ddef8 | 63 | |
bdc4abec | 64 | tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); |
c7abb235 | 65 | if (!tmp) |
ef62dfef | 66 | return -ENOMEM; |
568ddef8 | 67 | |
568ddef8 YL |
68 | tmp->res = res; |
69 | tmp->dev = dev; | |
70 | tmp->start = res->start; | |
71 | tmp->end = res->end; | |
72 | tmp->flags = res->flags; | |
c8adf9a3 | 73 | tmp->add_size = add_size; |
2bbc6942 | 74 | tmp->min_align = min_align; |
bdc4abec YL |
75 | |
76 | list_add(&tmp->list, head); | |
ef62dfef YL |
77 | |
78 | return 0; | |
568ddef8 YL |
79 | } |
80 | ||
0d607618 | 81 | static void remove_from_list(struct list_head *head, struct resource *res) |
3e6e0d80 | 82 | { |
b9b0bba9 | 83 | struct pci_dev_resource *dev_res, *tmp; |
3e6e0d80 | 84 | |
b9b0bba9 YL |
85 | list_for_each_entry_safe(dev_res, tmp, head, list) { |
86 | if (dev_res->res == res) { | |
87 | list_del(&dev_res->list); | |
88 | kfree(dev_res); | |
bdc4abec | 89 | break; |
3e6e0d80 | 90 | } |
3e6e0d80 YL |
91 | } |
92 | } | |
93 | ||
d74b9027 WY |
94 | static struct pci_dev_resource *res_to_dev_res(struct list_head *head, |
95 | struct resource *res) | |
1c372353 | 96 | { |
b9b0bba9 | 97 | struct pci_dev_resource *dev_res; |
bdc4abec | 98 | |
b9b0bba9 | 99 | list_for_each_entry(dev_res, head, list) { |
25e77388 | 100 | if (dev_res->res == res) |
d74b9027 | 101 | return dev_res; |
3e6e0d80 | 102 | } |
1c372353 | 103 | |
d74b9027 | 104 | return NULL; |
1c372353 YL |
105 | } |
106 | ||
d74b9027 WY |
107 | static resource_size_t get_res_add_size(struct list_head *head, |
108 | struct resource *res) | |
109 | { | |
110 | struct pci_dev_resource *dev_res; | |
111 | ||
112 | dev_res = res_to_dev_res(head, res); | |
113 | return dev_res ? dev_res->add_size : 0; | |
114 | } | |
115 | ||
116 | static resource_size_t get_res_add_align(struct list_head *head, | |
117 | struct resource *res) | |
118 | { | |
119 | struct pci_dev_resource *dev_res; | |
120 | ||
121 | dev_res = res_to_dev_res(head, res); | |
122 | return dev_res ? dev_res->min_align : 0; | |
123 | } | |
124 | ||
125 | ||
78c3b329 | 126 | /* Sort resources by alignment */ |
bdc4abec | 127 | static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head) |
78c3b329 YL |
128 | { |
129 | int i; | |
130 | ||
131 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
132 | struct resource *r; | |
bdc4abec | 133 | struct pci_dev_resource *dev_res, *tmp; |
78c3b329 | 134 | resource_size_t r_align; |
bdc4abec | 135 | struct list_head *n; |
78c3b329 YL |
136 | |
137 | r = &dev->resource[i]; | |
138 | ||
139 | if (r->flags & IORESOURCE_PCI_FIXED) | |
140 | continue; | |
141 | ||
142 | if (!(r->flags) || r->parent) | |
143 | continue; | |
144 | ||
145 | r_align = pci_resource_alignment(dev, r); | |
146 | if (!r_align) { | |
7506dc79 | 147 | pci_warn(dev, "BAR %d: %pR has bogus alignment\n", |
78c3b329 YL |
148 | i, r); |
149 | continue; | |
150 | } | |
78c3b329 | 151 | |
bdc4abec YL |
152 | tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); |
153 | if (!tmp) | |
227f0647 | 154 | panic("pdev_sort_resources(): kmalloc() failed!\n"); |
bdc4abec YL |
155 | tmp->res = r; |
156 | tmp->dev = dev; | |
157 | ||
0d607618 | 158 | /* Fallback is smallest one or list is empty */ |
bdc4abec YL |
159 | n = head; |
160 | list_for_each_entry(dev_res, head, list) { | |
161 | resource_size_t align; | |
162 | ||
163 | align = pci_resource_alignment(dev_res->dev, | |
164 | dev_res->res); | |
78c3b329 YL |
165 | |
166 | if (r_align > align) { | |
bdc4abec | 167 | n = &dev_res->list; |
78c3b329 YL |
168 | break; |
169 | } | |
170 | } | |
0d607618 | 171 | /* Insert it just before n */ |
bdc4abec | 172 | list_add_tail(&tmp->list, n); |
78c3b329 YL |
173 | } |
174 | } | |
175 | ||
0d607618 | 176 | static void __dev_sort_resources(struct pci_dev *dev, struct list_head *head) |
1da177e4 | 177 | { |
6841ec68 | 178 | u16 class = dev->class >> 8; |
1da177e4 | 179 | |
0d607618 | 180 | /* Don't touch classless devices or host bridges or IOAPICs */ |
6841ec68 YL |
181 | if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST) |
182 | return; | |
1da177e4 | 183 | |
0d607618 | 184 | /* Don't touch IOAPIC devices already enabled by firmware */ |
6841ec68 YL |
185 | if (class == PCI_CLASS_SYSTEM_PIC) { |
186 | u16 command; | |
187 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
188 | if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | |
189 | return; | |
190 | } | |
1da177e4 | 191 | |
6841ec68 YL |
192 | pdev_sort_resources(dev, head); |
193 | } | |
23186279 | 194 | |
fc075e1d RP |
195 | static inline void reset_resource(struct resource *res) |
196 | { | |
197 | res->start = 0; | |
198 | res->end = 0; | |
199 | res->flags = 0; | |
200 | } | |
201 | ||
c8adf9a3 | 202 | /** |
0d607618 | 203 | * reassign_resources_sorted() - Satisfy any additional resource requests |
c8adf9a3 | 204 | * |
0d607618 NJ |
205 | * @realloc_head: Head of the list tracking requests requiring |
206 | * additional resources | |
207 | * @head: Head of the list tracking requests with allocated | |
208 | * resources | |
c8adf9a3 | 209 | * |
0d607618 NJ |
210 | * Walk through each element of the realloc_head and try to procure additional |
211 | * resources for the element, provided the element is in the head list. | |
c8adf9a3 | 212 | */ |
bdc4abec | 213 | static void reassign_resources_sorted(struct list_head *realloc_head, |
0d607618 | 214 | struct list_head *head) |
6841ec68 YL |
215 | { |
216 | struct resource *res; | |
b9b0bba9 | 217 | struct pci_dev_resource *add_res, *tmp; |
bdc4abec | 218 | struct pci_dev_resource *dev_res; |
d74b9027 | 219 | resource_size_t add_size, align; |
6841ec68 | 220 | int idx; |
1da177e4 | 221 | |
b9b0bba9 | 222 | list_for_each_entry_safe(add_res, tmp, realloc_head, list) { |
bdc4abec YL |
223 | bool found_match = false; |
224 | ||
b9b0bba9 | 225 | res = add_res->res; |
0d607618 | 226 | /* Skip resource that has been reset */ |
c8adf9a3 RP |
227 | if (!res->flags) |
228 | goto out; | |
229 | ||
0d607618 | 230 | /* Skip this resource if not found in head list */ |
bdc4abec YL |
231 | list_for_each_entry(dev_res, head, list) { |
232 | if (dev_res->res == res) { | |
233 | found_match = true; | |
234 | break; | |
235 | } | |
c8adf9a3 | 236 | } |
0d607618 | 237 | if (!found_match) /* Just skip */ |
bdc4abec | 238 | continue; |
c8adf9a3 | 239 | |
b9b0bba9 YL |
240 | idx = res - &add_res->dev->resource[0]; |
241 | add_size = add_res->add_size; | |
d74b9027 | 242 | align = add_res->min_align; |
2bbc6942 | 243 | if (!resource_size(res)) { |
d74b9027 | 244 | res->start = align; |
2bbc6942 | 245 | res->end = res->start + add_size - 1; |
b9b0bba9 | 246 | if (pci_assign_resource(add_res->dev, idx)) |
c8adf9a3 | 247 | reset_resource(res); |
2bbc6942 | 248 | } else { |
b9b0bba9 | 249 | res->flags |= add_res->flags & |
bdc4abec | 250 | (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN); |
b9b0bba9 | 251 | if (pci_reassign_resource(add_res->dev, idx, |
bdc4abec | 252 | add_size, align)) |
34c6b710 MK |
253 | pci_info(add_res->dev, "failed to add %llx res[%d]=%pR\n", |
254 | (unsigned long long) add_size, idx, | |
255 | res); | |
c8adf9a3 RP |
256 | } |
257 | out: | |
b9b0bba9 YL |
258 | list_del(&add_res->list); |
259 | kfree(add_res); | |
c8adf9a3 RP |
260 | } |
261 | } | |
262 | ||
263 | /** | |
0d607618 | 264 | * assign_requested_resources_sorted() - Satisfy resource requests |
c8adf9a3 | 265 | * |
0d607618 NJ |
266 | * @head: Head of the list tracking requests for resources |
267 | * @fail_head: Head of the list tracking requests that could not be | |
268 | * allocated | |
c8adf9a3 | 269 | * |
0d607618 NJ |
270 | * Satisfy resource requests of each element in the list. Add requests that |
271 | * could not be satisfied to the failed_list. | |
c8adf9a3 | 272 | */ |
bdc4abec YL |
273 | static void assign_requested_resources_sorted(struct list_head *head, |
274 | struct list_head *fail_head) | |
c8adf9a3 RP |
275 | { |
276 | struct resource *res; | |
bdc4abec | 277 | struct pci_dev_resource *dev_res; |
c8adf9a3 | 278 | int idx; |
9a928660 | 279 | |
bdc4abec YL |
280 | list_for_each_entry(dev_res, head, list) { |
281 | res = dev_res->res; | |
282 | idx = res - &dev_res->dev->resource[0]; | |
283 | if (resource_size(res) && | |
284 | pci_assign_resource(dev_res->dev, idx)) { | |
a3cb999d | 285 | if (fail_head) { |
9a928660 | 286 | /* |
0d607618 NJ |
287 | * If the failed resource is a ROM BAR and |
288 | * it will be enabled later, don't add it | |
289 | * to the list. | |
9a928660 YL |
290 | */ |
291 | if (!((idx == PCI_ROM_RESOURCE) && | |
292 | (!(res->flags & IORESOURCE_ROM_ENABLE)))) | |
67cc7e26 YL |
293 | add_to_list(fail_head, |
294 | dev_res->dev, res, | |
f7625980 BH |
295 | 0 /* don't care */, |
296 | 0 /* don't care */); | |
9a928660 | 297 | } |
fc075e1d | 298 | reset_resource(res); |
542df5de | 299 | } |
1da177e4 LT |
300 | } |
301 | } | |
302 | ||
aa914f5e YL |
303 | static unsigned long pci_fail_res_type_mask(struct list_head *fail_head) |
304 | { | |
305 | struct pci_dev_resource *fail_res; | |
306 | unsigned long mask = 0; | |
307 | ||
0d607618 | 308 | /* Check failed type */ |
aa914f5e YL |
309 | list_for_each_entry(fail_res, fail_head, list) |
310 | mask |= fail_res->flags; | |
311 | ||
312 | /* | |
0d607618 NJ |
313 | * One pref failed resource will set IORESOURCE_MEM, as we can |
314 | * allocate pref in non-pref range. Will release all assigned | |
315 | * non-pref sibling resources according to that bit. | |
aa914f5e YL |
316 | */ |
317 | return mask & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH); | |
318 | } | |
319 | ||
320 | static bool pci_need_to_release(unsigned long mask, struct resource *res) | |
321 | { | |
322 | if (res->flags & IORESOURCE_IO) | |
323 | return !!(mask & IORESOURCE_IO); | |
324 | ||
0d607618 | 325 | /* Check pref at first */ |
aa914f5e YL |
326 | if (res->flags & IORESOURCE_PREFETCH) { |
327 | if (mask & IORESOURCE_PREFETCH) | |
328 | return true; | |
0d607618 | 329 | /* Count pref if its parent is non-pref */ |
aa914f5e YL |
330 | else if ((mask & IORESOURCE_MEM) && |
331 | !(res->parent->flags & IORESOURCE_PREFETCH)) | |
332 | return true; | |
333 | else | |
334 | return false; | |
335 | } | |
336 | ||
337 | if (res->flags & IORESOURCE_MEM) | |
338 | return !!(mask & IORESOURCE_MEM); | |
339 | ||
0d607618 | 340 | return false; /* Should not get here */ |
aa914f5e YL |
341 | } |
342 | ||
bdc4abec | 343 | static void __assign_resources_sorted(struct list_head *head, |
0d607618 NJ |
344 | struct list_head *realloc_head, |
345 | struct list_head *fail_head) | |
c8adf9a3 | 346 | { |
3e6e0d80 | 347 | /* |
0d607618 NJ |
348 | * Should not assign requested resources at first. They could be |
349 | * adjacent, so later reassign can not reallocate them one by one in | |
350 | * parent resource window. | |
351 | * | |
352 | * Try to assign requested + add_size at beginning. If could do that, | |
353 | * could get out early. If could not do that, we still try to assign | |
354 | * requested at first, then try to reassign add_size for some resources. | |
aa914f5e YL |
355 | * |
356 | * Separate three resource type checking if we need to release | |
357 | * assigned resource after requested + add_size try. | |
0d607618 NJ |
358 | * |
359 | * 1. If IO port assignment fails, will release assigned IO | |
360 | * port. | |
361 | * 2. If pref MMIO assignment fails, release assigned pref | |
362 | * MMIO. If assigned pref MMIO's parent is non-pref MMIO | |
363 | * and non-pref MMIO assignment fails, will release that | |
364 | * assigned pref MMIO. | |
365 | * 3. If non-pref MMIO assignment fails or pref MMIO | |
366 | * assignment fails, will release assigned non-pref MMIO. | |
3e6e0d80 | 367 | */ |
bdc4abec YL |
368 | LIST_HEAD(save_head); |
369 | LIST_HEAD(local_fail_head); | |
b9b0bba9 | 370 | struct pci_dev_resource *save_res; |
d74b9027 | 371 | struct pci_dev_resource *dev_res, *tmp_res, *dev_res2; |
aa914f5e | 372 | unsigned long fail_type; |
d74b9027 | 373 | resource_size_t add_align, align; |
3e6e0d80 YL |
374 | |
375 | /* Check if optional add_size is there */ | |
bdc4abec | 376 | if (!realloc_head || list_empty(realloc_head)) |
3e6e0d80 YL |
377 | goto requested_and_reassign; |
378 | ||
379 | /* Save original start, end, flags etc at first */ | |
bdc4abec YL |
380 | list_for_each_entry(dev_res, head, list) { |
381 | if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) { | |
bffc56d4 | 382 | free_list(&save_head); |
3e6e0d80 YL |
383 | goto requested_and_reassign; |
384 | } | |
bdc4abec | 385 | } |
3e6e0d80 YL |
386 | |
387 | /* Update res in head list with add_size in realloc_head list */ | |
d74b9027 | 388 | list_for_each_entry_safe(dev_res, tmp_res, head, list) { |
bdc4abec YL |
389 | dev_res->res->end += get_res_add_size(realloc_head, |
390 | dev_res->res); | |
3e6e0d80 | 391 | |
d74b9027 WY |
392 | /* |
393 | * There are two kinds of additional resources in the list: | |
394 | * 1. bridge resource -- IORESOURCE_STARTALIGN | |
0d607618 | 395 | * 2. SR-IOV resource -- IORESOURCE_SIZEALIGN |
d74b9027 WY |
396 | * Here just fix the additional alignment for bridge |
397 | */ | |
398 | if (!(dev_res->res->flags & IORESOURCE_STARTALIGN)) | |
399 | continue; | |
400 | ||
401 | add_align = get_res_add_align(realloc_head, dev_res->res); | |
402 | ||
403 | /* | |
0d607618 NJ |
404 | * The "head" list is sorted by alignment so resources with |
405 | * bigger alignment will be assigned first. After we | |
406 | * change the alignment of a dev_res in "head" list, we | |
407 | * need to reorder the list by alignment to make it | |
d74b9027 WY |
408 | * consistent. |
409 | */ | |
410 | if (add_align > dev_res->res->start) { | |
552bc94e YL |
411 | resource_size_t r_size = resource_size(dev_res->res); |
412 | ||
d74b9027 | 413 | dev_res->res->start = add_align; |
552bc94e | 414 | dev_res->res->end = add_align + r_size - 1; |
d74b9027 WY |
415 | |
416 | list_for_each_entry(dev_res2, head, list) { | |
417 | align = pci_resource_alignment(dev_res2->dev, | |
418 | dev_res2->res); | |
a6b65983 | 419 | if (add_align > align) { |
d74b9027 WY |
420 | list_move_tail(&dev_res->list, |
421 | &dev_res2->list); | |
a6b65983 WY |
422 | break; |
423 | } | |
d74b9027 | 424 | } |
ff3ce480 | 425 | } |
d74b9027 WY |
426 | |
427 | } | |
428 | ||
3e6e0d80 | 429 | /* Try updated head list with add_size added */ |
3e6e0d80 YL |
430 | assign_requested_resources_sorted(head, &local_fail_head); |
431 | ||
0d607618 | 432 | /* All assigned with add_size? */ |
bdc4abec | 433 | if (list_empty(&local_fail_head)) { |
3e6e0d80 | 434 | /* Remove head list from realloc_head list */ |
bdc4abec YL |
435 | list_for_each_entry(dev_res, head, list) |
436 | remove_from_list(realloc_head, dev_res->res); | |
bffc56d4 YL |
437 | free_list(&save_head); |
438 | free_list(head); | |
3e6e0d80 YL |
439 | return; |
440 | } | |
441 | ||
0d607618 | 442 | /* Check failed type */ |
aa914f5e | 443 | fail_type = pci_fail_res_type_mask(&local_fail_head); |
0d607618 | 444 | /* Remove not need to be released assigned res from head list etc */ |
aa914f5e YL |
445 | list_for_each_entry_safe(dev_res, tmp_res, head, list) |
446 | if (dev_res->res->parent && | |
447 | !pci_need_to_release(fail_type, dev_res->res)) { | |
0d607618 | 448 | /* Remove it from realloc_head list */ |
aa914f5e YL |
449 | remove_from_list(realloc_head, dev_res->res); |
450 | remove_from_list(&save_head, dev_res->res); | |
451 | list_del(&dev_res->list); | |
452 | kfree(dev_res); | |
453 | } | |
454 | ||
bffc56d4 | 455 | free_list(&local_fail_head); |
3e6e0d80 | 456 | /* Release assigned resource */ |
bdc4abec YL |
457 | list_for_each_entry(dev_res, head, list) |
458 | if (dev_res->res->parent) | |
459 | release_resource(dev_res->res); | |
3e6e0d80 | 460 | /* Restore start/end/flags from saved list */ |
b9b0bba9 YL |
461 | list_for_each_entry(save_res, &save_head, list) { |
462 | struct resource *res = save_res->res; | |
3e6e0d80 | 463 | |
b9b0bba9 YL |
464 | res->start = save_res->start; |
465 | res->end = save_res->end; | |
466 | res->flags = save_res->flags; | |
3e6e0d80 | 467 | } |
bffc56d4 | 468 | free_list(&save_head); |
3e6e0d80 YL |
469 | |
470 | requested_and_reassign: | |
c8adf9a3 RP |
471 | /* Satisfy the must-have resource requests */ |
472 | assign_requested_resources_sorted(head, fail_head); | |
473 | ||
0d607618 | 474 | /* Try to satisfy any additional optional resource requests */ |
9e8bf93a RP |
475 | if (realloc_head) |
476 | reassign_resources_sorted(realloc_head, head); | |
bffc56d4 | 477 | free_list(head); |
c8adf9a3 RP |
478 | } |
479 | ||
6841ec68 | 480 | static void pdev_assign_resources_sorted(struct pci_dev *dev, |
0d607618 NJ |
481 | struct list_head *add_head, |
482 | struct list_head *fail_head) | |
6841ec68 | 483 | { |
bdc4abec | 484 | LIST_HEAD(head); |
6841ec68 | 485 | |
6841ec68 | 486 | __dev_sort_resources(dev, &head); |
8424d759 | 487 | __assign_resources_sorted(&head, add_head, fail_head); |
6841ec68 YL |
488 | |
489 | } | |
490 | ||
491 | static void pbus_assign_resources_sorted(const struct pci_bus *bus, | |
bdc4abec YL |
492 | struct list_head *realloc_head, |
493 | struct list_head *fail_head) | |
6841ec68 YL |
494 | { |
495 | struct pci_dev *dev; | |
bdc4abec | 496 | LIST_HEAD(head); |
6841ec68 | 497 | |
6841ec68 YL |
498 | list_for_each_entry(dev, &bus->devices, bus_list) |
499 | __dev_sort_resources(dev, &head); | |
500 | ||
9e8bf93a | 501 | __assign_resources_sorted(&head, realloc_head, fail_head); |
6841ec68 YL |
502 | } |
503 | ||
b3743fa4 | 504 | void pci_setup_cardbus(struct pci_bus *bus) |
1da177e4 LT |
505 | { |
506 | struct pci_dev *bridge = bus->self; | |
c7dabef8 | 507 | struct resource *res; |
1da177e4 LT |
508 | struct pci_bus_region region; |
509 | ||
7506dc79 | 510 | pci_info(bridge, "CardBus bridge to %pR\n", |
b918c62e | 511 | &bus->busn_res); |
1da177e4 | 512 | |
c7dabef8 | 513 | res = bus->resource[0]; |
fc279850 | 514 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 | 515 | if (res->flags & IORESOURCE_IO) { |
1da177e4 LT |
516 | /* |
517 | * The IO resource is allocated a range twice as large as it | |
518 | * would normally need. This allows us to set both IO regs. | |
519 | */ | |
7506dc79 | 520 | pci_info(bridge, " bridge window %pR\n", res); |
1da177e4 LT |
521 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, |
522 | region.start); | |
523 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0, | |
524 | region.end); | |
525 | } | |
526 | ||
c7dabef8 | 527 | res = bus->resource[1]; |
fc279850 | 528 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 | 529 | if (res->flags & IORESOURCE_IO) { |
7506dc79 | 530 | pci_info(bridge, " bridge window %pR\n", res); |
1da177e4 LT |
531 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, |
532 | region.start); | |
533 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1, | |
534 | region.end); | |
535 | } | |
536 | ||
c7dabef8 | 537 | res = bus->resource[2]; |
fc279850 | 538 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 | 539 | if (res->flags & IORESOURCE_MEM) { |
7506dc79 | 540 | pci_info(bridge, " bridge window %pR\n", res); |
1da177e4 LT |
541 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, |
542 | region.start); | |
543 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0, | |
544 | region.end); | |
545 | } | |
546 | ||
c7dabef8 | 547 | res = bus->resource[3]; |
fc279850 | 548 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 | 549 | if (res->flags & IORESOURCE_MEM) { |
7506dc79 | 550 | pci_info(bridge, " bridge window %pR\n", res); |
1da177e4 LT |
551 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, |
552 | region.start); | |
553 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1, | |
554 | region.end); | |
555 | } | |
556 | } | |
b3743fa4 | 557 | EXPORT_SYMBOL(pci_setup_cardbus); |
1da177e4 | 558 | |
0d607618 NJ |
559 | /* |
560 | * Initialize bridges with base/limit values we have collected. PCI-to-PCI | |
561 | * Bridge Architecture Specification rev. 1.1 (1998) requires that if there | |
562 | * are no I/O ports or memory behind the bridge, the corresponding range | |
563 | * must be turned off by writing base value greater than limit to the | |
564 | * bridge's base/limit registers. | |
565 | * | |
566 | * Note: care must be taken when updating I/O base/limit registers of | |
567 | * bridges which support 32-bit I/O. This update requires two config space | |
568 | * writes, so it's quite possible that an I/O window of the bridge will | |
569 | * have some undesirable address (e.g. 0) after the first write. Ditto | |
570 | * 64-bit prefetchable MMIO. | |
571 | */ | |
3f2f4dc4 | 572 | static void pci_setup_bridge_io(struct pci_dev *bridge) |
1da177e4 | 573 | { |
c7dabef8 | 574 | struct resource *res; |
1da177e4 | 575 | struct pci_bus_region region; |
2b28ae19 BH |
576 | unsigned long io_mask; |
577 | u8 io_base_lo, io_limit_lo; | |
5b764b83 BH |
578 | u16 l; |
579 | u32 io_upper16; | |
1da177e4 | 580 | |
2b28ae19 BH |
581 | io_mask = PCI_IO_RANGE_MASK; |
582 | if (bridge->io_window_1k) | |
583 | io_mask = PCI_IO_1K_RANGE_MASK; | |
584 | ||
0d607618 | 585 | /* Set up the top and bottom of the PCI I/O segment for this bus */ |
3f2f4dc4 | 586 | res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0]; |
fc279850 | 587 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 | 588 | if (res->flags & IORESOURCE_IO) { |
5b764b83 | 589 | pci_read_config_word(bridge, PCI_IO_BASE, &l); |
2b28ae19 BH |
590 | io_base_lo = (region.start >> 8) & io_mask; |
591 | io_limit_lo = (region.end >> 8) & io_mask; | |
5b764b83 | 592 | l = ((u16) io_limit_lo << 8) | io_base_lo; |
0d607618 | 593 | /* Set up upper 16 bits of I/O base/limit */ |
1da177e4 | 594 | io_upper16 = (region.end & 0xffff0000) | (region.start >> 16); |
7506dc79 | 595 | pci_info(bridge, " bridge window %pR\n", res); |
7cc5997d | 596 | } else { |
0d607618 | 597 | /* Clear upper 16 bits of I/O base/limit */ |
1da177e4 LT |
598 | io_upper16 = 0; |
599 | l = 0x00f0; | |
1da177e4 | 600 | } |
0d607618 | 601 | /* Temporarily disable the I/O range before updating PCI_IO_BASE */ |
1da177e4 | 602 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff); |
0d607618 | 603 | /* Update lower 16 bits of I/O base/limit */ |
5b764b83 | 604 | pci_write_config_word(bridge, PCI_IO_BASE, l); |
0d607618 | 605 | /* Update upper 16 bits of I/O base/limit */ |
1da177e4 | 606 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16); |
7cc5997d YL |
607 | } |
608 | ||
3f2f4dc4 | 609 | static void pci_setup_bridge_mmio(struct pci_dev *bridge) |
7cc5997d | 610 | { |
7cc5997d YL |
611 | struct resource *res; |
612 | struct pci_bus_region region; | |
613 | u32 l; | |
1da177e4 | 614 | |
0d607618 | 615 | /* Set up the top and bottom of the PCI Memory segment for this bus */ |
3f2f4dc4 | 616 | res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1]; |
fc279850 | 617 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 | 618 | if (res->flags & IORESOURCE_MEM) { |
1da177e4 LT |
619 | l = (region.start >> 16) & 0xfff0; |
620 | l |= region.end & 0xfff00000; | |
7506dc79 | 621 | pci_info(bridge, " bridge window %pR\n", res); |
7cc5997d | 622 | } else { |
1da177e4 | 623 | l = 0x0000fff0; |
1da177e4 LT |
624 | } |
625 | pci_write_config_dword(bridge, PCI_MEMORY_BASE, l); | |
7cc5997d YL |
626 | } |
627 | ||
3f2f4dc4 | 628 | static void pci_setup_bridge_mmio_pref(struct pci_dev *bridge) |
7cc5997d | 629 | { |
7cc5997d YL |
630 | struct resource *res; |
631 | struct pci_bus_region region; | |
632 | u32 l, bu, lu; | |
1da177e4 | 633 | |
0d607618 NJ |
634 | /* |
635 | * Clear out the upper 32 bits of PREF limit. If | |
636 | * PCI_PREF_BASE_UPPER32 was non-zero, this temporarily disables | |
637 | * PREF range, which is ok. | |
638 | */ | |
1da177e4 LT |
639 | pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0); |
640 | ||
0d607618 | 641 | /* Set up PREF base/limit */ |
c40a22e0 | 642 | bu = lu = 0; |
3f2f4dc4 | 643 | res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2]; |
fc279850 | 644 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 | 645 | if (res->flags & IORESOURCE_PREFETCH) { |
1da177e4 LT |
646 | l = (region.start >> 16) & 0xfff0; |
647 | l |= region.end & 0xfff00000; | |
c7dabef8 | 648 | if (res->flags & IORESOURCE_MEM_64) { |
1f82de10 YL |
649 | bu = upper_32_bits(region.start); |
650 | lu = upper_32_bits(region.end); | |
1f82de10 | 651 | } |
7506dc79 | 652 | pci_info(bridge, " bridge window %pR\n", res); |
7cc5997d | 653 | } else { |
1da177e4 | 654 | l = 0x0000fff0; |
1da177e4 LT |
655 | } |
656 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l); | |
657 | ||
0d607618 | 658 | /* Set the upper 32 bits of PREF base & limit */ |
59353ea3 AW |
659 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu); |
660 | pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu); | |
7cc5997d YL |
661 | } |
662 | ||
663 | static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type) | |
664 | { | |
665 | struct pci_dev *bridge = bus->self; | |
666 | ||
7506dc79 | 667 | pci_info(bridge, "PCI bridge to %pR\n", |
b918c62e | 668 | &bus->busn_res); |
7cc5997d YL |
669 | |
670 | if (type & IORESOURCE_IO) | |
3f2f4dc4 | 671 | pci_setup_bridge_io(bridge); |
7cc5997d YL |
672 | |
673 | if (type & IORESOURCE_MEM) | |
3f2f4dc4 | 674 | pci_setup_bridge_mmio(bridge); |
7cc5997d YL |
675 | |
676 | if (type & IORESOURCE_PREFETCH) | |
3f2f4dc4 | 677 | pci_setup_bridge_mmio_pref(bridge); |
1da177e4 LT |
678 | |
679 | pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl); | |
680 | } | |
681 | ||
d366d28c GS |
682 | void __weak pcibios_setup_bridge(struct pci_bus *bus, unsigned long type) |
683 | { | |
684 | } | |
685 | ||
e2444273 | 686 | void pci_setup_bridge(struct pci_bus *bus) |
7cc5997d YL |
687 | { |
688 | unsigned long type = IORESOURCE_IO | IORESOURCE_MEM | | |
689 | IORESOURCE_PREFETCH; | |
690 | ||
d366d28c | 691 | pcibios_setup_bridge(bus, type); |
7cc5997d YL |
692 | __pci_setup_bridge(bus, type); |
693 | } | |
694 | ||
8505e729 YL |
695 | |
696 | int pci_claim_bridge_resource(struct pci_dev *bridge, int i) | |
697 | { | |
698 | if (i < PCI_BRIDGE_RESOURCES || i > PCI_BRIDGE_RESOURCE_END) | |
699 | return 0; | |
700 | ||
701 | if (pci_claim_resource(bridge, i) == 0) | |
0d607618 | 702 | return 0; /* Claimed the window */ |
8505e729 YL |
703 | |
704 | if ((bridge->class >> 8) != PCI_CLASS_BRIDGE_PCI) | |
705 | return 0; | |
706 | ||
707 | if (!pci_bus_clip_resource(bridge, i)) | |
0d607618 | 708 | return -EINVAL; /* Clipping didn't change anything */ |
8505e729 YL |
709 | |
710 | switch (i - PCI_BRIDGE_RESOURCES) { | |
711 | case 0: | |
712 | pci_setup_bridge_io(bridge); | |
713 | break; | |
714 | case 1: | |
715 | pci_setup_bridge_mmio(bridge); | |
716 | break; | |
717 | case 2: | |
718 | pci_setup_bridge_mmio_pref(bridge); | |
719 | break; | |
720 | default: | |
721 | return -EINVAL; | |
722 | } | |
723 | ||
724 | if (pci_claim_resource(bridge, i) == 0) | |
0d607618 | 725 | return 0; /* Claimed a smaller window */ |
8505e729 YL |
726 | |
727 | return -EINVAL; | |
728 | } | |
729 | ||
0d607618 NJ |
730 | /* |
731 | * Check whether the bridge supports optional I/O and prefetchable memory | |
732 | * ranges. If not, the respective base/limit registers must be read-only | |
733 | * and read as 0. | |
734 | */ | |
96bde06a | 735 | static void pci_bridge_check_ranges(struct pci_bus *bus) |
1da177e4 | 736 | { |
1da177e4 | 737 | struct pci_dev *bridge = bus->self; |
51c48b31 | 738 | struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; |
1da177e4 | 739 | |
1da177e4 LT |
740 | b_res[1].flags |= IORESOURCE_MEM; |
741 | ||
51c48b31 | 742 | if (bridge->io_window) |
1da177e4 | 743 | b_res[0].flags |= IORESOURCE_IO; |
d2f54d9b | 744 | |
51c48b31 | 745 | if (bridge->pref_window) { |
1da177e4 | 746 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; |
51c48b31 | 747 | if (bridge->pref_64_window) { |
1f82de10 | 748 | b_res[2].flags |= IORESOURCE_MEM_64; |
99586105 YL |
749 | b_res[2].flags |= PCI_PREF_RANGE_TYPE_64; |
750 | } | |
1f82de10 | 751 | } |
1da177e4 LT |
752 | } |
753 | ||
0d607618 NJ |
754 | /* |
755 | * Helper function for sizing routines: find first available bus resource | |
756 | * of a given type. Note: we intentionally skip the bus resources which | |
757 | * have already been assigned (that is, have non-NULL parent resource). | |
758 | */ | |
5b285415 | 759 | static struct resource *find_free_bus_resource(struct pci_bus *bus, |
0d607618 NJ |
760 | unsigned long type_mask, |
761 | unsigned long type) | |
1da177e4 LT |
762 | { |
763 | int i; | |
764 | struct resource *r; | |
1da177e4 | 765 | |
89a74ecc | 766 | pci_bus_for_each_resource(bus, r, i) { |
299de034 IK |
767 | if (r == &ioport_resource || r == &iomem_resource) |
768 | continue; | |
55a10984 JB |
769 | if (r && (r->flags & type_mask) == type && !r->parent) |
770 | return r; | |
1da177e4 LT |
771 | } |
772 | return NULL; | |
773 | } | |
774 | ||
13583b16 | 775 | static resource_size_t calculate_iosize(resource_size_t size, |
0d607618 NJ |
776 | resource_size_t min_size, |
777 | resource_size_t size1, | |
778 | resource_size_t add_size, | |
779 | resource_size_t children_add_size, | |
780 | resource_size_t old_size, | |
781 | resource_size_t align) | |
13583b16 RP |
782 | { |
783 | if (size < min_size) | |
784 | size = min_size; | |
3c78bc61 | 785 | if (old_size == 1) |
13583b16 | 786 | old_size = 0; |
0d607618 NJ |
787 | /* |
788 | * To be fixed in 2.5: we should have sort of HAVE_ISA flag in the | |
789 | * struct pci_bus. | |
790 | */ | |
13583b16 RP |
791 | #if defined(CONFIG_ISA) || defined(CONFIG_EISA) |
792 | size = (size & 0xff) + ((size & ~0xffUL) << 2); | |
793 | #endif | |
de3ffa30 | 794 | size = size + size1; |
13583b16 RP |
795 | if (size < old_size) |
796 | size = old_size; | |
de3ffa30 JD |
797 | |
798 | size = ALIGN(max(size, add_size) + children_add_size, align); | |
13583b16 RP |
799 | return size; |
800 | } | |
801 | ||
802 | static resource_size_t calculate_memsize(resource_size_t size, | |
0d607618 NJ |
803 | resource_size_t min_size, |
804 | resource_size_t add_size, | |
805 | resource_size_t children_add_size, | |
806 | resource_size_t old_size, | |
807 | resource_size_t align) | |
13583b16 RP |
808 | { |
809 | if (size < min_size) | |
810 | size = min_size; | |
3c78bc61 | 811 | if (old_size == 1) |
13583b16 RP |
812 | old_size = 0; |
813 | if (size < old_size) | |
814 | size = old_size; | |
de3ffa30 JD |
815 | |
816 | size = ALIGN(max(size, add_size) + children_add_size, align); | |
13583b16 RP |
817 | return size; |
818 | } | |
819 | ||
ac5ad93e GS |
820 | resource_size_t __weak pcibios_window_alignment(struct pci_bus *bus, |
821 | unsigned long type) | |
822 | { | |
823 | return 1; | |
824 | } | |
825 | ||
826 | #define PCI_P2P_DEFAULT_MEM_ALIGN 0x100000 /* 1MiB */ | |
827 | #define PCI_P2P_DEFAULT_IO_ALIGN 0x1000 /* 4KiB */ | |
828 | #define PCI_P2P_DEFAULT_IO_ALIGN_1K 0x400 /* 1KiB */ | |
829 | ||
0d607618 | 830 | static resource_size_t window_alignment(struct pci_bus *bus, unsigned long type) |
ac5ad93e GS |
831 | { |
832 | resource_size_t align = 1, arch_align; | |
833 | ||
834 | if (type & IORESOURCE_MEM) | |
835 | align = PCI_P2P_DEFAULT_MEM_ALIGN; | |
836 | else if (type & IORESOURCE_IO) { | |
837 | /* | |
0d607618 NJ |
838 | * Per spec, I/O windows are 4K-aligned, but some bridges have |
839 | * an extension to support 1K alignment. | |
ac5ad93e GS |
840 | */ |
841 | if (bus->self->io_window_1k) | |
842 | align = PCI_P2P_DEFAULT_IO_ALIGN_1K; | |
843 | else | |
844 | align = PCI_P2P_DEFAULT_IO_ALIGN; | |
845 | } | |
846 | ||
847 | arch_align = pcibios_window_alignment(bus, type); | |
848 | return max(align, arch_align); | |
849 | } | |
850 | ||
c8adf9a3 | 851 | /** |
0d607618 | 852 | * pbus_size_io() - Size the I/O window of a given bus |
c8adf9a3 | 853 | * |
0d607618 NJ |
854 | * @bus: The bus |
855 | * @min_size: The minimum I/O window that must be allocated | |
856 | * @add_size: Additional optional I/O window | |
857 | * @realloc_head: Track the additional I/O window on this list | |
c8adf9a3 | 858 | * |
0d607618 NJ |
859 | * Sizing the I/O windows of the PCI-PCI bridge is trivial, since these |
860 | * windows have 1K or 4K granularity and the I/O ranges of non-bridge PCI | |
861 | * devices are limited to 256 bytes. We must be careful with the ISA | |
862 | * aliasing though. | |
c8adf9a3 RP |
863 | */ |
864 | static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size, | |
0d607618 NJ |
865 | resource_size_t add_size, |
866 | struct list_head *realloc_head) | |
1da177e4 LT |
867 | { |
868 | struct pci_dev *dev; | |
5b285415 YL |
869 | struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO, |
870 | IORESOURCE_IO); | |
11251a86 | 871 | resource_size_t size = 0, size0 = 0, size1 = 0; |
be768912 | 872 | resource_size_t children_add_size = 0; |
2d1d6678 | 873 | resource_size_t min_align, align; |
1da177e4 LT |
874 | |
875 | if (!b_res) | |
f7625980 | 876 | return; |
1da177e4 | 877 | |
2d1d6678 | 878 | min_align = window_alignment(bus, IORESOURCE_IO); |
1da177e4 LT |
879 | list_for_each_entry(dev, &bus->devices, bus_list) { |
880 | int i; | |
881 | ||
882 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
883 | struct resource *r = &dev->resource[i]; | |
884 | unsigned long r_size; | |
885 | ||
886 | if (r->parent || !(r->flags & IORESOURCE_IO)) | |
887 | continue; | |
022edd86 | 888 | r_size = resource_size(r); |
1da177e4 LT |
889 | |
890 | if (r_size < 0x400) | |
891 | /* Might be re-aligned for ISA */ | |
892 | size += r_size; | |
893 | else | |
894 | size1 += r_size; | |
be768912 | 895 | |
fd591341 YL |
896 | align = pci_resource_alignment(dev, r); |
897 | if (align > min_align) | |
898 | min_align = align; | |
899 | ||
9e8bf93a RP |
900 | if (realloc_head) |
901 | children_add_size += get_res_add_size(realloc_head, r); | |
1da177e4 LT |
902 | } |
903 | } | |
fd591341 | 904 | |
de3ffa30 | 905 | size0 = calculate_iosize(size, min_size, size1, 0, 0, |
fd591341 | 906 | resource_size(b_res), min_align); |
de3ffa30 JD |
907 | size1 = (!realloc_head || (realloc_head && !add_size && !children_add_size)) ? size0 : |
908 | calculate_iosize(size, min_size, size1, add_size, children_add_size, | |
fd591341 | 909 | resource_size(b_res), min_align); |
c8adf9a3 | 910 | if (!size0 && !size1) { |
865df576 | 911 | if (b_res->start || b_res->end) |
7506dc79 | 912 | pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n", |
227f0647 | 913 | b_res, &bus->busn_res); |
1da177e4 LT |
914 | b_res->flags = 0; |
915 | return; | |
916 | } | |
fd591341 YL |
917 | |
918 | b_res->start = min_align; | |
c8adf9a3 | 919 | b_res->end = b_res->start + size0 - 1; |
88452565 | 920 | b_res->flags |= IORESOURCE_STARTALIGN; |
b592443d | 921 | if (size1 > size0 && realloc_head) { |
fd591341 YL |
922 | add_to_list(realloc_head, bus->self, b_res, size1-size0, |
923 | min_align); | |
34c6b710 MK |
924 | pci_info(bus->self, "bridge window %pR to %pR add_size %llx\n", |
925 | b_res, &bus->busn_res, | |
926 | (unsigned long long) size1 - size0); | |
b592443d | 927 | } |
1da177e4 LT |
928 | } |
929 | ||
c121504e GS |
930 | static inline resource_size_t calculate_mem_align(resource_size_t *aligns, |
931 | int max_order) | |
932 | { | |
933 | resource_size_t align = 0; | |
934 | resource_size_t min_align = 0; | |
935 | int order; | |
936 | ||
937 | for (order = 0; order <= max_order; order++) { | |
938 | resource_size_t align1 = 1; | |
939 | ||
940 | align1 <<= (order + 20); | |
941 | ||
942 | if (!align) | |
943 | min_align = align1; | |
944 | else if (ALIGN(align + min_align, min_align) < align1) | |
945 | min_align = align1 >> 1; | |
946 | align += aligns[order]; | |
947 | } | |
948 | ||
949 | return min_align; | |
950 | } | |
951 | ||
c8adf9a3 | 952 | /** |
0d607618 | 953 | * pbus_size_mem() - Size the memory window of a given bus |
c8adf9a3 | 954 | * |
0d607618 NJ |
955 | * @bus: The bus |
956 | * @mask: Mask the resource flag, then compare it with type | |
957 | * @type: The type of free resource from bridge | |
958 | * @type2: Second match type | |
959 | * @type3: Third match type | |
960 | * @min_size: The minimum memory window that must be allocated | |
961 | * @add_size: Additional optional memory window | |
962 | * @realloc_head: Track the additional memory window on this list | |
c8adf9a3 | 963 | * |
0d607618 NJ |
964 | * Calculate the size of the bus and minimal alignment which guarantees |
965 | * that all child resources fit in this size. | |
30afe8d0 | 966 | * |
0d607618 NJ |
967 | * Return -ENOSPC if there's no available bus resource of the desired |
968 | * type. Otherwise, set the bus resource start/end to indicate the | |
969 | * required size, add things to realloc_head (if supplied), and return 0. | |
c8adf9a3 | 970 | */ |
28760489 | 971 | static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, |
5b285415 | 972 | unsigned long type, unsigned long type2, |
0d607618 NJ |
973 | unsigned long type3, resource_size_t min_size, |
974 | resource_size_t add_size, | |
5b285415 | 975 | struct list_head *realloc_head) |
1da177e4 LT |
976 | { |
977 | struct pci_dev *dev; | |
c8adf9a3 | 978 | resource_size_t min_align, align, size, size0, size1; |
0d607618 | 979 | resource_size_t aligns[18]; /* Alignments from 1MB to 128GB */ |
1da177e4 | 980 | int order, max_order; |
5b285415 YL |
981 | struct resource *b_res = find_free_bus_resource(bus, |
982 | mask | IORESOURCE_PREFETCH, type); | |
be768912 | 983 | resource_size_t children_add_size = 0; |
d74b9027 WY |
984 | resource_size_t children_add_align = 0; |
985 | resource_size_t add_align = 0; | |
1da177e4 LT |
986 | |
987 | if (!b_res) | |
30afe8d0 | 988 | return -ENOSPC; |
1da177e4 LT |
989 | |
990 | memset(aligns, 0, sizeof(aligns)); | |
991 | max_order = 0; | |
992 | size = 0; | |
993 | ||
994 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
995 | int i; | |
1f82de10 | 996 | |
1da177e4 LT |
997 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { |
998 | struct resource *r = &dev->resource[i]; | |
c40a22e0 | 999 | resource_size_t r_size; |
1da177e4 | 1000 | |
a2220d80 DD |
1001 | if (r->parent || (r->flags & IORESOURCE_PCI_FIXED) || |
1002 | ((r->flags & mask) != type && | |
1003 | (r->flags & mask) != type2 && | |
1004 | (r->flags & mask) != type3)) | |
1da177e4 | 1005 | continue; |
022edd86 | 1006 | r_size = resource_size(r); |
2aceefcb | 1007 | #ifdef CONFIG_PCI_IOV |
0d607618 | 1008 | /* Put SRIOV requested res to the optional list */ |
9e8bf93a | 1009 | if (realloc_head && i >= PCI_IOV_RESOURCES && |
2aceefcb | 1010 | i <= PCI_IOV_RESOURCE_END) { |
d74b9027 | 1011 | add_align = max(pci_resource_alignment(dev, r), add_align); |
2aceefcb | 1012 | r->end = r->start - 1; |
0d607618 | 1013 | add_to_list(realloc_head, dev, r, r_size, 0 /* Don't care */); |
2aceefcb YL |
1014 | children_add_size += r_size; |
1015 | continue; | |
1016 | } | |
1017 | #endif | |
14c8530d A |
1018 | /* |
1019 | * aligns[0] is for 1MB (since bridge memory | |
1020 | * windows are always at least 1MB aligned), so | |
1021 | * keep "order" from being negative for smaller | |
1022 | * resources. | |
1023 | */ | |
6faf17f6 | 1024 | align = pci_resource_alignment(dev, r); |
1da177e4 | 1025 | order = __ffs(align) - 20; |
14c8530d A |
1026 | if (order < 0) |
1027 | order = 0; | |
1028 | if (order >= ARRAY_SIZE(aligns)) { | |
7506dc79 | 1029 | pci_warn(dev, "disabling BAR %d: %pR (bad alignment %#llx)\n", |
227f0647 | 1030 | i, r, (unsigned long long) align); |
1da177e4 LT |
1031 | r->flags = 0; |
1032 | continue; | |
1033 | } | |
c9c75143 | 1034 | size += max(r_size, align); |
0d607618 NJ |
1035 | /* |
1036 | * Exclude ranges with size > align from calculation of | |
1037 | * the alignment. | |
1038 | */ | |
c9c75143 | 1039 | if (r_size <= align) |
1da177e4 LT |
1040 | aligns[order] += align; |
1041 | if (order > max_order) | |
1042 | max_order = order; | |
be768912 | 1043 | |
d74b9027 | 1044 | if (realloc_head) { |
9e8bf93a | 1045 | children_add_size += get_res_add_size(realloc_head, r); |
d74b9027 WY |
1046 | children_add_align = get_res_add_align(realloc_head, r); |
1047 | add_align = max(add_align, children_add_align); | |
1048 | } | |
1da177e4 LT |
1049 | } |
1050 | } | |
462d9303 | 1051 | |
c121504e | 1052 | min_align = calculate_mem_align(aligns, max_order); |
3ad94b0d | 1053 | min_align = max(min_align, window_alignment(bus, b_res->flags)); |
de3ffa30 | 1054 | size0 = calculate_memsize(size, min_size, 0, 0, resource_size(b_res), min_align); |
d74b9027 | 1055 | add_align = max(min_align, add_align); |
de3ffa30 JD |
1056 | size1 = (!realloc_head || (realloc_head && !add_size && !children_add_size)) ? size0 : |
1057 | calculate_memsize(size, min_size, add_size, children_add_size, | |
d74b9027 | 1058 | resource_size(b_res), add_align); |
c8adf9a3 | 1059 | if (!size0 && !size1) { |
865df576 | 1060 | if (b_res->start || b_res->end) |
7506dc79 | 1061 | pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n", |
227f0647 | 1062 | b_res, &bus->busn_res); |
1da177e4 | 1063 | b_res->flags = 0; |
30afe8d0 | 1064 | return 0; |
1da177e4 LT |
1065 | } |
1066 | b_res->start = min_align; | |
c8adf9a3 | 1067 | b_res->end = size0 + min_align - 1; |
5b285415 | 1068 | b_res->flags |= IORESOURCE_STARTALIGN; |
b592443d | 1069 | if (size1 > size0 && realloc_head) { |
d74b9027 | 1070 | add_to_list(realloc_head, bus->self, b_res, size1-size0, add_align); |
34c6b710 | 1071 | pci_info(bus->self, "bridge window %pR to %pR add_size %llx add_align %llx\n", |
227f0647 | 1072 | b_res, &bus->busn_res, |
d74b9027 WY |
1073 | (unsigned long long) (size1 - size0), |
1074 | (unsigned long long) add_align); | |
b592443d | 1075 | } |
30afe8d0 | 1076 | return 0; |
1da177e4 LT |
1077 | } |
1078 | ||
0a2daa1c RP |
1079 | unsigned long pci_cardbus_resource_alignment(struct resource *res) |
1080 | { | |
1081 | if (res->flags & IORESOURCE_IO) | |
1082 | return pci_cardbus_io_size; | |
1083 | if (res->flags & IORESOURCE_MEM) | |
1084 | return pci_cardbus_mem_size; | |
1085 | return 0; | |
1086 | } | |
1087 | ||
1088 | static void pci_bus_size_cardbus(struct pci_bus *bus, | |
0d607618 | 1089 | struct list_head *realloc_head) |
1da177e4 LT |
1090 | { |
1091 | struct pci_dev *bridge = bus->self; | |
1092 | struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; | |
11848934 | 1093 | resource_size_t b_res_3_size = pci_cardbus_mem_size * 2; |
1da177e4 LT |
1094 | u16 ctrl; |
1095 | ||
3796f1e2 YL |
1096 | if (b_res[0].parent) |
1097 | goto handle_b_res_1; | |
1da177e4 | 1098 | /* |
0d607618 NJ |
1099 | * Reserve some resources for CardBus. We reserve a fixed amount |
1100 | * of bus space for CardBus bridges. | |
1da177e4 | 1101 | */ |
11848934 YL |
1102 | b_res[0].start = pci_cardbus_io_size; |
1103 | b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1; | |
1104 | b_res[0].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN; | |
1105 | if (realloc_head) { | |
1106 | b_res[0].end -= pci_cardbus_io_size; | |
1107 | add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size, | |
1108 | pci_cardbus_io_size); | |
1109 | } | |
1da177e4 | 1110 | |
3796f1e2 YL |
1111 | handle_b_res_1: |
1112 | if (b_res[1].parent) | |
1113 | goto handle_b_res_2; | |
11848934 YL |
1114 | b_res[1].start = pci_cardbus_io_size; |
1115 | b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1; | |
1116 | b_res[1].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN; | |
1117 | if (realloc_head) { | |
1118 | b_res[1].end -= pci_cardbus_io_size; | |
1119 | add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size, | |
1120 | pci_cardbus_io_size); | |
1121 | } | |
1da177e4 | 1122 | |
3796f1e2 | 1123 | handle_b_res_2: |
0d607618 | 1124 | /* MEM1 must not be pref MMIO */ |
dcef0d06 YL |
1125 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); |
1126 | if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) { | |
1127 | ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1; | |
1128 | pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); | |
1129 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
1130 | } | |
1131 | ||
0d607618 | 1132 | /* Check whether prefetchable memory is supported by this bridge. */ |
1da177e4 LT |
1133 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); |
1134 | if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) { | |
1135 | ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; | |
1136 | pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); | |
1137 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
1138 | } | |
1139 | ||
3796f1e2 YL |
1140 | if (b_res[2].parent) |
1141 | goto handle_b_res_3; | |
1da177e4 | 1142 | /* |
0d607618 NJ |
1143 | * If we have prefetchable memory support, allocate two regions. |
1144 | * Otherwise, allocate one region of twice the size. | |
1da177e4 LT |
1145 | */ |
1146 | if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) { | |
11848934 YL |
1147 | b_res[2].start = pci_cardbus_mem_size; |
1148 | b_res[2].end = b_res[2].start + pci_cardbus_mem_size - 1; | |
1149 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | | |
1150 | IORESOURCE_STARTALIGN; | |
1151 | if (realloc_head) { | |
1152 | b_res[2].end -= pci_cardbus_mem_size; | |
1153 | add_to_list(realloc_head, bridge, b_res+2, | |
1154 | pci_cardbus_mem_size, pci_cardbus_mem_size); | |
1155 | } | |
1156 | ||
0d607618 | 1157 | /* Reduce that to half */ |
11848934 YL |
1158 | b_res_3_size = pci_cardbus_mem_size; |
1159 | } | |
1160 | ||
3796f1e2 YL |
1161 | handle_b_res_3: |
1162 | if (b_res[3].parent) | |
1163 | goto handle_done; | |
11848934 YL |
1164 | b_res[3].start = pci_cardbus_mem_size; |
1165 | b_res[3].end = b_res[3].start + b_res_3_size - 1; | |
1166 | b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN; | |
1167 | if (realloc_head) { | |
1168 | b_res[3].end -= b_res_3_size; | |
1169 | add_to_list(realloc_head, bridge, b_res+3, b_res_3_size, | |
1170 | pci_cardbus_mem_size); | |
1171 | } | |
3796f1e2 YL |
1172 | |
1173 | handle_done: | |
1174 | ; | |
1da177e4 LT |
1175 | } |
1176 | ||
10874f5a | 1177 | void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head) |
1da177e4 LT |
1178 | { |
1179 | struct pci_dev *dev; | |
5b285415 | 1180 | unsigned long mask, prefmask, type2 = 0, type3 = 0; |
c8adf9a3 | 1181 | resource_size_t additional_mem_size = 0, additional_io_size = 0; |
5b285415 | 1182 | struct resource *b_res; |
30afe8d0 | 1183 | int ret; |
1da177e4 LT |
1184 | |
1185 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1186 | struct pci_bus *b = dev->subordinate; | |
1187 | if (!b) | |
1188 | continue; | |
1189 | ||
b2fb5cc5 HZ |
1190 | switch (dev->hdr_type) { |
1191 | case PCI_HEADER_TYPE_CARDBUS: | |
9e8bf93a | 1192 | pci_bus_size_cardbus(b, realloc_head); |
1da177e4 LT |
1193 | break; |
1194 | ||
b2fb5cc5 | 1195 | case PCI_HEADER_TYPE_BRIDGE: |
1da177e4 | 1196 | default: |
9e8bf93a | 1197 | __pci_bus_size_bridges(b, realloc_head); |
1da177e4 LT |
1198 | break; |
1199 | } | |
1200 | } | |
1201 | ||
1202 | /* The root bus? */ | |
2ba29e27 | 1203 | if (pci_is_root_bus(bus)) |
1da177e4 LT |
1204 | return; |
1205 | ||
b2fb5cc5 HZ |
1206 | switch (bus->self->hdr_type) { |
1207 | case PCI_HEADER_TYPE_CARDBUS: | |
0d607618 | 1208 | /* Don't size CardBuses yet */ |
1da177e4 LT |
1209 | break; |
1210 | ||
b2fb5cc5 | 1211 | case PCI_HEADER_TYPE_BRIDGE: |
1da177e4 | 1212 | pci_bridge_check_ranges(bus); |
28760489 | 1213 | if (bus->self->is_hotplug_bridge) { |
c8adf9a3 RP |
1214 | additional_io_size = pci_hotplug_io_size; |
1215 | additional_mem_size = pci_hotplug_mem_size; | |
28760489 | 1216 | } |
67d29b5c | 1217 | /* Fall through */ |
1da177e4 | 1218 | default: |
19aa7ee4 YL |
1219 | pbus_size_io(bus, realloc_head ? 0 : additional_io_size, |
1220 | additional_io_size, realloc_head); | |
67d29b5c BH |
1221 | |
1222 | /* | |
1223 | * If there's a 64-bit prefetchable MMIO window, compute | |
1224 | * the size required to put all 64-bit prefetchable | |
1225 | * resources in it. | |
1226 | */ | |
5b285415 | 1227 | b_res = &bus->self->resource[PCI_BRIDGE_RESOURCES]; |
1da177e4 LT |
1228 | mask = IORESOURCE_MEM; |
1229 | prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
5b285415 YL |
1230 | if (b_res[2].flags & IORESOURCE_MEM_64) { |
1231 | prefmask |= IORESOURCE_MEM_64; | |
30afe8d0 | 1232 | ret = pbus_size_mem(bus, prefmask, prefmask, |
5b285415 | 1233 | prefmask, prefmask, |
19aa7ee4 | 1234 | realloc_head ? 0 : additional_mem_size, |
30afe8d0 | 1235 | additional_mem_size, realloc_head); |
67d29b5c BH |
1236 | |
1237 | /* | |
1238 | * If successful, all non-prefetchable resources | |
1239 | * and any 32-bit prefetchable resources will go in | |
1240 | * the non-prefetchable window. | |
1241 | */ | |
30afe8d0 | 1242 | if (ret == 0) { |
30afe8d0 BH |
1243 | mask = prefmask; |
1244 | type2 = prefmask & ~IORESOURCE_MEM_64; | |
1245 | type3 = prefmask & ~IORESOURCE_PREFETCH; | |
5b285415 YL |
1246 | } |
1247 | } | |
67d29b5c BH |
1248 | |
1249 | /* | |
1250 | * If there is no 64-bit prefetchable window, compute the | |
1251 | * size required to put all prefetchable resources in the | |
1252 | * 32-bit prefetchable window (if there is one). | |
1253 | */ | |
5b285415 YL |
1254 | if (!type2) { |
1255 | prefmask &= ~IORESOURCE_MEM_64; | |
30afe8d0 | 1256 | ret = pbus_size_mem(bus, prefmask, prefmask, |
5b285415 YL |
1257 | prefmask, prefmask, |
1258 | realloc_head ? 0 : additional_mem_size, | |
30afe8d0 | 1259 | additional_mem_size, realloc_head); |
67d29b5c BH |
1260 | |
1261 | /* | |
1262 | * If successful, only non-prefetchable resources | |
1263 | * will go in the non-prefetchable window. | |
1264 | */ | |
1265 | if (ret == 0) | |
5b285415 | 1266 | mask = prefmask; |
67d29b5c | 1267 | else |
5b285415 | 1268 | additional_mem_size += additional_mem_size; |
67d29b5c | 1269 | |
5b285415 YL |
1270 | type2 = type3 = IORESOURCE_MEM; |
1271 | } | |
67d29b5c BH |
1272 | |
1273 | /* | |
1274 | * Compute the size required to put everything else in the | |
0d607618 | 1275 | * non-prefetchable window. This includes: |
67d29b5c BH |
1276 | * |
1277 | * - all non-prefetchable resources | |
1278 | * - 32-bit prefetchable resources if there's a 64-bit | |
1279 | * prefetchable window or no prefetchable window at all | |
0d607618 NJ |
1280 | * - 64-bit prefetchable resources if there's no prefetchable |
1281 | * window at all | |
67d29b5c | 1282 | * |
0d607618 NJ |
1283 | * Note that the strategy in __pci_assign_resource() must match |
1284 | * that used here. Specifically, we cannot put a 32-bit | |
1285 | * prefetchable resource in a 64-bit prefetchable window. | |
67d29b5c | 1286 | */ |
5b285415 | 1287 | pbus_size_mem(bus, mask, IORESOURCE_MEM, type2, type3, |
19aa7ee4 YL |
1288 | realloc_head ? 0 : additional_mem_size, |
1289 | additional_mem_size, realloc_head); | |
1da177e4 LT |
1290 | break; |
1291 | } | |
1292 | } | |
c8adf9a3 | 1293 | |
10874f5a | 1294 | void pci_bus_size_bridges(struct pci_bus *bus) |
c8adf9a3 RP |
1295 | { |
1296 | __pci_bus_size_bridges(bus, NULL); | |
1297 | } | |
1da177e4 LT |
1298 | EXPORT_SYMBOL(pci_bus_size_bridges); |
1299 | ||
d04d0111 DD |
1300 | static void assign_fixed_resource_on_bus(struct pci_bus *b, struct resource *r) |
1301 | { | |
1302 | int i; | |
1303 | struct resource *parent_r; | |
1304 | unsigned long mask = IORESOURCE_IO | IORESOURCE_MEM | | |
1305 | IORESOURCE_PREFETCH; | |
1306 | ||
1307 | pci_bus_for_each_resource(b, parent_r, i) { | |
1308 | if (!parent_r) | |
1309 | continue; | |
1310 | ||
1311 | if ((r->flags & mask) == (parent_r->flags & mask) && | |
1312 | resource_contains(parent_r, r)) | |
1313 | request_resource(parent_r, r); | |
1314 | } | |
1315 | } | |
1316 | ||
1317 | /* | |
0d607618 NJ |
1318 | * Try to assign any resources marked as IORESOURCE_PCI_FIXED, as they are |
1319 | * skipped by pbus_assign_resources_sorted(). | |
d04d0111 DD |
1320 | */ |
1321 | static void pdev_assign_fixed_resources(struct pci_dev *dev) | |
1322 | { | |
1323 | int i; | |
1324 | ||
1325 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
1326 | struct pci_bus *b; | |
1327 | struct resource *r = &dev->resource[i]; | |
1328 | ||
1329 | if (r->parent || !(r->flags & IORESOURCE_PCI_FIXED) || | |
1330 | !(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) | |
1331 | continue; | |
1332 | ||
1333 | b = dev->bus; | |
1334 | while (b && !r->parent) { | |
1335 | assign_fixed_resource_on_bus(b, r); | |
1336 | b = b->parent; | |
1337 | } | |
1338 | } | |
1339 | } | |
1340 | ||
10874f5a BH |
1341 | void __pci_bus_assign_resources(const struct pci_bus *bus, |
1342 | struct list_head *realloc_head, | |
1343 | struct list_head *fail_head) | |
1da177e4 LT |
1344 | { |
1345 | struct pci_bus *b; | |
1346 | struct pci_dev *dev; | |
1347 | ||
9e8bf93a | 1348 | pbus_assign_resources_sorted(bus, realloc_head, fail_head); |
1da177e4 | 1349 | |
1da177e4 | 1350 | list_for_each_entry(dev, &bus->devices, bus_list) { |
d04d0111 DD |
1351 | pdev_assign_fixed_resources(dev); |
1352 | ||
1da177e4 LT |
1353 | b = dev->subordinate; |
1354 | if (!b) | |
1355 | continue; | |
1356 | ||
9e8bf93a | 1357 | __pci_bus_assign_resources(b, realloc_head, fail_head); |
1da177e4 | 1358 | |
b2fb5cc5 HZ |
1359 | switch (dev->hdr_type) { |
1360 | case PCI_HEADER_TYPE_BRIDGE: | |
6841ec68 YL |
1361 | if (!pci_is_enabled(dev)) |
1362 | pci_setup_bridge(b); | |
1da177e4 LT |
1363 | break; |
1364 | ||
b2fb5cc5 | 1365 | case PCI_HEADER_TYPE_CARDBUS: |
1da177e4 LT |
1366 | pci_setup_cardbus(b); |
1367 | break; | |
1368 | ||
1369 | default: | |
7506dc79 | 1370 | pci_info(dev, "not setting up bridge for bus %04x:%02x\n", |
227f0647 | 1371 | pci_domain_nr(b), b->number); |
1da177e4 LT |
1372 | break; |
1373 | } | |
1374 | } | |
1375 | } | |
568ddef8 | 1376 | |
10874f5a | 1377 | void pci_bus_assign_resources(const struct pci_bus *bus) |
568ddef8 | 1378 | { |
c8adf9a3 | 1379 | __pci_bus_assign_resources(bus, NULL, NULL); |
568ddef8 | 1380 | } |
1da177e4 LT |
1381 | EXPORT_SYMBOL(pci_bus_assign_resources); |
1382 | ||
765bf9b7 LP |
1383 | static void pci_claim_device_resources(struct pci_dev *dev) |
1384 | { | |
1385 | int i; | |
1386 | ||
1387 | for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) { | |
1388 | struct resource *r = &dev->resource[i]; | |
1389 | ||
1390 | if (!r->flags || r->parent) | |
1391 | continue; | |
1392 | ||
1393 | pci_claim_resource(dev, i); | |
1394 | } | |
1395 | } | |
1396 | ||
1397 | static void pci_claim_bridge_resources(struct pci_dev *dev) | |
1398 | { | |
1399 | int i; | |
1400 | ||
1401 | for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) { | |
1402 | struct resource *r = &dev->resource[i]; | |
1403 | ||
1404 | if (!r->flags || r->parent) | |
1405 | continue; | |
1406 | ||
1407 | pci_claim_bridge_resource(dev, i); | |
1408 | } | |
1409 | } | |
1410 | ||
1411 | static void pci_bus_allocate_dev_resources(struct pci_bus *b) | |
1412 | { | |
1413 | struct pci_dev *dev; | |
1414 | struct pci_bus *child; | |
1415 | ||
1416 | list_for_each_entry(dev, &b->devices, bus_list) { | |
1417 | pci_claim_device_resources(dev); | |
1418 | ||
1419 | child = dev->subordinate; | |
1420 | if (child) | |
1421 | pci_bus_allocate_dev_resources(child); | |
1422 | } | |
1423 | } | |
1424 | ||
1425 | static void pci_bus_allocate_resources(struct pci_bus *b) | |
1426 | { | |
1427 | struct pci_bus *child; | |
1428 | ||
1429 | /* | |
0d607618 NJ |
1430 | * Carry out a depth-first search on the PCI bus tree to allocate |
1431 | * bridge apertures. Read the programmed bridge bases and | |
1432 | * recursively claim the respective bridge resources. | |
765bf9b7 LP |
1433 | */ |
1434 | if (b->self) { | |
1435 | pci_read_bridge_bases(b); | |
1436 | pci_claim_bridge_resources(b->self); | |
1437 | } | |
1438 | ||
1439 | list_for_each_entry(child, &b->children, node) | |
1440 | pci_bus_allocate_resources(child); | |
1441 | } | |
1442 | ||
1443 | void pci_bus_claim_resources(struct pci_bus *b) | |
1444 | { | |
1445 | pci_bus_allocate_resources(b); | |
1446 | pci_bus_allocate_dev_resources(b); | |
1447 | } | |
1448 | EXPORT_SYMBOL(pci_bus_claim_resources); | |
1449 | ||
10874f5a BH |
1450 | static void __pci_bridge_assign_resources(const struct pci_dev *bridge, |
1451 | struct list_head *add_head, | |
1452 | struct list_head *fail_head) | |
6841ec68 YL |
1453 | { |
1454 | struct pci_bus *b; | |
1455 | ||
8424d759 YL |
1456 | pdev_assign_resources_sorted((struct pci_dev *)bridge, |
1457 | add_head, fail_head); | |
6841ec68 YL |
1458 | |
1459 | b = bridge->subordinate; | |
1460 | if (!b) | |
1461 | return; | |
1462 | ||
8424d759 | 1463 | __pci_bus_assign_resources(b, add_head, fail_head); |
6841ec68 YL |
1464 | |
1465 | switch (bridge->class >> 8) { | |
1466 | case PCI_CLASS_BRIDGE_PCI: | |
1467 | pci_setup_bridge(b); | |
1468 | break; | |
1469 | ||
1470 | case PCI_CLASS_BRIDGE_CARDBUS: | |
1471 | pci_setup_cardbus(b); | |
1472 | break; | |
1473 | ||
1474 | default: | |
7506dc79 | 1475 | pci_info(bridge, "not setting up bridge for bus %04x:%02x\n", |
227f0647 | 1476 | pci_domain_nr(b), b->number); |
6841ec68 YL |
1477 | break; |
1478 | } | |
1479 | } | |
cb21bc94 CK |
1480 | |
1481 | #define PCI_RES_TYPE_MASK \ | |
1482 | (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH |\ | |
1483 | IORESOURCE_MEM_64) | |
1484 | ||
5009b460 | 1485 | static void pci_bridge_release_resources(struct pci_bus *bus, |
0d607618 | 1486 | unsigned long type) |
5009b460 | 1487 | { |
5b285415 | 1488 | struct pci_dev *dev = bus->self; |
5009b460 | 1489 | struct resource *r; |
5b285415 YL |
1490 | unsigned old_flags = 0; |
1491 | struct resource *b_res; | |
1492 | int idx = 1; | |
5009b460 | 1493 | |
5b285415 YL |
1494 | b_res = &dev->resource[PCI_BRIDGE_RESOURCES]; |
1495 | ||
1496 | /* | |
0d607618 NJ |
1497 | * 1. If IO port assignment fails, release bridge IO port. |
1498 | * 2. If non pref MMIO assignment fails, release bridge nonpref MMIO. | |
1499 | * 3. If 64bit pref MMIO assignment fails, and bridge pref is 64bit, | |
1500 | * release bridge pref MMIO. | |
1501 | * 4. If pref MMIO assignment fails, and bridge pref is 32bit, | |
1502 | * release bridge pref MMIO. | |
1503 | * 5. If pref MMIO assignment fails, and bridge pref is not | |
1504 | * assigned, release bridge nonpref MMIO. | |
5b285415 YL |
1505 | */ |
1506 | if (type & IORESOURCE_IO) | |
1507 | idx = 0; | |
1508 | else if (!(type & IORESOURCE_PREFETCH)) | |
1509 | idx = 1; | |
1510 | else if ((type & IORESOURCE_MEM_64) && | |
1511 | (b_res[2].flags & IORESOURCE_MEM_64)) | |
1512 | idx = 2; | |
1513 | else if (!(b_res[2].flags & IORESOURCE_MEM_64) && | |
1514 | (b_res[2].flags & IORESOURCE_PREFETCH)) | |
1515 | idx = 2; | |
1516 | else | |
1517 | idx = 1; | |
1518 | ||
1519 | r = &b_res[idx]; | |
1520 | ||
1521 | if (!r->parent) | |
1522 | return; | |
1523 | ||
0d607618 | 1524 | /* If there are children, release them all */ |
5b285415 YL |
1525 | release_child_resources(r); |
1526 | if (!release_resource(r)) { | |
cb21bc94 | 1527 | type = old_flags = r->flags & PCI_RES_TYPE_MASK; |
34c6b710 MK |
1528 | pci_info(dev, "resource %d %pR released\n", |
1529 | PCI_BRIDGE_RESOURCES + idx, r); | |
0d607618 | 1530 | /* Keep the old size */ |
5b285415 YL |
1531 | r->end = resource_size(r) - 1; |
1532 | r->start = 0; | |
1533 | r->flags = 0; | |
5009b460 | 1534 | |
0d607618 | 1535 | /* Avoiding touch the one without PREF */ |
5009b460 YL |
1536 | if (type & IORESOURCE_PREFETCH) |
1537 | type = IORESOURCE_PREFETCH; | |
1538 | __pci_setup_bridge(bus, type); | |
0d607618 | 1539 | /* For next child res under same bridge */ |
5b285415 | 1540 | r->flags = old_flags; |
5009b460 YL |
1541 | } |
1542 | } | |
1543 | ||
1544 | enum release_type { | |
1545 | leaf_only, | |
1546 | whole_subtree, | |
1547 | }; | |
0d607618 | 1548 | |
5009b460 | 1549 | /* |
0d607618 NJ |
1550 | * Try to release PCI bridge resources from leaf bridge, so we can allocate |
1551 | * a larger window later. | |
5009b460 | 1552 | */ |
10874f5a BH |
1553 | static void pci_bus_release_bridge_resources(struct pci_bus *bus, |
1554 | unsigned long type, | |
1555 | enum release_type rel_type) | |
5009b460 YL |
1556 | { |
1557 | struct pci_dev *dev; | |
1558 | bool is_leaf_bridge = true; | |
1559 | ||
1560 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1561 | struct pci_bus *b = dev->subordinate; | |
1562 | if (!b) | |
1563 | continue; | |
1564 | ||
1565 | is_leaf_bridge = false; | |
1566 | ||
1567 | if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) | |
1568 | continue; | |
1569 | ||
1570 | if (rel_type == whole_subtree) | |
1571 | pci_bus_release_bridge_resources(b, type, | |
1572 | whole_subtree); | |
1573 | } | |
1574 | ||
1575 | if (pci_is_root_bus(bus)) | |
1576 | return; | |
1577 | ||
1578 | if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI) | |
1579 | return; | |
1580 | ||
1581 | if ((rel_type == whole_subtree) || is_leaf_bridge) | |
1582 | pci_bridge_release_resources(bus, type); | |
1583 | } | |
1584 | ||
76fbc263 YL |
1585 | static void pci_bus_dump_res(struct pci_bus *bus) |
1586 | { | |
89a74ecc BH |
1587 | struct resource *res; |
1588 | int i; | |
7c9342b8 | 1589 | |
89a74ecc | 1590 | pci_bus_for_each_resource(bus, res, i) { |
7c9342b8 | 1591 | if (!res || !res->end || !res->flags) |
3c78bc61 | 1592 | continue; |
76fbc263 | 1593 | |
34c6b710 | 1594 | dev_info(&bus->dev, "resource %d %pR\n", i, res); |
3c78bc61 | 1595 | } |
76fbc263 YL |
1596 | } |
1597 | ||
1598 | static void pci_bus_dump_resources(struct pci_bus *bus) | |
1599 | { | |
1600 | struct pci_bus *b; | |
1601 | struct pci_dev *dev; | |
1602 | ||
1603 | ||
1604 | pci_bus_dump_res(bus); | |
1605 | ||
1606 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1607 | b = dev->subordinate; | |
1608 | if (!b) | |
1609 | continue; | |
1610 | ||
1611 | pci_bus_dump_resources(b); | |
1612 | } | |
1613 | } | |
1614 | ||
ff35147c | 1615 | static int pci_bus_get_depth(struct pci_bus *bus) |
da7822e5 YL |
1616 | { |
1617 | int depth = 0; | |
f2a230bd | 1618 | struct pci_bus *child_bus; |
da7822e5 | 1619 | |
3c78bc61 | 1620 | list_for_each_entry(child_bus, &bus->children, node) { |
da7822e5 | 1621 | int ret; |
da7822e5 | 1622 | |
f2a230bd | 1623 | ret = pci_bus_get_depth(child_bus); |
da7822e5 YL |
1624 | if (ret + 1 > depth) |
1625 | depth = ret + 1; | |
1626 | } | |
1627 | ||
1628 | return depth; | |
1629 | } | |
da7822e5 | 1630 | |
b55438fd YL |
1631 | /* |
1632 | * -1: undefined, will auto detect later | |
1633 | * 0: disabled by user | |
1634 | * 1: disabled by auto detect | |
1635 | * 2: enabled by user | |
1636 | * 3: enabled by auto detect | |
1637 | */ | |
1638 | enum enable_type { | |
1639 | undefined = -1, | |
1640 | user_disabled, | |
1641 | auto_disabled, | |
1642 | user_enabled, | |
1643 | auto_enabled, | |
1644 | }; | |
1645 | ||
ff35147c | 1646 | static enum enable_type pci_realloc_enable = undefined; |
b55438fd YL |
1647 | void __init pci_realloc_get_opt(char *str) |
1648 | { | |
1649 | if (!strncmp(str, "off", 3)) | |
1650 | pci_realloc_enable = user_disabled; | |
1651 | else if (!strncmp(str, "on", 2)) | |
1652 | pci_realloc_enable = user_enabled; | |
1653 | } | |
ff35147c | 1654 | static bool pci_realloc_enabled(enum enable_type enable) |
b55438fd | 1655 | { |
967260cd | 1656 | return enable >= user_enabled; |
b55438fd | 1657 | } |
f483d392 | 1658 | |
b07f2ebc | 1659 | #if defined(CONFIG_PCI_IOV) && defined(CONFIG_PCI_REALLOC_ENABLE_AUTO) |
ff35147c | 1660 | static int iov_resources_unassigned(struct pci_dev *dev, void *data) |
223d96fc YL |
1661 | { |
1662 | int i; | |
1663 | bool *unassigned = data; | |
b07f2ebc | 1664 | |
223d96fc YL |
1665 | for (i = PCI_IOV_RESOURCES; i <= PCI_IOV_RESOURCE_END; i++) { |
1666 | struct resource *r = &dev->resource[i]; | |
fa216bf4 | 1667 | struct pci_bus_region region; |
b07f2ebc | 1668 | |
223d96fc | 1669 | /* Not assigned or rejected by kernel? */ |
fa216bf4 YL |
1670 | if (!r->flags) |
1671 | continue; | |
b07f2ebc | 1672 | |
fc279850 | 1673 | pcibios_resource_to_bus(dev->bus, ®ion, r); |
fa216bf4 | 1674 | if (!region.start) { |
223d96fc | 1675 | *unassigned = true; |
0d607618 | 1676 | return 1; /* Return early from pci_walk_bus() */ |
b07f2ebc YL |
1677 | } |
1678 | } | |
b07f2ebc | 1679 | |
223d96fc | 1680 | return 0; |
b07f2ebc YL |
1681 | } |
1682 | ||
ff35147c | 1683 | static enum enable_type pci_realloc_detect(struct pci_bus *bus, |
0d607618 | 1684 | enum enable_type enable_local) |
223d96fc YL |
1685 | { |
1686 | bool unassigned = false; | |
7ac0d094 | 1687 | struct pci_host_bridge *host; |
b07f2ebc | 1688 | |
967260cd YL |
1689 | if (enable_local != undefined) |
1690 | return enable_local; | |
223d96fc | 1691 | |
7ac0d094 BH |
1692 | host = pci_find_host_bridge(bus); |
1693 | if (host->preserve_config) | |
1694 | return auto_disabled; | |
1695 | ||
967260cd YL |
1696 | pci_walk_bus(bus, iov_resources_unassigned, &unassigned); |
1697 | if (unassigned) | |
1698 | return auto_enabled; | |
1699 | ||
1700 | return enable_local; | |
b07f2ebc | 1701 | } |
223d96fc | 1702 | #else |
ff35147c | 1703 | static enum enable_type pci_realloc_detect(struct pci_bus *bus, |
0d607618 | 1704 | enum enable_type enable_local) |
967260cd YL |
1705 | { |
1706 | return enable_local; | |
b07f2ebc | 1707 | } |
223d96fc | 1708 | #endif |
b07f2ebc | 1709 | |
da7822e5 | 1710 | /* |
0d607618 NJ |
1711 | * First try will not touch PCI bridge res. |
1712 | * Second and later try will clear small leaf bridge res. | |
1713 | * Will stop till to the max depth if can not find good one. | |
da7822e5 | 1714 | */ |
39772038 | 1715 | void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus) |
1da177e4 | 1716 | { |
0d607618 NJ |
1717 | LIST_HEAD(realloc_head); |
1718 | /* List of resources that want additional resources */ | |
bdc4abec | 1719 | struct list_head *add_list = NULL; |
da7822e5 YL |
1720 | int tried_times = 0; |
1721 | enum release_type rel_type = leaf_only; | |
bdc4abec | 1722 | LIST_HEAD(fail_head); |
b9b0bba9 | 1723 | struct pci_dev_resource *fail_res; |
19aa7ee4 | 1724 | int pci_try_num = 1; |
55ed83a6 | 1725 | enum enable_type enable_local; |
da7822e5 | 1726 | |
0d607618 | 1727 | /* Don't realloc if asked to do so */ |
55ed83a6 | 1728 | enable_local = pci_realloc_detect(bus, pci_realloc_enable); |
967260cd | 1729 | if (pci_realloc_enabled(enable_local)) { |
55ed83a6 | 1730 | int max_depth = pci_bus_get_depth(bus); |
19aa7ee4 YL |
1731 | |
1732 | pci_try_num = max_depth + 1; | |
34c6b710 MK |
1733 | dev_info(&bus->dev, "max bus depth: %d pci_try_num: %d\n", |
1734 | max_depth, pci_try_num); | |
19aa7ee4 | 1735 | } |
da7822e5 YL |
1736 | |
1737 | again: | |
19aa7ee4 | 1738 | /* |
0d607618 NJ |
1739 | * Last try will use add_list, otherwise will try good to have as must |
1740 | * have, so can realloc parent bridge resource | |
19aa7ee4 YL |
1741 | */ |
1742 | if (tried_times + 1 == pci_try_num) | |
bdc4abec | 1743 | add_list = &realloc_head; |
0d607618 NJ |
1744 | /* |
1745 | * Depth first, calculate sizes and alignments of all subordinate buses. | |
1746 | */ | |
55ed83a6 | 1747 | __pci_bus_size_bridges(bus, add_list); |
c8adf9a3 | 1748 | |
1da177e4 | 1749 | /* Depth last, allocate resources and update the hardware. */ |
55ed83a6 | 1750 | __pci_bus_assign_resources(bus, add_list, &fail_head); |
19aa7ee4 | 1751 | if (add_list) |
bdc4abec | 1752 | BUG_ON(!list_empty(add_list)); |
da7822e5 YL |
1753 | tried_times++; |
1754 | ||
0d607618 | 1755 | /* Any device complain? */ |
bdc4abec | 1756 | if (list_empty(&fail_head)) |
928bea96 | 1757 | goto dump; |
f483d392 | 1758 | |
0c5be0cb | 1759 | if (tried_times >= pci_try_num) { |
967260cd | 1760 | if (enable_local == undefined) |
55ed83a6 | 1761 | dev_info(&bus->dev, "Some PCI device resources are unassigned, try booting with pci=realloc\n"); |
967260cd | 1762 | else if (enable_local == auto_enabled) |
55ed83a6 | 1763 | dev_info(&bus->dev, "Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n"); |
eb572e7c | 1764 | |
bffc56d4 | 1765 | free_list(&fail_head); |
928bea96 | 1766 | goto dump; |
da7822e5 YL |
1767 | } |
1768 | ||
34c6b710 MK |
1769 | dev_info(&bus->dev, "No. %d try to assign unassigned res\n", |
1770 | tried_times + 1); | |
da7822e5 | 1771 | |
0d607618 | 1772 | /* Third times and later will not check if it is leaf */ |
da7822e5 YL |
1773 | if ((tried_times + 1) > 2) |
1774 | rel_type = whole_subtree; | |
1775 | ||
1776 | /* | |
1777 | * Try to release leaf bridge's resources that doesn't fit resource of | |
0d607618 | 1778 | * child device under that bridge. |
da7822e5 | 1779 | */ |
61e83cdd YL |
1780 | list_for_each_entry(fail_res, &fail_head, list) |
1781 | pci_bus_release_bridge_resources(fail_res->dev->bus, | |
cb21bc94 | 1782 | fail_res->flags & PCI_RES_TYPE_MASK, |
bdc4abec | 1783 | rel_type); |
61e83cdd | 1784 | |
0d607618 | 1785 | /* Restore size and flags */ |
b9b0bba9 YL |
1786 | list_for_each_entry(fail_res, &fail_head, list) { |
1787 | struct resource *res = fail_res->res; | |
da7822e5 | 1788 | |
b9b0bba9 YL |
1789 | res->start = fail_res->start; |
1790 | res->end = fail_res->end; | |
1791 | res->flags = fail_res->flags; | |
1792 | if (fail_res->dev->subordinate) | |
da7822e5 | 1793 | res->flags = 0; |
da7822e5 | 1794 | } |
bffc56d4 | 1795 | free_list(&fail_head); |
da7822e5 YL |
1796 | |
1797 | goto again; | |
1798 | ||
928bea96 | 1799 | dump: |
0d607618 | 1800 | /* Dump the resource on buses */ |
55ed83a6 YL |
1801 | pci_bus_dump_resources(bus); |
1802 | } | |
1803 | ||
1804 | void __init pci_assign_unassigned_resources(void) | |
1805 | { | |
1806 | struct pci_bus *root_bus; | |
1807 | ||
584c5c42 | 1808 | list_for_each_entry(root_bus, &pci_root_buses, node) { |
55ed83a6 | 1809 | pci_assign_unassigned_root_bus_resources(root_bus); |
d9c149d6 | 1810 | |
0d607618 | 1811 | /* Make sure the root bridge has a companion ACPI device */ |
d9c149d6 RW |
1812 | if (ACPI_HANDLE(root_bus->bridge)) |
1813 | acpi_ioapic_add(ACPI_HANDLE(root_bus->bridge)); | |
584c5c42 | 1814 | } |
1da177e4 | 1815 | } |
6841ec68 | 1816 | |
1a576772 | 1817 | static void extend_bridge_window(struct pci_dev *bridge, struct resource *res, |
0d607618 NJ |
1818 | struct list_head *add_list, |
1819 | resource_size_t available) | |
1a576772 MW |
1820 | { |
1821 | struct pci_dev_resource *dev_res; | |
1822 | ||
1823 | if (res->parent) | |
1824 | return; | |
1825 | ||
1826 | if (resource_size(res) >= available) | |
1827 | return; | |
1828 | ||
1829 | dev_res = res_to_dev_res(add_list, res); | |
1830 | if (!dev_res) | |
1831 | return; | |
1832 | ||
1833 | /* Is there room to extend the window? */ | |
1834 | if (available - resource_size(res) <= dev_res->add_size) | |
1835 | return; | |
1836 | ||
1837 | dev_res->add_size = available - resource_size(res); | |
7506dc79 | 1838 | pci_dbg(bridge, "bridge window %pR extended by %pa\n", res, |
1a576772 MW |
1839 | &dev_res->add_size); |
1840 | } | |
1841 | ||
1842 | static void pci_bus_distribute_available_resources(struct pci_bus *bus, | |
0d607618 NJ |
1843 | struct list_head *add_list, |
1844 | resource_size_t available_io, | |
1845 | resource_size_t available_mmio, | |
1846 | resource_size_t available_mmio_pref) | |
1a576772 MW |
1847 | { |
1848 | resource_size_t remaining_io, remaining_mmio, remaining_mmio_pref; | |
1849 | unsigned int normal_bridges = 0, hotplug_bridges = 0; | |
1850 | struct resource *io_res, *mmio_res, *mmio_pref_res; | |
1851 | struct pci_dev *dev, *bridge = bus->self; | |
1852 | ||
1853 | io_res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0]; | |
1854 | mmio_res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1]; | |
1855 | mmio_pref_res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2]; | |
1856 | ||
1857 | /* | |
1858 | * Update additional resource list (add_list) to fill all the | |
1859 | * extra resource space available for this port except the space | |
1860 | * calculated in __pci_bus_size_bridges() which covers all the | |
1861 | * devices currently connected to the port and below. | |
1862 | */ | |
1863 | extend_bridge_window(bridge, io_res, add_list, available_io); | |
1864 | extend_bridge_window(bridge, mmio_res, add_list, available_mmio); | |
1865 | extend_bridge_window(bridge, mmio_pref_res, add_list, | |
1866 | available_mmio_pref); | |
1867 | ||
1868 | /* | |
1869 | * Calculate the total amount of extra resource space we can | |
0d607618 | 1870 | * pass to bridges below this one. This is basically the |
1a576772 MW |
1871 | * extra space reduced by the minimal required space for the |
1872 | * non-hotplug bridges. | |
1873 | */ | |
1874 | remaining_io = available_io; | |
1875 | remaining_mmio = available_mmio; | |
1876 | remaining_mmio_pref = available_mmio_pref; | |
1877 | ||
1878 | /* | |
1879 | * Calculate how many hotplug bridges and normal bridges there | |
0d607618 | 1880 | * are on this bus. We will distribute the additional available |
1a576772 MW |
1881 | * resources between hotplug bridges. |
1882 | */ | |
1883 | for_each_pci_bridge(dev, bus) { | |
1884 | if (dev->is_hotplug_bridge) | |
1885 | hotplug_bridges++; | |
1886 | else | |
1887 | normal_bridges++; | |
1888 | } | |
1889 | ||
1890 | for_each_pci_bridge(dev, bus) { | |
1891 | const struct resource *res; | |
1892 | ||
1893 | if (dev->is_hotplug_bridge) | |
1894 | continue; | |
1895 | ||
1896 | /* | |
1897 | * Reduce the available resource space by what the | |
1898 | * bridge and devices below it occupy. | |
1899 | */ | |
1900 | res = &dev->resource[PCI_BRIDGE_RESOURCES + 0]; | |
1901 | if (!res->parent && available_io > resource_size(res)) | |
1902 | remaining_io -= resource_size(res); | |
1903 | ||
1904 | res = &dev->resource[PCI_BRIDGE_RESOURCES + 1]; | |
1905 | if (!res->parent && available_mmio > resource_size(res)) | |
1906 | remaining_mmio -= resource_size(res); | |
1907 | ||
1908 | res = &dev->resource[PCI_BRIDGE_RESOURCES + 2]; | |
1909 | if (!res->parent && available_mmio_pref > resource_size(res)) | |
1910 | remaining_mmio_pref -= resource_size(res); | |
1911 | } | |
1912 | ||
14fe5951 MW |
1913 | /* |
1914 | * There is only one bridge on the bus so it gets all available | |
0d607618 NJ |
1915 | * resources which it can then distribute to the possible hotplug |
1916 | * bridges below. | |
14fe5951 MW |
1917 | */ |
1918 | if (hotplug_bridges + normal_bridges == 1) { | |
1919 | dev = list_first_entry(&bus->devices, struct pci_dev, bus_list); | |
1920 | if (dev->subordinate) { | |
1921 | pci_bus_distribute_available_resources(dev->subordinate, | |
1922 | add_list, available_io, available_mmio, | |
1923 | available_mmio_pref); | |
1924 | } | |
1925 | return; | |
1926 | } | |
1927 | ||
1a576772 MW |
1928 | /* |
1929 | * Go over devices on this bus and distribute the remaining | |
1930 | * resource space between hotplug bridges. | |
1931 | */ | |
1932 | for_each_pci_bridge(dev, bus) { | |
14fe5951 | 1933 | resource_size_t align, io, mmio, mmio_pref; |
1a576772 MW |
1934 | struct pci_bus *b; |
1935 | ||
1936 | b = dev->subordinate; | |
14fe5951 | 1937 | if (!b || !dev->is_hotplug_bridge) |
1a576772 MW |
1938 | continue; |
1939 | ||
14fe5951 MW |
1940 | /* |
1941 | * Distribute available extra resources equally between | |
1942 | * hotplug-capable downstream ports taking alignment into | |
1943 | * account. | |
1944 | * | |
1945 | * Here hotplug_bridges is always != 0. | |
1946 | */ | |
1947 | align = pci_resource_alignment(bridge, io_res); | |
1948 | io = div64_ul(available_io, hotplug_bridges); | |
1949 | io = min(ALIGN(io, align), remaining_io); | |
1950 | remaining_io -= io; | |
1951 | ||
1952 | align = pci_resource_alignment(bridge, mmio_res); | |
1953 | mmio = div64_ul(available_mmio, hotplug_bridges); | |
1954 | mmio = min(ALIGN(mmio, align), remaining_mmio); | |
1955 | remaining_mmio -= mmio; | |
1956 | ||
1957 | align = pci_resource_alignment(bridge, mmio_pref_res); | |
1958 | mmio_pref = div64_ul(available_mmio_pref, hotplug_bridges); | |
1959 | mmio_pref = min(ALIGN(mmio_pref, align), remaining_mmio_pref); | |
1960 | remaining_mmio_pref -= mmio_pref; | |
1961 | ||
1962 | pci_bus_distribute_available_resources(b, add_list, io, mmio, | |
1963 | mmio_pref); | |
1a576772 MW |
1964 | } |
1965 | } | |
1966 | ||
0d607618 NJ |
1967 | static void pci_bridge_distribute_available_resources(struct pci_dev *bridge, |
1968 | struct list_head *add_list) | |
1a576772 MW |
1969 | { |
1970 | resource_size_t available_io, available_mmio, available_mmio_pref; | |
1971 | const struct resource *res; | |
1972 | ||
1973 | if (!bridge->is_hotplug_bridge) | |
1974 | return; | |
1975 | ||
1976 | /* Take the initial extra resources from the hotplug port */ | |
1977 | res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0]; | |
1978 | available_io = resource_size(res); | |
1979 | res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1]; | |
1980 | available_mmio = resource_size(res); | |
1981 | res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2]; | |
1982 | available_mmio_pref = resource_size(res); | |
1983 | ||
1984 | pci_bus_distribute_available_resources(bridge->subordinate, | |
0d607618 NJ |
1985 | add_list, available_io, |
1986 | available_mmio, | |
1987 | available_mmio_pref); | |
1a576772 MW |
1988 | } |
1989 | ||
6841ec68 YL |
1990 | void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge) |
1991 | { | |
1992 | struct pci_bus *parent = bridge->subordinate; | |
0d607618 NJ |
1993 | /* List of resources that want additional resources */ |
1994 | LIST_HEAD(add_list); | |
1995 | ||
32180e40 | 1996 | int tried_times = 0; |
bdc4abec | 1997 | LIST_HEAD(fail_head); |
b9b0bba9 | 1998 | struct pci_dev_resource *fail_res; |
6841ec68 | 1999 | int retval; |
32180e40 | 2000 | |
32180e40 | 2001 | again: |
8424d759 | 2002 | __pci_bus_size_bridges(parent, &add_list); |
1a576772 MW |
2003 | |
2004 | /* | |
0d607618 NJ |
2005 | * Distribute remaining resources (if any) equally between hotplug |
2006 | * bridges below. This makes it possible to extend the hierarchy | |
2007 | * later without running out of resources. | |
1a576772 MW |
2008 | */ |
2009 | pci_bridge_distribute_available_resources(bridge, &add_list); | |
2010 | ||
bdc4abec YL |
2011 | __pci_bridge_assign_resources(bridge, &add_list, &fail_head); |
2012 | BUG_ON(!list_empty(&add_list)); | |
32180e40 YL |
2013 | tried_times++; |
2014 | ||
bdc4abec | 2015 | if (list_empty(&fail_head)) |
3f579c34 | 2016 | goto enable_all; |
32180e40 YL |
2017 | |
2018 | if (tried_times >= 2) { | |
0d607618 | 2019 | /* Still fail, don't need to try more */ |
bffc56d4 | 2020 | free_list(&fail_head); |
3f579c34 | 2021 | goto enable_all; |
32180e40 YL |
2022 | } |
2023 | ||
2024 | printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n", | |
2025 | tried_times + 1); | |
2026 | ||
2027 | /* | |
0d607618 NJ |
2028 | * Try to release leaf bridge's resources that aren't big enough |
2029 | * to contain child device resources. | |
32180e40 | 2030 | */ |
61e83cdd YL |
2031 | list_for_each_entry(fail_res, &fail_head, list) |
2032 | pci_bus_release_bridge_resources(fail_res->dev->bus, | |
cb21bc94 | 2033 | fail_res->flags & PCI_RES_TYPE_MASK, |
32180e40 | 2034 | whole_subtree); |
61e83cdd | 2035 | |
0d607618 | 2036 | /* Restore size and flags */ |
b9b0bba9 YL |
2037 | list_for_each_entry(fail_res, &fail_head, list) { |
2038 | struct resource *res = fail_res->res; | |
32180e40 | 2039 | |
b9b0bba9 YL |
2040 | res->start = fail_res->start; |
2041 | res->end = fail_res->end; | |
2042 | res->flags = fail_res->flags; | |
2043 | if (fail_res->dev->subordinate) | |
32180e40 | 2044 | res->flags = 0; |
32180e40 | 2045 | } |
bffc56d4 | 2046 | free_list(&fail_head); |
32180e40 YL |
2047 | |
2048 | goto again; | |
3f579c34 YL |
2049 | |
2050 | enable_all: | |
2051 | retval = pci_reenable_device(bridge); | |
9fc9eea0 | 2052 | if (retval) |
7506dc79 | 2053 | pci_err(bridge, "Error reenabling bridge (%d)\n", retval); |
3f579c34 | 2054 | pci_set_master(bridge); |
6841ec68 YL |
2055 | } |
2056 | EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources); | |
9b03088f | 2057 | |
8bb705e3 CK |
2058 | int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type) |
2059 | { | |
2060 | struct pci_dev_resource *dev_res; | |
2061 | struct pci_dev *next; | |
2062 | LIST_HEAD(saved); | |
2063 | LIST_HEAD(added); | |
2064 | LIST_HEAD(failed); | |
2065 | unsigned int i; | |
2066 | int ret; | |
2067 | ||
2068 | /* Walk to the root hub, releasing bridge BARs when possible */ | |
2069 | next = bridge; | |
2070 | do { | |
2071 | bridge = next; | |
2072 | for (i = PCI_BRIDGE_RESOURCES; i < PCI_BRIDGE_RESOURCE_END; | |
2073 | i++) { | |
2074 | struct resource *res = &bridge->resource[i]; | |
2075 | ||
2076 | if ((res->flags ^ type) & PCI_RES_TYPE_MASK) | |
2077 | continue; | |
2078 | ||
2079 | /* Ignore BARs which are still in use */ | |
2080 | if (res->child) | |
2081 | continue; | |
2082 | ||
2083 | ret = add_to_list(&saved, bridge, res, 0, 0); | |
2084 | if (ret) | |
2085 | goto cleanup; | |
2086 | ||
7506dc79 | 2087 | pci_info(bridge, "BAR %d: releasing %pR\n", |
8bb705e3 CK |
2088 | i, res); |
2089 | ||
2090 | if (res->parent) | |
2091 | release_resource(res); | |
2092 | res->start = 0; | |
2093 | res->end = 0; | |
2094 | break; | |
2095 | } | |
2096 | if (i == PCI_BRIDGE_RESOURCE_END) | |
2097 | break; | |
2098 | ||
2099 | next = bridge->bus ? bridge->bus->self : NULL; | |
2100 | } while (next); | |
2101 | ||
2102 | if (list_empty(&saved)) | |
2103 | return -ENOENT; | |
2104 | ||
2105 | __pci_bus_size_bridges(bridge->subordinate, &added); | |
2106 | __pci_bridge_assign_resources(bridge, &added, &failed); | |
2107 | BUG_ON(!list_empty(&added)); | |
2108 | ||
2109 | if (!list_empty(&failed)) { | |
2110 | ret = -ENOSPC; | |
2111 | goto cleanup; | |
2112 | } | |
2113 | ||
2114 | list_for_each_entry(dev_res, &saved, list) { | |
0d607618 | 2115 | /* Skip the bridge we just assigned resources for */ |
8bb705e3 CK |
2116 | if (bridge == dev_res->dev) |
2117 | continue; | |
2118 | ||
2119 | bridge = dev_res->dev; | |
2120 | pci_setup_bridge(bridge->subordinate); | |
2121 | } | |
2122 | ||
2123 | free_list(&saved); | |
2124 | return 0; | |
2125 | ||
2126 | cleanup: | |
0d607618 | 2127 | /* Restore size and flags */ |
8bb705e3 CK |
2128 | list_for_each_entry(dev_res, &failed, list) { |
2129 | struct resource *res = dev_res->res; | |
2130 | ||
2131 | res->start = dev_res->start; | |
2132 | res->end = dev_res->end; | |
2133 | res->flags = dev_res->flags; | |
2134 | } | |
2135 | free_list(&failed); | |
2136 | ||
2137 | /* Revert to the old configuration */ | |
2138 | list_for_each_entry(dev_res, &saved, list) { | |
2139 | struct resource *res = dev_res->res; | |
2140 | ||
2141 | bridge = dev_res->dev; | |
2142 | i = res - bridge->resource; | |
2143 | ||
2144 | res->start = dev_res->start; | |
2145 | res->end = dev_res->end; | |
2146 | res->flags = dev_res->flags; | |
2147 | ||
2148 | pci_claim_resource(bridge, i); | |
2149 | pci_setup_bridge(bridge->subordinate); | |
2150 | } | |
2151 | free_list(&saved); | |
2152 | ||
2153 | return ret; | |
2154 | } | |
2155 | ||
17787940 | 2156 | void pci_assign_unassigned_bus_resources(struct pci_bus *bus) |
9b03088f | 2157 | { |
9b03088f | 2158 | struct pci_dev *dev; |
0d607618 NJ |
2159 | /* List of resources that want additional resources */ |
2160 | LIST_HEAD(add_list); | |
9b03088f | 2161 | |
9b03088f | 2162 | down_read(&pci_bus_sem); |
24a0c654 AS |
2163 | for_each_pci_bridge(dev, bus) |
2164 | if (pci_has_subordinate(dev)) | |
2165 | __pci_bus_size_bridges(dev->subordinate, &add_list); | |
9b03088f YL |
2166 | up_read(&pci_bus_sem); |
2167 | __pci_bus_assign_resources(bus, &add_list, NULL); | |
bdc4abec | 2168 | BUG_ON(!list_empty(&add_list)); |
17787940 | 2169 | } |
e6b29dea | 2170 | EXPORT_SYMBOL_GPL(pci_assign_unassigned_bus_resources); |