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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * drivers/pci/setup-bus.c | |
3 | * | |
4 | * Extruded from code written by | |
5 | * Dave Rusling (david.rusling@reo.mts.dec.com) | |
6 | * David Mosberger (davidm@cs.arizona.edu) | |
7 | * David Miller (davem@redhat.com) | |
8 | * | |
9 | * Support routines for initializing a PCI subsystem. | |
10 | */ | |
11 | ||
12 | /* | |
13 | * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> | |
14 | * PCI-PCI bridges cleanup, sorted resource allocation. | |
15 | * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru> | |
16 | * Converted to allocation in 3 passes, which gives | |
17 | * tighter packing. Prefetchable range support. | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/pci.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/ioport.h> | |
26 | #include <linux/cache.h> | |
27 | #include <linux/slab.h> | |
6faf17f6 | 28 | #include "pci.h" |
1da177e4 | 29 | |
568ddef8 YL |
30 | struct resource_list_x { |
31 | struct resource_list_x *next; | |
32 | struct resource *res; | |
33 | struct pci_dev *dev; | |
34 | resource_size_t start; | |
35 | resource_size_t end; | |
36 | unsigned long flags; | |
37 | }; | |
38 | ||
39 | static void add_to_failed_list(struct resource_list_x *head, | |
40 | struct pci_dev *dev, struct resource *res) | |
41 | { | |
42 | struct resource_list_x *list = head; | |
43 | struct resource_list_x *ln = list->next; | |
44 | struct resource_list_x *tmp; | |
45 | ||
46 | tmp = kmalloc(sizeof(*tmp), GFP_KERNEL); | |
47 | if (!tmp) { | |
48 | pr_warning("add_to_failed_list: kmalloc() failed!\n"); | |
49 | return; | |
50 | } | |
51 | ||
52 | tmp->next = ln; | |
53 | tmp->res = res; | |
54 | tmp->dev = dev; | |
55 | tmp->start = res->start; | |
56 | tmp->end = res->end; | |
57 | tmp->flags = res->flags; | |
58 | list->next = tmp; | |
59 | } | |
60 | ||
61 | static void free_failed_list(struct resource_list_x *head) | |
62 | { | |
63 | struct resource_list_x *list, *tmp; | |
64 | ||
65 | for (list = head->next; list;) { | |
66 | tmp = list; | |
67 | list = list->next; | |
68 | kfree(tmp); | |
69 | } | |
70 | ||
71 | head->next = NULL; | |
72 | } | |
73 | ||
74 | static void pbus_assign_resources_sorted(const struct pci_bus *bus, | |
75 | struct resource_list_x *fail_head) | |
1da177e4 LT |
76 | { |
77 | struct pci_dev *dev; | |
78 | struct resource *res; | |
79 | struct resource_list head, *list, *tmp; | |
80 | int idx; | |
81 | ||
1da177e4 LT |
82 | head.next = NULL; |
83 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
84 | u16 class = dev->class >> 8; | |
85 | ||
9bded00b | 86 | /* Don't touch classless devices or host bridges or ioapics. */ |
1da177e4 | 87 | if (class == PCI_CLASS_NOT_DEFINED || |
23186279 | 88 | class == PCI_CLASS_BRIDGE_HOST) |
1da177e4 LT |
89 | continue; |
90 | ||
9bded00b | 91 | /* Don't touch ioapic devices already enabled by firmware */ |
23186279 | 92 | if (class == PCI_CLASS_SYSTEM_PIC) { |
9bded00b KK |
93 | u16 command; |
94 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
95 | if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | |
23186279 ST |
96 | continue; |
97 | } | |
98 | ||
1da177e4 LT |
99 | pdev_sort_resources(dev, &head); |
100 | } | |
101 | ||
102 | for (list = head.next; list;) { | |
103 | res = list->res; | |
104 | idx = res - &list->dev->resource[0]; | |
542df5de | 105 | if (pci_assign_resource(list->dev, idx)) { |
568ddef8 YL |
106 | if (fail_head && !pci_is_root_bus(list->dev->bus)) |
107 | add_to_failed_list(fail_head, list->dev, res); | |
542df5de | 108 | res->start = 0; |
960b8466 | 109 | res->end = 0; |
542df5de RS |
110 | res->flags = 0; |
111 | } | |
1da177e4 LT |
112 | tmp = list; |
113 | list = list->next; | |
114 | kfree(tmp); | |
115 | } | |
116 | } | |
117 | ||
b3743fa4 | 118 | void pci_setup_cardbus(struct pci_bus *bus) |
1da177e4 LT |
119 | { |
120 | struct pci_dev *bridge = bus->self; | |
c7dabef8 | 121 | struct resource *res; |
1da177e4 LT |
122 | struct pci_bus_region region; |
123 | ||
865df576 BH |
124 | dev_info(&bridge->dev, "CardBus bridge to [bus %02x-%02x]\n", |
125 | bus->secondary, bus->subordinate); | |
1da177e4 | 126 | |
c7dabef8 BH |
127 | res = bus->resource[0]; |
128 | pcibios_resource_to_bus(bridge, ®ion, res); | |
129 | if (res->flags & IORESOURCE_IO) { | |
1da177e4 LT |
130 | /* |
131 | * The IO resource is allocated a range twice as large as it | |
132 | * would normally need. This allows us to set both IO regs. | |
133 | */ | |
c7dabef8 | 134 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
1da177e4 LT |
135 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, |
136 | region.start); | |
137 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0, | |
138 | region.end); | |
139 | } | |
140 | ||
c7dabef8 BH |
141 | res = bus->resource[1]; |
142 | pcibios_resource_to_bus(bridge, ®ion, res); | |
143 | if (res->flags & IORESOURCE_IO) { | |
144 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
145 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, |
146 | region.start); | |
147 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1, | |
148 | region.end); | |
149 | } | |
150 | ||
c7dabef8 BH |
151 | res = bus->resource[2]; |
152 | pcibios_resource_to_bus(bridge, ®ion, res); | |
153 | if (res->flags & IORESOURCE_MEM) { | |
154 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
155 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, |
156 | region.start); | |
157 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0, | |
158 | region.end); | |
159 | } | |
160 | ||
c7dabef8 BH |
161 | res = bus->resource[3]; |
162 | pcibios_resource_to_bus(bridge, ®ion, res); | |
163 | if (res->flags & IORESOURCE_MEM) { | |
164 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
165 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, |
166 | region.start); | |
167 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1, | |
168 | region.end); | |
169 | } | |
170 | } | |
b3743fa4 | 171 | EXPORT_SYMBOL(pci_setup_cardbus); |
1da177e4 LT |
172 | |
173 | /* Initialize bridges with base/limit values we have collected. | |
174 | PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998) | |
175 | requires that if there is no I/O ports or memory behind the | |
176 | bridge, corresponding range must be turned off by writing base | |
177 | value greater than limit to the bridge's base/limit registers. | |
178 | ||
179 | Note: care must be taken when updating I/O base/limit registers | |
180 | of bridges which support 32-bit I/O. This update requires two | |
181 | config space writes, so it's quite possible that an I/O window of | |
182 | the bridge will have some undesirable address (e.g. 0) after the | |
183 | first write. Ditto 64-bit prefetchable MMIO. */ | |
7cc5997d | 184 | static void pci_setup_bridge_io(struct pci_bus *bus) |
1da177e4 LT |
185 | { |
186 | struct pci_dev *bridge = bus->self; | |
c7dabef8 | 187 | struct resource *res; |
1da177e4 | 188 | struct pci_bus_region region; |
7cc5997d | 189 | u32 l, io_upper16; |
1da177e4 LT |
190 | |
191 | /* Set up the top and bottom of the PCI I/O segment for this bus. */ | |
c7dabef8 BH |
192 | res = bus->resource[0]; |
193 | pcibios_resource_to_bus(bridge, ®ion, res); | |
194 | if (res->flags & IORESOURCE_IO) { | |
1da177e4 LT |
195 | pci_read_config_dword(bridge, PCI_IO_BASE, &l); |
196 | l &= 0xffff0000; | |
197 | l |= (region.start >> 8) & 0x00f0; | |
198 | l |= region.end & 0xf000; | |
199 | /* Set up upper 16 bits of I/O base/limit. */ | |
200 | io_upper16 = (region.end & 0xffff0000) | (region.start >> 16); | |
c7dabef8 | 201 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 202 | } else { |
1da177e4 LT |
203 | /* Clear upper 16 bits of I/O base/limit. */ |
204 | io_upper16 = 0; | |
205 | l = 0x00f0; | |
c7dabef8 | 206 | dev_info(&bridge->dev, " bridge window [io disabled]\n"); |
1da177e4 LT |
207 | } |
208 | /* Temporarily disable the I/O range before updating PCI_IO_BASE. */ | |
209 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff); | |
210 | /* Update lower 16 bits of I/O base/limit. */ | |
211 | pci_write_config_dword(bridge, PCI_IO_BASE, l); | |
212 | /* Update upper 16 bits of I/O base/limit. */ | |
213 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16); | |
7cc5997d YL |
214 | } |
215 | ||
216 | static void pci_setup_bridge_mmio(struct pci_bus *bus) | |
217 | { | |
218 | struct pci_dev *bridge = bus->self; | |
219 | struct resource *res; | |
220 | struct pci_bus_region region; | |
221 | u32 l; | |
1da177e4 | 222 | |
7cc5997d | 223 | /* Set up the top and bottom of the PCI Memory segment for this bus. */ |
c7dabef8 BH |
224 | res = bus->resource[1]; |
225 | pcibios_resource_to_bus(bridge, ®ion, res); | |
226 | if (res->flags & IORESOURCE_MEM) { | |
1da177e4 LT |
227 | l = (region.start >> 16) & 0xfff0; |
228 | l |= region.end & 0xfff00000; | |
c7dabef8 | 229 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 230 | } else { |
1da177e4 | 231 | l = 0x0000fff0; |
c7dabef8 | 232 | dev_info(&bridge->dev, " bridge window [mem disabled]\n"); |
1da177e4 LT |
233 | } |
234 | pci_write_config_dword(bridge, PCI_MEMORY_BASE, l); | |
7cc5997d YL |
235 | } |
236 | ||
237 | static void pci_setup_bridge_mmio_pref(struct pci_bus *bus) | |
238 | { | |
239 | struct pci_dev *bridge = bus->self; | |
240 | struct resource *res; | |
241 | struct pci_bus_region region; | |
242 | u32 l, bu, lu; | |
1da177e4 LT |
243 | |
244 | /* Clear out the upper 32 bits of PREF limit. | |
245 | If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily | |
246 | disables PREF range, which is ok. */ | |
247 | pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0); | |
248 | ||
249 | /* Set up PREF base/limit. */ | |
c40a22e0 | 250 | bu = lu = 0; |
c7dabef8 BH |
251 | res = bus->resource[2]; |
252 | pcibios_resource_to_bus(bridge, ®ion, res); | |
253 | if (res->flags & IORESOURCE_PREFETCH) { | |
1da177e4 LT |
254 | l = (region.start >> 16) & 0xfff0; |
255 | l |= region.end & 0xfff00000; | |
c7dabef8 | 256 | if (res->flags & IORESOURCE_MEM_64) { |
1f82de10 YL |
257 | bu = upper_32_bits(region.start); |
258 | lu = upper_32_bits(region.end); | |
1f82de10 | 259 | } |
c7dabef8 | 260 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 261 | } else { |
1da177e4 | 262 | l = 0x0000fff0; |
c7dabef8 | 263 | dev_info(&bridge->dev, " bridge window [mem pref disabled]\n"); |
1da177e4 LT |
264 | } |
265 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l); | |
266 | ||
59353ea3 AW |
267 | /* Set the upper 32 bits of PREF base & limit. */ |
268 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu); | |
269 | pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu); | |
7cc5997d YL |
270 | } |
271 | ||
272 | static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type) | |
273 | { | |
274 | struct pci_dev *bridge = bus->self; | |
275 | ||
276 | if (pci_is_enabled(bridge)) | |
277 | return; | |
278 | ||
279 | dev_info(&bridge->dev, "PCI bridge to [bus %02x-%02x]\n", | |
280 | bus->secondary, bus->subordinate); | |
281 | ||
282 | if (type & IORESOURCE_IO) | |
283 | pci_setup_bridge_io(bus); | |
284 | ||
285 | if (type & IORESOURCE_MEM) | |
286 | pci_setup_bridge_mmio(bus); | |
287 | ||
288 | if (type & IORESOURCE_PREFETCH) | |
289 | pci_setup_bridge_mmio_pref(bus); | |
1da177e4 LT |
290 | |
291 | pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl); | |
292 | } | |
293 | ||
7cc5997d YL |
294 | static void pci_setup_bridge(struct pci_bus *bus) |
295 | { | |
296 | unsigned long type = IORESOURCE_IO | IORESOURCE_MEM | | |
297 | IORESOURCE_PREFETCH; | |
298 | ||
299 | __pci_setup_bridge(bus, type); | |
300 | } | |
301 | ||
1da177e4 LT |
302 | /* Check whether the bridge supports optional I/O and |
303 | prefetchable memory ranges. If not, the respective | |
304 | base/limit registers must be read-only and read as 0. */ | |
96bde06a | 305 | static void pci_bridge_check_ranges(struct pci_bus *bus) |
1da177e4 LT |
306 | { |
307 | u16 io; | |
308 | u32 pmem; | |
309 | struct pci_dev *bridge = bus->self; | |
310 | struct resource *b_res; | |
311 | ||
312 | b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; | |
313 | b_res[1].flags |= IORESOURCE_MEM; | |
314 | ||
315 | pci_read_config_word(bridge, PCI_IO_BASE, &io); | |
316 | if (!io) { | |
317 | pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0); | |
318 | pci_read_config_word(bridge, PCI_IO_BASE, &io); | |
319 | pci_write_config_word(bridge, PCI_IO_BASE, 0x0); | |
320 | } | |
321 | if (io) | |
322 | b_res[0].flags |= IORESOURCE_IO; | |
323 | /* DECchip 21050 pass 2 errata: the bridge may miss an address | |
324 | disconnect boundary by one PCI data phase. | |
325 | Workaround: do not use prefetching on this device. */ | |
326 | if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) | |
327 | return; | |
328 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); | |
329 | if (!pmem) { | |
330 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, | |
331 | 0xfff0fff0); | |
332 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); | |
333 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); | |
334 | } | |
1f82de10 | 335 | if (pmem) { |
1da177e4 | 336 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; |
1f82de10 YL |
337 | if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) |
338 | b_res[2].flags |= IORESOURCE_MEM_64; | |
339 | } | |
340 | ||
341 | /* double check if bridge does support 64 bit pref */ | |
342 | if (b_res[2].flags & IORESOURCE_MEM_64) { | |
343 | u32 mem_base_hi, tmp; | |
344 | pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
345 | &mem_base_hi); | |
346 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
347 | 0xffffffff); | |
348 | pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp); | |
349 | if (!tmp) | |
350 | b_res[2].flags &= ~IORESOURCE_MEM_64; | |
351 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
352 | mem_base_hi); | |
353 | } | |
1da177e4 LT |
354 | } |
355 | ||
356 | /* Helper function for sizing routines: find first available | |
357 | bus resource of a given type. Note: we intentionally skip | |
358 | the bus resources which have already been assigned (that is, | |
359 | have non-NULL parent resource). */ | |
96bde06a | 360 | static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type) |
1da177e4 LT |
361 | { |
362 | int i; | |
363 | struct resource *r; | |
364 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | | |
365 | IORESOURCE_PREFETCH; | |
366 | ||
367 | for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) { | |
368 | r = bus->resource[i]; | |
299de034 IK |
369 | if (r == &ioport_resource || r == &iomem_resource) |
370 | continue; | |
55a10984 JB |
371 | if (r && (r->flags & type_mask) == type && !r->parent) |
372 | return r; | |
1da177e4 LT |
373 | } |
374 | return NULL; | |
375 | } | |
376 | ||
377 | /* Sizing the IO windows of the PCI-PCI bridge is trivial, | |
378 | since these windows have 4K granularity and the IO ranges | |
379 | of non-bridge PCI devices are limited to 256 bytes. | |
380 | We must be careful with the ISA aliasing though. */ | |
28760489 | 381 | static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size) |
1da177e4 LT |
382 | { |
383 | struct pci_dev *dev; | |
384 | struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO); | |
d65245c3 | 385 | unsigned long size = 0, size1 = 0, old_size; |
1da177e4 LT |
386 | |
387 | if (!b_res) | |
388 | return; | |
389 | ||
390 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
391 | int i; | |
392 | ||
393 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
394 | struct resource *r = &dev->resource[i]; | |
395 | unsigned long r_size; | |
396 | ||
397 | if (r->parent || !(r->flags & IORESOURCE_IO)) | |
398 | continue; | |
022edd86 | 399 | r_size = resource_size(r); |
1da177e4 LT |
400 | |
401 | if (r_size < 0x400) | |
402 | /* Might be re-aligned for ISA */ | |
403 | size += r_size; | |
404 | else | |
405 | size1 += r_size; | |
406 | } | |
407 | } | |
28760489 EB |
408 | if (size < min_size) |
409 | size = min_size; | |
d65245c3 YL |
410 | old_size = resource_size(b_res); |
411 | if (old_size == 1) | |
412 | old_size = 0; | |
1da177e4 LT |
413 | /* To be fixed in 2.5: we should have sort of HAVE_ISA |
414 | flag in the struct pci_bus. */ | |
415 | #if defined(CONFIG_ISA) || defined(CONFIG_EISA) | |
416 | size = (size & 0xff) + ((size & ~0xffUL) << 2); | |
417 | #endif | |
6f6f8c2f | 418 | size = ALIGN(size + size1, 4096); |
d65245c3 YL |
419 | if (size < old_size) |
420 | size = old_size; | |
1da177e4 | 421 | if (!size) { |
865df576 BH |
422 | if (b_res->start || b_res->end) |
423 | dev_info(&bus->self->dev, "disabling bridge window " | |
424 | "%pR to [bus %02x-%02x] (unused)\n", b_res, | |
425 | bus->secondary, bus->subordinate); | |
1da177e4 LT |
426 | b_res->flags = 0; |
427 | return; | |
428 | } | |
429 | /* Alignment of the IO window is always 4K */ | |
430 | b_res->start = 4096; | |
431 | b_res->end = b_res->start + size - 1; | |
88452565 | 432 | b_res->flags |= IORESOURCE_STARTALIGN; |
1da177e4 LT |
433 | } |
434 | ||
435 | /* Calculate the size of the bus and minimal alignment which | |
436 | guarantees that all child resources fit in this size. */ | |
28760489 EB |
437 | static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, |
438 | unsigned long type, resource_size_t min_size) | |
1da177e4 LT |
439 | { |
440 | struct pci_dev *dev; | |
d65245c3 | 441 | resource_size_t min_align, align, size, old_size; |
c40a22e0 | 442 | resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */ |
1da177e4 LT |
443 | int order, max_order; |
444 | struct resource *b_res = find_free_bus_resource(bus, type); | |
1f82de10 | 445 | unsigned int mem64_mask = 0; |
1da177e4 LT |
446 | |
447 | if (!b_res) | |
448 | return 0; | |
449 | ||
450 | memset(aligns, 0, sizeof(aligns)); | |
451 | max_order = 0; | |
452 | size = 0; | |
453 | ||
1f82de10 YL |
454 | mem64_mask = b_res->flags & IORESOURCE_MEM_64; |
455 | b_res->flags &= ~IORESOURCE_MEM_64; | |
456 | ||
1da177e4 LT |
457 | list_for_each_entry(dev, &bus->devices, bus_list) { |
458 | int i; | |
1f82de10 | 459 | |
1da177e4 LT |
460 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { |
461 | struct resource *r = &dev->resource[i]; | |
c40a22e0 | 462 | resource_size_t r_size; |
1da177e4 LT |
463 | |
464 | if (r->parent || (r->flags & mask) != type) | |
465 | continue; | |
022edd86 | 466 | r_size = resource_size(r); |
1da177e4 | 467 | /* For bridges size != alignment */ |
6faf17f6 | 468 | align = pci_resource_alignment(dev, r); |
1da177e4 LT |
469 | order = __ffs(align) - 20; |
470 | if (order > 11) { | |
865df576 BH |
471 | dev_warn(&dev->dev, "disabling BAR %d: %pR " |
472 | "(bad alignment %#llx)\n", i, r, | |
473 | (unsigned long long) align); | |
1da177e4 LT |
474 | r->flags = 0; |
475 | continue; | |
476 | } | |
477 | size += r_size; | |
478 | if (order < 0) | |
479 | order = 0; | |
480 | /* Exclude ranges with size > align from | |
481 | calculation of the alignment. */ | |
482 | if (r_size == align) | |
483 | aligns[order] += align; | |
484 | if (order > max_order) | |
485 | max_order = order; | |
1f82de10 | 486 | mem64_mask &= r->flags & IORESOURCE_MEM_64; |
1da177e4 LT |
487 | } |
488 | } | |
28760489 EB |
489 | if (size < min_size) |
490 | size = min_size; | |
d65245c3 YL |
491 | old_size = resource_size(b_res); |
492 | if (old_size == 1) | |
493 | old_size = 0; | |
494 | if (size < old_size) | |
495 | size = old_size; | |
1da177e4 LT |
496 | |
497 | align = 0; | |
498 | min_align = 0; | |
499 | for (order = 0; order <= max_order; order++) { | |
8308c54d JF |
500 | resource_size_t align1 = 1; |
501 | ||
502 | align1 <<= (order + 20); | |
503 | ||
1da177e4 LT |
504 | if (!align) |
505 | min_align = align1; | |
6f6f8c2f | 506 | else if (ALIGN(align + min_align, min_align) < align1) |
1da177e4 LT |
507 | min_align = align1 >> 1; |
508 | align += aligns[order]; | |
509 | } | |
6f6f8c2f | 510 | size = ALIGN(size, min_align); |
1da177e4 | 511 | if (!size) { |
865df576 BH |
512 | if (b_res->start || b_res->end) |
513 | dev_info(&bus->self->dev, "disabling bridge window " | |
514 | "%pR to [bus %02x-%02x] (unused)\n", b_res, | |
515 | bus->secondary, bus->subordinate); | |
1da177e4 LT |
516 | b_res->flags = 0; |
517 | return 1; | |
518 | } | |
519 | b_res->start = min_align; | |
520 | b_res->end = size + min_align - 1; | |
88452565 | 521 | b_res->flags |= IORESOURCE_STARTALIGN; |
1f82de10 | 522 | b_res->flags |= mem64_mask; |
1da177e4 LT |
523 | return 1; |
524 | } | |
525 | ||
5468ae61 | 526 | static void pci_bus_size_cardbus(struct pci_bus *bus) |
1da177e4 LT |
527 | { |
528 | struct pci_dev *bridge = bus->self; | |
529 | struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; | |
530 | u16 ctrl; | |
531 | ||
532 | /* | |
533 | * Reserve some resources for CardBus. We reserve | |
534 | * a fixed amount of bus space for CardBus bridges. | |
535 | */ | |
934b7024 LT |
536 | b_res[0].start = 0; |
537 | b_res[0].end = pci_cardbus_io_size - 1; | |
538 | b_res[0].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN; | |
1da177e4 | 539 | |
934b7024 LT |
540 | b_res[1].start = 0; |
541 | b_res[1].end = pci_cardbus_io_size - 1; | |
542 | b_res[1].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN; | |
1da177e4 LT |
543 | |
544 | /* | |
545 | * Check whether prefetchable memory is supported | |
546 | * by this bridge. | |
547 | */ | |
548 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
549 | if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) { | |
550 | ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; | |
551 | pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); | |
552 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
553 | } | |
554 | ||
555 | /* | |
556 | * If we have prefetchable memory support, allocate | |
557 | * two regions. Otherwise, allocate one region of | |
558 | * twice the size. | |
559 | */ | |
560 | if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) { | |
934b7024 LT |
561 | b_res[2].start = 0; |
562 | b_res[2].end = pci_cardbus_mem_size - 1; | |
563 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_SIZEALIGN; | |
1da177e4 | 564 | |
934b7024 LT |
565 | b_res[3].start = 0; |
566 | b_res[3].end = pci_cardbus_mem_size - 1; | |
567 | b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN; | |
1da177e4 | 568 | } else { |
934b7024 LT |
569 | b_res[3].start = 0; |
570 | b_res[3].end = pci_cardbus_mem_size * 2 - 1; | |
571 | b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN; | |
1da177e4 LT |
572 | } |
573 | } | |
574 | ||
451124a7 | 575 | void __ref pci_bus_size_bridges(struct pci_bus *bus) |
1da177e4 LT |
576 | { |
577 | struct pci_dev *dev; | |
578 | unsigned long mask, prefmask; | |
28760489 | 579 | resource_size_t min_mem_size = 0, min_io_size = 0; |
1da177e4 LT |
580 | |
581 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
582 | struct pci_bus *b = dev->subordinate; | |
583 | if (!b) | |
584 | continue; | |
585 | ||
586 | switch (dev->class >> 8) { | |
587 | case PCI_CLASS_BRIDGE_CARDBUS: | |
588 | pci_bus_size_cardbus(b); | |
589 | break; | |
590 | ||
591 | case PCI_CLASS_BRIDGE_PCI: | |
592 | default: | |
593 | pci_bus_size_bridges(b); | |
594 | break; | |
595 | } | |
596 | } | |
597 | ||
598 | /* The root bus? */ | |
599 | if (!bus->self) | |
600 | return; | |
601 | ||
602 | switch (bus->self->class >> 8) { | |
603 | case PCI_CLASS_BRIDGE_CARDBUS: | |
604 | /* don't size cardbuses yet. */ | |
605 | break; | |
606 | ||
607 | case PCI_CLASS_BRIDGE_PCI: | |
608 | pci_bridge_check_ranges(bus); | |
28760489 EB |
609 | if (bus->self->is_hotplug_bridge) { |
610 | min_io_size = pci_hotplug_io_size; | |
611 | min_mem_size = pci_hotplug_mem_size; | |
612 | } | |
1da177e4 | 613 | default: |
28760489 | 614 | pbus_size_io(bus, min_io_size); |
1da177e4 LT |
615 | /* If the bridge supports prefetchable range, size it |
616 | separately. If it doesn't, or its prefetchable window | |
617 | has already been allocated by arch code, try | |
618 | non-prefetchable range for both types of PCI memory | |
619 | resources. */ | |
620 | mask = IORESOURCE_MEM; | |
621 | prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
28760489 | 622 | if (pbus_size_mem(bus, prefmask, prefmask, min_mem_size)) |
1da177e4 | 623 | mask = prefmask; /* Success, size non-prefetch only. */ |
28760489 EB |
624 | else |
625 | min_mem_size += min_mem_size; | |
626 | pbus_size_mem(bus, mask, IORESOURCE_MEM, min_mem_size); | |
1da177e4 LT |
627 | break; |
628 | } | |
629 | } | |
630 | EXPORT_SYMBOL(pci_bus_size_bridges); | |
631 | ||
568ddef8 YL |
632 | static void __ref __pci_bus_assign_resources(const struct pci_bus *bus, |
633 | struct resource_list_x *fail_head) | |
1da177e4 LT |
634 | { |
635 | struct pci_bus *b; | |
636 | struct pci_dev *dev; | |
637 | ||
568ddef8 | 638 | pbus_assign_resources_sorted(bus, fail_head); |
1da177e4 | 639 | |
1da177e4 LT |
640 | list_for_each_entry(dev, &bus->devices, bus_list) { |
641 | b = dev->subordinate; | |
642 | if (!b) | |
643 | continue; | |
644 | ||
568ddef8 | 645 | __pci_bus_assign_resources(b, fail_head); |
1da177e4 LT |
646 | |
647 | switch (dev->class >> 8) { | |
648 | case PCI_CLASS_BRIDGE_PCI: | |
649 | pci_setup_bridge(b); | |
650 | break; | |
651 | ||
652 | case PCI_CLASS_BRIDGE_CARDBUS: | |
653 | pci_setup_cardbus(b); | |
654 | break; | |
655 | ||
656 | default: | |
80ccba11 BH |
657 | dev_info(&dev->dev, "not setting up bridge for bus " |
658 | "%04x:%02x\n", pci_domain_nr(b), b->number); | |
1da177e4 LT |
659 | break; |
660 | } | |
661 | } | |
662 | } | |
568ddef8 YL |
663 | |
664 | void __ref pci_bus_assign_resources(const struct pci_bus *bus) | |
665 | { | |
666 | __pci_bus_assign_resources(bus, NULL); | |
667 | } | |
1da177e4 LT |
668 | EXPORT_SYMBOL(pci_bus_assign_resources); |
669 | ||
5009b460 YL |
670 | static void pci_bridge_release_resources(struct pci_bus *bus, |
671 | unsigned long type) | |
672 | { | |
673 | int idx; | |
674 | bool changed = false; | |
675 | struct pci_dev *dev; | |
676 | struct resource *r; | |
677 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | | |
678 | IORESOURCE_PREFETCH; | |
679 | ||
680 | dev = bus->self; | |
681 | for (idx = PCI_BRIDGE_RESOURCES; idx <= PCI_BRIDGE_RESOURCE_END; | |
682 | idx++) { | |
683 | r = &dev->resource[idx]; | |
684 | if ((r->flags & type_mask) != type) | |
685 | continue; | |
686 | if (!r->parent) | |
687 | continue; | |
688 | /* | |
689 | * if there are children under that, we should release them | |
690 | * all | |
691 | */ | |
692 | release_child_resources(r); | |
693 | if (!release_resource(r)) { | |
694 | dev_printk(KERN_DEBUG, &dev->dev, | |
695 | "resource %d %pR released\n", idx, r); | |
696 | /* keep the old size */ | |
697 | r->end = resource_size(r) - 1; | |
698 | r->start = 0; | |
699 | r->flags = 0; | |
700 | changed = true; | |
701 | } | |
702 | } | |
703 | ||
704 | if (changed) { | |
705 | /* avoiding touch the one without PREF */ | |
706 | if (type & IORESOURCE_PREFETCH) | |
707 | type = IORESOURCE_PREFETCH; | |
708 | __pci_setup_bridge(bus, type); | |
709 | } | |
710 | } | |
711 | ||
712 | enum release_type { | |
713 | leaf_only, | |
714 | whole_subtree, | |
715 | }; | |
716 | /* | |
717 | * try to release pci bridge resources that is from leaf bridge, | |
718 | * so we can allocate big new one later | |
719 | */ | |
720 | static void __ref pci_bus_release_bridge_resources(struct pci_bus *bus, | |
721 | unsigned long type, | |
722 | enum release_type rel_type) | |
723 | { | |
724 | struct pci_dev *dev; | |
725 | bool is_leaf_bridge = true; | |
726 | ||
727 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
728 | struct pci_bus *b = dev->subordinate; | |
729 | if (!b) | |
730 | continue; | |
731 | ||
732 | is_leaf_bridge = false; | |
733 | ||
734 | if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) | |
735 | continue; | |
736 | ||
737 | if (rel_type == whole_subtree) | |
738 | pci_bus_release_bridge_resources(b, type, | |
739 | whole_subtree); | |
740 | } | |
741 | ||
742 | if (pci_is_root_bus(bus)) | |
743 | return; | |
744 | ||
745 | if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI) | |
746 | return; | |
747 | ||
748 | if ((rel_type == whole_subtree) || is_leaf_bridge) | |
749 | pci_bridge_release_resources(bus, type); | |
750 | } | |
751 | ||
76fbc263 YL |
752 | static void pci_bus_dump_res(struct pci_bus *bus) |
753 | { | |
754 | int i; | |
755 | ||
756 | for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) { | |
757 | struct resource *res = bus->resource[i]; | |
7c9342b8 YL |
758 | |
759 | if (!res || !res->end || !res->flags) | |
76fbc263 YL |
760 | continue; |
761 | ||
c7dabef8 | 762 | dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res); |
76fbc263 YL |
763 | } |
764 | } | |
765 | ||
766 | static void pci_bus_dump_resources(struct pci_bus *bus) | |
767 | { | |
768 | struct pci_bus *b; | |
769 | struct pci_dev *dev; | |
770 | ||
771 | ||
772 | pci_bus_dump_res(bus); | |
773 | ||
774 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
775 | b = dev->subordinate; | |
776 | if (!b) | |
777 | continue; | |
778 | ||
779 | pci_bus_dump_resources(b); | |
780 | } | |
781 | } | |
782 | ||
977d17bb YL |
783 | static int __init pci_bus_get_depth(struct pci_bus *bus) |
784 | { | |
785 | int depth = 0; | |
786 | struct pci_dev *dev; | |
787 | ||
788 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
789 | int ret; | |
790 | struct pci_bus *b = dev->subordinate; | |
791 | if (!b) | |
792 | continue; | |
793 | ||
794 | ret = pci_bus_get_depth(b); | |
795 | if (ret + 1 > depth) | |
796 | depth = ret + 1; | |
797 | } | |
798 | ||
799 | return depth; | |
800 | } | |
801 | static int __init pci_get_max_depth(void) | |
802 | { | |
803 | int depth = 0; | |
804 | struct pci_bus *bus; | |
805 | ||
806 | list_for_each_entry(bus, &pci_root_buses, node) { | |
807 | int ret; | |
808 | ||
809 | ret = pci_bus_get_depth(bus); | |
810 | if (ret > depth) | |
811 | depth = ret; | |
812 | } | |
813 | ||
814 | return depth; | |
815 | } | |
816 | ||
817 | /* | |
818 | * first try will not touch pci bridge res | |
819 | * second and later try will clear small leaf bridge res | |
820 | * will stop till to the max deepth if can not find good one | |
821 | */ | |
1da177e4 LT |
822 | void __init |
823 | pci_assign_unassigned_resources(void) | |
824 | { | |
825 | struct pci_bus *bus; | |
977d17bb YL |
826 | int tried_times = 0; |
827 | enum release_type rel_type = leaf_only; | |
828 | struct resource_list_x head, *list; | |
829 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | | |
830 | IORESOURCE_PREFETCH; | |
831 | unsigned long failed_type; | |
832 | int max_depth = pci_get_max_depth(); | |
833 | int pci_try_num; | |
834 | ||
835 | head.next = NULL; | |
1da177e4 | 836 | |
977d17bb YL |
837 | pci_try_num = max_depth + 1; |
838 | printk(KERN_DEBUG "PCI: max bus depth: %d pci_try_num: %d\n", | |
839 | max_depth, pci_try_num); | |
840 | ||
841 | again: | |
1da177e4 LT |
842 | /* Depth first, calculate sizes and alignments of all |
843 | subordinate buses. */ | |
844 | list_for_each_entry(bus, &pci_root_buses, node) { | |
845 | pci_bus_size_bridges(bus); | |
846 | } | |
847 | /* Depth last, allocate resources and update the hardware. */ | |
848 | list_for_each_entry(bus, &pci_root_buses, node) { | |
977d17bb YL |
849 | __pci_bus_assign_resources(bus, &head); |
850 | } | |
851 | tried_times++; | |
852 | ||
853 | /* any device complain? */ | |
854 | if (!head.next) | |
855 | goto enable_and_dump; | |
856 | failed_type = 0; | |
857 | for (list = head.next; list;) { | |
858 | failed_type |= list->flags; | |
859 | list = list->next; | |
860 | } | |
861 | /* | |
862 | * io port are tight, don't try extra | |
863 | * or if reach the limit, don't want to try more | |
864 | */ | |
865 | failed_type &= type_mask; | |
866 | if ((failed_type == IORESOURCE_IO) || (tried_times >= pci_try_num)) { | |
867 | free_failed_list(&head); | |
868 | goto enable_and_dump; | |
869 | } | |
870 | ||
871 | printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n", | |
872 | tried_times + 1); | |
873 | ||
874 | /* third times and later will not check if it is leaf */ | |
875 | if ((tried_times + 1) > 2) | |
876 | rel_type = whole_subtree; | |
877 | ||
878 | /* | |
879 | * Try to release leaf bridge's resources that doesn't fit resource of | |
880 | * child device under that bridge | |
881 | */ | |
882 | for (list = head.next; list;) { | |
883 | bus = list->dev->bus; | |
884 | pci_bus_release_bridge_resources(bus, list->flags & type_mask, | |
885 | rel_type); | |
886 | list = list->next; | |
1da177e4 | 887 | } |
977d17bb YL |
888 | /* restore size and flags */ |
889 | for (list = head.next; list;) { | |
890 | struct resource *res = list->res; | |
891 | ||
892 | res->start = list->start; | |
893 | res->end = list->end; | |
894 | res->flags = list->flags; | |
895 | if (list->dev->subordinate) | |
896 | res->flags = 0; | |
897 | ||
898 | list = list->next; | |
899 | } | |
900 | free_failed_list(&head); | |
901 | ||
902 | goto again; | |
903 | ||
904 | enable_and_dump: | |
905 | /* Depth last, update the hardware. */ | |
906 | list_for_each_entry(bus, &pci_root_buses, node) | |
907 | pci_enable_bridges(bus); | |
76fbc263 YL |
908 | |
909 | /* dump the resource on buses */ | |
910 | list_for_each_entry(bus, &pci_root_buses, node) { | |
911 | pci_bus_dump_resources(bus); | |
912 | } | |
1da177e4 | 913 | } |