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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * drivers/pci/setup-bus.c | |
3 | * | |
4 | * Extruded from code written by | |
5 | * Dave Rusling (david.rusling@reo.mts.dec.com) | |
6 | * David Mosberger (davidm@cs.arizona.edu) | |
7 | * David Miller (davem@redhat.com) | |
8 | * | |
9 | * Support routines for initializing a PCI subsystem. | |
10 | */ | |
11 | ||
12 | /* | |
13 | * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> | |
14 | * PCI-PCI bridges cleanup, sorted resource allocation. | |
15 | * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru> | |
16 | * Converted to allocation in 3 passes, which gives | |
17 | * tighter packing. Prefetchable range support. | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/pci.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/ioport.h> | |
26 | #include <linux/cache.h> | |
27 | #include <linux/slab.h> | |
6faf17f6 | 28 | #include "pci.h" |
1da177e4 | 29 | |
bdc4abec YL |
30 | struct pci_dev_resource { |
31 | struct list_head list; | |
2934a0de YL |
32 | struct resource *res; |
33 | struct pci_dev *dev; | |
34 | }; | |
35 | ||
bdc4abec YL |
36 | struct pci_dev_resource_x { |
37 | struct list_head list; | |
568ddef8 YL |
38 | struct resource *res; |
39 | struct pci_dev *dev; | |
40 | resource_size_t start; | |
41 | resource_size_t end; | |
c8adf9a3 | 42 | resource_size_t add_size; |
2bbc6942 | 43 | resource_size_t min_align; |
568ddef8 YL |
44 | unsigned long flags; |
45 | }; | |
46 | ||
bdc4abec YL |
47 | #define free_list(type, head) do { \ |
48 | struct type *dev_res, *tmp; \ | |
49 | list_for_each_entry_safe(dev_res, tmp, head, list) { \ | |
50 | list_del(&dev_res->list); \ | |
51 | kfree(dev_res); \ | |
52 | } \ | |
094732a5 RP |
53 | } while (0) |
54 | ||
f483d392 RP |
55 | int pci_realloc_enable = 0; |
56 | #define pci_realloc_enabled() pci_realloc_enable | |
57 | void pci_realloc(void) | |
58 | { | |
59 | pci_realloc_enable = 1; | |
60 | } | |
61 | ||
c8adf9a3 RP |
62 | /** |
63 | * add_to_list() - add a new resource tracker to the list | |
64 | * @head: Head of the list | |
65 | * @dev: device corresponding to which the resource | |
66 | * belongs | |
67 | * @res: The resource to be tracked | |
68 | * @add_size: additional size to be optionally added | |
69 | * to the resource | |
70 | */ | |
bdc4abec | 71 | static int add_to_list(struct list_head *head, |
c8adf9a3 | 72 | struct pci_dev *dev, struct resource *res, |
2bbc6942 | 73 | resource_size_t add_size, resource_size_t min_align) |
568ddef8 | 74 | { |
bdc4abec | 75 | struct pci_dev_resource_x *tmp; |
568ddef8 | 76 | |
bdc4abec | 77 | tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); |
568ddef8 | 78 | if (!tmp) { |
c8adf9a3 | 79 | pr_warning("add_to_list: kmalloc() failed!\n"); |
ef62dfef | 80 | return -ENOMEM; |
568ddef8 YL |
81 | } |
82 | ||
568ddef8 YL |
83 | tmp->res = res; |
84 | tmp->dev = dev; | |
85 | tmp->start = res->start; | |
86 | tmp->end = res->end; | |
87 | tmp->flags = res->flags; | |
c8adf9a3 | 88 | tmp->add_size = add_size; |
2bbc6942 | 89 | tmp->min_align = min_align; |
bdc4abec YL |
90 | |
91 | list_add(&tmp->list, head); | |
ef62dfef YL |
92 | |
93 | return 0; | |
568ddef8 YL |
94 | } |
95 | ||
bdc4abec | 96 | static void add_to_failed_list(struct list_head *head, |
c8adf9a3 RP |
97 | struct pci_dev *dev, struct resource *res) |
98 | { | |
2bbc6942 RP |
99 | add_to_list(head, dev, res, |
100 | 0 /* dont care */, | |
101 | 0 /* dont care */); | |
c8adf9a3 RP |
102 | } |
103 | ||
bdc4abec | 104 | static void remove_from_list(struct list_head *realloc_head, |
3e6e0d80 YL |
105 | struct resource *res) |
106 | { | |
bdc4abec | 107 | struct pci_dev_resource_x *dev_res_x, *tmp; |
3e6e0d80 | 108 | |
bdc4abec YL |
109 | list_for_each_entry_safe(dev_res_x, tmp, realloc_head, list) { |
110 | if (dev_res_x->res == res) { | |
111 | list_del(&dev_res_x->list); | |
112 | kfree(dev_res_x); | |
113 | break; | |
3e6e0d80 | 114 | } |
3e6e0d80 YL |
115 | } |
116 | } | |
117 | ||
bdc4abec | 118 | static resource_size_t get_res_add_size(struct list_head *realloc_head, |
1c372353 YL |
119 | struct resource *res) |
120 | { | |
bdc4abec YL |
121 | struct pci_dev_resource_x *dev_res_x; |
122 | ||
123 | list_for_each_entry(dev_res_x, realloc_head, list) { | |
124 | if (dev_res_x->res == res) { | |
125 | dev_printk(KERN_DEBUG, &dev_res_x->dev->dev, | |
126 | "%pR get_res_add_size add_size %llx\n", | |
127 | dev_res_x->res, | |
128 | (unsigned long long)dev_res_x->add_size); | |
129 | return dev_res_x->add_size; | |
130 | } | |
3e6e0d80 | 131 | } |
1c372353 YL |
132 | |
133 | return 0; | |
134 | } | |
135 | ||
78c3b329 | 136 | /* Sort resources by alignment */ |
bdc4abec | 137 | static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head) |
78c3b329 YL |
138 | { |
139 | int i; | |
140 | ||
141 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
142 | struct resource *r; | |
bdc4abec | 143 | struct pci_dev_resource *dev_res, *tmp; |
78c3b329 | 144 | resource_size_t r_align; |
bdc4abec | 145 | struct list_head *n; |
78c3b329 YL |
146 | |
147 | r = &dev->resource[i]; | |
148 | ||
149 | if (r->flags & IORESOURCE_PCI_FIXED) | |
150 | continue; | |
151 | ||
152 | if (!(r->flags) || r->parent) | |
153 | continue; | |
154 | ||
155 | r_align = pci_resource_alignment(dev, r); | |
156 | if (!r_align) { | |
157 | dev_warn(&dev->dev, "BAR %d: %pR has bogus alignment\n", | |
158 | i, r); | |
159 | continue; | |
160 | } | |
78c3b329 | 161 | |
bdc4abec YL |
162 | tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); |
163 | if (!tmp) | |
164 | panic("pdev_sort_resources(): " | |
165 | "kmalloc() failed!\n"); | |
166 | tmp->res = r; | |
167 | tmp->dev = dev; | |
168 | ||
169 | /* fallback is smallest one or list is empty*/ | |
170 | n = head; | |
171 | list_for_each_entry(dev_res, head, list) { | |
172 | resource_size_t align; | |
173 | ||
174 | align = pci_resource_alignment(dev_res->dev, | |
175 | dev_res->res); | |
78c3b329 YL |
176 | |
177 | if (r_align > align) { | |
bdc4abec | 178 | n = &dev_res->list; |
78c3b329 YL |
179 | break; |
180 | } | |
181 | } | |
bdc4abec YL |
182 | /* Insert it just before n*/ |
183 | list_add_tail(&tmp->list, n); | |
78c3b329 YL |
184 | } |
185 | } | |
186 | ||
6841ec68 | 187 | static void __dev_sort_resources(struct pci_dev *dev, |
bdc4abec | 188 | struct list_head *head) |
1da177e4 | 189 | { |
6841ec68 | 190 | u16 class = dev->class >> 8; |
1da177e4 | 191 | |
6841ec68 YL |
192 | /* Don't touch classless devices or host bridges or ioapics. */ |
193 | if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST) | |
194 | return; | |
1da177e4 | 195 | |
6841ec68 YL |
196 | /* Don't touch ioapic devices already enabled by firmware */ |
197 | if (class == PCI_CLASS_SYSTEM_PIC) { | |
198 | u16 command; | |
199 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
200 | if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | |
201 | return; | |
202 | } | |
1da177e4 | 203 | |
6841ec68 YL |
204 | pdev_sort_resources(dev, head); |
205 | } | |
23186279 | 206 | |
fc075e1d RP |
207 | static inline void reset_resource(struct resource *res) |
208 | { | |
209 | res->start = 0; | |
210 | res->end = 0; | |
211 | res->flags = 0; | |
212 | } | |
213 | ||
c8adf9a3 | 214 | /** |
9e8bf93a | 215 | * reassign_resources_sorted() - satisfy any additional resource requests |
c8adf9a3 | 216 | * |
9e8bf93a | 217 | * @realloc_head : head of the list tracking requests requiring additional |
c8adf9a3 RP |
218 | * resources |
219 | * @head : head of the list tracking requests with allocated | |
220 | * resources | |
221 | * | |
9e8bf93a | 222 | * Walk through each element of the realloc_head and try to procure |
c8adf9a3 RP |
223 | * additional resources for the element, provided the element |
224 | * is in the head list. | |
225 | */ | |
bdc4abec YL |
226 | static void reassign_resources_sorted(struct list_head *realloc_head, |
227 | struct list_head *head) | |
6841ec68 YL |
228 | { |
229 | struct resource *res; | |
bdc4abec YL |
230 | struct pci_dev_resource_x *dev_res_x, *tmp; |
231 | struct pci_dev_resource *dev_res; | |
c8adf9a3 | 232 | resource_size_t add_size; |
6841ec68 | 233 | int idx; |
1da177e4 | 234 | |
bdc4abec YL |
235 | list_for_each_entry_safe(dev_res_x, tmp, realloc_head, list) { |
236 | bool found_match = false; | |
237 | ||
238 | res = dev_res_x->res; | |
c8adf9a3 RP |
239 | /* skip resource that has been reset */ |
240 | if (!res->flags) | |
241 | goto out; | |
242 | ||
243 | /* skip this resource if not found in head list */ | |
bdc4abec YL |
244 | list_for_each_entry(dev_res, head, list) { |
245 | if (dev_res->res == res) { | |
246 | found_match = true; | |
247 | break; | |
248 | } | |
c8adf9a3 | 249 | } |
bdc4abec YL |
250 | if (!found_match)/* just skip */ |
251 | continue; | |
c8adf9a3 | 252 | |
bdc4abec YL |
253 | idx = res - &dev_res_x->dev->resource[0]; |
254 | add_size = dev_res_x->add_size; | |
2bbc6942 | 255 | if (!resource_size(res)) { |
bdc4abec | 256 | res->start = dev_res_x->start; |
2bbc6942 | 257 | res->end = res->start + add_size - 1; |
bdc4abec | 258 | if (pci_assign_resource(dev_res_x->dev, idx)) |
c8adf9a3 | 259 | reset_resource(res); |
2bbc6942 | 260 | } else { |
bdc4abec YL |
261 | resource_size_t align = dev_res_x->min_align; |
262 | res->flags |= dev_res_x->flags & | |
263 | (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN); | |
264 | if (pci_reassign_resource(dev_res_x->dev, idx, | |
265 | add_size, align)) | |
266 | dev_printk(KERN_DEBUG, &dev_res_x->dev->dev, | |
267 | "failed to add optional resources res=%pR\n", | |
2bbc6942 | 268 | res); |
c8adf9a3 RP |
269 | } |
270 | out: | |
bdc4abec YL |
271 | list_del(&dev_res_x->list); |
272 | kfree(dev_res_x); | |
c8adf9a3 RP |
273 | } |
274 | } | |
275 | ||
276 | /** | |
277 | * assign_requested_resources_sorted() - satisfy resource requests | |
278 | * | |
279 | * @head : head of the list tracking requests for resources | |
280 | * @failed_list : head of the list tracking requests that could | |
281 | * not be allocated | |
282 | * | |
283 | * Satisfy resource requests of each element in the list. Add | |
284 | * requests that could not satisfied to the failed_list. | |
285 | */ | |
bdc4abec YL |
286 | static void assign_requested_resources_sorted(struct list_head *head, |
287 | struct list_head *fail_head) | |
c8adf9a3 RP |
288 | { |
289 | struct resource *res; | |
bdc4abec | 290 | struct pci_dev_resource *dev_res; |
c8adf9a3 | 291 | int idx; |
9a928660 | 292 | |
bdc4abec YL |
293 | list_for_each_entry(dev_res, head, list) { |
294 | res = dev_res->res; | |
295 | idx = res - &dev_res->dev->resource[0]; | |
296 | if (resource_size(res) && | |
297 | pci_assign_resource(dev_res->dev, idx)) { | |
298 | if (fail_head && !pci_is_root_bus(dev_res->dev->bus)) { | |
9a928660 YL |
299 | /* |
300 | * if the failed res is for ROM BAR, and it will | |
301 | * be enabled later, don't add it to the list | |
302 | */ | |
303 | if (!((idx == PCI_ROM_RESOURCE) && | |
304 | (!(res->flags & IORESOURCE_ROM_ENABLE)))) | |
bdc4abec YL |
305 | add_to_failed_list(fail_head, |
306 | dev_res->dev, res); | |
9a928660 | 307 | } |
fc075e1d | 308 | reset_resource(res); |
542df5de | 309 | } |
1da177e4 LT |
310 | } |
311 | } | |
312 | ||
bdc4abec YL |
313 | static void __assign_resources_sorted(struct list_head *head, |
314 | struct list_head *realloc_head, | |
315 | struct list_head *fail_head) | |
c8adf9a3 | 316 | { |
3e6e0d80 YL |
317 | /* |
318 | * Should not assign requested resources at first. | |
319 | * they could be adjacent, so later reassign can not reallocate | |
320 | * them one by one in parent resource window. | |
321 | * Try to assign requested + add_size at begining | |
322 | * if could do that, could get out early. | |
323 | * if could not do that, we still try to assign requested at first, | |
324 | * then try to reassign add_size for some resources. | |
325 | */ | |
bdc4abec YL |
326 | LIST_HEAD(save_head); |
327 | LIST_HEAD(local_fail_head); | |
328 | struct pci_dev_resource_x *dev_res_x; | |
329 | struct pci_dev_resource *dev_res; | |
3e6e0d80 YL |
330 | |
331 | /* Check if optional add_size is there */ | |
bdc4abec | 332 | if (!realloc_head || list_empty(realloc_head)) |
3e6e0d80 YL |
333 | goto requested_and_reassign; |
334 | ||
335 | /* Save original start, end, flags etc at first */ | |
bdc4abec YL |
336 | list_for_each_entry(dev_res, head, list) { |
337 | if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) { | |
338 | free_list(pci_dev_resource_x, &save_head); | |
3e6e0d80 YL |
339 | goto requested_and_reassign; |
340 | } | |
bdc4abec | 341 | } |
3e6e0d80 YL |
342 | |
343 | /* Update res in head list with add_size in realloc_head list */ | |
bdc4abec YL |
344 | list_for_each_entry(dev_res, head, list) |
345 | dev_res->res->end += get_res_add_size(realloc_head, | |
346 | dev_res->res); | |
3e6e0d80 YL |
347 | |
348 | /* Try updated head list with add_size added */ | |
3e6e0d80 YL |
349 | assign_requested_resources_sorted(head, &local_fail_head); |
350 | ||
351 | /* all assigned with add_size ? */ | |
bdc4abec | 352 | if (list_empty(&local_fail_head)) { |
3e6e0d80 | 353 | /* Remove head list from realloc_head list */ |
bdc4abec YL |
354 | list_for_each_entry(dev_res, head, list) |
355 | remove_from_list(realloc_head, dev_res->res); | |
356 | free_list(pci_dev_resource_x, &save_head); | |
357 | free_list(pci_dev_resource, head); | |
3e6e0d80 YL |
358 | return; |
359 | } | |
360 | ||
bdc4abec | 361 | free_list(pci_dev_resource_x, &local_fail_head); |
3e6e0d80 | 362 | /* Release assigned resource */ |
bdc4abec YL |
363 | list_for_each_entry(dev_res, head, list) |
364 | if (dev_res->res->parent) | |
365 | release_resource(dev_res->res); | |
3e6e0d80 | 366 | /* Restore start/end/flags from saved list */ |
bdc4abec YL |
367 | list_for_each_entry(dev_res_x, &save_head, list) { |
368 | struct resource *res = dev_res_x->res; | |
3e6e0d80 | 369 | |
bdc4abec YL |
370 | res->start = dev_res_x->start; |
371 | res->end = dev_res_x->end; | |
372 | res->flags = dev_res_x->flags; | |
3e6e0d80 | 373 | } |
bdc4abec | 374 | free_list(pci_dev_resource_x, &save_head); |
3e6e0d80 YL |
375 | |
376 | requested_and_reassign: | |
c8adf9a3 RP |
377 | /* Satisfy the must-have resource requests */ |
378 | assign_requested_resources_sorted(head, fail_head); | |
379 | ||
0a2daa1c | 380 | /* Try to satisfy any additional optional resource |
c8adf9a3 | 381 | requests */ |
9e8bf93a RP |
382 | if (realloc_head) |
383 | reassign_resources_sorted(realloc_head, head); | |
bdc4abec | 384 | free_list(pci_dev_resource, head); |
c8adf9a3 RP |
385 | } |
386 | ||
6841ec68 | 387 | static void pdev_assign_resources_sorted(struct pci_dev *dev, |
bdc4abec YL |
388 | struct list_head *add_head, |
389 | struct list_head *fail_head) | |
6841ec68 | 390 | { |
bdc4abec | 391 | LIST_HEAD(head); |
6841ec68 | 392 | |
6841ec68 | 393 | __dev_sort_resources(dev, &head); |
8424d759 | 394 | __assign_resources_sorted(&head, add_head, fail_head); |
6841ec68 YL |
395 | |
396 | } | |
397 | ||
398 | static void pbus_assign_resources_sorted(const struct pci_bus *bus, | |
bdc4abec YL |
399 | struct list_head *realloc_head, |
400 | struct list_head *fail_head) | |
6841ec68 YL |
401 | { |
402 | struct pci_dev *dev; | |
bdc4abec | 403 | LIST_HEAD(head); |
6841ec68 | 404 | |
6841ec68 YL |
405 | list_for_each_entry(dev, &bus->devices, bus_list) |
406 | __dev_sort_resources(dev, &head); | |
407 | ||
9e8bf93a | 408 | __assign_resources_sorted(&head, realloc_head, fail_head); |
6841ec68 YL |
409 | } |
410 | ||
b3743fa4 | 411 | void pci_setup_cardbus(struct pci_bus *bus) |
1da177e4 LT |
412 | { |
413 | struct pci_dev *bridge = bus->self; | |
c7dabef8 | 414 | struct resource *res; |
1da177e4 LT |
415 | struct pci_bus_region region; |
416 | ||
865df576 BH |
417 | dev_info(&bridge->dev, "CardBus bridge to [bus %02x-%02x]\n", |
418 | bus->secondary, bus->subordinate); | |
1da177e4 | 419 | |
c7dabef8 BH |
420 | res = bus->resource[0]; |
421 | pcibios_resource_to_bus(bridge, ®ion, res); | |
422 | if (res->flags & IORESOURCE_IO) { | |
1da177e4 LT |
423 | /* |
424 | * The IO resource is allocated a range twice as large as it | |
425 | * would normally need. This allows us to set both IO regs. | |
426 | */ | |
c7dabef8 | 427 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
1da177e4 LT |
428 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, |
429 | region.start); | |
430 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0, | |
431 | region.end); | |
432 | } | |
433 | ||
c7dabef8 BH |
434 | res = bus->resource[1]; |
435 | pcibios_resource_to_bus(bridge, ®ion, res); | |
436 | if (res->flags & IORESOURCE_IO) { | |
437 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
438 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, |
439 | region.start); | |
440 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1, | |
441 | region.end); | |
442 | } | |
443 | ||
c7dabef8 BH |
444 | res = bus->resource[2]; |
445 | pcibios_resource_to_bus(bridge, ®ion, res); | |
446 | if (res->flags & IORESOURCE_MEM) { | |
447 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
448 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, |
449 | region.start); | |
450 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0, | |
451 | region.end); | |
452 | } | |
453 | ||
c7dabef8 BH |
454 | res = bus->resource[3]; |
455 | pcibios_resource_to_bus(bridge, ®ion, res); | |
456 | if (res->flags & IORESOURCE_MEM) { | |
457 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
458 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, |
459 | region.start); | |
460 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1, | |
461 | region.end); | |
462 | } | |
463 | } | |
b3743fa4 | 464 | EXPORT_SYMBOL(pci_setup_cardbus); |
1da177e4 LT |
465 | |
466 | /* Initialize bridges with base/limit values we have collected. | |
467 | PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998) | |
468 | requires that if there is no I/O ports or memory behind the | |
469 | bridge, corresponding range must be turned off by writing base | |
470 | value greater than limit to the bridge's base/limit registers. | |
471 | ||
472 | Note: care must be taken when updating I/O base/limit registers | |
473 | of bridges which support 32-bit I/O. This update requires two | |
474 | config space writes, so it's quite possible that an I/O window of | |
475 | the bridge will have some undesirable address (e.g. 0) after the | |
476 | first write. Ditto 64-bit prefetchable MMIO. */ | |
7cc5997d | 477 | static void pci_setup_bridge_io(struct pci_bus *bus) |
1da177e4 LT |
478 | { |
479 | struct pci_dev *bridge = bus->self; | |
c7dabef8 | 480 | struct resource *res; |
1da177e4 | 481 | struct pci_bus_region region; |
7cc5997d | 482 | u32 l, io_upper16; |
1da177e4 LT |
483 | |
484 | /* Set up the top and bottom of the PCI I/O segment for this bus. */ | |
c7dabef8 BH |
485 | res = bus->resource[0]; |
486 | pcibios_resource_to_bus(bridge, ®ion, res); | |
487 | if (res->flags & IORESOURCE_IO) { | |
1da177e4 LT |
488 | pci_read_config_dword(bridge, PCI_IO_BASE, &l); |
489 | l &= 0xffff0000; | |
490 | l |= (region.start >> 8) & 0x00f0; | |
491 | l |= region.end & 0xf000; | |
492 | /* Set up upper 16 bits of I/O base/limit. */ | |
493 | io_upper16 = (region.end & 0xffff0000) | (region.start >> 16); | |
c7dabef8 | 494 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 495 | } else { |
1da177e4 LT |
496 | /* Clear upper 16 bits of I/O base/limit. */ |
497 | io_upper16 = 0; | |
498 | l = 0x00f0; | |
1da177e4 LT |
499 | } |
500 | /* Temporarily disable the I/O range before updating PCI_IO_BASE. */ | |
501 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff); | |
502 | /* Update lower 16 bits of I/O base/limit. */ | |
503 | pci_write_config_dword(bridge, PCI_IO_BASE, l); | |
504 | /* Update upper 16 bits of I/O base/limit. */ | |
505 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16); | |
7cc5997d YL |
506 | } |
507 | ||
508 | static void pci_setup_bridge_mmio(struct pci_bus *bus) | |
509 | { | |
510 | struct pci_dev *bridge = bus->self; | |
511 | struct resource *res; | |
512 | struct pci_bus_region region; | |
513 | u32 l; | |
1da177e4 | 514 | |
7cc5997d | 515 | /* Set up the top and bottom of the PCI Memory segment for this bus. */ |
c7dabef8 BH |
516 | res = bus->resource[1]; |
517 | pcibios_resource_to_bus(bridge, ®ion, res); | |
518 | if (res->flags & IORESOURCE_MEM) { | |
1da177e4 LT |
519 | l = (region.start >> 16) & 0xfff0; |
520 | l |= region.end & 0xfff00000; | |
c7dabef8 | 521 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 522 | } else { |
1da177e4 | 523 | l = 0x0000fff0; |
1da177e4 LT |
524 | } |
525 | pci_write_config_dword(bridge, PCI_MEMORY_BASE, l); | |
7cc5997d YL |
526 | } |
527 | ||
528 | static void pci_setup_bridge_mmio_pref(struct pci_bus *bus) | |
529 | { | |
530 | struct pci_dev *bridge = bus->self; | |
531 | struct resource *res; | |
532 | struct pci_bus_region region; | |
533 | u32 l, bu, lu; | |
1da177e4 LT |
534 | |
535 | /* Clear out the upper 32 bits of PREF limit. | |
536 | If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily | |
537 | disables PREF range, which is ok. */ | |
538 | pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0); | |
539 | ||
540 | /* Set up PREF base/limit. */ | |
c40a22e0 | 541 | bu = lu = 0; |
c7dabef8 BH |
542 | res = bus->resource[2]; |
543 | pcibios_resource_to_bus(bridge, ®ion, res); | |
544 | if (res->flags & IORESOURCE_PREFETCH) { | |
1da177e4 LT |
545 | l = (region.start >> 16) & 0xfff0; |
546 | l |= region.end & 0xfff00000; | |
c7dabef8 | 547 | if (res->flags & IORESOURCE_MEM_64) { |
1f82de10 YL |
548 | bu = upper_32_bits(region.start); |
549 | lu = upper_32_bits(region.end); | |
1f82de10 | 550 | } |
c7dabef8 | 551 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 552 | } else { |
1da177e4 | 553 | l = 0x0000fff0; |
1da177e4 LT |
554 | } |
555 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l); | |
556 | ||
59353ea3 AW |
557 | /* Set the upper 32 bits of PREF base & limit. */ |
558 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu); | |
559 | pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu); | |
7cc5997d YL |
560 | } |
561 | ||
562 | static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type) | |
563 | { | |
564 | struct pci_dev *bridge = bus->self; | |
565 | ||
7cc5997d YL |
566 | dev_info(&bridge->dev, "PCI bridge to [bus %02x-%02x]\n", |
567 | bus->secondary, bus->subordinate); | |
568 | ||
569 | if (type & IORESOURCE_IO) | |
570 | pci_setup_bridge_io(bus); | |
571 | ||
572 | if (type & IORESOURCE_MEM) | |
573 | pci_setup_bridge_mmio(bus); | |
574 | ||
575 | if (type & IORESOURCE_PREFETCH) | |
576 | pci_setup_bridge_mmio_pref(bus); | |
1da177e4 LT |
577 | |
578 | pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl); | |
579 | } | |
580 | ||
e2444273 | 581 | void pci_setup_bridge(struct pci_bus *bus) |
7cc5997d YL |
582 | { |
583 | unsigned long type = IORESOURCE_IO | IORESOURCE_MEM | | |
584 | IORESOURCE_PREFETCH; | |
585 | ||
586 | __pci_setup_bridge(bus, type); | |
587 | } | |
588 | ||
1da177e4 LT |
589 | /* Check whether the bridge supports optional I/O and |
590 | prefetchable memory ranges. If not, the respective | |
591 | base/limit registers must be read-only and read as 0. */ | |
96bde06a | 592 | static void pci_bridge_check_ranges(struct pci_bus *bus) |
1da177e4 LT |
593 | { |
594 | u16 io; | |
595 | u32 pmem; | |
596 | struct pci_dev *bridge = bus->self; | |
597 | struct resource *b_res; | |
598 | ||
599 | b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; | |
600 | b_res[1].flags |= IORESOURCE_MEM; | |
601 | ||
602 | pci_read_config_word(bridge, PCI_IO_BASE, &io); | |
603 | if (!io) { | |
604 | pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0); | |
605 | pci_read_config_word(bridge, PCI_IO_BASE, &io); | |
606 | pci_write_config_word(bridge, PCI_IO_BASE, 0x0); | |
607 | } | |
608 | if (io) | |
609 | b_res[0].flags |= IORESOURCE_IO; | |
610 | /* DECchip 21050 pass 2 errata: the bridge may miss an address | |
611 | disconnect boundary by one PCI data phase. | |
612 | Workaround: do not use prefetching on this device. */ | |
613 | if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) | |
614 | return; | |
615 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); | |
616 | if (!pmem) { | |
617 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, | |
618 | 0xfff0fff0); | |
619 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); | |
620 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); | |
621 | } | |
1f82de10 | 622 | if (pmem) { |
1da177e4 | 623 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; |
99586105 YL |
624 | if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == |
625 | PCI_PREF_RANGE_TYPE_64) { | |
1f82de10 | 626 | b_res[2].flags |= IORESOURCE_MEM_64; |
99586105 YL |
627 | b_res[2].flags |= PCI_PREF_RANGE_TYPE_64; |
628 | } | |
1f82de10 YL |
629 | } |
630 | ||
631 | /* double check if bridge does support 64 bit pref */ | |
632 | if (b_res[2].flags & IORESOURCE_MEM_64) { | |
633 | u32 mem_base_hi, tmp; | |
634 | pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
635 | &mem_base_hi); | |
636 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
637 | 0xffffffff); | |
638 | pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp); | |
639 | if (!tmp) | |
640 | b_res[2].flags &= ~IORESOURCE_MEM_64; | |
641 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
642 | mem_base_hi); | |
643 | } | |
1da177e4 LT |
644 | } |
645 | ||
646 | /* Helper function for sizing routines: find first available | |
647 | bus resource of a given type. Note: we intentionally skip | |
648 | the bus resources which have already been assigned (that is, | |
649 | have non-NULL parent resource). */ | |
96bde06a | 650 | static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type) |
1da177e4 LT |
651 | { |
652 | int i; | |
653 | struct resource *r; | |
654 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | | |
655 | IORESOURCE_PREFETCH; | |
656 | ||
89a74ecc | 657 | pci_bus_for_each_resource(bus, r, i) { |
299de034 IK |
658 | if (r == &ioport_resource || r == &iomem_resource) |
659 | continue; | |
55a10984 JB |
660 | if (r && (r->flags & type_mask) == type && !r->parent) |
661 | return r; | |
1da177e4 LT |
662 | } |
663 | return NULL; | |
664 | } | |
665 | ||
13583b16 RP |
666 | static resource_size_t calculate_iosize(resource_size_t size, |
667 | resource_size_t min_size, | |
668 | resource_size_t size1, | |
669 | resource_size_t old_size, | |
670 | resource_size_t align) | |
671 | { | |
672 | if (size < min_size) | |
673 | size = min_size; | |
674 | if (old_size == 1 ) | |
675 | old_size = 0; | |
676 | /* To be fixed in 2.5: we should have sort of HAVE_ISA | |
677 | flag in the struct pci_bus. */ | |
678 | #if defined(CONFIG_ISA) || defined(CONFIG_EISA) | |
679 | size = (size & 0xff) + ((size & ~0xffUL) << 2); | |
680 | #endif | |
681 | size = ALIGN(size + size1, align); | |
682 | if (size < old_size) | |
683 | size = old_size; | |
684 | return size; | |
685 | } | |
686 | ||
687 | static resource_size_t calculate_memsize(resource_size_t size, | |
688 | resource_size_t min_size, | |
689 | resource_size_t size1, | |
690 | resource_size_t old_size, | |
691 | resource_size_t align) | |
692 | { | |
693 | if (size < min_size) | |
694 | size = min_size; | |
695 | if (old_size == 1 ) | |
696 | old_size = 0; | |
697 | if (size < old_size) | |
698 | size = old_size; | |
699 | size = ALIGN(size + size1, align); | |
700 | return size; | |
701 | } | |
702 | ||
c8adf9a3 RP |
703 | /** |
704 | * pbus_size_io() - size the io window of a given bus | |
705 | * | |
706 | * @bus : the bus | |
707 | * @min_size : the minimum io window that must to be allocated | |
708 | * @add_size : additional optional io window | |
9e8bf93a | 709 | * @realloc_head : track the additional io window on this list |
c8adf9a3 RP |
710 | * |
711 | * Sizing the IO windows of the PCI-PCI bridge is trivial, | |
712 | * since these windows have 4K granularity and the IO ranges | |
713 | * of non-bridge PCI devices are limited to 256 bytes. | |
714 | * We must be careful with the ISA aliasing though. | |
715 | */ | |
716 | static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size, | |
bdc4abec | 717 | resource_size_t add_size, struct list_head *realloc_head) |
1da177e4 LT |
718 | { |
719 | struct pci_dev *dev; | |
720 | struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO); | |
c8adf9a3 | 721 | unsigned long size = 0, size0 = 0, size1 = 0; |
be768912 | 722 | resource_size_t children_add_size = 0; |
1da177e4 LT |
723 | |
724 | if (!b_res) | |
725 | return; | |
726 | ||
727 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
728 | int i; | |
729 | ||
730 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
731 | struct resource *r = &dev->resource[i]; | |
732 | unsigned long r_size; | |
733 | ||
734 | if (r->parent || !(r->flags & IORESOURCE_IO)) | |
735 | continue; | |
022edd86 | 736 | r_size = resource_size(r); |
1da177e4 LT |
737 | |
738 | if (r_size < 0x400) | |
739 | /* Might be re-aligned for ISA */ | |
740 | size += r_size; | |
741 | else | |
742 | size1 += r_size; | |
be768912 | 743 | |
9e8bf93a RP |
744 | if (realloc_head) |
745 | children_add_size += get_res_add_size(realloc_head, r); | |
1da177e4 LT |
746 | } |
747 | } | |
c8adf9a3 RP |
748 | size0 = calculate_iosize(size, min_size, size1, |
749 | resource_size(b_res), 4096); | |
be768912 YL |
750 | if (children_add_size > add_size) |
751 | add_size = children_add_size; | |
9e8bf93a | 752 | size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 : |
a4ac9fea | 753 | calculate_iosize(size, min_size, add_size + size1, |
13583b16 | 754 | resource_size(b_res), 4096); |
c8adf9a3 | 755 | if (!size0 && !size1) { |
865df576 BH |
756 | if (b_res->start || b_res->end) |
757 | dev_info(&bus->self->dev, "disabling bridge window " | |
758 | "%pR to [bus %02x-%02x] (unused)\n", b_res, | |
759 | bus->secondary, bus->subordinate); | |
1da177e4 LT |
760 | b_res->flags = 0; |
761 | return; | |
762 | } | |
763 | /* Alignment of the IO window is always 4K */ | |
764 | b_res->start = 4096; | |
c8adf9a3 | 765 | b_res->end = b_res->start + size0 - 1; |
88452565 | 766 | b_res->flags |= IORESOURCE_STARTALIGN; |
9e8bf93a RP |
767 | if (size1 > size0 && realloc_head) |
768 | add_to_list(realloc_head, bus->self, b_res, size1-size0, 4096); | |
1da177e4 LT |
769 | } |
770 | ||
c8adf9a3 RP |
771 | /** |
772 | * pbus_size_mem() - size the memory window of a given bus | |
773 | * | |
774 | * @bus : the bus | |
775 | * @min_size : the minimum memory window that must to be allocated | |
776 | * @add_size : additional optional memory window | |
9e8bf93a | 777 | * @realloc_head : track the additional memory window on this list |
c8adf9a3 RP |
778 | * |
779 | * Calculate the size of the bus and minimal alignment which | |
780 | * guarantees that all child resources fit in this size. | |
781 | */ | |
28760489 | 782 | static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, |
c8adf9a3 RP |
783 | unsigned long type, resource_size_t min_size, |
784 | resource_size_t add_size, | |
bdc4abec | 785 | struct list_head *realloc_head) |
1da177e4 LT |
786 | { |
787 | struct pci_dev *dev; | |
c8adf9a3 | 788 | resource_size_t min_align, align, size, size0, size1; |
c40a22e0 | 789 | resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */ |
1da177e4 LT |
790 | int order, max_order; |
791 | struct resource *b_res = find_free_bus_resource(bus, type); | |
1f82de10 | 792 | unsigned int mem64_mask = 0; |
be768912 | 793 | resource_size_t children_add_size = 0; |
1da177e4 LT |
794 | |
795 | if (!b_res) | |
796 | return 0; | |
797 | ||
798 | memset(aligns, 0, sizeof(aligns)); | |
799 | max_order = 0; | |
800 | size = 0; | |
801 | ||
1f82de10 YL |
802 | mem64_mask = b_res->flags & IORESOURCE_MEM_64; |
803 | b_res->flags &= ~IORESOURCE_MEM_64; | |
804 | ||
1da177e4 LT |
805 | list_for_each_entry(dev, &bus->devices, bus_list) { |
806 | int i; | |
1f82de10 | 807 | |
1da177e4 LT |
808 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { |
809 | struct resource *r = &dev->resource[i]; | |
c40a22e0 | 810 | resource_size_t r_size; |
1da177e4 LT |
811 | |
812 | if (r->parent || (r->flags & mask) != type) | |
813 | continue; | |
022edd86 | 814 | r_size = resource_size(r); |
2aceefcb YL |
815 | #ifdef CONFIG_PCI_IOV |
816 | /* put SRIOV requested res to the optional list */ | |
9e8bf93a | 817 | if (realloc_head && i >= PCI_IOV_RESOURCES && |
2aceefcb YL |
818 | i <= PCI_IOV_RESOURCE_END) { |
819 | r->end = r->start - 1; | |
9e8bf93a | 820 | add_to_list(realloc_head, dev, r, r_size, 0/* dont' care */); |
2aceefcb YL |
821 | children_add_size += r_size; |
822 | continue; | |
823 | } | |
824 | #endif | |
1da177e4 | 825 | /* For bridges size != alignment */ |
6faf17f6 | 826 | align = pci_resource_alignment(dev, r); |
1da177e4 LT |
827 | order = __ffs(align) - 20; |
828 | if (order > 11) { | |
865df576 BH |
829 | dev_warn(&dev->dev, "disabling BAR %d: %pR " |
830 | "(bad alignment %#llx)\n", i, r, | |
831 | (unsigned long long) align); | |
1da177e4 LT |
832 | r->flags = 0; |
833 | continue; | |
834 | } | |
835 | size += r_size; | |
836 | if (order < 0) | |
837 | order = 0; | |
838 | /* Exclude ranges with size > align from | |
839 | calculation of the alignment. */ | |
840 | if (r_size == align) | |
841 | aligns[order] += align; | |
842 | if (order > max_order) | |
843 | max_order = order; | |
1f82de10 | 844 | mem64_mask &= r->flags & IORESOURCE_MEM_64; |
be768912 | 845 | |
9e8bf93a RP |
846 | if (realloc_head) |
847 | children_add_size += get_res_add_size(realloc_head, r); | |
1da177e4 LT |
848 | } |
849 | } | |
1da177e4 LT |
850 | align = 0; |
851 | min_align = 0; | |
852 | for (order = 0; order <= max_order; order++) { | |
8308c54d JF |
853 | resource_size_t align1 = 1; |
854 | ||
855 | align1 <<= (order + 20); | |
856 | ||
1da177e4 LT |
857 | if (!align) |
858 | min_align = align1; | |
6f6f8c2f | 859 | else if (ALIGN(align + min_align, min_align) < align1) |
1da177e4 LT |
860 | min_align = align1 >> 1; |
861 | align += aligns[order]; | |
862 | } | |
b42282e5 | 863 | size0 = calculate_memsize(size, min_size, 0, resource_size(b_res), min_align); |
be768912 YL |
864 | if (children_add_size > add_size) |
865 | add_size = children_add_size; | |
9e8bf93a | 866 | size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 : |
a4ac9fea | 867 | calculate_memsize(size, min_size, add_size, |
b42282e5 | 868 | resource_size(b_res), min_align); |
c8adf9a3 | 869 | if (!size0 && !size1) { |
865df576 BH |
870 | if (b_res->start || b_res->end) |
871 | dev_info(&bus->self->dev, "disabling bridge window " | |
872 | "%pR to [bus %02x-%02x] (unused)\n", b_res, | |
873 | bus->secondary, bus->subordinate); | |
1da177e4 LT |
874 | b_res->flags = 0; |
875 | return 1; | |
876 | } | |
877 | b_res->start = min_align; | |
c8adf9a3 RP |
878 | b_res->end = size0 + min_align - 1; |
879 | b_res->flags |= IORESOURCE_STARTALIGN | mem64_mask; | |
9e8bf93a RP |
880 | if (size1 > size0 && realloc_head) |
881 | add_to_list(realloc_head, bus->self, b_res, size1-size0, min_align); | |
1da177e4 LT |
882 | return 1; |
883 | } | |
884 | ||
0a2daa1c RP |
885 | unsigned long pci_cardbus_resource_alignment(struct resource *res) |
886 | { | |
887 | if (res->flags & IORESOURCE_IO) | |
888 | return pci_cardbus_io_size; | |
889 | if (res->flags & IORESOURCE_MEM) | |
890 | return pci_cardbus_mem_size; | |
891 | return 0; | |
892 | } | |
893 | ||
894 | static void pci_bus_size_cardbus(struct pci_bus *bus, | |
bdc4abec | 895 | struct list_head *realloc_head) |
1da177e4 LT |
896 | { |
897 | struct pci_dev *bridge = bus->self; | |
898 | struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; | |
899 | u16 ctrl; | |
900 | ||
901 | /* | |
902 | * Reserve some resources for CardBus. We reserve | |
903 | * a fixed amount of bus space for CardBus bridges. | |
904 | */ | |
934b7024 | 905 | b_res[0].start = 0; |
934b7024 | 906 | b_res[0].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN; |
9e8bf93a RP |
907 | if (realloc_head) |
908 | add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size, 0 /* dont care */); | |
1da177e4 | 909 | |
934b7024 | 910 | b_res[1].start = 0; |
934b7024 | 911 | b_res[1].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN; |
9e8bf93a RP |
912 | if (realloc_head) |
913 | add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size, 0 /* dont care */); | |
1da177e4 LT |
914 | |
915 | /* | |
916 | * Check whether prefetchable memory is supported | |
917 | * by this bridge. | |
918 | */ | |
919 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
920 | if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) { | |
921 | ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; | |
922 | pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); | |
923 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
924 | } | |
925 | ||
926 | /* | |
927 | * If we have prefetchable memory support, allocate | |
928 | * two regions. Otherwise, allocate one region of | |
929 | * twice the size. | |
930 | */ | |
931 | if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) { | |
934b7024 | 932 | b_res[2].start = 0; |
934b7024 | 933 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_SIZEALIGN; |
9e8bf93a RP |
934 | if (realloc_head) |
935 | add_to_list(realloc_head, bridge, b_res+2, pci_cardbus_mem_size, 0 /* dont care */); | |
1da177e4 | 936 | |
934b7024 | 937 | b_res[3].start = 0; |
934b7024 | 938 | b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN; |
9e8bf93a RP |
939 | if (realloc_head) |
940 | add_to_list(realloc_head, bridge, b_res+3, pci_cardbus_mem_size, 0 /* dont care */); | |
1da177e4 | 941 | } else { |
934b7024 | 942 | b_res[3].start = 0; |
934b7024 | 943 | b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN; |
9e8bf93a RP |
944 | if (realloc_head) |
945 | add_to_list(realloc_head, bridge, b_res+3, pci_cardbus_mem_size * 2, 0 /* dont care */); | |
1da177e4 | 946 | } |
0a2daa1c RP |
947 | |
948 | /* set the size of the resource to zero, so that the resource does not | |
949 | * get assigned during required-resource allocation cycle but gets assigned | |
950 | * during the optional-resource allocation cycle. | |
951 | */ | |
952 | b_res[0].start = b_res[1].start = b_res[2].start = b_res[3].start = 1; | |
953 | b_res[0].end = b_res[1].end = b_res[2].end = b_res[3].end = 0; | |
1da177e4 LT |
954 | } |
955 | ||
c8adf9a3 | 956 | void __ref __pci_bus_size_bridges(struct pci_bus *bus, |
bdc4abec | 957 | struct list_head *realloc_head) |
1da177e4 LT |
958 | { |
959 | struct pci_dev *dev; | |
960 | unsigned long mask, prefmask; | |
c8adf9a3 | 961 | resource_size_t additional_mem_size = 0, additional_io_size = 0; |
1da177e4 LT |
962 | |
963 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
964 | struct pci_bus *b = dev->subordinate; | |
965 | if (!b) | |
966 | continue; | |
967 | ||
968 | switch (dev->class >> 8) { | |
969 | case PCI_CLASS_BRIDGE_CARDBUS: | |
9e8bf93a | 970 | pci_bus_size_cardbus(b, realloc_head); |
1da177e4 LT |
971 | break; |
972 | ||
973 | case PCI_CLASS_BRIDGE_PCI: | |
974 | default: | |
9e8bf93a | 975 | __pci_bus_size_bridges(b, realloc_head); |
1da177e4 LT |
976 | break; |
977 | } | |
978 | } | |
979 | ||
980 | /* The root bus? */ | |
981 | if (!bus->self) | |
982 | return; | |
983 | ||
984 | switch (bus->self->class >> 8) { | |
985 | case PCI_CLASS_BRIDGE_CARDBUS: | |
986 | /* don't size cardbuses yet. */ | |
987 | break; | |
988 | ||
989 | case PCI_CLASS_BRIDGE_PCI: | |
990 | pci_bridge_check_ranges(bus); | |
28760489 | 991 | if (bus->self->is_hotplug_bridge) { |
c8adf9a3 RP |
992 | additional_io_size = pci_hotplug_io_size; |
993 | additional_mem_size = pci_hotplug_mem_size; | |
28760489 | 994 | } |
c8adf9a3 RP |
995 | /* |
996 | * Follow thru | |
997 | */ | |
1da177e4 | 998 | default: |
19aa7ee4 YL |
999 | pbus_size_io(bus, realloc_head ? 0 : additional_io_size, |
1000 | additional_io_size, realloc_head); | |
1da177e4 LT |
1001 | /* If the bridge supports prefetchable range, size it |
1002 | separately. If it doesn't, or its prefetchable window | |
1003 | has already been allocated by arch code, try | |
1004 | non-prefetchable range for both types of PCI memory | |
1005 | resources. */ | |
1006 | mask = IORESOURCE_MEM; | |
1007 | prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
19aa7ee4 YL |
1008 | if (pbus_size_mem(bus, prefmask, prefmask, |
1009 | realloc_head ? 0 : additional_mem_size, | |
1010 | additional_mem_size, realloc_head)) | |
1da177e4 | 1011 | mask = prefmask; /* Success, size non-prefetch only. */ |
28760489 | 1012 | else |
c8adf9a3 | 1013 | additional_mem_size += additional_mem_size; |
19aa7ee4 YL |
1014 | pbus_size_mem(bus, mask, IORESOURCE_MEM, |
1015 | realloc_head ? 0 : additional_mem_size, | |
1016 | additional_mem_size, realloc_head); | |
1da177e4 LT |
1017 | break; |
1018 | } | |
1019 | } | |
c8adf9a3 RP |
1020 | |
1021 | void __ref pci_bus_size_bridges(struct pci_bus *bus) | |
1022 | { | |
1023 | __pci_bus_size_bridges(bus, NULL); | |
1024 | } | |
1da177e4 LT |
1025 | EXPORT_SYMBOL(pci_bus_size_bridges); |
1026 | ||
568ddef8 | 1027 | static void __ref __pci_bus_assign_resources(const struct pci_bus *bus, |
bdc4abec YL |
1028 | struct list_head *realloc_head, |
1029 | struct list_head *fail_head) | |
1da177e4 LT |
1030 | { |
1031 | struct pci_bus *b; | |
1032 | struct pci_dev *dev; | |
1033 | ||
9e8bf93a | 1034 | pbus_assign_resources_sorted(bus, realloc_head, fail_head); |
1da177e4 | 1035 | |
1da177e4 LT |
1036 | list_for_each_entry(dev, &bus->devices, bus_list) { |
1037 | b = dev->subordinate; | |
1038 | if (!b) | |
1039 | continue; | |
1040 | ||
9e8bf93a | 1041 | __pci_bus_assign_resources(b, realloc_head, fail_head); |
1da177e4 LT |
1042 | |
1043 | switch (dev->class >> 8) { | |
1044 | case PCI_CLASS_BRIDGE_PCI: | |
6841ec68 YL |
1045 | if (!pci_is_enabled(dev)) |
1046 | pci_setup_bridge(b); | |
1da177e4 LT |
1047 | break; |
1048 | ||
1049 | case PCI_CLASS_BRIDGE_CARDBUS: | |
1050 | pci_setup_cardbus(b); | |
1051 | break; | |
1052 | ||
1053 | default: | |
80ccba11 BH |
1054 | dev_info(&dev->dev, "not setting up bridge for bus " |
1055 | "%04x:%02x\n", pci_domain_nr(b), b->number); | |
1da177e4 LT |
1056 | break; |
1057 | } | |
1058 | } | |
1059 | } | |
568ddef8 YL |
1060 | |
1061 | void __ref pci_bus_assign_resources(const struct pci_bus *bus) | |
1062 | { | |
c8adf9a3 | 1063 | __pci_bus_assign_resources(bus, NULL, NULL); |
568ddef8 | 1064 | } |
1da177e4 LT |
1065 | EXPORT_SYMBOL(pci_bus_assign_resources); |
1066 | ||
6841ec68 | 1067 | static void __ref __pci_bridge_assign_resources(const struct pci_dev *bridge, |
bdc4abec YL |
1068 | struct list_head *add_head, |
1069 | struct list_head *fail_head) | |
6841ec68 YL |
1070 | { |
1071 | struct pci_bus *b; | |
1072 | ||
8424d759 YL |
1073 | pdev_assign_resources_sorted((struct pci_dev *)bridge, |
1074 | add_head, fail_head); | |
6841ec68 YL |
1075 | |
1076 | b = bridge->subordinate; | |
1077 | if (!b) | |
1078 | return; | |
1079 | ||
8424d759 | 1080 | __pci_bus_assign_resources(b, add_head, fail_head); |
6841ec68 YL |
1081 | |
1082 | switch (bridge->class >> 8) { | |
1083 | case PCI_CLASS_BRIDGE_PCI: | |
1084 | pci_setup_bridge(b); | |
1085 | break; | |
1086 | ||
1087 | case PCI_CLASS_BRIDGE_CARDBUS: | |
1088 | pci_setup_cardbus(b); | |
1089 | break; | |
1090 | ||
1091 | default: | |
1092 | dev_info(&bridge->dev, "not setting up bridge for bus " | |
1093 | "%04x:%02x\n", pci_domain_nr(b), b->number); | |
1094 | break; | |
1095 | } | |
1096 | } | |
5009b460 YL |
1097 | static void pci_bridge_release_resources(struct pci_bus *bus, |
1098 | unsigned long type) | |
1099 | { | |
1100 | int idx; | |
1101 | bool changed = false; | |
1102 | struct pci_dev *dev; | |
1103 | struct resource *r; | |
1104 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | | |
1105 | IORESOURCE_PREFETCH; | |
1106 | ||
1107 | dev = bus->self; | |
1108 | for (idx = PCI_BRIDGE_RESOURCES; idx <= PCI_BRIDGE_RESOURCE_END; | |
1109 | idx++) { | |
1110 | r = &dev->resource[idx]; | |
1111 | if ((r->flags & type_mask) != type) | |
1112 | continue; | |
1113 | if (!r->parent) | |
1114 | continue; | |
1115 | /* | |
1116 | * if there are children under that, we should release them | |
1117 | * all | |
1118 | */ | |
1119 | release_child_resources(r); | |
1120 | if (!release_resource(r)) { | |
1121 | dev_printk(KERN_DEBUG, &dev->dev, | |
1122 | "resource %d %pR released\n", idx, r); | |
1123 | /* keep the old size */ | |
1124 | r->end = resource_size(r) - 1; | |
1125 | r->start = 0; | |
1126 | r->flags = 0; | |
1127 | changed = true; | |
1128 | } | |
1129 | } | |
1130 | ||
1131 | if (changed) { | |
1132 | /* avoiding touch the one without PREF */ | |
1133 | if (type & IORESOURCE_PREFETCH) | |
1134 | type = IORESOURCE_PREFETCH; | |
1135 | __pci_setup_bridge(bus, type); | |
1136 | } | |
1137 | } | |
1138 | ||
1139 | enum release_type { | |
1140 | leaf_only, | |
1141 | whole_subtree, | |
1142 | }; | |
1143 | /* | |
1144 | * try to release pci bridge resources that is from leaf bridge, | |
1145 | * so we can allocate big new one later | |
1146 | */ | |
1147 | static void __ref pci_bus_release_bridge_resources(struct pci_bus *bus, | |
1148 | unsigned long type, | |
1149 | enum release_type rel_type) | |
1150 | { | |
1151 | struct pci_dev *dev; | |
1152 | bool is_leaf_bridge = true; | |
1153 | ||
1154 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1155 | struct pci_bus *b = dev->subordinate; | |
1156 | if (!b) | |
1157 | continue; | |
1158 | ||
1159 | is_leaf_bridge = false; | |
1160 | ||
1161 | if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) | |
1162 | continue; | |
1163 | ||
1164 | if (rel_type == whole_subtree) | |
1165 | pci_bus_release_bridge_resources(b, type, | |
1166 | whole_subtree); | |
1167 | } | |
1168 | ||
1169 | if (pci_is_root_bus(bus)) | |
1170 | return; | |
1171 | ||
1172 | if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI) | |
1173 | return; | |
1174 | ||
1175 | if ((rel_type == whole_subtree) || is_leaf_bridge) | |
1176 | pci_bridge_release_resources(bus, type); | |
1177 | } | |
1178 | ||
76fbc263 YL |
1179 | static void pci_bus_dump_res(struct pci_bus *bus) |
1180 | { | |
89a74ecc BH |
1181 | struct resource *res; |
1182 | int i; | |
7c9342b8 | 1183 | |
89a74ecc | 1184 | pci_bus_for_each_resource(bus, res, i) { |
7c9342b8 | 1185 | if (!res || !res->end || !res->flags) |
76fbc263 YL |
1186 | continue; |
1187 | ||
c7dabef8 | 1188 | dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res); |
76fbc263 YL |
1189 | } |
1190 | } | |
1191 | ||
1192 | static void pci_bus_dump_resources(struct pci_bus *bus) | |
1193 | { | |
1194 | struct pci_bus *b; | |
1195 | struct pci_dev *dev; | |
1196 | ||
1197 | ||
1198 | pci_bus_dump_res(bus); | |
1199 | ||
1200 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1201 | b = dev->subordinate; | |
1202 | if (!b) | |
1203 | continue; | |
1204 | ||
1205 | pci_bus_dump_resources(b); | |
1206 | } | |
1207 | } | |
1208 | ||
da7822e5 YL |
1209 | static int __init pci_bus_get_depth(struct pci_bus *bus) |
1210 | { | |
1211 | int depth = 0; | |
1212 | struct pci_dev *dev; | |
1213 | ||
1214 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1215 | int ret; | |
1216 | struct pci_bus *b = dev->subordinate; | |
1217 | if (!b) | |
1218 | continue; | |
1219 | ||
1220 | ret = pci_bus_get_depth(b); | |
1221 | if (ret + 1 > depth) | |
1222 | depth = ret + 1; | |
1223 | } | |
1224 | ||
1225 | return depth; | |
1226 | } | |
1227 | static int __init pci_get_max_depth(void) | |
1228 | { | |
1229 | int depth = 0; | |
1230 | struct pci_bus *bus; | |
1231 | ||
1232 | list_for_each_entry(bus, &pci_root_buses, node) { | |
1233 | int ret; | |
1234 | ||
1235 | ret = pci_bus_get_depth(bus); | |
1236 | if (ret > depth) | |
1237 | depth = ret; | |
1238 | } | |
1239 | ||
1240 | return depth; | |
1241 | } | |
1242 | ||
f483d392 | 1243 | |
da7822e5 YL |
1244 | /* |
1245 | * first try will not touch pci bridge res | |
1246 | * second and later try will clear small leaf bridge res | |
1247 | * will stop till to the max deepth if can not find good one | |
1248 | */ | |
1da177e4 LT |
1249 | void __init |
1250 | pci_assign_unassigned_resources(void) | |
1251 | { | |
1252 | struct pci_bus *bus; | |
bdc4abec | 1253 | LIST_HEAD(realloc_head); /* list of resources that |
c8adf9a3 | 1254 | want additional resources */ |
bdc4abec | 1255 | struct list_head *add_list = NULL; |
da7822e5 YL |
1256 | int tried_times = 0; |
1257 | enum release_type rel_type = leaf_only; | |
bdc4abec YL |
1258 | LIST_HEAD(fail_head); |
1259 | struct pci_dev_resource_x *dev_res_x; | |
da7822e5 YL |
1260 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | |
1261 | IORESOURCE_PREFETCH; | |
1262 | unsigned long failed_type; | |
19aa7ee4 | 1263 | int pci_try_num = 1; |
da7822e5 | 1264 | |
19aa7ee4 YL |
1265 | /* don't realloc if asked to do so */ |
1266 | if (pci_realloc_enabled()) { | |
1267 | int max_depth = pci_get_max_depth(); | |
1268 | ||
1269 | pci_try_num = max_depth + 1; | |
1270 | printk(KERN_DEBUG "PCI: max bus depth: %d pci_try_num: %d\n", | |
1271 | max_depth, pci_try_num); | |
1272 | } | |
da7822e5 YL |
1273 | |
1274 | again: | |
19aa7ee4 YL |
1275 | /* |
1276 | * last try will use add_list, otherwise will try good to have as | |
1277 | * must have, so can realloc parent bridge resource | |
1278 | */ | |
1279 | if (tried_times + 1 == pci_try_num) | |
bdc4abec | 1280 | add_list = &realloc_head; |
1da177e4 LT |
1281 | /* Depth first, calculate sizes and alignments of all |
1282 | subordinate buses. */ | |
da7822e5 | 1283 | list_for_each_entry(bus, &pci_root_buses, node) |
19aa7ee4 | 1284 | __pci_bus_size_bridges(bus, add_list); |
c8adf9a3 | 1285 | |
1da177e4 | 1286 | /* Depth last, allocate resources and update the hardware. */ |
da7822e5 | 1287 | list_for_each_entry(bus, &pci_root_buses, node) |
bdc4abec | 1288 | __pci_bus_assign_resources(bus, add_list, &fail_head); |
19aa7ee4 | 1289 | if (add_list) |
bdc4abec | 1290 | BUG_ON(!list_empty(add_list)); |
da7822e5 YL |
1291 | tried_times++; |
1292 | ||
1293 | /* any device complain? */ | |
bdc4abec | 1294 | if (list_empty(&fail_head)) |
da7822e5 | 1295 | goto enable_and_dump; |
f483d392 | 1296 | |
da7822e5 | 1297 | failed_type = 0; |
bdc4abec YL |
1298 | list_for_each_entry(dev_res_x, &fail_head, list) |
1299 | failed_type |= dev_res_x->flags; | |
1300 | ||
da7822e5 YL |
1301 | /* |
1302 | * io port are tight, don't try extra | |
1303 | * or if reach the limit, don't want to try more | |
1304 | */ | |
1305 | failed_type &= type_mask; | |
1306 | if ((failed_type == IORESOURCE_IO) || (tried_times >= pci_try_num)) { | |
bdc4abec | 1307 | free_list(pci_dev_resource_x, &fail_head); |
da7822e5 YL |
1308 | goto enable_and_dump; |
1309 | } | |
1310 | ||
1311 | printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n", | |
1312 | tried_times + 1); | |
1313 | ||
1314 | /* third times and later will not check if it is leaf */ | |
1315 | if ((tried_times + 1) > 2) | |
1316 | rel_type = whole_subtree; | |
1317 | ||
1318 | /* | |
1319 | * Try to release leaf bridge's resources that doesn't fit resource of | |
1320 | * child device under that bridge | |
1321 | */ | |
bdc4abec YL |
1322 | list_for_each_entry(dev_res_x, &fail_head, list) { |
1323 | bus = dev_res_x->dev->bus; | |
1324 | pci_bus_release_bridge_resources(bus, | |
1325 | dev_res_x->flags & type_mask, | |
1326 | rel_type); | |
da7822e5 YL |
1327 | } |
1328 | /* restore size and flags */ | |
bdc4abec YL |
1329 | list_for_each_entry(dev_res_x, &fail_head, list) { |
1330 | struct resource *res = dev_res_x->res; | |
da7822e5 | 1331 | |
bdc4abec YL |
1332 | res->start = dev_res_x->start; |
1333 | res->end = dev_res_x->end; | |
1334 | res->flags = dev_res_x->flags; | |
1335 | if (dev_res_x->dev->subordinate) | |
da7822e5 | 1336 | res->flags = 0; |
da7822e5 | 1337 | } |
bdc4abec | 1338 | free_list(pci_dev_resource_x, &fail_head); |
da7822e5 YL |
1339 | |
1340 | goto again; | |
1341 | ||
1342 | enable_and_dump: | |
1343 | /* Depth last, update the hardware. */ | |
1344 | list_for_each_entry(bus, &pci_root_buses, node) | |
1345 | pci_enable_bridges(bus); | |
76fbc263 YL |
1346 | |
1347 | /* dump the resource on buses */ | |
da7822e5 | 1348 | list_for_each_entry(bus, &pci_root_buses, node) |
76fbc263 | 1349 | pci_bus_dump_resources(bus); |
1da177e4 | 1350 | } |
6841ec68 YL |
1351 | |
1352 | void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge) | |
1353 | { | |
1354 | struct pci_bus *parent = bridge->subordinate; | |
bdc4abec | 1355 | LIST_HEAD(add_list); /* list of resources that |
8424d759 | 1356 | want additional resources */ |
32180e40 | 1357 | int tried_times = 0; |
bdc4abec YL |
1358 | LIST_HEAD(fail_head); |
1359 | struct pci_dev_resource_x *dev_res_x; | |
6841ec68 | 1360 | int retval; |
32180e40 YL |
1361 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | |
1362 | IORESOURCE_PREFETCH; | |
1363 | ||
32180e40 | 1364 | again: |
8424d759 | 1365 | __pci_bus_size_bridges(parent, &add_list); |
bdc4abec YL |
1366 | __pci_bridge_assign_resources(bridge, &add_list, &fail_head); |
1367 | BUG_ON(!list_empty(&add_list)); | |
32180e40 YL |
1368 | tried_times++; |
1369 | ||
bdc4abec | 1370 | if (list_empty(&fail_head)) |
3f579c34 | 1371 | goto enable_all; |
32180e40 YL |
1372 | |
1373 | if (tried_times >= 2) { | |
1374 | /* still fail, don't need to try more */ | |
bdc4abec | 1375 | free_list(pci_dev_resource_x, &fail_head); |
3f579c34 | 1376 | goto enable_all; |
32180e40 YL |
1377 | } |
1378 | ||
1379 | printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n", | |
1380 | tried_times + 1); | |
1381 | ||
1382 | /* | |
1383 | * Try to release leaf bridge's resources that doesn't fit resource of | |
1384 | * child device under that bridge | |
1385 | */ | |
bdc4abec YL |
1386 | list_for_each_entry(dev_res_x, &fail_head, list) { |
1387 | struct pci_bus *bus = dev_res_x->dev->bus; | |
1388 | unsigned long flags = dev_res_x->flags; | |
32180e40 YL |
1389 | |
1390 | pci_bus_release_bridge_resources(bus, flags & type_mask, | |
1391 | whole_subtree); | |
32180e40 YL |
1392 | } |
1393 | /* restore size and flags */ | |
bdc4abec YL |
1394 | list_for_each_entry(dev_res_x, &fail_head, list) { |
1395 | struct resource *res = dev_res_x->res; | |
32180e40 | 1396 | |
bdc4abec YL |
1397 | res->start = dev_res_x->start; |
1398 | res->end = dev_res_x->end; | |
1399 | res->flags = dev_res_x->flags; | |
1400 | if (dev_res_x->dev->subordinate) | |
32180e40 | 1401 | res->flags = 0; |
32180e40 | 1402 | } |
bdc4abec | 1403 | free_list(pci_dev_resource_x, &fail_head); |
32180e40 YL |
1404 | |
1405 | goto again; | |
3f579c34 YL |
1406 | |
1407 | enable_all: | |
1408 | retval = pci_reenable_device(bridge); | |
1409 | pci_set_master(bridge); | |
1410 | pci_enable_bridges(parent); | |
6841ec68 YL |
1411 | } |
1412 | EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources); | |
9b03088f YL |
1413 | |
1414 | #ifdef CONFIG_HOTPLUG | |
1415 | /** | |
1416 | * pci_rescan_bus - scan a PCI bus for devices. | |
1417 | * @bus: PCI bus to scan | |
1418 | * | |
1419 | * Scan a PCI bus and child buses for new devices, adds them, | |
1420 | * and enables them. | |
1421 | * | |
1422 | * Returns the max number of subordinate bus discovered. | |
1423 | */ | |
1424 | unsigned int __ref pci_rescan_bus(struct pci_bus *bus) | |
1425 | { | |
1426 | unsigned int max; | |
1427 | struct pci_dev *dev; | |
bdc4abec | 1428 | LIST_HEAD(add_list); /* list of resources that |
9b03088f YL |
1429 | want additional resources */ |
1430 | ||
1431 | max = pci_scan_child_bus(bus); | |
1432 | ||
9b03088f YL |
1433 | down_read(&pci_bus_sem); |
1434 | list_for_each_entry(dev, &bus->devices, bus_list) | |
1435 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || | |
1436 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) | |
1437 | if (dev->subordinate) | |
1438 | __pci_bus_size_bridges(dev->subordinate, | |
1439 | &add_list); | |
1440 | up_read(&pci_bus_sem); | |
1441 | __pci_bus_assign_resources(bus, &add_list, NULL); | |
bdc4abec | 1442 | BUG_ON(!list_empty(&add_list)); |
9b03088f YL |
1443 | |
1444 | pci_enable_bridges(bus); | |
1445 | pci_bus_add_devices(bus); | |
1446 | ||
1447 | return max; | |
1448 | } | |
1449 | EXPORT_SYMBOL_GPL(pci_rescan_bus); | |
1450 | #endif |