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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * drivers/pci/setup-bus.c | |
3 | * | |
4 | * Extruded from code written by | |
5 | * Dave Rusling (david.rusling@reo.mts.dec.com) | |
6 | * David Mosberger (davidm@cs.arizona.edu) | |
7 | * David Miller (davem@redhat.com) | |
8 | * | |
9 | * Support routines for initializing a PCI subsystem. | |
10 | */ | |
11 | ||
12 | /* | |
13 | * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> | |
14 | * PCI-PCI bridges cleanup, sorted resource allocation. | |
15 | * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru> | |
16 | * Converted to allocation in 3 passes, which gives | |
17 | * tighter packing. Prefetchable range support. | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/pci.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/ioport.h> | |
26 | #include <linux/cache.h> | |
27 | #include <linux/slab.h> | |
6faf17f6 | 28 | #include "pci.h" |
1da177e4 | 29 | |
844393f4 | 30 | unsigned int pci_flags; |
47087700 | 31 | |
bdc4abec YL |
32 | struct pci_dev_resource { |
33 | struct list_head list; | |
2934a0de YL |
34 | struct resource *res; |
35 | struct pci_dev *dev; | |
568ddef8 YL |
36 | resource_size_t start; |
37 | resource_size_t end; | |
c8adf9a3 | 38 | resource_size_t add_size; |
2bbc6942 | 39 | resource_size_t min_align; |
568ddef8 YL |
40 | unsigned long flags; |
41 | }; | |
42 | ||
bffc56d4 YL |
43 | static void free_list(struct list_head *head) |
44 | { | |
45 | struct pci_dev_resource *dev_res, *tmp; | |
46 | ||
47 | list_for_each_entry_safe(dev_res, tmp, head, list) { | |
48 | list_del(&dev_res->list); | |
49 | kfree(dev_res); | |
50 | } | |
51 | } | |
094732a5 | 52 | |
c8adf9a3 RP |
53 | /** |
54 | * add_to_list() - add a new resource tracker to the list | |
55 | * @head: Head of the list | |
56 | * @dev: device corresponding to which the resource | |
57 | * belongs | |
58 | * @res: The resource to be tracked | |
59 | * @add_size: additional size to be optionally added | |
60 | * to the resource | |
61 | */ | |
bdc4abec | 62 | static int add_to_list(struct list_head *head, |
c8adf9a3 | 63 | struct pci_dev *dev, struct resource *res, |
2bbc6942 | 64 | resource_size_t add_size, resource_size_t min_align) |
568ddef8 | 65 | { |
764242a0 | 66 | struct pci_dev_resource *tmp; |
568ddef8 | 67 | |
bdc4abec | 68 | tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); |
568ddef8 | 69 | if (!tmp) { |
3c78bc61 | 70 | pr_warn("add_to_list: kmalloc() failed!\n"); |
ef62dfef | 71 | return -ENOMEM; |
568ddef8 YL |
72 | } |
73 | ||
568ddef8 YL |
74 | tmp->res = res; |
75 | tmp->dev = dev; | |
76 | tmp->start = res->start; | |
77 | tmp->end = res->end; | |
78 | tmp->flags = res->flags; | |
c8adf9a3 | 79 | tmp->add_size = add_size; |
2bbc6942 | 80 | tmp->min_align = min_align; |
bdc4abec YL |
81 | |
82 | list_add(&tmp->list, head); | |
ef62dfef YL |
83 | |
84 | return 0; | |
568ddef8 YL |
85 | } |
86 | ||
b9b0bba9 | 87 | static void remove_from_list(struct list_head *head, |
3e6e0d80 YL |
88 | struct resource *res) |
89 | { | |
b9b0bba9 | 90 | struct pci_dev_resource *dev_res, *tmp; |
3e6e0d80 | 91 | |
b9b0bba9 YL |
92 | list_for_each_entry_safe(dev_res, tmp, head, list) { |
93 | if (dev_res->res == res) { | |
94 | list_del(&dev_res->list); | |
95 | kfree(dev_res); | |
bdc4abec | 96 | break; |
3e6e0d80 | 97 | } |
3e6e0d80 YL |
98 | } |
99 | } | |
100 | ||
d74b9027 WY |
101 | static struct pci_dev_resource *res_to_dev_res(struct list_head *head, |
102 | struct resource *res) | |
1c372353 | 103 | { |
b9b0bba9 | 104 | struct pci_dev_resource *dev_res; |
bdc4abec | 105 | |
b9b0bba9 YL |
106 | list_for_each_entry(dev_res, head, list) { |
107 | if (dev_res->res == res) { | |
b592443d YL |
108 | int idx = res - &dev_res->dev->resource[0]; |
109 | ||
b9b0bba9 | 110 | dev_printk(KERN_DEBUG, &dev_res->dev->dev, |
d74b9027 | 111 | "res[%d]=%pR res_to_dev_res add_size %llx min_align %llx\n", |
b592443d | 112 | idx, dev_res->res, |
d74b9027 WY |
113 | (unsigned long long)dev_res->add_size, |
114 | (unsigned long long)dev_res->min_align); | |
b592443d | 115 | |
d74b9027 | 116 | return dev_res; |
bdc4abec | 117 | } |
3e6e0d80 | 118 | } |
1c372353 | 119 | |
d74b9027 | 120 | return NULL; |
1c372353 YL |
121 | } |
122 | ||
d74b9027 WY |
123 | static resource_size_t get_res_add_size(struct list_head *head, |
124 | struct resource *res) | |
125 | { | |
126 | struct pci_dev_resource *dev_res; | |
127 | ||
128 | dev_res = res_to_dev_res(head, res); | |
129 | return dev_res ? dev_res->add_size : 0; | |
130 | } | |
131 | ||
132 | static resource_size_t get_res_add_align(struct list_head *head, | |
133 | struct resource *res) | |
134 | { | |
135 | struct pci_dev_resource *dev_res; | |
136 | ||
137 | dev_res = res_to_dev_res(head, res); | |
138 | return dev_res ? dev_res->min_align : 0; | |
139 | } | |
140 | ||
141 | ||
78c3b329 | 142 | /* Sort resources by alignment */ |
bdc4abec | 143 | static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head) |
78c3b329 YL |
144 | { |
145 | int i; | |
146 | ||
147 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
148 | struct resource *r; | |
bdc4abec | 149 | struct pci_dev_resource *dev_res, *tmp; |
78c3b329 | 150 | resource_size_t r_align; |
bdc4abec | 151 | struct list_head *n; |
78c3b329 YL |
152 | |
153 | r = &dev->resource[i]; | |
154 | ||
155 | if (r->flags & IORESOURCE_PCI_FIXED) | |
156 | continue; | |
157 | ||
158 | if (!(r->flags) || r->parent) | |
159 | continue; | |
160 | ||
161 | r_align = pci_resource_alignment(dev, r); | |
162 | if (!r_align) { | |
163 | dev_warn(&dev->dev, "BAR %d: %pR has bogus alignment\n", | |
164 | i, r); | |
165 | continue; | |
166 | } | |
78c3b329 | 167 | |
bdc4abec YL |
168 | tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); |
169 | if (!tmp) | |
227f0647 | 170 | panic("pdev_sort_resources(): kmalloc() failed!\n"); |
bdc4abec YL |
171 | tmp->res = r; |
172 | tmp->dev = dev; | |
173 | ||
174 | /* fallback is smallest one or list is empty*/ | |
175 | n = head; | |
176 | list_for_each_entry(dev_res, head, list) { | |
177 | resource_size_t align; | |
178 | ||
179 | align = pci_resource_alignment(dev_res->dev, | |
180 | dev_res->res); | |
78c3b329 YL |
181 | |
182 | if (r_align > align) { | |
bdc4abec | 183 | n = &dev_res->list; |
78c3b329 YL |
184 | break; |
185 | } | |
186 | } | |
bdc4abec YL |
187 | /* Insert it just before n*/ |
188 | list_add_tail(&tmp->list, n); | |
78c3b329 YL |
189 | } |
190 | } | |
191 | ||
6841ec68 | 192 | static void __dev_sort_resources(struct pci_dev *dev, |
bdc4abec | 193 | struct list_head *head) |
1da177e4 | 194 | { |
6841ec68 | 195 | u16 class = dev->class >> 8; |
1da177e4 | 196 | |
6841ec68 YL |
197 | /* Don't touch classless devices or host bridges or ioapics. */ |
198 | if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST) | |
199 | return; | |
1da177e4 | 200 | |
6841ec68 YL |
201 | /* Don't touch ioapic devices already enabled by firmware */ |
202 | if (class == PCI_CLASS_SYSTEM_PIC) { | |
203 | u16 command; | |
204 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
205 | if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | |
206 | return; | |
207 | } | |
1da177e4 | 208 | |
6841ec68 YL |
209 | pdev_sort_resources(dev, head); |
210 | } | |
23186279 | 211 | |
fc075e1d RP |
212 | static inline void reset_resource(struct resource *res) |
213 | { | |
214 | res->start = 0; | |
215 | res->end = 0; | |
216 | res->flags = 0; | |
217 | } | |
218 | ||
c8adf9a3 | 219 | /** |
9e8bf93a | 220 | * reassign_resources_sorted() - satisfy any additional resource requests |
c8adf9a3 | 221 | * |
9e8bf93a | 222 | * @realloc_head : head of the list tracking requests requiring additional |
c8adf9a3 RP |
223 | * resources |
224 | * @head : head of the list tracking requests with allocated | |
225 | * resources | |
226 | * | |
9e8bf93a | 227 | * Walk through each element of the realloc_head and try to procure |
c8adf9a3 RP |
228 | * additional resources for the element, provided the element |
229 | * is in the head list. | |
230 | */ | |
bdc4abec YL |
231 | static void reassign_resources_sorted(struct list_head *realloc_head, |
232 | struct list_head *head) | |
6841ec68 YL |
233 | { |
234 | struct resource *res; | |
b9b0bba9 | 235 | struct pci_dev_resource *add_res, *tmp; |
bdc4abec | 236 | struct pci_dev_resource *dev_res; |
d74b9027 | 237 | resource_size_t add_size, align; |
6841ec68 | 238 | int idx; |
1da177e4 | 239 | |
b9b0bba9 | 240 | list_for_each_entry_safe(add_res, tmp, realloc_head, list) { |
bdc4abec YL |
241 | bool found_match = false; |
242 | ||
b9b0bba9 | 243 | res = add_res->res; |
c8adf9a3 RP |
244 | /* skip resource that has been reset */ |
245 | if (!res->flags) | |
246 | goto out; | |
247 | ||
248 | /* skip this resource if not found in head list */ | |
bdc4abec YL |
249 | list_for_each_entry(dev_res, head, list) { |
250 | if (dev_res->res == res) { | |
251 | found_match = true; | |
252 | break; | |
253 | } | |
c8adf9a3 | 254 | } |
bdc4abec YL |
255 | if (!found_match)/* just skip */ |
256 | continue; | |
c8adf9a3 | 257 | |
b9b0bba9 YL |
258 | idx = res - &add_res->dev->resource[0]; |
259 | add_size = add_res->add_size; | |
d74b9027 | 260 | align = add_res->min_align; |
2bbc6942 | 261 | if (!resource_size(res)) { |
d74b9027 | 262 | res->start = align; |
2bbc6942 | 263 | res->end = res->start + add_size - 1; |
b9b0bba9 | 264 | if (pci_assign_resource(add_res->dev, idx)) |
c8adf9a3 | 265 | reset_resource(res); |
2bbc6942 | 266 | } else { |
b9b0bba9 | 267 | res->flags |= add_res->flags & |
bdc4abec | 268 | (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN); |
b9b0bba9 | 269 | if (pci_reassign_resource(add_res->dev, idx, |
bdc4abec | 270 | add_size, align)) |
b9b0bba9 | 271 | dev_printk(KERN_DEBUG, &add_res->dev->dev, |
b592443d YL |
272 | "failed to add %llx res[%d]=%pR\n", |
273 | (unsigned long long)add_size, | |
274 | idx, res); | |
c8adf9a3 RP |
275 | } |
276 | out: | |
b9b0bba9 YL |
277 | list_del(&add_res->list); |
278 | kfree(add_res); | |
c8adf9a3 RP |
279 | } |
280 | } | |
281 | ||
282 | /** | |
283 | * assign_requested_resources_sorted() - satisfy resource requests | |
284 | * | |
285 | * @head : head of the list tracking requests for resources | |
8356aad4 | 286 | * @fail_head : head of the list tracking requests that could |
c8adf9a3 RP |
287 | * not be allocated |
288 | * | |
289 | * Satisfy resource requests of each element in the list. Add | |
290 | * requests that could not satisfied to the failed_list. | |
291 | */ | |
bdc4abec YL |
292 | static void assign_requested_resources_sorted(struct list_head *head, |
293 | struct list_head *fail_head) | |
c8adf9a3 RP |
294 | { |
295 | struct resource *res; | |
bdc4abec | 296 | struct pci_dev_resource *dev_res; |
c8adf9a3 | 297 | int idx; |
9a928660 | 298 | |
bdc4abec YL |
299 | list_for_each_entry(dev_res, head, list) { |
300 | res = dev_res->res; | |
301 | idx = res - &dev_res->dev->resource[0]; | |
302 | if (resource_size(res) && | |
303 | pci_assign_resource(dev_res->dev, idx)) { | |
a3cb999d | 304 | if (fail_head) { |
9a928660 YL |
305 | /* |
306 | * if the failed res is for ROM BAR, and it will | |
307 | * be enabled later, don't add it to the list | |
308 | */ | |
309 | if (!((idx == PCI_ROM_RESOURCE) && | |
310 | (!(res->flags & IORESOURCE_ROM_ENABLE)))) | |
67cc7e26 YL |
311 | add_to_list(fail_head, |
312 | dev_res->dev, res, | |
f7625980 BH |
313 | 0 /* don't care */, |
314 | 0 /* don't care */); | |
9a928660 | 315 | } |
fc075e1d | 316 | reset_resource(res); |
542df5de | 317 | } |
1da177e4 LT |
318 | } |
319 | } | |
320 | ||
aa914f5e YL |
321 | static unsigned long pci_fail_res_type_mask(struct list_head *fail_head) |
322 | { | |
323 | struct pci_dev_resource *fail_res; | |
324 | unsigned long mask = 0; | |
325 | ||
326 | /* check failed type */ | |
327 | list_for_each_entry(fail_res, fail_head, list) | |
328 | mask |= fail_res->flags; | |
329 | ||
330 | /* | |
331 | * one pref failed resource will set IORESOURCE_MEM, | |
332 | * as we can allocate pref in non-pref range. | |
333 | * Will release all assigned non-pref sibling resources | |
334 | * according to that bit. | |
335 | */ | |
336 | return mask & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH); | |
337 | } | |
338 | ||
339 | static bool pci_need_to_release(unsigned long mask, struct resource *res) | |
340 | { | |
341 | if (res->flags & IORESOURCE_IO) | |
342 | return !!(mask & IORESOURCE_IO); | |
343 | ||
344 | /* check pref at first */ | |
345 | if (res->flags & IORESOURCE_PREFETCH) { | |
346 | if (mask & IORESOURCE_PREFETCH) | |
347 | return true; | |
348 | /* count pref if its parent is non-pref */ | |
349 | else if ((mask & IORESOURCE_MEM) && | |
350 | !(res->parent->flags & IORESOURCE_PREFETCH)) | |
351 | return true; | |
352 | else | |
353 | return false; | |
354 | } | |
355 | ||
356 | if (res->flags & IORESOURCE_MEM) | |
357 | return !!(mask & IORESOURCE_MEM); | |
358 | ||
359 | return false; /* should not get here */ | |
360 | } | |
361 | ||
bdc4abec YL |
362 | static void __assign_resources_sorted(struct list_head *head, |
363 | struct list_head *realloc_head, | |
364 | struct list_head *fail_head) | |
c8adf9a3 | 365 | { |
3e6e0d80 YL |
366 | /* |
367 | * Should not assign requested resources at first. | |
368 | * they could be adjacent, so later reassign can not reallocate | |
369 | * them one by one in parent resource window. | |
367fa982 | 370 | * Try to assign requested + add_size at beginning |
3e6e0d80 YL |
371 | * if could do that, could get out early. |
372 | * if could not do that, we still try to assign requested at first, | |
373 | * then try to reassign add_size for some resources. | |
aa914f5e YL |
374 | * |
375 | * Separate three resource type checking if we need to release | |
376 | * assigned resource after requested + add_size try. | |
377 | * 1. if there is io port assign fail, will release assigned | |
378 | * io port. | |
379 | * 2. if there is pref mmio assign fail, release assigned | |
380 | * pref mmio. | |
381 | * if assigned pref mmio's parent is non-pref mmio and there | |
382 | * is non-pref mmio assign fail, will release that assigned | |
383 | * pref mmio. | |
384 | * 3. if there is non-pref mmio assign fail or pref mmio | |
385 | * assigned fail, will release assigned non-pref mmio. | |
3e6e0d80 | 386 | */ |
bdc4abec YL |
387 | LIST_HEAD(save_head); |
388 | LIST_HEAD(local_fail_head); | |
b9b0bba9 | 389 | struct pci_dev_resource *save_res; |
d74b9027 | 390 | struct pci_dev_resource *dev_res, *tmp_res, *dev_res2; |
aa914f5e | 391 | unsigned long fail_type; |
d74b9027 | 392 | resource_size_t add_align, align; |
3e6e0d80 YL |
393 | |
394 | /* Check if optional add_size is there */ | |
bdc4abec | 395 | if (!realloc_head || list_empty(realloc_head)) |
3e6e0d80 YL |
396 | goto requested_and_reassign; |
397 | ||
398 | /* Save original start, end, flags etc at first */ | |
bdc4abec YL |
399 | list_for_each_entry(dev_res, head, list) { |
400 | if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) { | |
bffc56d4 | 401 | free_list(&save_head); |
3e6e0d80 YL |
402 | goto requested_and_reassign; |
403 | } | |
bdc4abec | 404 | } |
3e6e0d80 YL |
405 | |
406 | /* Update res in head list with add_size in realloc_head list */ | |
d74b9027 | 407 | list_for_each_entry_safe(dev_res, tmp_res, head, list) { |
bdc4abec YL |
408 | dev_res->res->end += get_res_add_size(realloc_head, |
409 | dev_res->res); | |
3e6e0d80 | 410 | |
d74b9027 WY |
411 | /* |
412 | * There are two kinds of additional resources in the list: | |
413 | * 1. bridge resource -- IORESOURCE_STARTALIGN | |
414 | * 2. SR-IOV resource -- IORESOURCE_SIZEALIGN | |
415 | * Here just fix the additional alignment for bridge | |
416 | */ | |
417 | if (!(dev_res->res->flags & IORESOURCE_STARTALIGN)) | |
418 | continue; | |
419 | ||
420 | add_align = get_res_add_align(realloc_head, dev_res->res); | |
421 | ||
422 | /* | |
423 | * The "head" list is sorted by the alignment to make sure | |
424 | * resources with bigger alignment will be assigned first. | |
425 | * After we change the alignment of a dev_res in "head" list, | |
426 | * we need to reorder the list by alignment to make it | |
427 | * consistent. | |
428 | */ | |
429 | if (add_align > dev_res->res->start) { | |
552bc94e YL |
430 | resource_size_t r_size = resource_size(dev_res->res); |
431 | ||
d74b9027 | 432 | dev_res->res->start = add_align; |
552bc94e | 433 | dev_res->res->end = add_align + r_size - 1; |
d74b9027 WY |
434 | |
435 | list_for_each_entry(dev_res2, head, list) { | |
436 | align = pci_resource_alignment(dev_res2->dev, | |
437 | dev_res2->res); | |
a6b65983 | 438 | if (add_align > align) { |
d74b9027 WY |
439 | list_move_tail(&dev_res->list, |
440 | &dev_res2->list); | |
a6b65983 WY |
441 | break; |
442 | } | |
d74b9027 | 443 | } |
ff3ce480 | 444 | } |
d74b9027 WY |
445 | |
446 | } | |
447 | ||
3e6e0d80 | 448 | /* Try updated head list with add_size added */ |
3e6e0d80 YL |
449 | assign_requested_resources_sorted(head, &local_fail_head); |
450 | ||
451 | /* all assigned with add_size ? */ | |
bdc4abec | 452 | if (list_empty(&local_fail_head)) { |
3e6e0d80 | 453 | /* Remove head list from realloc_head list */ |
bdc4abec YL |
454 | list_for_each_entry(dev_res, head, list) |
455 | remove_from_list(realloc_head, dev_res->res); | |
bffc56d4 YL |
456 | free_list(&save_head); |
457 | free_list(head); | |
3e6e0d80 YL |
458 | return; |
459 | } | |
460 | ||
aa914f5e YL |
461 | /* check failed type */ |
462 | fail_type = pci_fail_res_type_mask(&local_fail_head); | |
463 | /* remove not need to be released assigned res from head list etc */ | |
464 | list_for_each_entry_safe(dev_res, tmp_res, head, list) | |
465 | if (dev_res->res->parent && | |
466 | !pci_need_to_release(fail_type, dev_res->res)) { | |
467 | /* remove it from realloc_head list */ | |
468 | remove_from_list(realloc_head, dev_res->res); | |
469 | remove_from_list(&save_head, dev_res->res); | |
470 | list_del(&dev_res->list); | |
471 | kfree(dev_res); | |
472 | } | |
473 | ||
bffc56d4 | 474 | free_list(&local_fail_head); |
3e6e0d80 | 475 | /* Release assigned resource */ |
bdc4abec YL |
476 | list_for_each_entry(dev_res, head, list) |
477 | if (dev_res->res->parent) | |
478 | release_resource(dev_res->res); | |
3e6e0d80 | 479 | /* Restore start/end/flags from saved list */ |
b9b0bba9 YL |
480 | list_for_each_entry(save_res, &save_head, list) { |
481 | struct resource *res = save_res->res; | |
3e6e0d80 | 482 | |
b9b0bba9 YL |
483 | res->start = save_res->start; |
484 | res->end = save_res->end; | |
485 | res->flags = save_res->flags; | |
3e6e0d80 | 486 | } |
bffc56d4 | 487 | free_list(&save_head); |
3e6e0d80 YL |
488 | |
489 | requested_and_reassign: | |
c8adf9a3 RP |
490 | /* Satisfy the must-have resource requests */ |
491 | assign_requested_resources_sorted(head, fail_head); | |
492 | ||
0a2daa1c | 493 | /* Try to satisfy any additional optional resource |
c8adf9a3 | 494 | requests */ |
9e8bf93a RP |
495 | if (realloc_head) |
496 | reassign_resources_sorted(realloc_head, head); | |
bffc56d4 | 497 | free_list(head); |
c8adf9a3 RP |
498 | } |
499 | ||
6841ec68 | 500 | static void pdev_assign_resources_sorted(struct pci_dev *dev, |
bdc4abec YL |
501 | struct list_head *add_head, |
502 | struct list_head *fail_head) | |
6841ec68 | 503 | { |
bdc4abec | 504 | LIST_HEAD(head); |
6841ec68 | 505 | |
6841ec68 | 506 | __dev_sort_resources(dev, &head); |
8424d759 | 507 | __assign_resources_sorted(&head, add_head, fail_head); |
6841ec68 YL |
508 | |
509 | } | |
510 | ||
511 | static void pbus_assign_resources_sorted(const struct pci_bus *bus, | |
bdc4abec YL |
512 | struct list_head *realloc_head, |
513 | struct list_head *fail_head) | |
6841ec68 YL |
514 | { |
515 | struct pci_dev *dev; | |
bdc4abec | 516 | LIST_HEAD(head); |
6841ec68 | 517 | |
6841ec68 YL |
518 | list_for_each_entry(dev, &bus->devices, bus_list) |
519 | __dev_sort_resources(dev, &head); | |
520 | ||
9e8bf93a | 521 | __assign_resources_sorted(&head, realloc_head, fail_head); |
6841ec68 YL |
522 | } |
523 | ||
b3743fa4 | 524 | void pci_setup_cardbus(struct pci_bus *bus) |
1da177e4 LT |
525 | { |
526 | struct pci_dev *bridge = bus->self; | |
c7dabef8 | 527 | struct resource *res; |
1da177e4 LT |
528 | struct pci_bus_region region; |
529 | ||
b918c62e YL |
530 | dev_info(&bridge->dev, "CardBus bridge to %pR\n", |
531 | &bus->busn_res); | |
1da177e4 | 532 | |
c7dabef8 | 533 | res = bus->resource[0]; |
fc279850 | 534 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 | 535 | if (res->flags & IORESOURCE_IO) { |
1da177e4 LT |
536 | /* |
537 | * The IO resource is allocated a range twice as large as it | |
538 | * would normally need. This allows us to set both IO regs. | |
539 | */ | |
c7dabef8 | 540 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
1da177e4 LT |
541 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, |
542 | region.start); | |
543 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0, | |
544 | region.end); | |
545 | } | |
546 | ||
c7dabef8 | 547 | res = bus->resource[1]; |
fc279850 | 548 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 BH |
549 | if (res->flags & IORESOURCE_IO) { |
550 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
551 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, |
552 | region.start); | |
553 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1, | |
554 | region.end); | |
555 | } | |
556 | ||
c7dabef8 | 557 | res = bus->resource[2]; |
fc279850 | 558 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 BH |
559 | if (res->flags & IORESOURCE_MEM) { |
560 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
561 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, |
562 | region.start); | |
563 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0, | |
564 | region.end); | |
565 | } | |
566 | ||
c7dabef8 | 567 | res = bus->resource[3]; |
fc279850 | 568 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 BH |
569 | if (res->flags & IORESOURCE_MEM) { |
570 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
571 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, |
572 | region.start); | |
573 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1, | |
574 | region.end); | |
575 | } | |
576 | } | |
b3743fa4 | 577 | EXPORT_SYMBOL(pci_setup_cardbus); |
1da177e4 LT |
578 | |
579 | /* Initialize bridges with base/limit values we have collected. | |
580 | PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998) | |
581 | requires that if there is no I/O ports or memory behind the | |
582 | bridge, corresponding range must be turned off by writing base | |
583 | value greater than limit to the bridge's base/limit registers. | |
584 | ||
585 | Note: care must be taken when updating I/O base/limit registers | |
586 | of bridges which support 32-bit I/O. This update requires two | |
587 | config space writes, so it's quite possible that an I/O window of | |
588 | the bridge will have some undesirable address (e.g. 0) after the | |
589 | first write. Ditto 64-bit prefetchable MMIO. */ | |
3f2f4dc4 | 590 | static void pci_setup_bridge_io(struct pci_dev *bridge) |
1da177e4 | 591 | { |
c7dabef8 | 592 | struct resource *res; |
1da177e4 | 593 | struct pci_bus_region region; |
2b28ae19 BH |
594 | unsigned long io_mask; |
595 | u8 io_base_lo, io_limit_lo; | |
5b764b83 BH |
596 | u16 l; |
597 | u32 io_upper16; | |
1da177e4 | 598 | |
2b28ae19 BH |
599 | io_mask = PCI_IO_RANGE_MASK; |
600 | if (bridge->io_window_1k) | |
601 | io_mask = PCI_IO_1K_RANGE_MASK; | |
602 | ||
1da177e4 | 603 | /* Set up the top and bottom of the PCI I/O segment for this bus. */ |
3f2f4dc4 | 604 | res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0]; |
fc279850 | 605 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 | 606 | if (res->flags & IORESOURCE_IO) { |
5b764b83 | 607 | pci_read_config_word(bridge, PCI_IO_BASE, &l); |
2b28ae19 BH |
608 | io_base_lo = (region.start >> 8) & io_mask; |
609 | io_limit_lo = (region.end >> 8) & io_mask; | |
5b764b83 | 610 | l = ((u16) io_limit_lo << 8) | io_base_lo; |
1da177e4 LT |
611 | /* Set up upper 16 bits of I/O base/limit. */ |
612 | io_upper16 = (region.end & 0xffff0000) | (region.start >> 16); | |
c7dabef8 | 613 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 614 | } else { |
1da177e4 LT |
615 | /* Clear upper 16 bits of I/O base/limit. */ |
616 | io_upper16 = 0; | |
617 | l = 0x00f0; | |
1da177e4 LT |
618 | } |
619 | /* Temporarily disable the I/O range before updating PCI_IO_BASE. */ | |
620 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff); | |
621 | /* Update lower 16 bits of I/O base/limit. */ | |
5b764b83 | 622 | pci_write_config_word(bridge, PCI_IO_BASE, l); |
1da177e4 LT |
623 | /* Update upper 16 bits of I/O base/limit. */ |
624 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16); | |
7cc5997d YL |
625 | } |
626 | ||
3f2f4dc4 | 627 | static void pci_setup_bridge_mmio(struct pci_dev *bridge) |
7cc5997d | 628 | { |
7cc5997d YL |
629 | struct resource *res; |
630 | struct pci_bus_region region; | |
631 | u32 l; | |
1da177e4 | 632 | |
7cc5997d | 633 | /* Set up the top and bottom of the PCI Memory segment for this bus. */ |
3f2f4dc4 | 634 | res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1]; |
fc279850 | 635 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 | 636 | if (res->flags & IORESOURCE_MEM) { |
1da177e4 LT |
637 | l = (region.start >> 16) & 0xfff0; |
638 | l |= region.end & 0xfff00000; | |
c7dabef8 | 639 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 640 | } else { |
1da177e4 | 641 | l = 0x0000fff0; |
1da177e4 LT |
642 | } |
643 | pci_write_config_dword(bridge, PCI_MEMORY_BASE, l); | |
7cc5997d YL |
644 | } |
645 | ||
3f2f4dc4 | 646 | static void pci_setup_bridge_mmio_pref(struct pci_dev *bridge) |
7cc5997d | 647 | { |
7cc5997d YL |
648 | struct resource *res; |
649 | struct pci_bus_region region; | |
650 | u32 l, bu, lu; | |
1da177e4 LT |
651 | |
652 | /* Clear out the upper 32 bits of PREF limit. | |
653 | If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily | |
654 | disables PREF range, which is ok. */ | |
655 | pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0); | |
656 | ||
657 | /* Set up PREF base/limit. */ | |
c40a22e0 | 658 | bu = lu = 0; |
3f2f4dc4 | 659 | res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2]; |
fc279850 | 660 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 | 661 | if (res->flags & IORESOURCE_PREFETCH) { |
1da177e4 LT |
662 | l = (region.start >> 16) & 0xfff0; |
663 | l |= region.end & 0xfff00000; | |
c7dabef8 | 664 | if (res->flags & IORESOURCE_MEM_64) { |
1f82de10 YL |
665 | bu = upper_32_bits(region.start); |
666 | lu = upper_32_bits(region.end); | |
1f82de10 | 667 | } |
c7dabef8 | 668 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 669 | } else { |
1da177e4 | 670 | l = 0x0000fff0; |
1da177e4 LT |
671 | } |
672 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l); | |
673 | ||
59353ea3 AW |
674 | /* Set the upper 32 bits of PREF base & limit. */ |
675 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu); | |
676 | pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu); | |
7cc5997d YL |
677 | } |
678 | ||
679 | static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type) | |
680 | { | |
681 | struct pci_dev *bridge = bus->self; | |
682 | ||
b918c62e YL |
683 | dev_info(&bridge->dev, "PCI bridge to %pR\n", |
684 | &bus->busn_res); | |
7cc5997d YL |
685 | |
686 | if (type & IORESOURCE_IO) | |
3f2f4dc4 | 687 | pci_setup_bridge_io(bridge); |
7cc5997d YL |
688 | |
689 | if (type & IORESOURCE_MEM) | |
3f2f4dc4 | 690 | pci_setup_bridge_mmio(bridge); |
7cc5997d YL |
691 | |
692 | if (type & IORESOURCE_PREFETCH) | |
3f2f4dc4 | 693 | pci_setup_bridge_mmio_pref(bridge); |
1da177e4 LT |
694 | |
695 | pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl); | |
696 | } | |
697 | ||
e2444273 | 698 | void pci_setup_bridge(struct pci_bus *bus) |
7cc5997d YL |
699 | { |
700 | unsigned long type = IORESOURCE_IO | IORESOURCE_MEM | | |
701 | IORESOURCE_PREFETCH; | |
702 | ||
703 | __pci_setup_bridge(bus, type); | |
704 | } | |
705 | ||
8505e729 YL |
706 | |
707 | int pci_claim_bridge_resource(struct pci_dev *bridge, int i) | |
708 | { | |
709 | if (i < PCI_BRIDGE_RESOURCES || i > PCI_BRIDGE_RESOURCE_END) | |
710 | return 0; | |
711 | ||
712 | if (pci_claim_resource(bridge, i) == 0) | |
713 | return 0; /* claimed the window */ | |
714 | ||
715 | if ((bridge->class >> 8) != PCI_CLASS_BRIDGE_PCI) | |
716 | return 0; | |
717 | ||
718 | if (!pci_bus_clip_resource(bridge, i)) | |
719 | return -EINVAL; /* clipping didn't change anything */ | |
720 | ||
721 | switch (i - PCI_BRIDGE_RESOURCES) { | |
722 | case 0: | |
723 | pci_setup_bridge_io(bridge); | |
724 | break; | |
725 | case 1: | |
726 | pci_setup_bridge_mmio(bridge); | |
727 | break; | |
728 | case 2: | |
729 | pci_setup_bridge_mmio_pref(bridge); | |
730 | break; | |
731 | default: | |
732 | return -EINVAL; | |
733 | } | |
734 | ||
735 | if (pci_claim_resource(bridge, i) == 0) | |
736 | return 0; /* claimed a smaller window */ | |
737 | ||
738 | return -EINVAL; | |
739 | } | |
740 | ||
1da177e4 LT |
741 | /* Check whether the bridge supports optional I/O and |
742 | prefetchable memory ranges. If not, the respective | |
743 | base/limit registers must be read-only and read as 0. */ | |
96bde06a | 744 | static void pci_bridge_check_ranges(struct pci_bus *bus) |
1da177e4 LT |
745 | { |
746 | u16 io; | |
747 | u32 pmem; | |
748 | struct pci_dev *bridge = bus->self; | |
749 | struct resource *b_res; | |
750 | ||
751 | b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; | |
752 | b_res[1].flags |= IORESOURCE_MEM; | |
753 | ||
754 | pci_read_config_word(bridge, PCI_IO_BASE, &io); | |
755 | if (!io) { | |
d2f54d9b | 756 | pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0); |
1da177e4 | 757 | pci_read_config_word(bridge, PCI_IO_BASE, &io); |
f7625980 BH |
758 | pci_write_config_word(bridge, PCI_IO_BASE, 0x0); |
759 | } | |
760 | if (io) | |
1da177e4 | 761 | b_res[0].flags |= IORESOURCE_IO; |
d2f54d9b | 762 | |
1da177e4 LT |
763 | /* DECchip 21050 pass 2 errata: the bridge may miss an address |
764 | disconnect boundary by one PCI data phase. | |
765 | Workaround: do not use prefetching on this device. */ | |
766 | if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) | |
767 | return; | |
d2f54d9b | 768 | |
1da177e4 LT |
769 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); |
770 | if (!pmem) { | |
771 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, | |
d2f54d9b | 772 | 0xffe0fff0); |
1da177e4 LT |
773 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); |
774 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); | |
775 | } | |
1f82de10 | 776 | if (pmem) { |
1da177e4 | 777 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; |
99586105 YL |
778 | if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == |
779 | PCI_PREF_RANGE_TYPE_64) { | |
1f82de10 | 780 | b_res[2].flags |= IORESOURCE_MEM_64; |
99586105 YL |
781 | b_res[2].flags |= PCI_PREF_RANGE_TYPE_64; |
782 | } | |
1f82de10 YL |
783 | } |
784 | ||
785 | /* double check if bridge does support 64 bit pref */ | |
786 | if (b_res[2].flags & IORESOURCE_MEM_64) { | |
787 | u32 mem_base_hi, tmp; | |
788 | pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
789 | &mem_base_hi); | |
790 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
791 | 0xffffffff); | |
792 | pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp); | |
793 | if (!tmp) | |
794 | b_res[2].flags &= ~IORESOURCE_MEM_64; | |
795 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
796 | mem_base_hi); | |
797 | } | |
1da177e4 LT |
798 | } |
799 | ||
800 | /* Helper function for sizing routines: find first available | |
801 | bus resource of a given type. Note: we intentionally skip | |
802 | the bus resources which have already been assigned (that is, | |
803 | have non-NULL parent resource). */ | |
5b285415 YL |
804 | static struct resource *find_free_bus_resource(struct pci_bus *bus, |
805 | unsigned long type_mask, unsigned long type) | |
1da177e4 LT |
806 | { |
807 | int i; | |
808 | struct resource *r; | |
1da177e4 | 809 | |
89a74ecc | 810 | pci_bus_for_each_resource(bus, r, i) { |
299de034 IK |
811 | if (r == &ioport_resource || r == &iomem_resource) |
812 | continue; | |
55a10984 JB |
813 | if (r && (r->flags & type_mask) == type && !r->parent) |
814 | return r; | |
1da177e4 LT |
815 | } |
816 | return NULL; | |
817 | } | |
818 | ||
13583b16 RP |
819 | static resource_size_t calculate_iosize(resource_size_t size, |
820 | resource_size_t min_size, | |
821 | resource_size_t size1, | |
822 | resource_size_t old_size, | |
823 | resource_size_t align) | |
824 | { | |
825 | if (size < min_size) | |
826 | size = min_size; | |
3c78bc61 | 827 | if (old_size == 1) |
13583b16 RP |
828 | old_size = 0; |
829 | /* To be fixed in 2.5: we should have sort of HAVE_ISA | |
830 | flag in the struct pci_bus. */ | |
831 | #if defined(CONFIG_ISA) || defined(CONFIG_EISA) | |
832 | size = (size & 0xff) + ((size & ~0xffUL) << 2); | |
833 | #endif | |
834 | size = ALIGN(size + size1, align); | |
835 | if (size < old_size) | |
836 | size = old_size; | |
837 | return size; | |
838 | } | |
839 | ||
840 | static resource_size_t calculate_memsize(resource_size_t size, | |
841 | resource_size_t min_size, | |
842 | resource_size_t size1, | |
843 | resource_size_t old_size, | |
844 | resource_size_t align) | |
845 | { | |
846 | if (size < min_size) | |
847 | size = min_size; | |
3c78bc61 | 848 | if (old_size == 1) |
13583b16 RP |
849 | old_size = 0; |
850 | if (size < old_size) | |
851 | size = old_size; | |
852 | size = ALIGN(size + size1, align); | |
853 | return size; | |
854 | } | |
855 | ||
ac5ad93e GS |
856 | resource_size_t __weak pcibios_window_alignment(struct pci_bus *bus, |
857 | unsigned long type) | |
858 | { | |
859 | return 1; | |
860 | } | |
861 | ||
862 | #define PCI_P2P_DEFAULT_MEM_ALIGN 0x100000 /* 1MiB */ | |
863 | #define PCI_P2P_DEFAULT_IO_ALIGN 0x1000 /* 4KiB */ | |
864 | #define PCI_P2P_DEFAULT_IO_ALIGN_1K 0x400 /* 1KiB */ | |
865 | ||
866 | static resource_size_t window_alignment(struct pci_bus *bus, | |
867 | unsigned long type) | |
868 | { | |
869 | resource_size_t align = 1, arch_align; | |
870 | ||
871 | if (type & IORESOURCE_MEM) | |
872 | align = PCI_P2P_DEFAULT_MEM_ALIGN; | |
873 | else if (type & IORESOURCE_IO) { | |
874 | /* | |
875 | * Per spec, I/O windows are 4K-aligned, but some | |
876 | * bridges have an extension to support 1K alignment. | |
877 | */ | |
878 | if (bus->self->io_window_1k) | |
879 | align = PCI_P2P_DEFAULT_IO_ALIGN_1K; | |
880 | else | |
881 | align = PCI_P2P_DEFAULT_IO_ALIGN; | |
882 | } | |
883 | ||
884 | arch_align = pcibios_window_alignment(bus, type); | |
885 | return max(align, arch_align); | |
886 | } | |
887 | ||
c8adf9a3 RP |
888 | /** |
889 | * pbus_size_io() - size the io window of a given bus | |
890 | * | |
891 | * @bus : the bus | |
892 | * @min_size : the minimum io window that must to be allocated | |
893 | * @add_size : additional optional io window | |
9e8bf93a | 894 | * @realloc_head : track the additional io window on this list |
c8adf9a3 RP |
895 | * |
896 | * Sizing the IO windows of the PCI-PCI bridge is trivial, | |
fd591341 | 897 | * since these windows have 1K or 4K granularity and the IO ranges |
c8adf9a3 RP |
898 | * of non-bridge PCI devices are limited to 256 bytes. |
899 | * We must be careful with the ISA aliasing though. | |
900 | */ | |
901 | static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size, | |
bdc4abec | 902 | resource_size_t add_size, struct list_head *realloc_head) |
1da177e4 LT |
903 | { |
904 | struct pci_dev *dev; | |
5b285415 YL |
905 | struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO, |
906 | IORESOURCE_IO); | |
11251a86 | 907 | resource_size_t size = 0, size0 = 0, size1 = 0; |
be768912 | 908 | resource_size_t children_add_size = 0; |
2d1d6678 | 909 | resource_size_t min_align, align; |
1da177e4 LT |
910 | |
911 | if (!b_res) | |
f7625980 | 912 | return; |
1da177e4 | 913 | |
2d1d6678 | 914 | min_align = window_alignment(bus, IORESOURCE_IO); |
1da177e4 LT |
915 | list_for_each_entry(dev, &bus->devices, bus_list) { |
916 | int i; | |
917 | ||
918 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
919 | struct resource *r = &dev->resource[i]; | |
920 | unsigned long r_size; | |
921 | ||
922 | if (r->parent || !(r->flags & IORESOURCE_IO)) | |
923 | continue; | |
022edd86 | 924 | r_size = resource_size(r); |
1da177e4 LT |
925 | |
926 | if (r_size < 0x400) | |
927 | /* Might be re-aligned for ISA */ | |
928 | size += r_size; | |
929 | else | |
930 | size1 += r_size; | |
be768912 | 931 | |
fd591341 YL |
932 | align = pci_resource_alignment(dev, r); |
933 | if (align > min_align) | |
934 | min_align = align; | |
935 | ||
9e8bf93a RP |
936 | if (realloc_head) |
937 | children_add_size += get_res_add_size(realloc_head, r); | |
1da177e4 LT |
938 | } |
939 | } | |
fd591341 | 940 | |
c8adf9a3 | 941 | size0 = calculate_iosize(size, min_size, size1, |
fd591341 | 942 | resource_size(b_res), min_align); |
be768912 YL |
943 | if (children_add_size > add_size) |
944 | add_size = children_add_size; | |
9e8bf93a | 945 | size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 : |
a4ac9fea | 946 | calculate_iosize(size, min_size, add_size + size1, |
fd591341 | 947 | resource_size(b_res), min_align); |
c8adf9a3 | 948 | if (!size0 && !size1) { |
865df576 | 949 | if (b_res->start || b_res->end) |
227f0647 RD |
950 | dev_info(&bus->self->dev, "disabling bridge window %pR to %pR (unused)\n", |
951 | b_res, &bus->busn_res); | |
1da177e4 LT |
952 | b_res->flags = 0; |
953 | return; | |
954 | } | |
fd591341 YL |
955 | |
956 | b_res->start = min_align; | |
c8adf9a3 | 957 | b_res->end = b_res->start + size0 - 1; |
88452565 | 958 | b_res->flags |= IORESOURCE_STARTALIGN; |
b592443d | 959 | if (size1 > size0 && realloc_head) { |
fd591341 YL |
960 | add_to_list(realloc_head, bus->self, b_res, size1-size0, |
961 | min_align); | |
227f0647 RD |
962 | dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window %pR to %pR add_size %llx\n", |
963 | b_res, &bus->busn_res, | |
964 | (unsigned long long)size1-size0); | |
b592443d | 965 | } |
1da177e4 LT |
966 | } |
967 | ||
c121504e GS |
968 | static inline resource_size_t calculate_mem_align(resource_size_t *aligns, |
969 | int max_order) | |
970 | { | |
971 | resource_size_t align = 0; | |
972 | resource_size_t min_align = 0; | |
973 | int order; | |
974 | ||
975 | for (order = 0; order <= max_order; order++) { | |
976 | resource_size_t align1 = 1; | |
977 | ||
978 | align1 <<= (order + 20); | |
979 | ||
980 | if (!align) | |
981 | min_align = align1; | |
982 | else if (ALIGN(align + min_align, min_align) < align1) | |
983 | min_align = align1 >> 1; | |
984 | align += aligns[order]; | |
985 | } | |
986 | ||
987 | return min_align; | |
988 | } | |
989 | ||
c8adf9a3 RP |
990 | /** |
991 | * pbus_size_mem() - size the memory window of a given bus | |
992 | * | |
993 | * @bus : the bus | |
496f70cf WY |
994 | * @mask: mask the resource flag, then compare it with type |
995 | * @type: the type of free resource from bridge | |
5b285415 YL |
996 | * @type2: second match type |
997 | * @type3: third match type | |
c8adf9a3 RP |
998 | * @min_size : the minimum memory window that must to be allocated |
999 | * @add_size : additional optional memory window | |
9e8bf93a | 1000 | * @realloc_head : track the additional memory window on this list |
c8adf9a3 RP |
1001 | * |
1002 | * Calculate the size of the bus and minimal alignment which | |
1003 | * guarantees that all child resources fit in this size. | |
30afe8d0 BH |
1004 | * |
1005 | * Returns -ENOSPC if there's no available bus resource of the desired type. | |
1006 | * Otherwise, sets the bus resource start/end to indicate the required | |
1007 | * size, adds things to realloc_head (if supplied), and returns 0. | |
c8adf9a3 | 1008 | */ |
28760489 | 1009 | static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, |
5b285415 YL |
1010 | unsigned long type, unsigned long type2, |
1011 | unsigned long type3, | |
1012 | resource_size_t min_size, resource_size_t add_size, | |
1013 | struct list_head *realloc_head) | |
1da177e4 LT |
1014 | { |
1015 | struct pci_dev *dev; | |
c8adf9a3 | 1016 | resource_size_t min_align, align, size, size0, size1; |
096d4221 | 1017 | resource_size_t aligns[18]; /* Alignments from 1Mb to 128Gb */ |
1da177e4 | 1018 | int order, max_order; |
5b285415 YL |
1019 | struct resource *b_res = find_free_bus_resource(bus, |
1020 | mask | IORESOURCE_PREFETCH, type); | |
be768912 | 1021 | resource_size_t children_add_size = 0; |
d74b9027 WY |
1022 | resource_size_t children_add_align = 0; |
1023 | resource_size_t add_align = 0; | |
1da177e4 LT |
1024 | |
1025 | if (!b_res) | |
30afe8d0 | 1026 | return -ENOSPC; |
1da177e4 LT |
1027 | |
1028 | memset(aligns, 0, sizeof(aligns)); | |
1029 | max_order = 0; | |
1030 | size = 0; | |
1031 | ||
1032 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1033 | int i; | |
1f82de10 | 1034 | |
1da177e4 LT |
1035 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { |
1036 | struct resource *r = &dev->resource[i]; | |
c40a22e0 | 1037 | resource_size_t r_size; |
1da177e4 | 1038 | |
a2220d80 DD |
1039 | if (r->parent || (r->flags & IORESOURCE_PCI_FIXED) || |
1040 | ((r->flags & mask) != type && | |
1041 | (r->flags & mask) != type2 && | |
1042 | (r->flags & mask) != type3)) | |
1da177e4 | 1043 | continue; |
022edd86 | 1044 | r_size = resource_size(r); |
2aceefcb YL |
1045 | #ifdef CONFIG_PCI_IOV |
1046 | /* put SRIOV requested res to the optional list */ | |
9e8bf93a | 1047 | if (realloc_head && i >= PCI_IOV_RESOURCES && |
2aceefcb | 1048 | i <= PCI_IOV_RESOURCE_END) { |
d74b9027 | 1049 | add_align = max(pci_resource_alignment(dev, r), add_align); |
2aceefcb | 1050 | r->end = r->start - 1; |
f7625980 | 1051 | add_to_list(realloc_head, dev, r, r_size, 0/* don't care */); |
2aceefcb YL |
1052 | children_add_size += r_size; |
1053 | continue; | |
1054 | } | |
1055 | #endif | |
14c8530d A |
1056 | /* |
1057 | * aligns[0] is for 1MB (since bridge memory | |
1058 | * windows are always at least 1MB aligned), so | |
1059 | * keep "order" from being negative for smaller | |
1060 | * resources. | |
1061 | */ | |
6faf17f6 | 1062 | align = pci_resource_alignment(dev, r); |
1da177e4 | 1063 | order = __ffs(align) - 20; |
14c8530d A |
1064 | if (order < 0) |
1065 | order = 0; | |
1066 | if (order >= ARRAY_SIZE(aligns)) { | |
227f0647 RD |
1067 | dev_warn(&dev->dev, "disabling BAR %d: %pR (bad alignment %#llx)\n", |
1068 | i, r, (unsigned long long) align); | |
1da177e4 LT |
1069 | r->flags = 0; |
1070 | continue; | |
1071 | } | |
1072 | size += r_size; | |
1da177e4 LT |
1073 | /* Exclude ranges with size > align from |
1074 | calculation of the alignment. */ | |
1075 | if (r_size == align) | |
1076 | aligns[order] += align; | |
1077 | if (order > max_order) | |
1078 | max_order = order; | |
be768912 | 1079 | |
d74b9027 | 1080 | if (realloc_head) { |
9e8bf93a | 1081 | children_add_size += get_res_add_size(realloc_head, r); |
d74b9027 WY |
1082 | children_add_align = get_res_add_align(realloc_head, r); |
1083 | add_align = max(add_align, children_add_align); | |
1084 | } | |
1da177e4 LT |
1085 | } |
1086 | } | |
462d9303 | 1087 | |
c121504e | 1088 | min_align = calculate_mem_align(aligns, max_order); |
3ad94b0d | 1089 | min_align = max(min_align, window_alignment(bus, b_res->flags)); |
b42282e5 | 1090 | size0 = calculate_memsize(size, min_size, 0, resource_size(b_res), min_align); |
d74b9027 | 1091 | add_align = max(min_align, add_align); |
be768912 YL |
1092 | if (children_add_size > add_size) |
1093 | add_size = children_add_size; | |
9e8bf93a | 1094 | size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 : |
a4ac9fea | 1095 | calculate_memsize(size, min_size, add_size, |
d74b9027 | 1096 | resource_size(b_res), add_align); |
c8adf9a3 | 1097 | if (!size0 && !size1) { |
865df576 | 1098 | if (b_res->start || b_res->end) |
227f0647 RD |
1099 | dev_info(&bus->self->dev, "disabling bridge window %pR to %pR (unused)\n", |
1100 | b_res, &bus->busn_res); | |
1da177e4 | 1101 | b_res->flags = 0; |
30afe8d0 | 1102 | return 0; |
1da177e4 LT |
1103 | } |
1104 | b_res->start = min_align; | |
c8adf9a3 | 1105 | b_res->end = size0 + min_align - 1; |
5b285415 | 1106 | b_res->flags |= IORESOURCE_STARTALIGN; |
b592443d | 1107 | if (size1 > size0 && realloc_head) { |
d74b9027 WY |
1108 | add_to_list(realloc_head, bus->self, b_res, size1-size0, add_align); |
1109 | dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window %pR to %pR add_size %llx add_align %llx\n", | |
227f0647 | 1110 | b_res, &bus->busn_res, |
d74b9027 WY |
1111 | (unsigned long long) (size1 - size0), |
1112 | (unsigned long long) add_align); | |
b592443d | 1113 | } |
30afe8d0 | 1114 | return 0; |
1da177e4 LT |
1115 | } |
1116 | ||
0a2daa1c RP |
1117 | unsigned long pci_cardbus_resource_alignment(struct resource *res) |
1118 | { | |
1119 | if (res->flags & IORESOURCE_IO) | |
1120 | return pci_cardbus_io_size; | |
1121 | if (res->flags & IORESOURCE_MEM) | |
1122 | return pci_cardbus_mem_size; | |
1123 | return 0; | |
1124 | } | |
1125 | ||
1126 | static void pci_bus_size_cardbus(struct pci_bus *bus, | |
bdc4abec | 1127 | struct list_head *realloc_head) |
1da177e4 LT |
1128 | { |
1129 | struct pci_dev *bridge = bus->self; | |
1130 | struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; | |
11848934 | 1131 | resource_size_t b_res_3_size = pci_cardbus_mem_size * 2; |
1da177e4 LT |
1132 | u16 ctrl; |
1133 | ||
3796f1e2 YL |
1134 | if (b_res[0].parent) |
1135 | goto handle_b_res_1; | |
1da177e4 LT |
1136 | /* |
1137 | * Reserve some resources for CardBus. We reserve | |
1138 | * a fixed amount of bus space for CardBus bridges. | |
1139 | */ | |
11848934 YL |
1140 | b_res[0].start = pci_cardbus_io_size; |
1141 | b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1; | |
1142 | b_res[0].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN; | |
1143 | if (realloc_head) { | |
1144 | b_res[0].end -= pci_cardbus_io_size; | |
1145 | add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size, | |
1146 | pci_cardbus_io_size); | |
1147 | } | |
1da177e4 | 1148 | |
3796f1e2 YL |
1149 | handle_b_res_1: |
1150 | if (b_res[1].parent) | |
1151 | goto handle_b_res_2; | |
11848934 YL |
1152 | b_res[1].start = pci_cardbus_io_size; |
1153 | b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1; | |
1154 | b_res[1].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN; | |
1155 | if (realloc_head) { | |
1156 | b_res[1].end -= pci_cardbus_io_size; | |
1157 | add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size, | |
1158 | pci_cardbus_io_size); | |
1159 | } | |
1da177e4 | 1160 | |
3796f1e2 | 1161 | handle_b_res_2: |
dcef0d06 YL |
1162 | /* MEM1 must not be pref mmio */ |
1163 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
1164 | if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) { | |
1165 | ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1; | |
1166 | pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); | |
1167 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
1168 | } | |
1169 | ||
1da177e4 LT |
1170 | /* |
1171 | * Check whether prefetchable memory is supported | |
1172 | * by this bridge. | |
1173 | */ | |
1174 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
1175 | if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) { | |
1176 | ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; | |
1177 | pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); | |
1178 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
1179 | } | |
1180 | ||
3796f1e2 YL |
1181 | if (b_res[2].parent) |
1182 | goto handle_b_res_3; | |
1da177e4 LT |
1183 | /* |
1184 | * If we have prefetchable memory support, allocate | |
1185 | * two regions. Otherwise, allocate one region of | |
1186 | * twice the size. | |
1187 | */ | |
1188 | if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) { | |
11848934 YL |
1189 | b_res[2].start = pci_cardbus_mem_size; |
1190 | b_res[2].end = b_res[2].start + pci_cardbus_mem_size - 1; | |
1191 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | | |
1192 | IORESOURCE_STARTALIGN; | |
1193 | if (realloc_head) { | |
1194 | b_res[2].end -= pci_cardbus_mem_size; | |
1195 | add_to_list(realloc_head, bridge, b_res+2, | |
1196 | pci_cardbus_mem_size, pci_cardbus_mem_size); | |
1197 | } | |
1198 | ||
1199 | /* reduce that to half */ | |
1200 | b_res_3_size = pci_cardbus_mem_size; | |
1201 | } | |
1202 | ||
3796f1e2 YL |
1203 | handle_b_res_3: |
1204 | if (b_res[3].parent) | |
1205 | goto handle_done; | |
11848934 YL |
1206 | b_res[3].start = pci_cardbus_mem_size; |
1207 | b_res[3].end = b_res[3].start + b_res_3_size - 1; | |
1208 | b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN; | |
1209 | if (realloc_head) { | |
1210 | b_res[3].end -= b_res_3_size; | |
1211 | add_to_list(realloc_head, bridge, b_res+3, b_res_3_size, | |
1212 | pci_cardbus_mem_size); | |
1213 | } | |
3796f1e2 YL |
1214 | |
1215 | handle_done: | |
1216 | ; | |
1da177e4 LT |
1217 | } |
1218 | ||
10874f5a | 1219 | void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head) |
1da177e4 LT |
1220 | { |
1221 | struct pci_dev *dev; | |
5b285415 | 1222 | unsigned long mask, prefmask, type2 = 0, type3 = 0; |
c8adf9a3 | 1223 | resource_size_t additional_mem_size = 0, additional_io_size = 0; |
5b285415 | 1224 | struct resource *b_res; |
30afe8d0 | 1225 | int ret; |
1da177e4 LT |
1226 | |
1227 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1228 | struct pci_bus *b = dev->subordinate; | |
1229 | if (!b) | |
1230 | continue; | |
1231 | ||
1232 | switch (dev->class >> 8) { | |
1233 | case PCI_CLASS_BRIDGE_CARDBUS: | |
9e8bf93a | 1234 | pci_bus_size_cardbus(b, realloc_head); |
1da177e4 LT |
1235 | break; |
1236 | ||
1237 | case PCI_CLASS_BRIDGE_PCI: | |
1238 | default: | |
9e8bf93a | 1239 | __pci_bus_size_bridges(b, realloc_head); |
1da177e4 LT |
1240 | break; |
1241 | } | |
1242 | } | |
1243 | ||
1244 | /* The root bus? */ | |
2ba29e27 | 1245 | if (pci_is_root_bus(bus)) |
1da177e4 LT |
1246 | return; |
1247 | ||
1248 | switch (bus->self->class >> 8) { | |
1249 | case PCI_CLASS_BRIDGE_CARDBUS: | |
1250 | /* don't size cardbuses yet. */ | |
1251 | break; | |
1252 | ||
1253 | case PCI_CLASS_BRIDGE_PCI: | |
1254 | pci_bridge_check_ranges(bus); | |
28760489 | 1255 | if (bus->self->is_hotplug_bridge) { |
c8adf9a3 RP |
1256 | additional_io_size = pci_hotplug_io_size; |
1257 | additional_mem_size = pci_hotplug_mem_size; | |
28760489 | 1258 | } |
67d29b5c | 1259 | /* Fall through */ |
1da177e4 | 1260 | default: |
19aa7ee4 YL |
1261 | pbus_size_io(bus, realloc_head ? 0 : additional_io_size, |
1262 | additional_io_size, realloc_head); | |
67d29b5c BH |
1263 | |
1264 | /* | |
1265 | * If there's a 64-bit prefetchable MMIO window, compute | |
1266 | * the size required to put all 64-bit prefetchable | |
1267 | * resources in it. | |
1268 | */ | |
5b285415 | 1269 | b_res = &bus->self->resource[PCI_BRIDGE_RESOURCES]; |
1da177e4 LT |
1270 | mask = IORESOURCE_MEM; |
1271 | prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
5b285415 YL |
1272 | if (b_res[2].flags & IORESOURCE_MEM_64) { |
1273 | prefmask |= IORESOURCE_MEM_64; | |
30afe8d0 | 1274 | ret = pbus_size_mem(bus, prefmask, prefmask, |
5b285415 | 1275 | prefmask, prefmask, |
19aa7ee4 | 1276 | realloc_head ? 0 : additional_mem_size, |
30afe8d0 | 1277 | additional_mem_size, realloc_head); |
67d29b5c BH |
1278 | |
1279 | /* | |
1280 | * If successful, all non-prefetchable resources | |
1281 | * and any 32-bit prefetchable resources will go in | |
1282 | * the non-prefetchable window. | |
1283 | */ | |
30afe8d0 | 1284 | if (ret == 0) { |
30afe8d0 BH |
1285 | mask = prefmask; |
1286 | type2 = prefmask & ~IORESOURCE_MEM_64; | |
1287 | type3 = prefmask & ~IORESOURCE_PREFETCH; | |
5b285415 YL |
1288 | } |
1289 | } | |
67d29b5c BH |
1290 | |
1291 | /* | |
1292 | * If there is no 64-bit prefetchable window, compute the | |
1293 | * size required to put all prefetchable resources in the | |
1294 | * 32-bit prefetchable window (if there is one). | |
1295 | */ | |
5b285415 YL |
1296 | if (!type2) { |
1297 | prefmask &= ~IORESOURCE_MEM_64; | |
30afe8d0 | 1298 | ret = pbus_size_mem(bus, prefmask, prefmask, |
5b285415 YL |
1299 | prefmask, prefmask, |
1300 | realloc_head ? 0 : additional_mem_size, | |
30afe8d0 | 1301 | additional_mem_size, realloc_head); |
67d29b5c BH |
1302 | |
1303 | /* | |
1304 | * If successful, only non-prefetchable resources | |
1305 | * will go in the non-prefetchable window. | |
1306 | */ | |
1307 | if (ret == 0) | |
5b285415 | 1308 | mask = prefmask; |
67d29b5c | 1309 | else |
5b285415 | 1310 | additional_mem_size += additional_mem_size; |
67d29b5c | 1311 | |
5b285415 YL |
1312 | type2 = type3 = IORESOURCE_MEM; |
1313 | } | |
67d29b5c BH |
1314 | |
1315 | /* | |
1316 | * Compute the size required to put everything else in the | |
1317 | * non-prefetchable window. This includes: | |
1318 | * | |
1319 | * - all non-prefetchable resources | |
1320 | * - 32-bit prefetchable resources if there's a 64-bit | |
1321 | * prefetchable window or no prefetchable window at all | |
1322 | * - 64-bit prefetchable resources if there's no | |
1323 | * prefetchable window at all | |
1324 | * | |
1325 | * Note that the strategy in __pci_assign_resource() must | |
1326 | * match that used here. Specifically, we cannot put a | |
1327 | * 32-bit prefetchable resource in a 64-bit prefetchable | |
1328 | * window. | |
1329 | */ | |
5b285415 | 1330 | pbus_size_mem(bus, mask, IORESOURCE_MEM, type2, type3, |
19aa7ee4 YL |
1331 | realloc_head ? 0 : additional_mem_size, |
1332 | additional_mem_size, realloc_head); | |
1da177e4 LT |
1333 | break; |
1334 | } | |
1335 | } | |
c8adf9a3 | 1336 | |
10874f5a | 1337 | void pci_bus_size_bridges(struct pci_bus *bus) |
c8adf9a3 RP |
1338 | { |
1339 | __pci_bus_size_bridges(bus, NULL); | |
1340 | } | |
1da177e4 LT |
1341 | EXPORT_SYMBOL(pci_bus_size_bridges); |
1342 | ||
d04d0111 DD |
1343 | static void assign_fixed_resource_on_bus(struct pci_bus *b, struct resource *r) |
1344 | { | |
1345 | int i; | |
1346 | struct resource *parent_r; | |
1347 | unsigned long mask = IORESOURCE_IO | IORESOURCE_MEM | | |
1348 | IORESOURCE_PREFETCH; | |
1349 | ||
1350 | pci_bus_for_each_resource(b, parent_r, i) { | |
1351 | if (!parent_r) | |
1352 | continue; | |
1353 | ||
1354 | if ((r->flags & mask) == (parent_r->flags & mask) && | |
1355 | resource_contains(parent_r, r)) | |
1356 | request_resource(parent_r, r); | |
1357 | } | |
1358 | } | |
1359 | ||
1360 | /* | |
1361 | * Try to assign any resources marked as IORESOURCE_PCI_FIXED, as they | |
1362 | * are skipped by pbus_assign_resources_sorted(). | |
1363 | */ | |
1364 | static void pdev_assign_fixed_resources(struct pci_dev *dev) | |
1365 | { | |
1366 | int i; | |
1367 | ||
1368 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
1369 | struct pci_bus *b; | |
1370 | struct resource *r = &dev->resource[i]; | |
1371 | ||
1372 | if (r->parent || !(r->flags & IORESOURCE_PCI_FIXED) || | |
1373 | !(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) | |
1374 | continue; | |
1375 | ||
1376 | b = dev->bus; | |
1377 | while (b && !r->parent) { | |
1378 | assign_fixed_resource_on_bus(b, r); | |
1379 | b = b->parent; | |
1380 | } | |
1381 | } | |
1382 | } | |
1383 | ||
10874f5a BH |
1384 | void __pci_bus_assign_resources(const struct pci_bus *bus, |
1385 | struct list_head *realloc_head, | |
1386 | struct list_head *fail_head) | |
1da177e4 LT |
1387 | { |
1388 | struct pci_bus *b; | |
1389 | struct pci_dev *dev; | |
1390 | ||
9e8bf93a | 1391 | pbus_assign_resources_sorted(bus, realloc_head, fail_head); |
1da177e4 | 1392 | |
1da177e4 | 1393 | list_for_each_entry(dev, &bus->devices, bus_list) { |
d04d0111 DD |
1394 | pdev_assign_fixed_resources(dev); |
1395 | ||
1da177e4 LT |
1396 | b = dev->subordinate; |
1397 | if (!b) | |
1398 | continue; | |
1399 | ||
9e8bf93a | 1400 | __pci_bus_assign_resources(b, realloc_head, fail_head); |
1da177e4 LT |
1401 | |
1402 | switch (dev->class >> 8) { | |
1403 | case PCI_CLASS_BRIDGE_PCI: | |
6841ec68 YL |
1404 | if (!pci_is_enabled(dev)) |
1405 | pci_setup_bridge(b); | |
1da177e4 LT |
1406 | break; |
1407 | ||
1408 | case PCI_CLASS_BRIDGE_CARDBUS: | |
1409 | pci_setup_cardbus(b); | |
1410 | break; | |
1411 | ||
1412 | default: | |
227f0647 RD |
1413 | dev_info(&dev->dev, "not setting up bridge for bus %04x:%02x\n", |
1414 | pci_domain_nr(b), b->number); | |
1da177e4 LT |
1415 | break; |
1416 | } | |
1417 | } | |
1418 | } | |
568ddef8 | 1419 | |
10874f5a | 1420 | void pci_bus_assign_resources(const struct pci_bus *bus) |
568ddef8 | 1421 | { |
c8adf9a3 | 1422 | __pci_bus_assign_resources(bus, NULL, NULL); |
568ddef8 | 1423 | } |
1da177e4 LT |
1424 | EXPORT_SYMBOL(pci_bus_assign_resources); |
1425 | ||
10874f5a BH |
1426 | static void __pci_bridge_assign_resources(const struct pci_dev *bridge, |
1427 | struct list_head *add_head, | |
1428 | struct list_head *fail_head) | |
6841ec68 YL |
1429 | { |
1430 | struct pci_bus *b; | |
1431 | ||
8424d759 YL |
1432 | pdev_assign_resources_sorted((struct pci_dev *)bridge, |
1433 | add_head, fail_head); | |
6841ec68 YL |
1434 | |
1435 | b = bridge->subordinate; | |
1436 | if (!b) | |
1437 | return; | |
1438 | ||
8424d759 | 1439 | __pci_bus_assign_resources(b, add_head, fail_head); |
6841ec68 YL |
1440 | |
1441 | switch (bridge->class >> 8) { | |
1442 | case PCI_CLASS_BRIDGE_PCI: | |
1443 | pci_setup_bridge(b); | |
1444 | break; | |
1445 | ||
1446 | case PCI_CLASS_BRIDGE_CARDBUS: | |
1447 | pci_setup_cardbus(b); | |
1448 | break; | |
1449 | ||
1450 | default: | |
227f0647 RD |
1451 | dev_info(&bridge->dev, "not setting up bridge for bus %04x:%02x\n", |
1452 | pci_domain_nr(b), b->number); | |
6841ec68 YL |
1453 | break; |
1454 | } | |
1455 | } | |
5009b460 YL |
1456 | static void pci_bridge_release_resources(struct pci_bus *bus, |
1457 | unsigned long type) | |
1458 | { | |
5b285415 | 1459 | struct pci_dev *dev = bus->self; |
5009b460 YL |
1460 | struct resource *r; |
1461 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | | |
5b285415 YL |
1462 | IORESOURCE_PREFETCH | IORESOURCE_MEM_64; |
1463 | unsigned old_flags = 0; | |
1464 | struct resource *b_res; | |
1465 | int idx = 1; | |
5009b460 | 1466 | |
5b285415 YL |
1467 | b_res = &dev->resource[PCI_BRIDGE_RESOURCES]; |
1468 | ||
1469 | /* | |
1470 | * 1. if there is io port assign fail, will release bridge | |
1471 | * io port. | |
1472 | * 2. if there is non pref mmio assign fail, release bridge | |
1473 | * nonpref mmio. | |
1474 | * 3. if there is 64bit pref mmio assign fail, and bridge pref | |
1475 | * is 64bit, release bridge pref mmio. | |
1476 | * 4. if there is pref mmio assign fail, and bridge pref is | |
1477 | * 32bit mmio, release bridge pref mmio | |
1478 | * 5. if there is pref mmio assign fail, and bridge pref is not | |
1479 | * assigned, release bridge nonpref mmio. | |
1480 | */ | |
1481 | if (type & IORESOURCE_IO) | |
1482 | idx = 0; | |
1483 | else if (!(type & IORESOURCE_PREFETCH)) | |
1484 | idx = 1; | |
1485 | else if ((type & IORESOURCE_MEM_64) && | |
1486 | (b_res[2].flags & IORESOURCE_MEM_64)) | |
1487 | idx = 2; | |
1488 | else if (!(b_res[2].flags & IORESOURCE_MEM_64) && | |
1489 | (b_res[2].flags & IORESOURCE_PREFETCH)) | |
1490 | idx = 2; | |
1491 | else | |
1492 | idx = 1; | |
1493 | ||
1494 | r = &b_res[idx]; | |
1495 | ||
1496 | if (!r->parent) | |
1497 | return; | |
1498 | ||
1499 | /* | |
1500 | * if there are children under that, we should release them | |
1501 | * all | |
1502 | */ | |
1503 | release_child_resources(r); | |
1504 | if (!release_resource(r)) { | |
1505 | type = old_flags = r->flags & type_mask; | |
1506 | dev_printk(KERN_DEBUG, &dev->dev, "resource %d %pR released\n", | |
1507 | PCI_BRIDGE_RESOURCES + idx, r); | |
1508 | /* keep the old size */ | |
1509 | r->end = resource_size(r) - 1; | |
1510 | r->start = 0; | |
1511 | r->flags = 0; | |
5009b460 | 1512 | |
5009b460 YL |
1513 | /* avoiding touch the one without PREF */ |
1514 | if (type & IORESOURCE_PREFETCH) | |
1515 | type = IORESOURCE_PREFETCH; | |
1516 | __pci_setup_bridge(bus, type); | |
5b285415 YL |
1517 | /* for next child res under same bridge */ |
1518 | r->flags = old_flags; | |
5009b460 YL |
1519 | } |
1520 | } | |
1521 | ||
1522 | enum release_type { | |
1523 | leaf_only, | |
1524 | whole_subtree, | |
1525 | }; | |
1526 | /* | |
1527 | * try to release pci bridge resources that is from leaf bridge, | |
1528 | * so we can allocate big new one later | |
1529 | */ | |
10874f5a BH |
1530 | static void pci_bus_release_bridge_resources(struct pci_bus *bus, |
1531 | unsigned long type, | |
1532 | enum release_type rel_type) | |
5009b460 YL |
1533 | { |
1534 | struct pci_dev *dev; | |
1535 | bool is_leaf_bridge = true; | |
1536 | ||
1537 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1538 | struct pci_bus *b = dev->subordinate; | |
1539 | if (!b) | |
1540 | continue; | |
1541 | ||
1542 | is_leaf_bridge = false; | |
1543 | ||
1544 | if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) | |
1545 | continue; | |
1546 | ||
1547 | if (rel_type == whole_subtree) | |
1548 | pci_bus_release_bridge_resources(b, type, | |
1549 | whole_subtree); | |
1550 | } | |
1551 | ||
1552 | if (pci_is_root_bus(bus)) | |
1553 | return; | |
1554 | ||
1555 | if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI) | |
1556 | return; | |
1557 | ||
1558 | if ((rel_type == whole_subtree) || is_leaf_bridge) | |
1559 | pci_bridge_release_resources(bus, type); | |
1560 | } | |
1561 | ||
76fbc263 YL |
1562 | static void pci_bus_dump_res(struct pci_bus *bus) |
1563 | { | |
89a74ecc BH |
1564 | struct resource *res; |
1565 | int i; | |
7c9342b8 | 1566 | |
89a74ecc | 1567 | pci_bus_for_each_resource(bus, res, i) { |
7c9342b8 | 1568 | if (!res || !res->end || !res->flags) |
3c78bc61 | 1569 | continue; |
76fbc263 | 1570 | |
c7dabef8 | 1571 | dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res); |
3c78bc61 | 1572 | } |
76fbc263 YL |
1573 | } |
1574 | ||
1575 | static void pci_bus_dump_resources(struct pci_bus *bus) | |
1576 | { | |
1577 | struct pci_bus *b; | |
1578 | struct pci_dev *dev; | |
1579 | ||
1580 | ||
1581 | pci_bus_dump_res(bus); | |
1582 | ||
1583 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1584 | b = dev->subordinate; | |
1585 | if (!b) | |
1586 | continue; | |
1587 | ||
1588 | pci_bus_dump_resources(b); | |
1589 | } | |
1590 | } | |
1591 | ||
ff35147c | 1592 | static int pci_bus_get_depth(struct pci_bus *bus) |
da7822e5 YL |
1593 | { |
1594 | int depth = 0; | |
f2a230bd | 1595 | struct pci_bus *child_bus; |
da7822e5 | 1596 | |
3c78bc61 | 1597 | list_for_each_entry(child_bus, &bus->children, node) { |
da7822e5 | 1598 | int ret; |
da7822e5 | 1599 | |
f2a230bd | 1600 | ret = pci_bus_get_depth(child_bus); |
da7822e5 YL |
1601 | if (ret + 1 > depth) |
1602 | depth = ret + 1; | |
1603 | } | |
1604 | ||
1605 | return depth; | |
1606 | } | |
da7822e5 | 1607 | |
b55438fd YL |
1608 | /* |
1609 | * -1: undefined, will auto detect later | |
1610 | * 0: disabled by user | |
1611 | * 1: disabled by auto detect | |
1612 | * 2: enabled by user | |
1613 | * 3: enabled by auto detect | |
1614 | */ | |
1615 | enum enable_type { | |
1616 | undefined = -1, | |
1617 | user_disabled, | |
1618 | auto_disabled, | |
1619 | user_enabled, | |
1620 | auto_enabled, | |
1621 | }; | |
1622 | ||
ff35147c | 1623 | static enum enable_type pci_realloc_enable = undefined; |
b55438fd YL |
1624 | void __init pci_realloc_get_opt(char *str) |
1625 | { | |
1626 | if (!strncmp(str, "off", 3)) | |
1627 | pci_realloc_enable = user_disabled; | |
1628 | else if (!strncmp(str, "on", 2)) | |
1629 | pci_realloc_enable = user_enabled; | |
1630 | } | |
ff35147c | 1631 | static bool pci_realloc_enabled(enum enable_type enable) |
b55438fd | 1632 | { |
967260cd | 1633 | return enable >= user_enabled; |
b55438fd | 1634 | } |
f483d392 | 1635 | |
b07f2ebc | 1636 | #if defined(CONFIG_PCI_IOV) && defined(CONFIG_PCI_REALLOC_ENABLE_AUTO) |
ff35147c | 1637 | static int iov_resources_unassigned(struct pci_dev *dev, void *data) |
223d96fc YL |
1638 | { |
1639 | int i; | |
1640 | bool *unassigned = data; | |
b07f2ebc | 1641 | |
223d96fc YL |
1642 | for (i = PCI_IOV_RESOURCES; i <= PCI_IOV_RESOURCE_END; i++) { |
1643 | struct resource *r = &dev->resource[i]; | |
fa216bf4 | 1644 | struct pci_bus_region region; |
b07f2ebc | 1645 | |
223d96fc | 1646 | /* Not assigned or rejected by kernel? */ |
fa216bf4 YL |
1647 | if (!r->flags) |
1648 | continue; | |
b07f2ebc | 1649 | |
fc279850 | 1650 | pcibios_resource_to_bus(dev->bus, ®ion, r); |
fa216bf4 | 1651 | if (!region.start) { |
223d96fc YL |
1652 | *unassigned = true; |
1653 | return 1; /* return early from pci_walk_bus() */ | |
b07f2ebc YL |
1654 | } |
1655 | } | |
b07f2ebc | 1656 | |
223d96fc | 1657 | return 0; |
b07f2ebc YL |
1658 | } |
1659 | ||
ff35147c | 1660 | static enum enable_type pci_realloc_detect(struct pci_bus *bus, |
967260cd | 1661 | enum enable_type enable_local) |
223d96fc YL |
1662 | { |
1663 | bool unassigned = false; | |
b07f2ebc | 1664 | |
967260cd YL |
1665 | if (enable_local != undefined) |
1666 | return enable_local; | |
223d96fc | 1667 | |
967260cd YL |
1668 | pci_walk_bus(bus, iov_resources_unassigned, &unassigned); |
1669 | if (unassigned) | |
1670 | return auto_enabled; | |
1671 | ||
1672 | return enable_local; | |
b07f2ebc | 1673 | } |
223d96fc | 1674 | #else |
ff35147c | 1675 | static enum enable_type pci_realloc_detect(struct pci_bus *bus, |
967260cd YL |
1676 | enum enable_type enable_local) |
1677 | { | |
1678 | return enable_local; | |
b07f2ebc | 1679 | } |
223d96fc | 1680 | #endif |
b07f2ebc | 1681 | |
da7822e5 YL |
1682 | /* |
1683 | * first try will not touch pci bridge res | |
f7625980 BH |
1684 | * second and later try will clear small leaf bridge res |
1685 | * will stop till to the max depth if can not find good one | |
da7822e5 | 1686 | */ |
39772038 | 1687 | void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus) |
1da177e4 | 1688 | { |
bdc4abec | 1689 | LIST_HEAD(realloc_head); /* list of resources that |
c8adf9a3 | 1690 | want additional resources */ |
bdc4abec | 1691 | struct list_head *add_list = NULL; |
da7822e5 YL |
1692 | int tried_times = 0; |
1693 | enum release_type rel_type = leaf_only; | |
bdc4abec | 1694 | LIST_HEAD(fail_head); |
b9b0bba9 | 1695 | struct pci_dev_resource *fail_res; |
da7822e5 | 1696 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | |
5b285415 | 1697 | IORESOURCE_PREFETCH | IORESOURCE_MEM_64; |
19aa7ee4 | 1698 | int pci_try_num = 1; |
55ed83a6 | 1699 | enum enable_type enable_local; |
da7822e5 | 1700 | |
19aa7ee4 | 1701 | /* don't realloc if asked to do so */ |
55ed83a6 | 1702 | enable_local = pci_realloc_detect(bus, pci_realloc_enable); |
967260cd | 1703 | if (pci_realloc_enabled(enable_local)) { |
55ed83a6 | 1704 | int max_depth = pci_bus_get_depth(bus); |
19aa7ee4 YL |
1705 | |
1706 | pci_try_num = max_depth + 1; | |
55ed83a6 YL |
1707 | dev_printk(KERN_DEBUG, &bus->dev, |
1708 | "max bus depth: %d pci_try_num: %d\n", | |
1709 | max_depth, pci_try_num); | |
19aa7ee4 | 1710 | } |
da7822e5 YL |
1711 | |
1712 | again: | |
19aa7ee4 YL |
1713 | /* |
1714 | * last try will use add_list, otherwise will try good to have as | |
1715 | * must have, so can realloc parent bridge resource | |
1716 | */ | |
1717 | if (tried_times + 1 == pci_try_num) | |
bdc4abec | 1718 | add_list = &realloc_head; |
1da177e4 LT |
1719 | /* Depth first, calculate sizes and alignments of all |
1720 | subordinate buses. */ | |
55ed83a6 | 1721 | __pci_bus_size_bridges(bus, add_list); |
c8adf9a3 | 1722 | |
1da177e4 | 1723 | /* Depth last, allocate resources and update the hardware. */ |
55ed83a6 | 1724 | __pci_bus_assign_resources(bus, add_list, &fail_head); |
19aa7ee4 | 1725 | if (add_list) |
bdc4abec | 1726 | BUG_ON(!list_empty(add_list)); |
da7822e5 YL |
1727 | tried_times++; |
1728 | ||
1729 | /* any device complain? */ | |
bdc4abec | 1730 | if (list_empty(&fail_head)) |
928bea96 | 1731 | goto dump; |
f483d392 | 1732 | |
0c5be0cb | 1733 | if (tried_times >= pci_try_num) { |
967260cd | 1734 | if (enable_local == undefined) |
55ed83a6 | 1735 | dev_info(&bus->dev, "Some PCI device resources are unassigned, try booting with pci=realloc\n"); |
967260cd | 1736 | else if (enable_local == auto_enabled) |
55ed83a6 | 1737 | dev_info(&bus->dev, "Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n"); |
eb572e7c | 1738 | |
bffc56d4 | 1739 | free_list(&fail_head); |
928bea96 | 1740 | goto dump; |
da7822e5 YL |
1741 | } |
1742 | ||
55ed83a6 YL |
1743 | dev_printk(KERN_DEBUG, &bus->dev, |
1744 | "No. %d try to assign unassigned res\n", tried_times + 1); | |
da7822e5 YL |
1745 | |
1746 | /* third times and later will not check if it is leaf */ | |
1747 | if ((tried_times + 1) > 2) | |
1748 | rel_type = whole_subtree; | |
1749 | ||
1750 | /* | |
1751 | * Try to release leaf bridge's resources that doesn't fit resource of | |
1752 | * child device under that bridge | |
1753 | */ | |
61e83cdd YL |
1754 | list_for_each_entry(fail_res, &fail_head, list) |
1755 | pci_bus_release_bridge_resources(fail_res->dev->bus, | |
b9b0bba9 | 1756 | fail_res->flags & type_mask, |
bdc4abec | 1757 | rel_type); |
61e83cdd | 1758 | |
da7822e5 | 1759 | /* restore size and flags */ |
b9b0bba9 YL |
1760 | list_for_each_entry(fail_res, &fail_head, list) { |
1761 | struct resource *res = fail_res->res; | |
da7822e5 | 1762 | |
b9b0bba9 YL |
1763 | res->start = fail_res->start; |
1764 | res->end = fail_res->end; | |
1765 | res->flags = fail_res->flags; | |
1766 | if (fail_res->dev->subordinate) | |
da7822e5 | 1767 | res->flags = 0; |
da7822e5 | 1768 | } |
bffc56d4 | 1769 | free_list(&fail_head); |
da7822e5 YL |
1770 | |
1771 | goto again; | |
1772 | ||
928bea96 | 1773 | dump: |
76fbc263 | 1774 | /* dump the resource on buses */ |
55ed83a6 YL |
1775 | pci_bus_dump_resources(bus); |
1776 | } | |
1777 | ||
1778 | void __init pci_assign_unassigned_resources(void) | |
1779 | { | |
1780 | struct pci_bus *root_bus; | |
1781 | ||
1782 | list_for_each_entry(root_bus, &pci_root_buses, node) | |
1783 | pci_assign_unassigned_root_bus_resources(root_bus); | |
1da177e4 | 1784 | } |
6841ec68 YL |
1785 | |
1786 | void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge) | |
1787 | { | |
1788 | struct pci_bus *parent = bridge->subordinate; | |
bdc4abec | 1789 | LIST_HEAD(add_list); /* list of resources that |
8424d759 | 1790 | want additional resources */ |
32180e40 | 1791 | int tried_times = 0; |
bdc4abec | 1792 | LIST_HEAD(fail_head); |
b9b0bba9 | 1793 | struct pci_dev_resource *fail_res; |
6841ec68 | 1794 | int retval; |
32180e40 | 1795 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | |
d61b0e87 | 1796 | IORESOURCE_PREFETCH | IORESOURCE_MEM_64; |
32180e40 | 1797 | |
32180e40 | 1798 | again: |
8424d759 | 1799 | __pci_bus_size_bridges(parent, &add_list); |
bdc4abec YL |
1800 | __pci_bridge_assign_resources(bridge, &add_list, &fail_head); |
1801 | BUG_ON(!list_empty(&add_list)); | |
32180e40 YL |
1802 | tried_times++; |
1803 | ||
bdc4abec | 1804 | if (list_empty(&fail_head)) |
3f579c34 | 1805 | goto enable_all; |
32180e40 YL |
1806 | |
1807 | if (tried_times >= 2) { | |
1808 | /* still fail, don't need to try more */ | |
bffc56d4 | 1809 | free_list(&fail_head); |
3f579c34 | 1810 | goto enable_all; |
32180e40 YL |
1811 | } |
1812 | ||
1813 | printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n", | |
1814 | tried_times + 1); | |
1815 | ||
1816 | /* | |
1817 | * Try to release leaf bridge's resources that doesn't fit resource of | |
1818 | * child device under that bridge | |
1819 | */ | |
61e83cdd YL |
1820 | list_for_each_entry(fail_res, &fail_head, list) |
1821 | pci_bus_release_bridge_resources(fail_res->dev->bus, | |
1822 | fail_res->flags & type_mask, | |
32180e40 | 1823 | whole_subtree); |
61e83cdd | 1824 | |
32180e40 | 1825 | /* restore size and flags */ |
b9b0bba9 YL |
1826 | list_for_each_entry(fail_res, &fail_head, list) { |
1827 | struct resource *res = fail_res->res; | |
32180e40 | 1828 | |
b9b0bba9 YL |
1829 | res->start = fail_res->start; |
1830 | res->end = fail_res->end; | |
1831 | res->flags = fail_res->flags; | |
1832 | if (fail_res->dev->subordinate) | |
32180e40 | 1833 | res->flags = 0; |
32180e40 | 1834 | } |
bffc56d4 | 1835 | free_list(&fail_head); |
32180e40 YL |
1836 | |
1837 | goto again; | |
3f579c34 YL |
1838 | |
1839 | enable_all: | |
1840 | retval = pci_reenable_device(bridge); | |
9fc9eea0 BH |
1841 | if (retval) |
1842 | dev_err(&bridge->dev, "Error reenabling bridge (%d)\n", retval); | |
3f579c34 | 1843 | pci_set_master(bridge); |
6841ec68 YL |
1844 | } |
1845 | EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources); | |
9b03088f | 1846 | |
17787940 | 1847 | void pci_assign_unassigned_bus_resources(struct pci_bus *bus) |
9b03088f | 1848 | { |
9b03088f | 1849 | struct pci_dev *dev; |
bdc4abec | 1850 | LIST_HEAD(add_list); /* list of resources that |
9b03088f YL |
1851 | want additional resources */ |
1852 | ||
9b03088f YL |
1853 | down_read(&pci_bus_sem); |
1854 | list_for_each_entry(dev, &bus->devices, bus_list) | |
6788a51f | 1855 | if (pci_is_bridge(dev) && pci_has_subordinate(dev)) |
9b03088f YL |
1856 | __pci_bus_size_bridges(dev->subordinate, |
1857 | &add_list); | |
1858 | up_read(&pci_bus_sem); | |
1859 | __pci_bus_assign_resources(bus, &add_list, NULL); | |
bdc4abec | 1860 | BUG_ON(!list_empty(&add_list)); |
17787940 | 1861 | } |
e6b29dea | 1862 | EXPORT_SYMBOL_GPL(pci_assign_unassigned_bus_resources); |