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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * drivers/pci/setup-bus.c | |
3 | * | |
4 | * Extruded from code written by | |
5 | * Dave Rusling (david.rusling@reo.mts.dec.com) | |
6 | * David Mosberger (davidm@cs.arizona.edu) | |
7 | * David Miller (davem@redhat.com) | |
8 | * | |
9 | * Support routines for initializing a PCI subsystem. | |
10 | */ | |
11 | ||
12 | /* | |
13 | * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> | |
14 | * PCI-PCI bridges cleanup, sorted resource allocation. | |
15 | * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru> | |
16 | * Converted to allocation in 3 passes, which gives | |
17 | * tighter packing. Prefetchable range support. | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/pci.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/ioport.h> | |
26 | #include <linux/cache.h> | |
27 | #include <linux/slab.h> | |
584c5c42 | 28 | #include <linux/acpi.h> |
6faf17f6 | 29 | #include "pci.h" |
1da177e4 | 30 | |
844393f4 | 31 | unsigned int pci_flags; |
47087700 | 32 | |
bdc4abec YL |
33 | struct pci_dev_resource { |
34 | struct list_head list; | |
2934a0de YL |
35 | struct resource *res; |
36 | struct pci_dev *dev; | |
568ddef8 YL |
37 | resource_size_t start; |
38 | resource_size_t end; | |
c8adf9a3 | 39 | resource_size_t add_size; |
2bbc6942 | 40 | resource_size_t min_align; |
568ddef8 YL |
41 | unsigned long flags; |
42 | }; | |
43 | ||
bffc56d4 YL |
44 | static void free_list(struct list_head *head) |
45 | { | |
46 | struct pci_dev_resource *dev_res, *tmp; | |
47 | ||
48 | list_for_each_entry_safe(dev_res, tmp, head, list) { | |
49 | list_del(&dev_res->list); | |
50 | kfree(dev_res); | |
51 | } | |
52 | } | |
094732a5 | 53 | |
c8adf9a3 RP |
54 | /** |
55 | * add_to_list() - add a new resource tracker to the list | |
56 | * @head: Head of the list | |
57 | * @dev: device corresponding to which the resource | |
58 | * belongs | |
59 | * @res: The resource to be tracked | |
60 | * @add_size: additional size to be optionally added | |
61 | * to the resource | |
62 | */ | |
bdc4abec | 63 | static int add_to_list(struct list_head *head, |
c8adf9a3 | 64 | struct pci_dev *dev, struct resource *res, |
2bbc6942 | 65 | resource_size_t add_size, resource_size_t min_align) |
568ddef8 | 66 | { |
764242a0 | 67 | struct pci_dev_resource *tmp; |
568ddef8 | 68 | |
bdc4abec | 69 | tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); |
568ddef8 | 70 | if (!tmp) { |
3c78bc61 | 71 | pr_warn("add_to_list: kmalloc() failed!\n"); |
ef62dfef | 72 | return -ENOMEM; |
568ddef8 YL |
73 | } |
74 | ||
568ddef8 YL |
75 | tmp->res = res; |
76 | tmp->dev = dev; | |
77 | tmp->start = res->start; | |
78 | tmp->end = res->end; | |
79 | tmp->flags = res->flags; | |
c8adf9a3 | 80 | tmp->add_size = add_size; |
2bbc6942 | 81 | tmp->min_align = min_align; |
bdc4abec YL |
82 | |
83 | list_add(&tmp->list, head); | |
ef62dfef YL |
84 | |
85 | return 0; | |
568ddef8 YL |
86 | } |
87 | ||
b9b0bba9 | 88 | static void remove_from_list(struct list_head *head, |
3e6e0d80 YL |
89 | struct resource *res) |
90 | { | |
b9b0bba9 | 91 | struct pci_dev_resource *dev_res, *tmp; |
3e6e0d80 | 92 | |
b9b0bba9 YL |
93 | list_for_each_entry_safe(dev_res, tmp, head, list) { |
94 | if (dev_res->res == res) { | |
95 | list_del(&dev_res->list); | |
96 | kfree(dev_res); | |
bdc4abec | 97 | break; |
3e6e0d80 | 98 | } |
3e6e0d80 YL |
99 | } |
100 | } | |
101 | ||
d74b9027 WY |
102 | static struct pci_dev_resource *res_to_dev_res(struct list_head *head, |
103 | struct resource *res) | |
1c372353 | 104 | { |
b9b0bba9 | 105 | struct pci_dev_resource *dev_res; |
bdc4abec | 106 | |
b9b0bba9 | 107 | list_for_each_entry(dev_res, head, list) { |
25e77388 | 108 | if (dev_res->res == res) |
d74b9027 | 109 | return dev_res; |
3e6e0d80 | 110 | } |
1c372353 | 111 | |
d74b9027 | 112 | return NULL; |
1c372353 YL |
113 | } |
114 | ||
d74b9027 WY |
115 | static resource_size_t get_res_add_size(struct list_head *head, |
116 | struct resource *res) | |
117 | { | |
118 | struct pci_dev_resource *dev_res; | |
119 | ||
120 | dev_res = res_to_dev_res(head, res); | |
121 | return dev_res ? dev_res->add_size : 0; | |
122 | } | |
123 | ||
124 | static resource_size_t get_res_add_align(struct list_head *head, | |
125 | struct resource *res) | |
126 | { | |
127 | struct pci_dev_resource *dev_res; | |
128 | ||
129 | dev_res = res_to_dev_res(head, res); | |
130 | return dev_res ? dev_res->min_align : 0; | |
131 | } | |
132 | ||
133 | ||
78c3b329 | 134 | /* Sort resources by alignment */ |
bdc4abec | 135 | static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head) |
78c3b329 YL |
136 | { |
137 | int i; | |
138 | ||
139 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
140 | struct resource *r; | |
bdc4abec | 141 | struct pci_dev_resource *dev_res, *tmp; |
78c3b329 | 142 | resource_size_t r_align; |
bdc4abec | 143 | struct list_head *n; |
78c3b329 YL |
144 | |
145 | r = &dev->resource[i]; | |
146 | ||
147 | if (r->flags & IORESOURCE_PCI_FIXED) | |
148 | continue; | |
149 | ||
150 | if (!(r->flags) || r->parent) | |
151 | continue; | |
152 | ||
153 | r_align = pci_resource_alignment(dev, r); | |
154 | if (!r_align) { | |
155 | dev_warn(&dev->dev, "BAR %d: %pR has bogus alignment\n", | |
156 | i, r); | |
157 | continue; | |
158 | } | |
78c3b329 | 159 | |
bdc4abec YL |
160 | tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); |
161 | if (!tmp) | |
227f0647 | 162 | panic("pdev_sort_resources(): kmalloc() failed!\n"); |
bdc4abec YL |
163 | tmp->res = r; |
164 | tmp->dev = dev; | |
165 | ||
166 | /* fallback is smallest one or list is empty*/ | |
167 | n = head; | |
168 | list_for_each_entry(dev_res, head, list) { | |
169 | resource_size_t align; | |
170 | ||
171 | align = pci_resource_alignment(dev_res->dev, | |
172 | dev_res->res); | |
78c3b329 YL |
173 | |
174 | if (r_align > align) { | |
bdc4abec | 175 | n = &dev_res->list; |
78c3b329 YL |
176 | break; |
177 | } | |
178 | } | |
bdc4abec YL |
179 | /* Insert it just before n*/ |
180 | list_add_tail(&tmp->list, n); | |
78c3b329 YL |
181 | } |
182 | } | |
183 | ||
6841ec68 | 184 | static void __dev_sort_resources(struct pci_dev *dev, |
bdc4abec | 185 | struct list_head *head) |
1da177e4 | 186 | { |
6841ec68 | 187 | u16 class = dev->class >> 8; |
1da177e4 | 188 | |
6841ec68 YL |
189 | /* Don't touch classless devices or host bridges or ioapics. */ |
190 | if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST) | |
191 | return; | |
1da177e4 | 192 | |
6841ec68 YL |
193 | /* Don't touch ioapic devices already enabled by firmware */ |
194 | if (class == PCI_CLASS_SYSTEM_PIC) { | |
195 | u16 command; | |
196 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
197 | if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | |
198 | return; | |
199 | } | |
1da177e4 | 200 | |
6841ec68 YL |
201 | pdev_sort_resources(dev, head); |
202 | } | |
23186279 | 203 | |
fc075e1d RP |
204 | static inline void reset_resource(struct resource *res) |
205 | { | |
206 | res->start = 0; | |
207 | res->end = 0; | |
208 | res->flags = 0; | |
209 | } | |
210 | ||
c8adf9a3 | 211 | /** |
9e8bf93a | 212 | * reassign_resources_sorted() - satisfy any additional resource requests |
c8adf9a3 | 213 | * |
9e8bf93a | 214 | * @realloc_head : head of the list tracking requests requiring additional |
c8adf9a3 RP |
215 | * resources |
216 | * @head : head of the list tracking requests with allocated | |
217 | * resources | |
218 | * | |
9e8bf93a | 219 | * Walk through each element of the realloc_head and try to procure |
c8adf9a3 RP |
220 | * additional resources for the element, provided the element |
221 | * is in the head list. | |
222 | */ | |
bdc4abec YL |
223 | static void reassign_resources_sorted(struct list_head *realloc_head, |
224 | struct list_head *head) | |
6841ec68 YL |
225 | { |
226 | struct resource *res; | |
b9b0bba9 | 227 | struct pci_dev_resource *add_res, *tmp; |
bdc4abec | 228 | struct pci_dev_resource *dev_res; |
d74b9027 | 229 | resource_size_t add_size, align; |
6841ec68 | 230 | int idx; |
1da177e4 | 231 | |
b9b0bba9 | 232 | list_for_each_entry_safe(add_res, tmp, realloc_head, list) { |
bdc4abec YL |
233 | bool found_match = false; |
234 | ||
b9b0bba9 | 235 | res = add_res->res; |
c8adf9a3 RP |
236 | /* skip resource that has been reset */ |
237 | if (!res->flags) | |
238 | goto out; | |
239 | ||
240 | /* skip this resource if not found in head list */ | |
bdc4abec YL |
241 | list_for_each_entry(dev_res, head, list) { |
242 | if (dev_res->res == res) { | |
243 | found_match = true; | |
244 | break; | |
245 | } | |
c8adf9a3 | 246 | } |
bdc4abec YL |
247 | if (!found_match)/* just skip */ |
248 | continue; | |
c8adf9a3 | 249 | |
b9b0bba9 YL |
250 | idx = res - &add_res->dev->resource[0]; |
251 | add_size = add_res->add_size; | |
d74b9027 | 252 | align = add_res->min_align; |
2bbc6942 | 253 | if (!resource_size(res)) { |
d74b9027 | 254 | res->start = align; |
2bbc6942 | 255 | res->end = res->start + add_size - 1; |
b9b0bba9 | 256 | if (pci_assign_resource(add_res->dev, idx)) |
c8adf9a3 | 257 | reset_resource(res); |
2bbc6942 | 258 | } else { |
b9b0bba9 | 259 | res->flags |= add_res->flags & |
bdc4abec | 260 | (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN); |
b9b0bba9 | 261 | if (pci_reassign_resource(add_res->dev, idx, |
bdc4abec | 262 | add_size, align)) |
b9b0bba9 | 263 | dev_printk(KERN_DEBUG, &add_res->dev->dev, |
b592443d YL |
264 | "failed to add %llx res[%d]=%pR\n", |
265 | (unsigned long long)add_size, | |
266 | idx, res); | |
c8adf9a3 RP |
267 | } |
268 | out: | |
b9b0bba9 YL |
269 | list_del(&add_res->list); |
270 | kfree(add_res); | |
c8adf9a3 RP |
271 | } |
272 | } | |
273 | ||
274 | /** | |
275 | * assign_requested_resources_sorted() - satisfy resource requests | |
276 | * | |
277 | * @head : head of the list tracking requests for resources | |
8356aad4 | 278 | * @fail_head : head of the list tracking requests that could |
c8adf9a3 RP |
279 | * not be allocated |
280 | * | |
281 | * Satisfy resource requests of each element in the list. Add | |
282 | * requests that could not satisfied to the failed_list. | |
283 | */ | |
bdc4abec YL |
284 | static void assign_requested_resources_sorted(struct list_head *head, |
285 | struct list_head *fail_head) | |
c8adf9a3 RP |
286 | { |
287 | struct resource *res; | |
bdc4abec | 288 | struct pci_dev_resource *dev_res; |
c8adf9a3 | 289 | int idx; |
9a928660 | 290 | |
bdc4abec YL |
291 | list_for_each_entry(dev_res, head, list) { |
292 | res = dev_res->res; | |
293 | idx = res - &dev_res->dev->resource[0]; | |
294 | if (resource_size(res) && | |
295 | pci_assign_resource(dev_res->dev, idx)) { | |
a3cb999d | 296 | if (fail_head) { |
9a928660 YL |
297 | /* |
298 | * if the failed res is for ROM BAR, and it will | |
299 | * be enabled later, don't add it to the list | |
300 | */ | |
301 | if (!((idx == PCI_ROM_RESOURCE) && | |
302 | (!(res->flags & IORESOURCE_ROM_ENABLE)))) | |
67cc7e26 YL |
303 | add_to_list(fail_head, |
304 | dev_res->dev, res, | |
f7625980 BH |
305 | 0 /* don't care */, |
306 | 0 /* don't care */); | |
9a928660 | 307 | } |
fc075e1d | 308 | reset_resource(res); |
542df5de | 309 | } |
1da177e4 LT |
310 | } |
311 | } | |
312 | ||
aa914f5e YL |
313 | static unsigned long pci_fail_res_type_mask(struct list_head *fail_head) |
314 | { | |
315 | struct pci_dev_resource *fail_res; | |
316 | unsigned long mask = 0; | |
317 | ||
318 | /* check failed type */ | |
319 | list_for_each_entry(fail_res, fail_head, list) | |
320 | mask |= fail_res->flags; | |
321 | ||
322 | /* | |
323 | * one pref failed resource will set IORESOURCE_MEM, | |
324 | * as we can allocate pref in non-pref range. | |
325 | * Will release all assigned non-pref sibling resources | |
326 | * according to that bit. | |
327 | */ | |
328 | return mask & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH); | |
329 | } | |
330 | ||
331 | static bool pci_need_to_release(unsigned long mask, struct resource *res) | |
332 | { | |
333 | if (res->flags & IORESOURCE_IO) | |
334 | return !!(mask & IORESOURCE_IO); | |
335 | ||
336 | /* check pref at first */ | |
337 | if (res->flags & IORESOURCE_PREFETCH) { | |
338 | if (mask & IORESOURCE_PREFETCH) | |
339 | return true; | |
340 | /* count pref if its parent is non-pref */ | |
341 | else if ((mask & IORESOURCE_MEM) && | |
342 | !(res->parent->flags & IORESOURCE_PREFETCH)) | |
343 | return true; | |
344 | else | |
345 | return false; | |
346 | } | |
347 | ||
348 | if (res->flags & IORESOURCE_MEM) | |
349 | return !!(mask & IORESOURCE_MEM); | |
350 | ||
351 | return false; /* should not get here */ | |
352 | } | |
353 | ||
bdc4abec YL |
354 | static void __assign_resources_sorted(struct list_head *head, |
355 | struct list_head *realloc_head, | |
356 | struct list_head *fail_head) | |
c8adf9a3 | 357 | { |
3e6e0d80 YL |
358 | /* |
359 | * Should not assign requested resources at first. | |
360 | * they could be adjacent, so later reassign can not reallocate | |
361 | * them one by one in parent resource window. | |
367fa982 | 362 | * Try to assign requested + add_size at beginning |
3e6e0d80 YL |
363 | * if could do that, could get out early. |
364 | * if could not do that, we still try to assign requested at first, | |
365 | * then try to reassign add_size for some resources. | |
aa914f5e YL |
366 | * |
367 | * Separate three resource type checking if we need to release | |
368 | * assigned resource after requested + add_size try. | |
369 | * 1. if there is io port assign fail, will release assigned | |
370 | * io port. | |
371 | * 2. if there is pref mmio assign fail, release assigned | |
372 | * pref mmio. | |
373 | * if assigned pref mmio's parent is non-pref mmio and there | |
374 | * is non-pref mmio assign fail, will release that assigned | |
375 | * pref mmio. | |
376 | * 3. if there is non-pref mmio assign fail or pref mmio | |
377 | * assigned fail, will release assigned non-pref mmio. | |
3e6e0d80 | 378 | */ |
bdc4abec YL |
379 | LIST_HEAD(save_head); |
380 | LIST_HEAD(local_fail_head); | |
b9b0bba9 | 381 | struct pci_dev_resource *save_res; |
d74b9027 | 382 | struct pci_dev_resource *dev_res, *tmp_res, *dev_res2; |
aa914f5e | 383 | unsigned long fail_type; |
d74b9027 | 384 | resource_size_t add_align, align; |
3e6e0d80 YL |
385 | |
386 | /* Check if optional add_size is there */ | |
bdc4abec | 387 | if (!realloc_head || list_empty(realloc_head)) |
3e6e0d80 YL |
388 | goto requested_and_reassign; |
389 | ||
390 | /* Save original start, end, flags etc at first */ | |
bdc4abec YL |
391 | list_for_each_entry(dev_res, head, list) { |
392 | if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) { | |
bffc56d4 | 393 | free_list(&save_head); |
3e6e0d80 YL |
394 | goto requested_and_reassign; |
395 | } | |
bdc4abec | 396 | } |
3e6e0d80 YL |
397 | |
398 | /* Update res in head list with add_size in realloc_head list */ | |
d74b9027 | 399 | list_for_each_entry_safe(dev_res, tmp_res, head, list) { |
bdc4abec YL |
400 | dev_res->res->end += get_res_add_size(realloc_head, |
401 | dev_res->res); | |
3e6e0d80 | 402 | |
d74b9027 WY |
403 | /* |
404 | * There are two kinds of additional resources in the list: | |
405 | * 1. bridge resource -- IORESOURCE_STARTALIGN | |
406 | * 2. SR-IOV resource -- IORESOURCE_SIZEALIGN | |
407 | * Here just fix the additional alignment for bridge | |
408 | */ | |
409 | if (!(dev_res->res->flags & IORESOURCE_STARTALIGN)) | |
410 | continue; | |
411 | ||
412 | add_align = get_res_add_align(realloc_head, dev_res->res); | |
413 | ||
414 | /* | |
415 | * The "head" list is sorted by the alignment to make sure | |
416 | * resources with bigger alignment will be assigned first. | |
417 | * After we change the alignment of a dev_res in "head" list, | |
418 | * we need to reorder the list by alignment to make it | |
419 | * consistent. | |
420 | */ | |
421 | if (add_align > dev_res->res->start) { | |
552bc94e YL |
422 | resource_size_t r_size = resource_size(dev_res->res); |
423 | ||
d74b9027 | 424 | dev_res->res->start = add_align; |
552bc94e | 425 | dev_res->res->end = add_align + r_size - 1; |
d74b9027 WY |
426 | |
427 | list_for_each_entry(dev_res2, head, list) { | |
428 | align = pci_resource_alignment(dev_res2->dev, | |
429 | dev_res2->res); | |
a6b65983 | 430 | if (add_align > align) { |
d74b9027 WY |
431 | list_move_tail(&dev_res->list, |
432 | &dev_res2->list); | |
a6b65983 WY |
433 | break; |
434 | } | |
d74b9027 | 435 | } |
ff3ce480 | 436 | } |
d74b9027 WY |
437 | |
438 | } | |
439 | ||
3e6e0d80 | 440 | /* Try updated head list with add_size added */ |
3e6e0d80 YL |
441 | assign_requested_resources_sorted(head, &local_fail_head); |
442 | ||
443 | /* all assigned with add_size ? */ | |
bdc4abec | 444 | if (list_empty(&local_fail_head)) { |
3e6e0d80 | 445 | /* Remove head list from realloc_head list */ |
bdc4abec YL |
446 | list_for_each_entry(dev_res, head, list) |
447 | remove_from_list(realloc_head, dev_res->res); | |
bffc56d4 YL |
448 | free_list(&save_head); |
449 | free_list(head); | |
3e6e0d80 YL |
450 | return; |
451 | } | |
452 | ||
aa914f5e YL |
453 | /* check failed type */ |
454 | fail_type = pci_fail_res_type_mask(&local_fail_head); | |
455 | /* remove not need to be released assigned res from head list etc */ | |
456 | list_for_each_entry_safe(dev_res, tmp_res, head, list) | |
457 | if (dev_res->res->parent && | |
458 | !pci_need_to_release(fail_type, dev_res->res)) { | |
459 | /* remove it from realloc_head list */ | |
460 | remove_from_list(realloc_head, dev_res->res); | |
461 | remove_from_list(&save_head, dev_res->res); | |
462 | list_del(&dev_res->list); | |
463 | kfree(dev_res); | |
464 | } | |
465 | ||
bffc56d4 | 466 | free_list(&local_fail_head); |
3e6e0d80 | 467 | /* Release assigned resource */ |
bdc4abec YL |
468 | list_for_each_entry(dev_res, head, list) |
469 | if (dev_res->res->parent) | |
470 | release_resource(dev_res->res); | |
3e6e0d80 | 471 | /* Restore start/end/flags from saved list */ |
b9b0bba9 YL |
472 | list_for_each_entry(save_res, &save_head, list) { |
473 | struct resource *res = save_res->res; | |
3e6e0d80 | 474 | |
b9b0bba9 YL |
475 | res->start = save_res->start; |
476 | res->end = save_res->end; | |
477 | res->flags = save_res->flags; | |
3e6e0d80 | 478 | } |
bffc56d4 | 479 | free_list(&save_head); |
3e6e0d80 YL |
480 | |
481 | requested_and_reassign: | |
c8adf9a3 RP |
482 | /* Satisfy the must-have resource requests */ |
483 | assign_requested_resources_sorted(head, fail_head); | |
484 | ||
0a2daa1c | 485 | /* Try to satisfy any additional optional resource |
c8adf9a3 | 486 | requests */ |
9e8bf93a RP |
487 | if (realloc_head) |
488 | reassign_resources_sorted(realloc_head, head); | |
bffc56d4 | 489 | free_list(head); |
c8adf9a3 RP |
490 | } |
491 | ||
6841ec68 | 492 | static void pdev_assign_resources_sorted(struct pci_dev *dev, |
bdc4abec YL |
493 | struct list_head *add_head, |
494 | struct list_head *fail_head) | |
6841ec68 | 495 | { |
bdc4abec | 496 | LIST_HEAD(head); |
6841ec68 | 497 | |
6841ec68 | 498 | __dev_sort_resources(dev, &head); |
8424d759 | 499 | __assign_resources_sorted(&head, add_head, fail_head); |
6841ec68 YL |
500 | |
501 | } | |
502 | ||
503 | static void pbus_assign_resources_sorted(const struct pci_bus *bus, | |
bdc4abec YL |
504 | struct list_head *realloc_head, |
505 | struct list_head *fail_head) | |
6841ec68 YL |
506 | { |
507 | struct pci_dev *dev; | |
bdc4abec | 508 | LIST_HEAD(head); |
6841ec68 | 509 | |
6841ec68 YL |
510 | list_for_each_entry(dev, &bus->devices, bus_list) |
511 | __dev_sort_resources(dev, &head); | |
512 | ||
9e8bf93a | 513 | __assign_resources_sorted(&head, realloc_head, fail_head); |
6841ec68 YL |
514 | } |
515 | ||
b3743fa4 | 516 | void pci_setup_cardbus(struct pci_bus *bus) |
1da177e4 LT |
517 | { |
518 | struct pci_dev *bridge = bus->self; | |
c7dabef8 | 519 | struct resource *res; |
1da177e4 LT |
520 | struct pci_bus_region region; |
521 | ||
b918c62e YL |
522 | dev_info(&bridge->dev, "CardBus bridge to %pR\n", |
523 | &bus->busn_res); | |
1da177e4 | 524 | |
c7dabef8 | 525 | res = bus->resource[0]; |
fc279850 | 526 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 | 527 | if (res->flags & IORESOURCE_IO) { |
1da177e4 LT |
528 | /* |
529 | * The IO resource is allocated a range twice as large as it | |
530 | * would normally need. This allows us to set both IO regs. | |
531 | */ | |
c7dabef8 | 532 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
1da177e4 LT |
533 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, |
534 | region.start); | |
535 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0, | |
536 | region.end); | |
537 | } | |
538 | ||
c7dabef8 | 539 | res = bus->resource[1]; |
fc279850 | 540 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 BH |
541 | if (res->flags & IORESOURCE_IO) { |
542 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
543 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, |
544 | region.start); | |
545 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1, | |
546 | region.end); | |
547 | } | |
548 | ||
c7dabef8 | 549 | res = bus->resource[2]; |
fc279850 | 550 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 BH |
551 | if (res->flags & IORESOURCE_MEM) { |
552 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
553 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, |
554 | region.start); | |
555 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0, | |
556 | region.end); | |
557 | } | |
558 | ||
c7dabef8 | 559 | res = bus->resource[3]; |
fc279850 | 560 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 BH |
561 | if (res->flags & IORESOURCE_MEM) { |
562 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
563 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, |
564 | region.start); | |
565 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1, | |
566 | region.end); | |
567 | } | |
568 | } | |
b3743fa4 | 569 | EXPORT_SYMBOL(pci_setup_cardbus); |
1da177e4 LT |
570 | |
571 | /* Initialize bridges with base/limit values we have collected. | |
572 | PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998) | |
573 | requires that if there is no I/O ports or memory behind the | |
574 | bridge, corresponding range must be turned off by writing base | |
575 | value greater than limit to the bridge's base/limit registers. | |
576 | ||
577 | Note: care must be taken when updating I/O base/limit registers | |
578 | of bridges which support 32-bit I/O. This update requires two | |
579 | config space writes, so it's quite possible that an I/O window of | |
580 | the bridge will have some undesirable address (e.g. 0) after the | |
581 | first write. Ditto 64-bit prefetchable MMIO. */ | |
3f2f4dc4 | 582 | static void pci_setup_bridge_io(struct pci_dev *bridge) |
1da177e4 | 583 | { |
c7dabef8 | 584 | struct resource *res; |
1da177e4 | 585 | struct pci_bus_region region; |
2b28ae19 BH |
586 | unsigned long io_mask; |
587 | u8 io_base_lo, io_limit_lo; | |
5b764b83 BH |
588 | u16 l; |
589 | u32 io_upper16; | |
1da177e4 | 590 | |
2b28ae19 BH |
591 | io_mask = PCI_IO_RANGE_MASK; |
592 | if (bridge->io_window_1k) | |
593 | io_mask = PCI_IO_1K_RANGE_MASK; | |
594 | ||
1da177e4 | 595 | /* Set up the top and bottom of the PCI I/O segment for this bus. */ |
3f2f4dc4 | 596 | res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0]; |
fc279850 | 597 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 | 598 | if (res->flags & IORESOURCE_IO) { |
5b764b83 | 599 | pci_read_config_word(bridge, PCI_IO_BASE, &l); |
2b28ae19 BH |
600 | io_base_lo = (region.start >> 8) & io_mask; |
601 | io_limit_lo = (region.end >> 8) & io_mask; | |
5b764b83 | 602 | l = ((u16) io_limit_lo << 8) | io_base_lo; |
1da177e4 LT |
603 | /* Set up upper 16 bits of I/O base/limit. */ |
604 | io_upper16 = (region.end & 0xffff0000) | (region.start >> 16); | |
c7dabef8 | 605 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 606 | } else { |
1da177e4 LT |
607 | /* Clear upper 16 bits of I/O base/limit. */ |
608 | io_upper16 = 0; | |
609 | l = 0x00f0; | |
1da177e4 LT |
610 | } |
611 | /* Temporarily disable the I/O range before updating PCI_IO_BASE. */ | |
612 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff); | |
613 | /* Update lower 16 bits of I/O base/limit. */ | |
5b764b83 | 614 | pci_write_config_word(bridge, PCI_IO_BASE, l); |
1da177e4 LT |
615 | /* Update upper 16 bits of I/O base/limit. */ |
616 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16); | |
7cc5997d YL |
617 | } |
618 | ||
3f2f4dc4 | 619 | static void pci_setup_bridge_mmio(struct pci_dev *bridge) |
7cc5997d | 620 | { |
7cc5997d YL |
621 | struct resource *res; |
622 | struct pci_bus_region region; | |
623 | u32 l; | |
1da177e4 | 624 | |
7cc5997d | 625 | /* Set up the top and bottom of the PCI Memory segment for this bus. */ |
3f2f4dc4 | 626 | res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1]; |
fc279850 | 627 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 | 628 | if (res->flags & IORESOURCE_MEM) { |
1da177e4 LT |
629 | l = (region.start >> 16) & 0xfff0; |
630 | l |= region.end & 0xfff00000; | |
c7dabef8 | 631 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 632 | } else { |
1da177e4 | 633 | l = 0x0000fff0; |
1da177e4 LT |
634 | } |
635 | pci_write_config_dword(bridge, PCI_MEMORY_BASE, l); | |
7cc5997d YL |
636 | } |
637 | ||
3f2f4dc4 | 638 | static void pci_setup_bridge_mmio_pref(struct pci_dev *bridge) |
7cc5997d | 639 | { |
7cc5997d YL |
640 | struct resource *res; |
641 | struct pci_bus_region region; | |
642 | u32 l, bu, lu; | |
1da177e4 LT |
643 | |
644 | /* Clear out the upper 32 bits of PREF limit. | |
645 | If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily | |
646 | disables PREF range, which is ok. */ | |
647 | pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0); | |
648 | ||
649 | /* Set up PREF base/limit. */ | |
c40a22e0 | 650 | bu = lu = 0; |
3f2f4dc4 | 651 | res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2]; |
fc279850 | 652 | pcibios_resource_to_bus(bridge->bus, ®ion, res); |
c7dabef8 | 653 | if (res->flags & IORESOURCE_PREFETCH) { |
1da177e4 LT |
654 | l = (region.start >> 16) & 0xfff0; |
655 | l |= region.end & 0xfff00000; | |
c7dabef8 | 656 | if (res->flags & IORESOURCE_MEM_64) { |
1f82de10 YL |
657 | bu = upper_32_bits(region.start); |
658 | lu = upper_32_bits(region.end); | |
1f82de10 | 659 | } |
c7dabef8 | 660 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 661 | } else { |
1da177e4 | 662 | l = 0x0000fff0; |
1da177e4 LT |
663 | } |
664 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l); | |
665 | ||
59353ea3 AW |
666 | /* Set the upper 32 bits of PREF base & limit. */ |
667 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu); | |
668 | pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu); | |
7cc5997d YL |
669 | } |
670 | ||
671 | static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type) | |
672 | { | |
673 | struct pci_dev *bridge = bus->self; | |
674 | ||
b918c62e YL |
675 | dev_info(&bridge->dev, "PCI bridge to %pR\n", |
676 | &bus->busn_res); | |
7cc5997d YL |
677 | |
678 | if (type & IORESOURCE_IO) | |
3f2f4dc4 | 679 | pci_setup_bridge_io(bridge); |
7cc5997d YL |
680 | |
681 | if (type & IORESOURCE_MEM) | |
3f2f4dc4 | 682 | pci_setup_bridge_mmio(bridge); |
7cc5997d YL |
683 | |
684 | if (type & IORESOURCE_PREFETCH) | |
3f2f4dc4 | 685 | pci_setup_bridge_mmio_pref(bridge); |
1da177e4 LT |
686 | |
687 | pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl); | |
688 | } | |
689 | ||
d366d28c GS |
690 | void __weak pcibios_setup_bridge(struct pci_bus *bus, unsigned long type) |
691 | { | |
692 | } | |
693 | ||
e2444273 | 694 | void pci_setup_bridge(struct pci_bus *bus) |
7cc5997d YL |
695 | { |
696 | unsigned long type = IORESOURCE_IO | IORESOURCE_MEM | | |
697 | IORESOURCE_PREFETCH; | |
698 | ||
d366d28c | 699 | pcibios_setup_bridge(bus, type); |
7cc5997d YL |
700 | __pci_setup_bridge(bus, type); |
701 | } | |
702 | ||
8505e729 YL |
703 | |
704 | int pci_claim_bridge_resource(struct pci_dev *bridge, int i) | |
705 | { | |
706 | if (i < PCI_BRIDGE_RESOURCES || i > PCI_BRIDGE_RESOURCE_END) | |
707 | return 0; | |
708 | ||
709 | if (pci_claim_resource(bridge, i) == 0) | |
710 | return 0; /* claimed the window */ | |
711 | ||
712 | if ((bridge->class >> 8) != PCI_CLASS_BRIDGE_PCI) | |
713 | return 0; | |
714 | ||
715 | if (!pci_bus_clip_resource(bridge, i)) | |
716 | return -EINVAL; /* clipping didn't change anything */ | |
717 | ||
718 | switch (i - PCI_BRIDGE_RESOURCES) { | |
719 | case 0: | |
720 | pci_setup_bridge_io(bridge); | |
721 | break; | |
722 | case 1: | |
723 | pci_setup_bridge_mmio(bridge); | |
724 | break; | |
725 | case 2: | |
726 | pci_setup_bridge_mmio_pref(bridge); | |
727 | break; | |
728 | default: | |
729 | return -EINVAL; | |
730 | } | |
731 | ||
732 | if (pci_claim_resource(bridge, i) == 0) | |
733 | return 0; /* claimed a smaller window */ | |
734 | ||
735 | return -EINVAL; | |
736 | } | |
737 | ||
1da177e4 LT |
738 | /* Check whether the bridge supports optional I/O and |
739 | prefetchable memory ranges. If not, the respective | |
740 | base/limit registers must be read-only and read as 0. */ | |
96bde06a | 741 | static void pci_bridge_check_ranges(struct pci_bus *bus) |
1da177e4 LT |
742 | { |
743 | u16 io; | |
744 | u32 pmem; | |
745 | struct pci_dev *bridge = bus->self; | |
746 | struct resource *b_res; | |
747 | ||
748 | b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; | |
749 | b_res[1].flags |= IORESOURCE_MEM; | |
750 | ||
751 | pci_read_config_word(bridge, PCI_IO_BASE, &io); | |
752 | if (!io) { | |
d2f54d9b | 753 | pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0); |
1da177e4 | 754 | pci_read_config_word(bridge, PCI_IO_BASE, &io); |
f7625980 BH |
755 | pci_write_config_word(bridge, PCI_IO_BASE, 0x0); |
756 | } | |
757 | if (io) | |
1da177e4 | 758 | b_res[0].flags |= IORESOURCE_IO; |
d2f54d9b | 759 | |
1da177e4 LT |
760 | /* DECchip 21050 pass 2 errata: the bridge may miss an address |
761 | disconnect boundary by one PCI data phase. | |
762 | Workaround: do not use prefetching on this device. */ | |
763 | if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) | |
764 | return; | |
d2f54d9b | 765 | |
1da177e4 LT |
766 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); |
767 | if (!pmem) { | |
768 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, | |
d2f54d9b | 769 | 0xffe0fff0); |
1da177e4 LT |
770 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); |
771 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); | |
772 | } | |
1f82de10 | 773 | if (pmem) { |
1da177e4 | 774 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; |
99586105 YL |
775 | if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == |
776 | PCI_PREF_RANGE_TYPE_64) { | |
1f82de10 | 777 | b_res[2].flags |= IORESOURCE_MEM_64; |
99586105 YL |
778 | b_res[2].flags |= PCI_PREF_RANGE_TYPE_64; |
779 | } | |
1f82de10 YL |
780 | } |
781 | ||
782 | /* double check if bridge does support 64 bit pref */ | |
783 | if (b_res[2].flags & IORESOURCE_MEM_64) { | |
784 | u32 mem_base_hi, tmp; | |
785 | pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
786 | &mem_base_hi); | |
787 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
788 | 0xffffffff); | |
789 | pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp); | |
790 | if (!tmp) | |
791 | b_res[2].flags &= ~IORESOURCE_MEM_64; | |
792 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
793 | mem_base_hi); | |
794 | } | |
1da177e4 LT |
795 | } |
796 | ||
797 | /* Helper function for sizing routines: find first available | |
798 | bus resource of a given type. Note: we intentionally skip | |
799 | the bus resources which have already been assigned (that is, | |
800 | have non-NULL parent resource). */ | |
5b285415 YL |
801 | static struct resource *find_free_bus_resource(struct pci_bus *bus, |
802 | unsigned long type_mask, unsigned long type) | |
1da177e4 LT |
803 | { |
804 | int i; | |
805 | struct resource *r; | |
1da177e4 | 806 | |
89a74ecc | 807 | pci_bus_for_each_resource(bus, r, i) { |
299de034 IK |
808 | if (r == &ioport_resource || r == &iomem_resource) |
809 | continue; | |
55a10984 JB |
810 | if (r && (r->flags & type_mask) == type && !r->parent) |
811 | return r; | |
1da177e4 LT |
812 | } |
813 | return NULL; | |
814 | } | |
815 | ||
13583b16 RP |
816 | static resource_size_t calculate_iosize(resource_size_t size, |
817 | resource_size_t min_size, | |
818 | resource_size_t size1, | |
819 | resource_size_t old_size, | |
820 | resource_size_t align) | |
821 | { | |
822 | if (size < min_size) | |
823 | size = min_size; | |
3c78bc61 | 824 | if (old_size == 1) |
13583b16 RP |
825 | old_size = 0; |
826 | /* To be fixed in 2.5: we should have sort of HAVE_ISA | |
827 | flag in the struct pci_bus. */ | |
828 | #if defined(CONFIG_ISA) || defined(CONFIG_EISA) | |
829 | size = (size & 0xff) + ((size & ~0xffUL) << 2); | |
830 | #endif | |
831 | size = ALIGN(size + size1, align); | |
832 | if (size < old_size) | |
833 | size = old_size; | |
834 | return size; | |
835 | } | |
836 | ||
837 | static resource_size_t calculate_memsize(resource_size_t size, | |
838 | resource_size_t min_size, | |
839 | resource_size_t size1, | |
840 | resource_size_t old_size, | |
841 | resource_size_t align) | |
842 | { | |
843 | if (size < min_size) | |
844 | size = min_size; | |
3c78bc61 | 845 | if (old_size == 1) |
13583b16 RP |
846 | old_size = 0; |
847 | if (size < old_size) | |
848 | size = old_size; | |
849 | size = ALIGN(size + size1, align); | |
850 | return size; | |
851 | } | |
852 | ||
ac5ad93e GS |
853 | resource_size_t __weak pcibios_window_alignment(struct pci_bus *bus, |
854 | unsigned long type) | |
855 | { | |
856 | return 1; | |
857 | } | |
858 | ||
859 | #define PCI_P2P_DEFAULT_MEM_ALIGN 0x100000 /* 1MiB */ | |
860 | #define PCI_P2P_DEFAULT_IO_ALIGN 0x1000 /* 4KiB */ | |
861 | #define PCI_P2P_DEFAULT_IO_ALIGN_1K 0x400 /* 1KiB */ | |
862 | ||
863 | static resource_size_t window_alignment(struct pci_bus *bus, | |
864 | unsigned long type) | |
865 | { | |
866 | resource_size_t align = 1, arch_align; | |
867 | ||
868 | if (type & IORESOURCE_MEM) | |
869 | align = PCI_P2P_DEFAULT_MEM_ALIGN; | |
870 | else if (type & IORESOURCE_IO) { | |
871 | /* | |
872 | * Per spec, I/O windows are 4K-aligned, but some | |
873 | * bridges have an extension to support 1K alignment. | |
874 | */ | |
875 | if (bus->self->io_window_1k) | |
876 | align = PCI_P2P_DEFAULT_IO_ALIGN_1K; | |
877 | else | |
878 | align = PCI_P2P_DEFAULT_IO_ALIGN; | |
879 | } | |
880 | ||
881 | arch_align = pcibios_window_alignment(bus, type); | |
882 | return max(align, arch_align); | |
883 | } | |
884 | ||
c8adf9a3 RP |
885 | /** |
886 | * pbus_size_io() - size the io window of a given bus | |
887 | * | |
888 | * @bus : the bus | |
889 | * @min_size : the minimum io window that must to be allocated | |
890 | * @add_size : additional optional io window | |
9e8bf93a | 891 | * @realloc_head : track the additional io window on this list |
c8adf9a3 RP |
892 | * |
893 | * Sizing the IO windows of the PCI-PCI bridge is trivial, | |
fd591341 | 894 | * since these windows have 1K or 4K granularity and the IO ranges |
c8adf9a3 RP |
895 | * of non-bridge PCI devices are limited to 256 bytes. |
896 | * We must be careful with the ISA aliasing though. | |
897 | */ | |
898 | static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size, | |
bdc4abec | 899 | resource_size_t add_size, struct list_head *realloc_head) |
1da177e4 LT |
900 | { |
901 | struct pci_dev *dev; | |
5b285415 YL |
902 | struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO, |
903 | IORESOURCE_IO); | |
11251a86 | 904 | resource_size_t size = 0, size0 = 0, size1 = 0; |
be768912 | 905 | resource_size_t children_add_size = 0; |
2d1d6678 | 906 | resource_size_t min_align, align; |
1da177e4 LT |
907 | |
908 | if (!b_res) | |
f7625980 | 909 | return; |
1da177e4 | 910 | |
2d1d6678 | 911 | min_align = window_alignment(bus, IORESOURCE_IO); |
1da177e4 LT |
912 | list_for_each_entry(dev, &bus->devices, bus_list) { |
913 | int i; | |
914 | ||
915 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
916 | struct resource *r = &dev->resource[i]; | |
917 | unsigned long r_size; | |
918 | ||
919 | if (r->parent || !(r->flags & IORESOURCE_IO)) | |
920 | continue; | |
022edd86 | 921 | r_size = resource_size(r); |
1da177e4 LT |
922 | |
923 | if (r_size < 0x400) | |
924 | /* Might be re-aligned for ISA */ | |
925 | size += r_size; | |
926 | else | |
927 | size1 += r_size; | |
be768912 | 928 | |
fd591341 YL |
929 | align = pci_resource_alignment(dev, r); |
930 | if (align > min_align) | |
931 | min_align = align; | |
932 | ||
9e8bf93a RP |
933 | if (realloc_head) |
934 | children_add_size += get_res_add_size(realloc_head, r); | |
1da177e4 LT |
935 | } |
936 | } | |
fd591341 | 937 | |
c8adf9a3 | 938 | size0 = calculate_iosize(size, min_size, size1, |
fd591341 | 939 | resource_size(b_res), min_align); |
be768912 YL |
940 | if (children_add_size > add_size) |
941 | add_size = children_add_size; | |
9e8bf93a | 942 | size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 : |
a4ac9fea | 943 | calculate_iosize(size, min_size, add_size + size1, |
fd591341 | 944 | resource_size(b_res), min_align); |
c8adf9a3 | 945 | if (!size0 && !size1) { |
865df576 | 946 | if (b_res->start || b_res->end) |
227f0647 RD |
947 | dev_info(&bus->self->dev, "disabling bridge window %pR to %pR (unused)\n", |
948 | b_res, &bus->busn_res); | |
1da177e4 LT |
949 | b_res->flags = 0; |
950 | return; | |
951 | } | |
fd591341 YL |
952 | |
953 | b_res->start = min_align; | |
c8adf9a3 | 954 | b_res->end = b_res->start + size0 - 1; |
88452565 | 955 | b_res->flags |= IORESOURCE_STARTALIGN; |
b592443d | 956 | if (size1 > size0 && realloc_head) { |
fd591341 YL |
957 | add_to_list(realloc_head, bus->self, b_res, size1-size0, |
958 | min_align); | |
227f0647 RD |
959 | dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window %pR to %pR add_size %llx\n", |
960 | b_res, &bus->busn_res, | |
961 | (unsigned long long)size1-size0); | |
b592443d | 962 | } |
1da177e4 LT |
963 | } |
964 | ||
c121504e GS |
965 | static inline resource_size_t calculate_mem_align(resource_size_t *aligns, |
966 | int max_order) | |
967 | { | |
968 | resource_size_t align = 0; | |
969 | resource_size_t min_align = 0; | |
970 | int order; | |
971 | ||
972 | for (order = 0; order <= max_order; order++) { | |
973 | resource_size_t align1 = 1; | |
974 | ||
975 | align1 <<= (order + 20); | |
976 | ||
977 | if (!align) | |
978 | min_align = align1; | |
979 | else if (ALIGN(align + min_align, min_align) < align1) | |
980 | min_align = align1 >> 1; | |
981 | align += aligns[order]; | |
982 | } | |
983 | ||
984 | return min_align; | |
985 | } | |
986 | ||
c8adf9a3 RP |
987 | /** |
988 | * pbus_size_mem() - size the memory window of a given bus | |
989 | * | |
990 | * @bus : the bus | |
496f70cf WY |
991 | * @mask: mask the resource flag, then compare it with type |
992 | * @type: the type of free resource from bridge | |
5b285415 YL |
993 | * @type2: second match type |
994 | * @type3: third match type | |
c8adf9a3 RP |
995 | * @min_size : the minimum memory window that must to be allocated |
996 | * @add_size : additional optional memory window | |
9e8bf93a | 997 | * @realloc_head : track the additional memory window on this list |
c8adf9a3 RP |
998 | * |
999 | * Calculate the size of the bus and minimal alignment which | |
1000 | * guarantees that all child resources fit in this size. | |
30afe8d0 BH |
1001 | * |
1002 | * Returns -ENOSPC if there's no available bus resource of the desired type. | |
1003 | * Otherwise, sets the bus resource start/end to indicate the required | |
1004 | * size, adds things to realloc_head (if supplied), and returns 0. | |
c8adf9a3 | 1005 | */ |
28760489 | 1006 | static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, |
5b285415 YL |
1007 | unsigned long type, unsigned long type2, |
1008 | unsigned long type3, | |
1009 | resource_size_t min_size, resource_size_t add_size, | |
1010 | struct list_head *realloc_head) | |
1da177e4 LT |
1011 | { |
1012 | struct pci_dev *dev; | |
c8adf9a3 | 1013 | resource_size_t min_align, align, size, size0, size1; |
096d4221 | 1014 | resource_size_t aligns[18]; /* Alignments from 1Mb to 128Gb */ |
1da177e4 | 1015 | int order, max_order; |
5b285415 YL |
1016 | struct resource *b_res = find_free_bus_resource(bus, |
1017 | mask | IORESOURCE_PREFETCH, type); | |
be768912 | 1018 | resource_size_t children_add_size = 0; |
d74b9027 WY |
1019 | resource_size_t children_add_align = 0; |
1020 | resource_size_t add_align = 0; | |
1da177e4 LT |
1021 | |
1022 | if (!b_res) | |
30afe8d0 | 1023 | return -ENOSPC; |
1da177e4 LT |
1024 | |
1025 | memset(aligns, 0, sizeof(aligns)); | |
1026 | max_order = 0; | |
1027 | size = 0; | |
1028 | ||
1029 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1030 | int i; | |
1f82de10 | 1031 | |
1da177e4 LT |
1032 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { |
1033 | struct resource *r = &dev->resource[i]; | |
c40a22e0 | 1034 | resource_size_t r_size; |
1da177e4 | 1035 | |
a2220d80 DD |
1036 | if (r->parent || (r->flags & IORESOURCE_PCI_FIXED) || |
1037 | ((r->flags & mask) != type && | |
1038 | (r->flags & mask) != type2 && | |
1039 | (r->flags & mask) != type3)) | |
1da177e4 | 1040 | continue; |
022edd86 | 1041 | r_size = resource_size(r); |
2aceefcb YL |
1042 | #ifdef CONFIG_PCI_IOV |
1043 | /* put SRIOV requested res to the optional list */ | |
9e8bf93a | 1044 | if (realloc_head && i >= PCI_IOV_RESOURCES && |
2aceefcb | 1045 | i <= PCI_IOV_RESOURCE_END) { |
d74b9027 | 1046 | add_align = max(pci_resource_alignment(dev, r), add_align); |
2aceefcb | 1047 | r->end = r->start - 1; |
f7625980 | 1048 | add_to_list(realloc_head, dev, r, r_size, 0/* don't care */); |
2aceefcb YL |
1049 | children_add_size += r_size; |
1050 | continue; | |
1051 | } | |
1052 | #endif | |
14c8530d A |
1053 | /* |
1054 | * aligns[0] is for 1MB (since bridge memory | |
1055 | * windows are always at least 1MB aligned), so | |
1056 | * keep "order" from being negative for smaller | |
1057 | * resources. | |
1058 | */ | |
6faf17f6 | 1059 | align = pci_resource_alignment(dev, r); |
1da177e4 | 1060 | order = __ffs(align) - 20; |
14c8530d A |
1061 | if (order < 0) |
1062 | order = 0; | |
1063 | if (order >= ARRAY_SIZE(aligns)) { | |
227f0647 RD |
1064 | dev_warn(&dev->dev, "disabling BAR %d: %pR (bad alignment %#llx)\n", |
1065 | i, r, (unsigned long long) align); | |
1da177e4 LT |
1066 | r->flags = 0; |
1067 | continue; | |
1068 | } | |
c9c75143 | 1069 | size += max(r_size, align); |
1da177e4 LT |
1070 | /* Exclude ranges with size > align from |
1071 | calculation of the alignment. */ | |
c9c75143 | 1072 | if (r_size <= align) |
1da177e4 LT |
1073 | aligns[order] += align; |
1074 | if (order > max_order) | |
1075 | max_order = order; | |
be768912 | 1076 | |
d74b9027 | 1077 | if (realloc_head) { |
9e8bf93a | 1078 | children_add_size += get_res_add_size(realloc_head, r); |
d74b9027 WY |
1079 | children_add_align = get_res_add_align(realloc_head, r); |
1080 | add_align = max(add_align, children_add_align); | |
1081 | } | |
1da177e4 LT |
1082 | } |
1083 | } | |
462d9303 | 1084 | |
c121504e | 1085 | min_align = calculate_mem_align(aligns, max_order); |
3ad94b0d | 1086 | min_align = max(min_align, window_alignment(bus, b_res->flags)); |
b42282e5 | 1087 | size0 = calculate_memsize(size, min_size, 0, resource_size(b_res), min_align); |
d74b9027 | 1088 | add_align = max(min_align, add_align); |
be768912 YL |
1089 | if (children_add_size > add_size) |
1090 | add_size = children_add_size; | |
9e8bf93a | 1091 | size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 : |
a4ac9fea | 1092 | calculate_memsize(size, min_size, add_size, |
d74b9027 | 1093 | resource_size(b_res), add_align); |
c8adf9a3 | 1094 | if (!size0 && !size1) { |
865df576 | 1095 | if (b_res->start || b_res->end) |
227f0647 RD |
1096 | dev_info(&bus->self->dev, "disabling bridge window %pR to %pR (unused)\n", |
1097 | b_res, &bus->busn_res); | |
1da177e4 | 1098 | b_res->flags = 0; |
30afe8d0 | 1099 | return 0; |
1da177e4 LT |
1100 | } |
1101 | b_res->start = min_align; | |
c8adf9a3 | 1102 | b_res->end = size0 + min_align - 1; |
5b285415 | 1103 | b_res->flags |= IORESOURCE_STARTALIGN; |
b592443d | 1104 | if (size1 > size0 && realloc_head) { |
d74b9027 WY |
1105 | add_to_list(realloc_head, bus->self, b_res, size1-size0, add_align); |
1106 | dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window %pR to %pR add_size %llx add_align %llx\n", | |
227f0647 | 1107 | b_res, &bus->busn_res, |
d74b9027 WY |
1108 | (unsigned long long) (size1 - size0), |
1109 | (unsigned long long) add_align); | |
b592443d | 1110 | } |
30afe8d0 | 1111 | return 0; |
1da177e4 LT |
1112 | } |
1113 | ||
0a2daa1c RP |
1114 | unsigned long pci_cardbus_resource_alignment(struct resource *res) |
1115 | { | |
1116 | if (res->flags & IORESOURCE_IO) | |
1117 | return pci_cardbus_io_size; | |
1118 | if (res->flags & IORESOURCE_MEM) | |
1119 | return pci_cardbus_mem_size; | |
1120 | return 0; | |
1121 | } | |
1122 | ||
1123 | static void pci_bus_size_cardbus(struct pci_bus *bus, | |
bdc4abec | 1124 | struct list_head *realloc_head) |
1da177e4 LT |
1125 | { |
1126 | struct pci_dev *bridge = bus->self; | |
1127 | struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; | |
11848934 | 1128 | resource_size_t b_res_3_size = pci_cardbus_mem_size * 2; |
1da177e4 LT |
1129 | u16 ctrl; |
1130 | ||
3796f1e2 YL |
1131 | if (b_res[0].parent) |
1132 | goto handle_b_res_1; | |
1da177e4 LT |
1133 | /* |
1134 | * Reserve some resources for CardBus. We reserve | |
1135 | * a fixed amount of bus space for CardBus bridges. | |
1136 | */ | |
11848934 YL |
1137 | b_res[0].start = pci_cardbus_io_size; |
1138 | b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1; | |
1139 | b_res[0].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN; | |
1140 | if (realloc_head) { | |
1141 | b_res[0].end -= pci_cardbus_io_size; | |
1142 | add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size, | |
1143 | pci_cardbus_io_size); | |
1144 | } | |
1da177e4 | 1145 | |
3796f1e2 YL |
1146 | handle_b_res_1: |
1147 | if (b_res[1].parent) | |
1148 | goto handle_b_res_2; | |
11848934 YL |
1149 | b_res[1].start = pci_cardbus_io_size; |
1150 | b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1; | |
1151 | b_res[1].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN; | |
1152 | if (realloc_head) { | |
1153 | b_res[1].end -= pci_cardbus_io_size; | |
1154 | add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size, | |
1155 | pci_cardbus_io_size); | |
1156 | } | |
1da177e4 | 1157 | |
3796f1e2 | 1158 | handle_b_res_2: |
dcef0d06 YL |
1159 | /* MEM1 must not be pref mmio */ |
1160 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
1161 | if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) { | |
1162 | ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1; | |
1163 | pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); | |
1164 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
1165 | } | |
1166 | ||
1da177e4 LT |
1167 | /* |
1168 | * Check whether prefetchable memory is supported | |
1169 | * by this bridge. | |
1170 | */ | |
1171 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
1172 | if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) { | |
1173 | ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; | |
1174 | pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); | |
1175 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
1176 | } | |
1177 | ||
3796f1e2 YL |
1178 | if (b_res[2].parent) |
1179 | goto handle_b_res_3; | |
1da177e4 LT |
1180 | /* |
1181 | * If we have prefetchable memory support, allocate | |
1182 | * two regions. Otherwise, allocate one region of | |
1183 | * twice the size. | |
1184 | */ | |
1185 | if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) { | |
11848934 YL |
1186 | b_res[2].start = pci_cardbus_mem_size; |
1187 | b_res[2].end = b_res[2].start + pci_cardbus_mem_size - 1; | |
1188 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | | |
1189 | IORESOURCE_STARTALIGN; | |
1190 | if (realloc_head) { | |
1191 | b_res[2].end -= pci_cardbus_mem_size; | |
1192 | add_to_list(realloc_head, bridge, b_res+2, | |
1193 | pci_cardbus_mem_size, pci_cardbus_mem_size); | |
1194 | } | |
1195 | ||
1196 | /* reduce that to half */ | |
1197 | b_res_3_size = pci_cardbus_mem_size; | |
1198 | } | |
1199 | ||
3796f1e2 YL |
1200 | handle_b_res_3: |
1201 | if (b_res[3].parent) | |
1202 | goto handle_done; | |
11848934 YL |
1203 | b_res[3].start = pci_cardbus_mem_size; |
1204 | b_res[3].end = b_res[3].start + b_res_3_size - 1; | |
1205 | b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN; | |
1206 | if (realloc_head) { | |
1207 | b_res[3].end -= b_res_3_size; | |
1208 | add_to_list(realloc_head, bridge, b_res+3, b_res_3_size, | |
1209 | pci_cardbus_mem_size); | |
1210 | } | |
3796f1e2 YL |
1211 | |
1212 | handle_done: | |
1213 | ; | |
1da177e4 LT |
1214 | } |
1215 | ||
10874f5a | 1216 | void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head) |
1da177e4 LT |
1217 | { |
1218 | struct pci_dev *dev; | |
5b285415 | 1219 | unsigned long mask, prefmask, type2 = 0, type3 = 0; |
c8adf9a3 | 1220 | resource_size_t additional_mem_size = 0, additional_io_size = 0; |
5b285415 | 1221 | struct resource *b_res; |
30afe8d0 | 1222 | int ret; |
1da177e4 LT |
1223 | |
1224 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1225 | struct pci_bus *b = dev->subordinate; | |
1226 | if (!b) | |
1227 | continue; | |
1228 | ||
1229 | switch (dev->class >> 8) { | |
1230 | case PCI_CLASS_BRIDGE_CARDBUS: | |
9e8bf93a | 1231 | pci_bus_size_cardbus(b, realloc_head); |
1da177e4 LT |
1232 | break; |
1233 | ||
1234 | case PCI_CLASS_BRIDGE_PCI: | |
1235 | default: | |
9e8bf93a | 1236 | __pci_bus_size_bridges(b, realloc_head); |
1da177e4 LT |
1237 | break; |
1238 | } | |
1239 | } | |
1240 | ||
1241 | /* The root bus? */ | |
2ba29e27 | 1242 | if (pci_is_root_bus(bus)) |
1da177e4 LT |
1243 | return; |
1244 | ||
1245 | switch (bus->self->class >> 8) { | |
1246 | case PCI_CLASS_BRIDGE_CARDBUS: | |
1247 | /* don't size cardbuses yet. */ | |
1248 | break; | |
1249 | ||
1250 | case PCI_CLASS_BRIDGE_PCI: | |
1251 | pci_bridge_check_ranges(bus); | |
28760489 | 1252 | if (bus->self->is_hotplug_bridge) { |
c8adf9a3 RP |
1253 | additional_io_size = pci_hotplug_io_size; |
1254 | additional_mem_size = pci_hotplug_mem_size; | |
28760489 | 1255 | } |
67d29b5c | 1256 | /* Fall through */ |
1da177e4 | 1257 | default: |
19aa7ee4 YL |
1258 | pbus_size_io(bus, realloc_head ? 0 : additional_io_size, |
1259 | additional_io_size, realloc_head); | |
67d29b5c BH |
1260 | |
1261 | /* | |
1262 | * If there's a 64-bit prefetchable MMIO window, compute | |
1263 | * the size required to put all 64-bit prefetchable | |
1264 | * resources in it. | |
1265 | */ | |
5b285415 | 1266 | b_res = &bus->self->resource[PCI_BRIDGE_RESOURCES]; |
1da177e4 LT |
1267 | mask = IORESOURCE_MEM; |
1268 | prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
5b285415 YL |
1269 | if (b_res[2].flags & IORESOURCE_MEM_64) { |
1270 | prefmask |= IORESOURCE_MEM_64; | |
30afe8d0 | 1271 | ret = pbus_size_mem(bus, prefmask, prefmask, |
5b285415 | 1272 | prefmask, prefmask, |
19aa7ee4 | 1273 | realloc_head ? 0 : additional_mem_size, |
30afe8d0 | 1274 | additional_mem_size, realloc_head); |
67d29b5c BH |
1275 | |
1276 | /* | |
1277 | * If successful, all non-prefetchable resources | |
1278 | * and any 32-bit prefetchable resources will go in | |
1279 | * the non-prefetchable window. | |
1280 | */ | |
30afe8d0 | 1281 | if (ret == 0) { |
30afe8d0 BH |
1282 | mask = prefmask; |
1283 | type2 = prefmask & ~IORESOURCE_MEM_64; | |
1284 | type3 = prefmask & ~IORESOURCE_PREFETCH; | |
5b285415 YL |
1285 | } |
1286 | } | |
67d29b5c BH |
1287 | |
1288 | /* | |
1289 | * If there is no 64-bit prefetchable window, compute the | |
1290 | * size required to put all prefetchable resources in the | |
1291 | * 32-bit prefetchable window (if there is one). | |
1292 | */ | |
5b285415 YL |
1293 | if (!type2) { |
1294 | prefmask &= ~IORESOURCE_MEM_64; | |
30afe8d0 | 1295 | ret = pbus_size_mem(bus, prefmask, prefmask, |
5b285415 YL |
1296 | prefmask, prefmask, |
1297 | realloc_head ? 0 : additional_mem_size, | |
30afe8d0 | 1298 | additional_mem_size, realloc_head); |
67d29b5c BH |
1299 | |
1300 | /* | |
1301 | * If successful, only non-prefetchable resources | |
1302 | * will go in the non-prefetchable window. | |
1303 | */ | |
1304 | if (ret == 0) | |
5b285415 | 1305 | mask = prefmask; |
67d29b5c | 1306 | else |
5b285415 | 1307 | additional_mem_size += additional_mem_size; |
67d29b5c | 1308 | |
5b285415 YL |
1309 | type2 = type3 = IORESOURCE_MEM; |
1310 | } | |
67d29b5c BH |
1311 | |
1312 | /* | |
1313 | * Compute the size required to put everything else in the | |
1314 | * non-prefetchable window. This includes: | |
1315 | * | |
1316 | * - all non-prefetchable resources | |
1317 | * - 32-bit prefetchable resources if there's a 64-bit | |
1318 | * prefetchable window or no prefetchable window at all | |
1319 | * - 64-bit prefetchable resources if there's no | |
1320 | * prefetchable window at all | |
1321 | * | |
1322 | * Note that the strategy in __pci_assign_resource() must | |
1323 | * match that used here. Specifically, we cannot put a | |
1324 | * 32-bit prefetchable resource in a 64-bit prefetchable | |
1325 | * window. | |
1326 | */ | |
5b285415 | 1327 | pbus_size_mem(bus, mask, IORESOURCE_MEM, type2, type3, |
19aa7ee4 YL |
1328 | realloc_head ? 0 : additional_mem_size, |
1329 | additional_mem_size, realloc_head); | |
1da177e4 LT |
1330 | break; |
1331 | } | |
1332 | } | |
c8adf9a3 | 1333 | |
10874f5a | 1334 | void pci_bus_size_bridges(struct pci_bus *bus) |
c8adf9a3 RP |
1335 | { |
1336 | __pci_bus_size_bridges(bus, NULL); | |
1337 | } | |
1da177e4 LT |
1338 | EXPORT_SYMBOL(pci_bus_size_bridges); |
1339 | ||
d04d0111 DD |
1340 | static void assign_fixed_resource_on_bus(struct pci_bus *b, struct resource *r) |
1341 | { | |
1342 | int i; | |
1343 | struct resource *parent_r; | |
1344 | unsigned long mask = IORESOURCE_IO | IORESOURCE_MEM | | |
1345 | IORESOURCE_PREFETCH; | |
1346 | ||
1347 | pci_bus_for_each_resource(b, parent_r, i) { | |
1348 | if (!parent_r) | |
1349 | continue; | |
1350 | ||
1351 | if ((r->flags & mask) == (parent_r->flags & mask) && | |
1352 | resource_contains(parent_r, r)) | |
1353 | request_resource(parent_r, r); | |
1354 | } | |
1355 | } | |
1356 | ||
1357 | /* | |
1358 | * Try to assign any resources marked as IORESOURCE_PCI_FIXED, as they | |
1359 | * are skipped by pbus_assign_resources_sorted(). | |
1360 | */ | |
1361 | static void pdev_assign_fixed_resources(struct pci_dev *dev) | |
1362 | { | |
1363 | int i; | |
1364 | ||
1365 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
1366 | struct pci_bus *b; | |
1367 | struct resource *r = &dev->resource[i]; | |
1368 | ||
1369 | if (r->parent || !(r->flags & IORESOURCE_PCI_FIXED) || | |
1370 | !(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) | |
1371 | continue; | |
1372 | ||
1373 | b = dev->bus; | |
1374 | while (b && !r->parent) { | |
1375 | assign_fixed_resource_on_bus(b, r); | |
1376 | b = b->parent; | |
1377 | } | |
1378 | } | |
1379 | } | |
1380 | ||
10874f5a BH |
1381 | void __pci_bus_assign_resources(const struct pci_bus *bus, |
1382 | struct list_head *realloc_head, | |
1383 | struct list_head *fail_head) | |
1da177e4 LT |
1384 | { |
1385 | struct pci_bus *b; | |
1386 | struct pci_dev *dev; | |
1387 | ||
9e8bf93a | 1388 | pbus_assign_resources_sorted(bus, realloc_head, fail_head); |
1da177e4 | 1389 | |
1da177e4 | 1390 | list_for_each_entry(dev, &bus->devices, bus_list) { |
d04d0111 DD |
1391 | pdev_assign_fixed_resources(dev); |
1392 | ||
1da177e4 LT |
1393 | b = dev->subordinate; |
1394 | if (!b) | |
1395 | continue; | |
1396 | ||
9e8bf93a | 1397 | __pci_bus_assign_resources(b, realloc_head, fail_head); |
1da177e4 LT |
1398 | |
1399 | switch (dev->class >> 8) { | |
1400 | case PCI_CLASS_BRIDGE_PCI: | |
6841ec68 YL |
1401 | if (!pci_is_enabled(dev)) |
1402 | pci_setup_bridge(b); | |
1da177e4 LT |
1403 | break; |
1404 | ||
1405 | case PCI_CLASS_BRIDGE_CARDBUS: | |
1406 | pci_setup_cardbus(b); | |
1407 | break; | |
1408 | ||
1409 | default: | |
227f0647 RD |
1410 | dev_info(&dev->dev, "not setting up bridge for bus %04x:%02x\n", |
1411 | pci_domain_nr(b), b->number); | |
1da177e4 LT |
1412 | break; |
1413 | } | |
1414 | } | |
1415 | } | |
568ddef8 | 1416 | |
10874f5a | 1417 | void pci_bus_assign_resources(const struct pci_bus *bus) |
568ddef8 | 1418 | { |
c8adf9a3 | 1419 | __pci_bus_assign_resources(bus, NULL, NULL); |
568ddef8 | 1420 | } |
1da177e4 LT |
1421 | EXPORT_SYMBOL(pci_bus_assign_resources); |
1422 | ||
765bf9b7 LP |
1423 | static void pci_claim_device_resources(struct pci_dev *dev) |
1424 | { | |
1425 | int i; | |
1426 | ||
1427 | for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) { | |
1428 | struct resource *r = &dev->resource[i]; | |
1429 | ||
1430 | if (!r->flags || r->parent) | |
1431 | continue; | |
1432 | ||
1433 | pci_claim_resource(dev, i); | |
1434 | } | |
1435 | } | |
1436 | ||
1437 | static void pci_claim_bridge_resources(struct pci_dev *dev) | |
1438 | { | |
1439 | int i; | |
1440 | ||
1441 | for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) { | |
1442 | struct resource *r = &dev->resource[i]; | |
1443 | ||
1444 | if (!r->flags || r->parent) | |
1445 | continue; | |
1446 | ||
1447 | pci_claim_bridge_resource(dev, i); | |
1448 | } | |
1449 | } | |
1450 | ||
1451 | static void pci_bus_allocate_dev_resources(struct pci_bus *b) | |
1452 | { | |
1453 | struct pci_dev *dev; | |
1454 | struct pci_bus *child; | |
1455 | ||
1456 | list_for_each_entry(dev, &b->devices, bus_list) { | |
1457 | pci_claim_device_resources(dev); | |
1458 | ||
1459 | child = dev->subordinate; | |
1460 | if (child) | |
1461 | pci_bus_allocate_dev_resources(child); | |
1462 | } | |
1463 | } | |
1464 | ||
1465 | static void pci_bus_allocate_resources(struct pci_bus *b) | |
1466 | { | |
1467 | struct pci_bus *child; | |
1468 | ||
1469 | /* | |
1470 | * Carry out a depth-first search on the PCI bus | |
1471 | * tree to allocate bridge apertures. Read the | |
1472 | * programmed bridge bases and recursively claim | |
1473 | * the respective bridge resources. | |
1474 | */ | |
1475 | if (b->self) { | |
1476 | pci_read_bridge_bases(b); | |
1477 | pci_claim_bridge_resources(b->self); | |
1478 | } | |
1479 | ||
1480 | list_for_each_entry(child, &b->children, node) | |
1481 | pci_bus_allocate_resources(child); | |
1482 | } | |
1483 | ||
1484 | void pci_bus_claim_resources(struct pci_bus *b) | |
1485 | { | |
1486 | pci_bus_allocate_resources(b); | |
1487 | pci_bus_allocate_dev_resources(b); | |
1488 | } | |
1489 | EXPORT_SYMBOL(pci_bus_claim_resources); | |
1490 | ||
10874f5a BH |
1491 | static void __pci_bridge_assign_resources(const struct pci_dev *bridge, |
1492 | struct list_head *add_head, | |
1493 | struct list_head *fail_head) | |
6841ec68 YL |
1494 | { |
1495 | struct pci_bus *b; | |
1496 | ||
8424d759 YL |
1497 | pdev_assign_resources_sorted((struct pci_dev *)bridge, |
1498 | add_head, fail_head); | |
6841ec68 YL |
1499 | |
1500 | b = bridge->subordinate; | |
1501 | if (!b) | |
1502 | return; | |
1503 | ||
8424d759 | 1504 | __pci_bus_assign_resources(b, add_head, fail_head); |
6841ec68 YL |
1505 | |
1506 | switch (bridge->class >> 8) { | |
1507 | case PCI_CLASS_BRIDGE_PCI: | |
1508 | pci_setup_bridge(b); | |
1509 | break; | |
1510 | ||
1511 | case PCI_CLASS_BRIDGE_CARDBUS: | |
1512 | pci_setup_cardbus(b); | |
1513 | break; | |
1514 | ||
1515 | default: | |
227f0647 RD |
1516 | dev_info(&bridge->dev, "not setting up bridge for bus %04x:%02x\n", |
1517 | pci_domain_nr(b), b->number); | |
6841ec68 YL |
1518 | break; |
1519 | } | |
1520 | } | |
cb21bc94 CK |
1521 | |
1522 | #define PCI_RES_TYPE_MASK \ | |
1523 | (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH |\ | |
1524 | IORESOURCE_MEM_64) | |
1525 | ||
5009b460 YL |
1526 | static void pci_bridge_release_resources(struct pci_bus *bus, |
1527 | unsigned long type) | |
1528 | { | |
5b285415 | 1529 | struct pci_dev *dev = bus->self; |
5009b460 | 1530 | struct resource *r; |
5b285415 YL |
1531 | unsigned old_flags = 0; |
1532 | struct resource *b_res; | |
1533 | int idx = 1; | |
5009b460 | 1534 | |
5b285415 YL |
1535 | b_res = &dev->resource[PCI_BRIDGE_RESOURCES]; |
1536 | ||
1537 | /* | |
1538 | * 1. if there is io port assign fail, will release bridge | |
1539 | * io port. | |
1540 | * 2. if there is non pref mmio assign fail, release bridge | |
1541 | * nonpref mmio. | |
1542 | * 3. if there is 64bit pref mmio assign fail, and bridge pref | |
1543 | * is 64bit, release bridge pref mmio. | |
1544 | * 4. if there is pref mmio assign fail, and bridge pref is | |
1545 | * 32bit mmio, release bridge pref mmio | |
1546 | * 5. if there is pref mmio assign fail, and bridge pref is not | |
1547 | * assigned, release bridge nonpref mmio. | |
1548 | */ | |
1549 | if (type & IORESOURCE_IO) | |
1550 | idx = 0; | |
1551 | else if (!(type & IORESOURCE_PREFETCH)) | |
1552 | idx = 1; | |
1553 | else if ((type & IORESOURCE_MEM_64) && | |
1554 | (b_res[2].flags & IORESOURCE_MEM_64)) | |
1555 | idx = 2; | |
1556 | else if (!(b_res[2].flags & IORESOURCE_MEM_64) && | |
1557 | (b_res[2].flags & IORESOURCE_PREFETCH)) | |
1558 | idx = 2; | |
1559 | else | |
1560 | idx = 1; | |
1561 | ||
1562 | r = &b_res[idx]; | |
1563 | ||
1564 | if (!r->parent) | |
1565 | return; | |
1566 | ||
1567 | /* | |
1568 | * if there are children under that, we should release them | |
1569 | * all | |
1570 | */ | |
1571 | release_child_resources(r); | |
1572 | if (!release_resource(r)) { | |
cb21bc94 | 1573 | type = old_flags = r->flags & PCI_RES_TYPE_MASK; |
5b285415 YL |
1574 | dev_printk(KERN_DEBUG, &dev->dev, "resource %d %pR released\n", |
1575 | PCI_BRIDGE_RESOURCES + idx, r); | |
1576 | /* keep the old size */ | |
1577 | r->end = resource_size(r) - 1; | |
1578 | r->start = 0; | |
1579 | r->flags = 0; | |
5009b460 | 1580 | |
5009b460 YL |
1581 | /* avoiding touch the one without PREF */ |
1582 | if (type & IORESOURCE_PREFETCH) | |
1583 | type = IORESOURCE_PREFETCH; | |
1584 | __pci_setup_bridge(bus, type); | |
5b285415 YL |
1585 | /* for next child res under same bridge */ |
1586 | r->flags = old_flags; | |
5009b460 YL |
1587 | } |
1588 | } | |
1589 | ||
1590 | enum release_type { | |
1591 | leaf_only, | |
1592 | whole_subtree, | |
1593 | }; | |
1594 | /* | |
1595 | * try to release pci bridge resources that is from leaf bridge, | |
1596 | * so we can allocate big new one later | |
1597 | */ | |
10874f5a BH |
1598 | static void pci_bus_release_bridge_resources(struct pci_bus *bus, |
1599 | unsigned long type, | |
1600 | enum release_type rel_type) | |
5009b460 YL |
1601 | { |
1602 | struct pci_dev *dev; | |
1603 | bool is_leaf_bridge = true; | |
1604 | ||
1605 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1606 | struct pci_bus *b = dev->subordinate; | |
1607 | if (!b) | |
1608 | continue; | |
1609 | ||
1610 | is_leaf_bridge = false; | |
1611 | ||
1612 | if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) | |
1613 | continue; | |
1614 | ||
1615 | if (rel_type == whole_subtree) | |
1616 | pci_bus_release_bridge_resources(b, type, | |
1617 | whole_subtree); | |
1618 | } | |
1619 | ||
1620 | if (pci_is_root_bus(bus)) | |
1621 | return; | |
1622 | ||
1623 | if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI) | |
1624 | return; | |
1625 | ||
1626 | if ((rel_type == whole_subtree) || is_leaf_bridge) | |
1627 | pci_bridge_release_resources(bus, type); | |
1628 | } | |
1629 | ||
76fbc263 YL |
1630 | static void pci_bus_dump_res(struct pci_bus *bus) |
1631 | { | |
89a74ecc BH |
1632 | struct resource *res; |
1633 | int i; | |
7c9342b8 | 1634 | |
89a74ecc | 1635 | pci_bus_for_each_resource(bus, res, i) { |
7c9342b8 | 1636 | if (!res || !res->end || !res->flags) |
3c78bc61 | 1637 | continue; |
76fbc263 | 1638 | |
c7dabef8 | 1639 | dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res); |
3c78bc61 | 1640 | } |
76fbc263 YL |
1641 | } |
1642 | ||
1643 | static void pci_bus_dump_resources(struct pci_bus *bus) | |
1644 | { | |
1645 | struct pci_bus *b; | |
1646 | struct pci_dev *dev; | |
1647 | ||
1648 | ||
1649 | pci_bus_dump_res(bus); | |
1650 | ||
1651 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1652 | b = dev->subordinate; | |
1653 | if (!b) | |
1654 | continue; | |
1655 | ||
1656 | pci_bus_dump_resources(b); | |
1657 | } | |
1658 | } | |
1659 | ||
ff35147c | 1660 | static int pci_bus_get_depth(struct pci_bus *bus) |
da7822e5 YL |
1661 | { |
1662 | int depth = 0; | |
f2a230bd | 1663 | struct pci_bus *child_bus; |
da7822e5 | 1664 | |
3c78bc61 | 1665 | list_for_each_entry(child_bus, &bus->children, node) { |
da7822e5 | 1666 | int ret; |
da7822e5 | 1667 | |
f2a230bd | 1668 | ret = pci_bus_get_depth(child_bus); |
da7822e5 YL |
1669 | if (ret + 1 > depth) |
1670 | depth = ret + 1; | |
1671 | } | |
1672 | ||
1673 | return depth; | |
1674 | } | |
da7822e5 | 1675 | |
b55438fd YL |
1676 | /* |
1677 | * -1: undefined, will auto detect later | |
1678 | * 0: disabled by user | |
1679 | * 1: disabled by auto detect | |
1680 | * 2: enabled by user | |
1681 | * 3: enabled by auto detect | |
1682 | */ | |
1683 | enum enable_type { | |
1684 | undefined = -1, | |
1685 | user_disabled, | |
1686 | auto_disabled, | |
1687 | user_enabled, | |
1688 | auto_enabled, | |
1689 | }; | |
1690 | ||
ff35147c | 1691 | static enum enable_type pci_realloc_enable = undefined; |
b55438fd YL |
1692 | void __init pci_realloc_get_opt(char *str) |
1693 | { | |
1694 | if (!strncmp(str, "off", 3)) | |
1695 | pci_realloc_enable = user_disabled; | |
1696 | else if (!strncmp(str, "on", 2)) | |
1697 | pci_realloc_enable = user_enabled; | |
1698 | } | |
ff35147c | 1699 | static bool pci_realloc_enabled(enum enable_type enable) |
b55438fd | 1700 | { |
967260cd | 1701 | return enable >= user_enabled; |
b55438fd | 1702 | } |
f483d392 | 1703 | |
b07f2ebc | 1704 | #if defined(CONFIG_PCI_IOV) && defined(CONFIG_PCI_REALLOC_ENABLE_AUTO) |
ff35147c | 1705 | static int iov_resources_unassigned(struct pci_dev *dev, void *data) |
223d96fc YL |
1706 | { |
1707 | int i; | |
1708 | bool *unassigned = data; | |
b07f2ebc | 1709 | |
223d96fc YL |
1710 | for (i = PCI_IOV_RESOURCES; i <= PCI_IOV_RESOURCE_END; i++) { |
1711 | struct resource *r = &dev->resource[i]; | |
fa216bf4 | 1712 | struct pci_bus_region region; |
b07f2ebc | 1713 | |
223d96fc | 1714 | /* Not assigned or rejected by kernel? */ |
fa216bf4 YL |
1715 | if (!r->flags) |
1716 | continue; | |
b07f2ebc | 1717 | |
fc279850 | 1718 | pcibios_resource_to_bus(dev->bus, ®ion, r); |
fa216bf4 | 1719 | if (!region.start) { |
223d96fc YL |
1720 | *unassigned = true; |
1721 | return 1; /* return early from pci_walk_bus() */ | |
b07f2ebc YL |
1722 | } |
1723 | } | |
b07f2ebc | 1724 | |
223d96fc | 1725 | return 0; |
b07f2ebc YL |
1726 | } |
1727 | ||
ff35147c | 1728 | static enum enable_type pci_realloc_detect(struct pci_bus *bus, |
967260cd | 1729 | enum enable_type enable_local) |
223d96fc YL |
1730 | { |
1731 | bool unassigned = false; | |
b07f2ebc | 1732 | |
967260cd YL |
1733 | if (enable_local != undefined) |
1734 | return enable_local; | |
223d96fc | 1735 | |
967260cd YL |
1736 | pci_walk_bus(bus, iov_resources_unassigned, &unassigned); |
1737 | if (unassigned) | |
1738 | return auto_enabled; | |
1739 | ||
1740 | return enable_local; | |
b07f2ebc | 1741 | } |
223d96fc | 1742 | #else |
ff35147c | 1743 | static enum enable_type pci_realloc_detect(struct pci_bus *bus, |
967260cd YL |
1744 | enum enable_type enable_local) |
1745 | { | |
1746 | return enable_local; | |
b07f2ebc | 1747 | } |
223d96fc | 1748 | #endif |
b07f2ebc | 1749 | |
da7822e5 YL |
1750 | /* |
1751 | * first try will not touch pci bridge res | |
f7625980 BH |
1752 | * second and later try will clear small leaf bridge res |
1753 | * will stop till to the max depth if can not find good one | |
da7822e5 | 1754 | */ |
39772038 | 1755 | void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus) |
1da177e4 | 1756 | { |
bdc4abec | 1757 | LIST_HEAD(realloc_head); /* list of resources that |
c8adf9a3 | 1758 | want additional resources */ |
bdc4abec | 1759 | struct list_head *add_list = NULL; |
da7822e5 YL |
1760 | int tried_times = 0; |
1761 | enum release_type rel_type = leaf_only; | |
bdc4abec | 1762 | LIST_HEAD(fail_head); |
b9b0bba9 | 1763 | struct pci_dev_resource *fail_res; |
19aa7ee4 | 1764 | int pci_try_num = 1; |
55ed83a6 | 1765 | enum enable_type enable_local; |
da7822e5 | 1766 | |
19aa7ee4 | 1767 | /* don't realloc if asked to do so */ |
55ed83a6 | 1768 | enable_local = pci_realloc_detect(bus, pci_realloc_enable); |
967260cd | 1769 | if (pci_realloc_enabled(enable_local)) { |
55ed83a6 | 1770 | int max_depth = pci_bus_get_depth(bus); |
19aa7ee4 YL |
1771 | |
1772 | pci_try_num = max_depth + 1; | |
55ed83a6 YL |
1773 | dev_printk(KERN_DEBUG, &bus->dev, |
1774 | "max bus depth: %d pci_try_num: %d\n", | |
1775 | max_depth, pci_try_num); | |
19aa7ee4 | 1776 | } |
da7822e5 YL |
1777 | |
1778 | again: | |
19aa7ee4 YL |
1779 | /* |
1780 | * last try will use add_list, otherwise will try good to have as | |
1781 | * must have, so can realloc parent bridge resource | |
1782 | */ | |
1783 | if (tried_times + 1 == pci_try_num) | |
bdc4abec | 1784 | add_list = &realloc_head; |
1da177e4 LT |
1785 | /* Depth first, calculate sizes and alignments of all |
1786 | subordinate buses. */ | |
55ed83a6 | 1787 | __pci_bus_size_bridges(bus, add_list); |
c8adf9a3 | 1788 | |
1da177e4 | 1789 | /* Depth last, allocate resources and update the hardware. */ |
55ed83a6 | 1790 | __pci_bus_assign_resources(bus, add_list, &fail_head); |
19aa7ee4 | 1791 | if (add_list) |
bdc4abec | 1792 | BUG_ON(!list_empty(add_list)); |
da7822e5 YL |
1793 | tried_times++; |
1794 | ||
1795 | /* any device complain? */ | |
bdc4abec | 1796 | if (list_empty(&fail_head)) |
928bea96 | 1797 | goto dump; |
f483d392 | 1798 | |
0c5be0cb | 1799 | if (tried_times >= pci_try_num) { |
967260cd | 1800 | if (enable_local == undefined) |
55ed83a6 | 1801 | dev_info(&bus->dev, "Some PCI device resources are unassigned, try booting with pci=realloc\n"); |
967260cd | 1802 | else if (enable_local == auto_enabled) |
55ed83a6 | 1803 | dev_info(&bus->dev, "Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n"); |
eb572e7c | 1804 | |
bffc56d4 | 1805 | free_list(&fail_head); |
928bea96 | 1806 | goto dump; |
da7822e5 YL |
1807 | } |
1808 | ||
55ed83a6 YL |
1809 | dev_printk(KERN_DEBUG, &bus->dev, |
1810 | "No. %d try to assign unassigned res\n", tried_times + 1); | |
da7822e5 YL |
1811 | |
1812 | /* third times and later will not check if it is leaf */ | |
1813 | if ((tried_times + 1) > 2) | |
1814 | rel_type = whole_subtree; | |
1815 | ||
1816 | /* | |
1817 | * Try to release leaf bridge's resources that doesn't fit resource of | |
1818 | * child device under that bridge | |
1819 | */ | |
61e83cdd YL |
1820 | list_for_each_entry(fail_res, &fail_head, list) |
1821 | pci_bus_release_bridge_resources(fail_res->dev->bus, | |
cb21bc94 | 1822 | fail_res->flags & PCI_RES_TYPE_MASK, |
bdc4abec | 1823 | rel_type); |
61e83cdd | 1824 | |
da7822e5 | 1825 | /* restore size and flags */ |
b9b0bba9 YL |
1826 | list_for_each_entry(fail_res, &fail_head, list) { |
1827 | struct resource *res = fail_res->res; | |
da7822e5 | 1828 | |
b9b0bba9 YL |
1829 | res->start = fail_res->start; |
1830 | res->end = fail_res->end; | |
1831 | res->flags = fail_res->flags; | |
1832 | if (fail_res->dev->subordinate) | |
da7822e5 | 1833 | res->flags = 0; |
da7822e5 | 1834 | } |
bffc56d4 | 1835 | free_list(&fail_head); |
da7822e5 YL |
1836 | |
1837 | goto again; | |
1838 | ||
928bea96 | 1839 | dump: |
76fbc263 | 1840 | /* dump the resource on buses */ |
55ed83a6 YL |
1841 | pci_bus_dump_resources(bus); |
1842 | } | |
1843 | ||
1844 | void __init pci_assign_unassigned_resources(void) | |
1845 | { | |
1846 | struct pci_bus *root_bus; | |
1847 | ||
584c5c42 | 1848 | list_for_each_entry(root_bus, &pci_root_buses, node) { |
55ed83a6 | 1849 | pci_assign_unassigned_root_bus_resources(root_bus); |
d9c149d6 RW |
1850 | |
1851 | /* Make sure the root bridge has a companion ACPI device: */ | |
1852 | if (ACPI_HANDLE(root_bus->bridge)) | |
1853 | acpi_ioapic_add(ACPI_HANDLE(root_bus->bridge)); | |
584c5c42 | 1854 | } |
1da177e4 | 1855 | } |
6841ec68 | 1856 | |
1a576772 MW |
1857 | static void extend_bridge_window(struct pci_dev *bridge, struct resource *res, |
1858 | struct list_head *add_list, resource_size_t available) | |
1859 | { | |
1860 | struct pci_dev_resource *dev_res; | |
1861 | ||
1862 | if (res->parent) | |
1863 | return; | |
1864 | ||
1865 | if (resource_size(res) >= available) | |
1866 | return; | |
1867 | ||
1868 | dev_res = res_to_dev_res(add_list, res); | |
1869 | if (!dev_res) | |
1870 | return; | |
1871 | ||
1872 | /* Is there room to extend the window? */ | |
1873 | if (available - resource_size(res) <= dev_res->add_size) | |
1874 | return; | |
1875 | ||
1876 | dev_res->add_size = available - resource_size(res); | |
1877 | dev_dbg(&bridge->dev, "bridge window %pR extended by %pa\n", res, | |
1878 | &dev_res->add_size); | |
1879 | } | |
1880 | ||
1881 | static void pci_bus_distribute_available_resources(struct pci_bus *bus, | |
1882 | struct list_head *add_list, resource_size_t available_io, | |
1883 | resource_size_t available_mmio, resource_size_t available_mmio_pref) | |
1884 | { | |
1885 | resource_size_t remaining_io, remaining_mmio, remaining_mmio_pref; | |
1886 | unsigned int normal_bridges = 0, hotplug_bridges = 0; | |
1887 | struct resource *io_res, *mmio_res, *mmio_pref_res; | |
1888 | struct pci_dev *dev, *bridge = bus->self; | |
1889 | ||
1890 | io_res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0]; | |
1891 | mmio_res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1]; | |
1892 | mmio_pref_res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2]; | |
1893 | ||
1894 | /* | |
1895 | * Update additional resource list (add_list) to fill all the | |
1896 | * extra resource space available for this port except the space | |
1897 | * calculated in __pci_bus_size_bridges() which covers all the | |
1898 | * devices currently connected to the port and below. | |
1899 | */ | |
1900 | extend_bridge_window(bridge, io_res, add_list, available_io); | |
1901 | extend_bridge_window(bridge, mmio_res, add_list, available_mmio); | |
1902 | extend_bridge_window(bridge, mmio_pref_res, add_list, | |
1903 | available_mmio_pref); | |
1904 | ||
1905 | /* | |
1906 | * Calculate the total amount of extra resource space we can | |
1907 | * pass to bridges below this one. This is basically the | |
1908 | * extra space reduced by the minimal required space for the | |
1909 | * non-hotplug bridges. | |
1910 | */ | |
1911 | remaining_io = available_io; | |
1912 | remaining_mmio = available_mmio; | |
1913 | remaining_mmio_pref = available_mmio_pref; | |
1914 | ||
1915 | /* | |
1916 | * Calculate how many hotplug bridges and normal bridges there | |
1917 | * are on this bus. We will distribute the additional available | |
1918 | * resources between hotplug bridges. | |
1919 | */ | |
1920 | for_each_pci_bridge(dev, bus) { | |
1921 | if (dev->is_hotplug_bridge) | |
1922 | hotplug_bridges++; | |
1923 | else | |
1924 | normal_bridges++; | |
1925 | } | |
1926 | ||
1927 | for_each_pci_bridge(dev, bus) { | |
1928 | const struct resource *res; | |
1929 | ||
1930 | if (dev->is_hotplug_bridge) | |
1931 | continue; | |
1932 | ||
1933 | /* | |
1934 | * Reduce the available resource space by what the | |
1935 | * bridge and devices below it occupy. | |
1936 | */ | |
1937 | res = &dev->resource[PCI_BRIDGE_RESOURCES + 0]; | |
1938 | if (!res->parent && available_io > resource_size(res)) | |
1939 | remaining_io -= resource_size(res); | |
1940 | ||
1941 | res = &dev->resource[PCI_BRIDGE_RESOURCES + 1]; | |
1942 | if (!res->parent && available_mmio > resource_size(res)) | |
1943 | remaining_mmio -= resource_size(res); | |
1944 | ||
1945 | res = &dev->resource[PCI_BRIDGE_RESOURCES + 2]; | |
1946 | if (!res->parent && available_mmio_pref > resource_size(res)) | |
1947 | remaining_mmio_pref -= resource_size(res); | |
1948 | } | |
1949 | ||
1950 | /* | |
1951 | * Go over devices on this bus and distribute the remaining | |
1952 | * resource space between hotplug bridges. | |
1953 | */ | |
1954 | for_each_pci_bridge(dev, bus) { | |
1955 | struct pci_bus *b; | |
1956 | ||
1957 | b = dev->subordinate; | |
1958 | if (!b) | |
1959 | continue; | |
1960 | ||
1961 | if (!hotplug_bridges && normal_bridges == 1) { | |
1962 | /* | |
1963 | * There is only one bridge on the bus (upstream | |
1964 | * port) so it gets all available resources | |
1965 | * which it can then distribute to the possible | |
1966 | * hotplug bridges below. | |
1967 | */ | |
1968 | pci_bus_distribute_available_resources(b, add_list, | |
1969 | available_io, available_mmio, | |
1970 | available_mmio_pref); | |
1971 | } else if (dev->is_hotplug_bridge) { | |
1972 | resource_size_t align, io, mmio, mmio_pref; | |
1973 | ||
1974 | /* | |
1975 | * Distribute available extra resources equally | |
1976 | * between hotplug-capable downstream ports | |
1977 | * taking alignment into account. | |
1978 | * | |
1979 | * Here hotplug_bridges is always != 0. | |
1980 | */ | |
1981 | align = pci_resource_alignment(bridge, io_res); | |
1982 | io = div64_ul(available_io, hotplug_bridges); | |
1983 | io = min(ALIGN(io, align), remaining_io); | |
1984 | remaining_io -= io; | |
1985 | ||
1986 | align = pci_resource_alignment(bridge, mmio_res); | |
1987 | mmio = div64_ul(available_mmio, hotplug_bridges); | |
1988 | mmio = min(ALIGN(mmio, align), remaining_mmio); | |
1989 | remaining_mmio -= mmio; | |
1990 | ||
1991 | align = pci_resource_alignment(bridge, mmio_pref_res); | |
1992 | mmio_pref = div64_ul(available_mmio_pref, | |
1993 | hotplug_bridges); | |
1994 | mmio_pref = min(ALIGN(mmio_pref, align), | |
1995 | remaining_mmio_pref); | |
1996 | remaining_mmio_pref -= mmio_pref; | |
1997 | ||
1998 | pci_bus_distribute_available_resources(b, add_list, io, | |
1999 | mmio, mmio_pref); | |
2000 | } | |
2001 | } | |
2002 | } | |
2003 | ||
2004 | static void | |
2005 | pci_bridge_distribute_available_resources(struct pci_dev *bridge, | |
2006 | struct list_head *add_list) | |
2007 | { | |
2008 | resource_size_t available_io, available_mmio, available_mmio_pref; | |
2009 | const struct resource *res; | |
2010 | ||
2011 | if (!bridge->is_hotplug_bridge) | |
2012 | return; | |
2013 | ||
2014 | /* Take the initial extra resources from the hotplug port */ | |
2015 | res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0]; | |
2016 | available_io = resource_size(res); | |
2017 | res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1]; | |
2018 | available_mmio = resource_size(res); | |
2019 | res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2]; | |
2020 | available_mmio_pref = resource_size(res); | |
2021 | ||
2022 | pci_bus_distribute_available_resources(bridge->subordinate, | |
2023 | add_list, available_io, available_mmio, available_mmio_pref); | |
2024 | } | |
2025 | ||
6841ec68 YL |
2026 | void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge) |
2027 | { | |
2028 | struct pci_bus *parent = bridge->subordinate; | |
bdc4abec | 2029 | LIST_HEAD(add_list); /* list of resources that |
8424d759 | 2030 | want additional resources */ |
32180e40 | 2031 | int tried_times = 0; |
bdc4abec | 2032 | LIST_HEAD(fail_head); |
b9b0bba9 | 2033 | struct pci_dev_resource *fail_res; |
6841ec68 | 2034 | int retval; |
32180e40 | 2035 | |
32180e40 | 2036 | again: |
8424d759 | 2037 | __pci_bus_size_bridges(parent, &add_list); |
1a576772 MW |
2038 | |
2039 | /* | |
2040 | * Distribute remaining resources (if any) equally between | |
2041 | * hotplug bridges below. This makes it possible to extend the | |
2042 | * hierarchy later without running out of resources. | |
2043 | */ | |
2044 | pci_bridge_distribute_available_resources(bridge, &add_list); | |
2045 | ||
bdc4abec YL |
2046 | __pci_bridge_assign_resources(bridge, &add_list, &fail_head); |
2047 | BUG_ON(!list_empty(&add_list)); | |
32180e40 YL |
2048 | tried_times++; |
2049 | ||
bdc4abec | 2050 | if (list_empty(&fail_head)) |
3f579c34 | 2051 | goto enable_all; |
32180e40 YL |
2052 | |
2053 | if (tried_times >= 2) { | |
2054 | /* still fail, don't need to try more */ | |
bffc56d4 | 2055 | free_list(&fail_head); |
3f579c34 | 2056 | goto enable_all; |
32180e40 YL |
2057 | } |
2058 | ||
2059 | printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n", | |
2060 | tried_times + 1); | |
2061 | ||
2062 | /* | |
2063 | * Try to release leaf bridge's resources that doesn't fit resource of | |
2064 | * child device under that bridge | |
2065 | */ | |
61e83cdd YL |
2066 | list_for_each_entry(fail_res, &fail_head, list) |
2067 | pci_bus_release_bridge_resources(fail_res->dev->bus, | |
cb21bc94 | 2068 | fail_res->flags & PCI_RES_TYPE_MASK, |
32180e40 | 2069 | whole_subtree); |
61e83cdd | 2070 | |
32180e40 | 2071 | /* restore size and flags */ |
b9b0bba9 YL |
2072 | list_for_each_entry(fail_res, &fail_head, list) { |
2073 | struct resource *res = fail_res->res; | |
32180e40 | 2074 | |
b9b0bba9 YL |
2075 | res->start = fail_res->start; |
2076 | res->end = fail_res->end; | |
2077 | res->flags = fail_res->flags; | |
2078 | if (fail_res->dev->subordinate) | |
32180e40 | 2079 | res->flags = 0; |
32180e40 | 2080 | } |
bffc56d4 | 2081 | free_list(&fail_head); |
32180e40 YL |
2082 | |
2083 | goto again; | |
3f579c34 YL |
2084 | |
2085 | enable_all: | |
2086 | retval = pci_reenable_device(bridge); | |
9fc9eea0 BH |
2087 | if (retval) |
2088 | dev_err(&bridge->dev, "Error reenabling bridge (%d)\n", retval); | |
3f579c34 | 2089 | pci_set_master(bridge); |
6841ec68 YL |
2090 | } |
2091 | EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources); | |
9b03088f | 2092 | |
8bb705e3 CK |
2093 | int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type) |
2094 | { | |
2095 | struct pci_dev_resource *dev_res; | |
2096 | struct pci_dev *next; | |
2097 | LIST_HEAD(saved); | |
2098 | LIST_HEAD(added); | |
2099 | LIST_HEAD(failed); | |
2100 | unsigned int i; | |
2101 | int ret; | |
2102 | ||
2103 | /* Walk to the root hub, releasing bridge BARs when possible */ | |
2104 | next = bridge; | |
2105 | do { | |
2106 | bridge = next; | |
2107 | for (i = PCI_BRIDGE_RESOURCES; i < PCI_BRIDGE_RESOURCE_END; | |
2108 | i++) { | |
2109 | struct resource *res = &bridge->resource[i]; | |
2110 | ||
2111 | if ((res->flags ^ type) & PCI_RES_TYPE_MASK) | |
2112 | continue; | |
2113 | ||
2114 | /* Ignore BARs which are still in use */ | |
2115 | if (res->child) | |
2116 | continue; | |
2117 | ||
2118 | ret = add_to_list(&saved, bridge, res, 0, 0); | |
2119 | if (ret) | |
2120 | goto cleanup; | |
2121 | ||
2122 | dev_info(&bridge->dev, "BAR %d: releasing %pR\n", | |
2123 | i, res); | |
2124 | ||
2125 | if (res->parent) | |
2126 | release_resource(res); | |
2127 | res->start = 0; | |
2128 | res->end = 0; | |
2129 | break; | |
2130 | } | |
2131 | if (i == PCI_BRIDGE_RESOURCE_END) | |
2132 | break; | |
2133 | ||
2134 | next = bridge->bus ? bridge->bus->self : NULL; | |
2135 | } while (next); | |
2136 | ||
2137 | if (list_empty(&saved)) | |
2138 | return -ENOENT; | |
2139 | ||
2140 | __pci_bus_size_bridges(bridge->subordinate, &added); | |
2141 | __pci_bridge_assign_resources(bridge, &added, &failed); | |
2142 | BUG_ON(!list_empty(&added)); | |
2143 | ||
2144 | if (!list_empty(&failed)) { | |
2145 | ret = -ENOSPC; | |
2146 | goto cleanup; | |
2147 | } | |
2148 | ||
2149 | list_for_each_entry(dev_res, &saved, list) { | |
2150 | /* Skip the bridge we just assigned resources for. */ | |
2151 | if (bridge == dev_res->dev) | |
2152 | continue; | |
2153 | ||
2154 | bridge = dev_res->dev; | |
2155 | pci_setup_bridge(bridge->subordinate); | |
2156 | } | |
2157 | ||
2158 | free_list(&saved); | |
2159 | return 0; | |
2160 | ||
2161 | cleanup: | |
2162 | /* restore size and flags */ | |
2163 | list_for_each_entry(dev_res, &failed, list) { | |
2164 | struct resource *res = dev_res->res; | |
2165 | ||
2166 | res->start = dev_res->start; | |
2167 | res->end = dev_res->end; | |
2168 | res->flags = dev_res->flags; | |
2169 | } | |
2170 | free_list(&failed); | |
2171 | ||
2172 | /* Revert to the old configuration */ | |
2173 | list_for_each_entry(dev_res, &saved, list) { | |
2174 | struct resource *res = dev_res->res; | |
2175 | ||
2176 | bridge = dev_res->dev; | |
2177 | i = res - bridge->resource; | |
2178 | ||
2179 | res->start = dev_res->start; | |
2180 | res->end = dev_res->end; | |
2181 | res->flags = dev_res->flags; | |
2182 | ||
2183 | pci_claim_resource(bridge, i); | |
2184 | pci_setup_bridge(bridge->subordinate); | |
2185 | } | |
2186 | free_list(&saved); | |
2187 | ||
2188 | return ret; | |
2189 | } | |
2190 | ||
17787940 | 2191 | void pci_assign_unassigned_bus_resources(struct pci_bus *bus) |
9b03088f | 2192 | { |
9b03088f | 2193 | struct pci_dev *dev; |
bdc4abec | 2194 | LIST_HEAD(add_list); /* list of resources that |
9b03088f YL |
2195 | want additional resources */ |
2196 | ||
9b03088f | 2197 | down_read(&pci_bus_sem); |
24a0c654 AS |
2198 | for_each_pci_bridge(dev, bus) |
2199 | if (pci_has_subordinate(dev)) | |
2200 | __pci_bus_size_bridges(dev->subordinate, &add_list); | |
9b03088f YL |
2201 | up_read(&pci_bus_sem); |
2202 | __pci_bus_assign_resources(bus, &add_list, NULL); | |
bdc4abec | 2203 | BUG_ON(!list_empty(&add_list)); |
17787940 | 2204 | } |
e6b29dea | 2205 | EXPORT_SYMBOL_GPL(pci_assign_unassigned_bus_resources); |