[mirror_ubuntu-jammy-kernel.git] / drivers / pci / setup-res.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Support routines for initializing a PCI subsystem
 *
 * Extruded from code written by
 *      Dave Rusling (david.rusling@reo.mts.dec.com)
 *      David Mosberger (davidm@cs.arizona.edu)
 *	David Miller (davem@redhat.com)
 *
 * Fixed for multiple PCI buses, 1999 Andrea Arcangeli <andrea@suse.de>
 *
 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
 *	     Resource sorting
 */

#include <linux/kernel.h>
#include <linux/export.h>
#include <linux/pci.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/cache.h>
#include <linux/slab.h>
#include "pci.h"

static void pci_std_update_resource(struct pci_dev *dev, int resno)
{
	struct pci_bus_region region;
	bool disable;
	u16 cmd;
	u32 new, check, mask;
	int reg;
	struct resource *res = dev->resource + resno;

	/* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */
	if (dev->is_virtfn)
		return;

	/*
	 * Ignore resources for unimplemented BARs and unused resource slots
	 * for 64 bit BARs.
	 */
	if (!res->flags)
		return;

	if (res->flags & IORESOURCE_UNSET)
		return;

	/*
	 * Ignore non-moveable resources.  This might be legacy resources for
	 * which no functional BAR register exists or another important
	 * system resource we shouldn't move around.
	 */
	if (res->flags & IORESOURCE_PCI_FIXED)
		return;

	pcibios_resource_to_bus(dev->bus, &region, res);
	new = region.start;

	if (res->flags & IORESOURCE_IO) {
		mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
		new |= res->flags & ~PCI_BASE_ADDRESS_IO_MASK;
	} else if (resno == PCI_ROM_RESOURCE) {
		mask = PCI_ROM_ADDRESS_MASK;
	} else {
		mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
		new |= res->flags & ~PCI_BASE_ADDRESS_MEM_MASK;
	}

	if (resno < PCI_ROM_RESOURCE) {
		reg = PCI_BASE_ADDRESS_0 + 4 * resno;
	} else if (resno == PCI_ROM_RESOURCE) {

		/*
		 * Apparently some Matrox devices have ROM BARs that read
		 * as zero when disabled, so don't update ROM BARs unless
		 * they're enabled.  See
		 * https://lore.kernel.org/r/43147B3D.1030309@vc.cvut.cz/
		 */
		if (!(res->flags & IORESOURCE_ROM_ENABLE))
			return;

		reg = dev->rom_base_reg;
		new |= PCI_ROM_ADDRESS_ENABLE;
	} else
		return;

	/*
	 * We can't update a 64-bit BAR atomically, so when possible,
	 * disable decoding so that a half-updated BAR won't conflict
	 * with another device.
	 */
	disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on;
	if (disable) {
		pci_read_config_word(dev, PCI_COMMAND, &cmd);
		pci_write_config_word(dev, PCI_COMMAND,
				      cmd & ~PCI_COMMAND_MEMORY);
	}

	pci_write_config_dword(dev, reg, new);
	pci_read_config_dword(dev, reg, &check);

	if ((new ^ check) & mask) {
		pci_err(dev, "BAR %d: error updating (%#08x != %#08x)\n",
			resno, new, check);
	}

	if (res->flags & IORESOURCE_MEM_64) {
		new = region.start >> 16 >> 16;
		pci_write_config_dword(dev, reg + 4, new);
		pci_read_config_dword(dev, reg + 4, &check);
		if (check != new) {
			pci_err(dev, "BAR %d: error updating (high %#08x != %#08x)\n",
				resno, new, check);
		}
	}

	if (disable)
		pci_write_config_word(dev, PCI_COMMAND, cmd);
}

void pci_update_resource(struct pci_dev *dev, int resno)
{
	if (resno <= PCI_ROM_RESOURCE)
		pci_std_update_resource(dev, resno);
#ifdef CONFIG_PCI_IOV
	else if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
		pci_iov_update_resource(dev, resno);
#endif
}

int pci_claim_resource(struct pci_dev *dev, int resource)
{
	struct resource *res = &dev->resource[resource];
	struct resource *root, *conflict;

	if (res->flags & IORESOURCE_UNSET) {
		pci_info(dev, "can't claim BAR %d %pR: no address assigned\n",
			 resource, res);
		return -EINVAL;
	}

	/*
	 * If we have a shadow copy in RAM, the PCI device doesn't respond
	 * to the shadow range, so we don't need to claim it, and upstream
	 * bridges don't need to route the range to the device.
	 */
	if (res->flags & IORESOURCE_ROM_SHADOW)
		return 0;

	root = pci_find_parent_resource(dev, res);
	if (!root) {
		pci_info(dev, "can't claim BAR %d %pR: no compatible bridge window\n",
			 resource, res);
		res->flags |= IORESOURCE_UNSET;
		return -EINVAL;
	}

	conflict = request_resource_conflict(root, res);
	if (conflict) {
		pci_info(dev, "can't claim BAR %d %pR: address conflict with %s %pR\n",
			 resource, res, conflict->name, conflict);
		res->flags |= IORESOURCE_UNSET;
		return -EBUSY;
	}

	return 0;
}
EXPORT_SYMBOL(pci_claim_resource);

void pci_disable_bridge_window(struct pci_dev *dev)
{
	/* MMIO Base/Limit */
	pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);

	/* Prefetchable MMIO Base/Limit */
	pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
	pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
	pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
}

/*
 * Generic function that returns a value indicating that the device's
 * original BIOS BAR address was not saved and so is not available for
 * reinstatement.
 *
 * Can be over-ridden by architecture specific code that implements
 * reinstatement functionality rather than leaving it disabled when
 * normal allocation attempts fail.
 */
resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
{
	return 0;
}

static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev,
		int resno, resource_size_t size)
{
	struct resource *root, *conflict;
	resource_size_t fw_addr, start, end;

	fw_addr = pcibios_retrieve_fw_addr(dev, resno);
	if (!fw_addr)
		return -ENOMEM;

	start = res->start;
	end = res->end;
	res->start = fw_addr;
	res->end = res->start + size - 1;
	res->flags &= ~IORESOURCE_UNSET;

	root = pci_find_parent_resource(dev, res);
	if (!root) {
		if (res->flags & IORESOURCE_IO)
			root = &ioport_resource;
		else
			root = &iomem_resource;
	}

	pci_info(dev, "BAR %d: trying firmware assignment %pR\n",
		 resno, res);
	conflict = request_resource_conflict(root, res);
	if (conflict) {
		pci_info(dev, "BAR %d: %pR conflicts with %s %pR\n",
			 resno, res, conflict->name, conflict);
		res->start = start;
		res->end = end;
		res->flags |= IORESOURCE_UNSET;
		return -EBUSY;
	}
	return 0;
}

/*
 * We don't have to worry about legacy ISA devices, so nothing to do here.
 * This is marked as __weak because multiple architectures define it; it should
 * eventually go away.
 */
resource_size_t __weak pcibios_align_resource(void *data,
					      const struct resource *res,
					      resource_size_t size,
					      resource_size_t align)
{
       return res->start;
}

static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
		int resno, resource_size_t size, resource_size_t align)
{
	struct resource *res = dev->resource + resno;
	resource_size_t min;
	int ret;

	min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;

	/*
	 * First, try exact prefetching match.  Even if a 64-bit
	 * prefetchable bridge window is below 4GB, we can't put a 32-bit
	 * prefetchable resource in it because pbus_size_mem() assumes a
	 * 64-bit window will contain no 32-bit resources.  If we assign
	 * things differently than they were sized, not everything will fit.
	 */
	ret = pci_bus_alloc_resource(bus, res, size, align, min,
				     IORESOURCE_PREFETCH | IORESOURCE_MEM_64,
				     pcibios_align_resource, dev);
	if (ret == 0)
		return 0;

	/*
	 * If the prefetchable window is only 32 bits wide, we can put
	 * 64-bit prefetchable resources in it.
	 */
	if ((res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) ==
	     (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) {
		ret = pci_bus_alloc_resource(bus, res, size, align, min,
					     IORESOURCE_PREFETCH,
					     pcibios_align_resource, dev);
		if (ret == 0)
			return 0;
	}

	/*
	 * If we didn't find a better match, we can put any memory resource
	 * in a non-prefetchable window.  If this resource is 32 bits and
	 * non-prefetchable, the first call already tried the only possibility
	 * so we don't need to try again.
	 */
	if (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64))
		ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
					     pcibios_align_resource, dev);

	return ret;
}

static int _pci_assign_resource(struct pci_dev *dev, int resno,
				resource_size_t size, resource_size_t min_align)
{
	struct pci_bus *bus;
	int ret;

	bus = dev->bus;
	while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
		if (!bus->parent || !bus->self->transparent)
			break;
		bus = bus->parent;
	}

	return ret;
}

int pci_assign_resource(struct pci_dev *dev, int resno)
{
	struct resource *res = dev->resource + resno;
	resource_size_t align, size;
	int ret;

	if (res->flags & IORESOURCE_PCI_FIXED)
		return 0;

	res->flags |= IORESOURCE_UNSET;
	align = pci_resource_alignment(dev, res);
	if (!align) {
		pci_info(dev, "BAR %d: can't assign %pR (bogus alignment)\n",
			 resno, res);
		return -EINVAL;
	}

	size = resource_size(res);
	ret = _pci_assign_resource(dev, resno, size, align);

	/*
	 * If we failed to assign anything, let's try the address
	 * where firmware left it.  That at least has a chance of
	 * working, which is better than just leaving it disabled.
	 */
	if (ret < 0) {
		pci_info(dev, "BAR %d: no space for %pR\n", resno, res);
		ret = pci_revert_fw_address(res, dev, resno, size);
	}

	if (ret < 0) {
		pci_info(dev, "BAR %d: failed to assign %pR\n", resno, res);
		return ret;
	}

	res->flags &= ~IORESOURCE_UNSET;
	res->flags &= ~IORESOURCE_STARTALIGN;
	pci_info(dev, "BAR %d: assigned %pR\n", resno, res);
	if (resno < PCI_BRIDGE_RESOURCES)
		pci_update_resource(dev, resno);

	return 0;
}
EXPORT_SYMBOL(pci_assign_resource);

int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
			resource_size_t min_align)
{
	struct resource *res = dev->resource + resno;
	unsigned long flags;
	resource_size_t new_size;
	int ret;

	if (res->flags & IORESOURCE_PCI_FIXED)
		return 0;

	flags = res->flags;
	res->flags |= IORESOURCE_UNSET;
	if (!res->parent) {
		pci_info(dev, "BAR %d: can't reassign an unassigned resource %pR\n",
			 resno, res);
		return -EINVAL;
	}

	/* already aligned with min_align */
	new_size = resource_size(res) + addsize;
	ret = _pci_assign_resource(dev, resno, new_size, min_align);
	if (ret) {
		res->flags = flags;
		pci_info(dev, "BAR %d: %pR (failed to expand by %#llx)\n",
			 resno, res, (unsigned long long) addsize);
		return ret;
	}

	res->flags &= ~IORESOURCE_UNSET;
	res->flags &= ~IORESOURCE_STARTALIGN;
	pci_info(dev, "BAR %d: reassigned %pR (expanded by %#llx)\n",
		 resno, res, (unsigned long long) addsize);
	if (resno < PCI_BRIDGE_RESOURCES)
		pci_update_resource(dev, resno);

	return 0;
}

void pci_release_resource(struct pci_dev *dev, int resno)
{
	struct resource *res = dev->resource + resno;

	pci_info(dev, "BAR %d: releasing %pR\n", resno, res);

	if (!res->parent)
		return;

	release_resource(res);
	res->end = resource_size(res) - 1;
	res->start = 0;
	res->flags |= IORESOURCE_UNSET;
}
EXPORT_SYMBOL(pci_release_resource);

int pci_resize_resource(struct pci_dev *dev, int resno, int size)
{
	struct resource *res = dev->resource + resno;
	struct pci_host_bridge *host;
	int old, ret;
	u32 sizes;
	u16 cmd;

	/* Check if we must preserve the firmware's resource assignment */
	host = pci_find_host_bridge(dev->bus);
	if (host->preserve_config)
		return -ENOTSUPP;

	/* Make sure the resource isn't assigned before resizing it. */
	if (!(res->flags & IORESOURCE_UNSET))
		return -EBUSY;

	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	if (cmd & PCI_COMMAND_MEMORY)
		return -EBUSY;

	sizes = pci_rebar_get_possible_sizes(dev, resno);
	if (!sizes)
		return -ENOTSUPP;

	if (!(sizes & BIT(size)))
		return -EINVAL;

	old = pci_rebar_get_current_size(dev, resno);
	if (old < 0)
		return old;

	ret = pci_rebar_set_size(dev, resno, size);
	if (ret)
		return ret;

	res->end = res->start + pci_rebar_size_to_bytes(size) - 1;

	/* Check if the new config works by trying to assign everything. */
	if (dev->bus->self) {
		ret = pci_reassign_bridge_resources(dev->bus->self, res->flags);
		if (ret)
			goto error_resize;
	}
	return 0;

error_resize:
	pci_rebar_set_size(dev, resno, old);
	res->end = res->start + pci_rebar_size_to_bytes(old) - 1;
	return ret;
}
EXPORT_SYMBOL(pci_resize_resource);

int pci_enable_resources(struct pci_dev *dev, int mask)
{
	u16 cmd, old_cmd;
	int i;
	struct resource *r;

	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	old_cmd = cmd;

	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
		if (!(mask & (1 << i)))
			continue;

		r = &dev->resource[i];

		if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
			continue;
		if ((i == PCI_ROM_RESOURCE) &&
				(!(r->flags & IORESOURCE_ROM_ENABLE)))
			continue;

		if (r->flags & IORESOURCE_UNSET) {
			pci_err(dev, "can't enable device: BAR %d %pR not assigned\n",
				i, r);
			return -EINVAL;
		}

		if (!r->parent) {
			pci_err(dev, "can't enable device: BAR %d %pR not claimed\n",
				i, r);
			return -EINVAL;
		}

		if (r->flags & IORESOURCE_IO)
			cmd |= PCI_COMMAND_IO;
		if (r->flags & IORESOURCE_MEM)
			cmd |= PCI_COMMAND_MEMORY;
	}

	if (cmd != old_cmd) {
		pci_info(dev, "enabling device (%04x -> %04x)\n", old_cmd, cmd);
		pci_write_config_word(dev, PCI_COMMAND, cmd);
	}
	return 0;
}
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
1da177e4	2	/*
df62ab5e	3	* Support routines for initializing a PCI subsystem
1da177e4 LT	4	*
	5	* Extruded from code written by
	6	* Dave Rusling (david.rusling@reo.mts.dec.com)
	7	* David Mosberger (davidm@cs.arizona.edu)
	8	* David Miller (davem@redhat.com)
	9	*
df62ab5e BH	10	* Fixed for multiple PCI buses, 1999 Andrea Arcangeli <andrea@suse.de>
df62ab5e BH	11	*
1da177e4 LT	12	* Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
	13	* Resource sorting
	14	*/
	15
1da177e4	16	#include <linux/kernel.h>
363c75db	17	#include <linux/export.h>
1da177e4 LT	18	#include <linux/pci.h>
	19	#include <linux/errno.h>
	20	#include <linux/ioport.h>
	21	#include <linux/cache.h>
	22	#include <linux/slab.h>
	23	#include "pci.h"
	24
6ffa2489	25	static void pci_std_update_resource(struct pci_dev *dev, int resno)
1da177e4 LT	26	{
1da177e4 LT	27	struct pci_bus_region region;
9aac537e BH	28	bool disable;
9aac537e BH	29	u16 cmd;
1da177e4 LT	30	u32 new, check, mask;
1da177e4 LT	31	int reg;
14add80b	32	struct resource *res = dev->resource + resno;
1da177e4	33
63880b23 BH	34	/* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */
63880b23 BH	35	if (dev->is_virtfn)
70675e0b	36	return;
70675e0b	37
fb0f2b40 RB	38	/*
	39	* Ignore resources for unimplemented BARs and unused resource slots
	40	* for 64 bit BARs.
	41	*/
cf7bee5a IK	42	if (!res->flags)
	43	return;
	44
cd8a4d36 BH	45	if (res->flags & IORESOURCE_UNSET)
	46	return;
	47
fb0f2b40 RB	48	/*
	49	* Ignore non-moveable resources. This might be legacy resources for
	50	* which no functional BAR register exists or another important
80ccba11	51	* system resource we shouldn't move around.
fb0f2b40 RB	52	*/
	53	if (res->flags & IORESOURCE_PCI_FIXED)
	54	return;
	55
fc279850	56	pcibios_resource_to_bus(dev->bus, &region, res);
45d004f4	57	new = region.start;
1da177e4	58
45d004f4	59	if (res->flags & IORESOURCE_IO) {
1da177e4	60	mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
45d004f4 BH	61	new \|= res->flags & ~PCI_BASE_ADDRESS_IO_MASK;
45d004f4 BH	62	} else if (resno == PCI_ROM_RESOURCE) {
76dc5268	63	mask = PCI_ROM_ADDRESS_MASK;
45d004f4	64	} else {
1da177e4	65	mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
45d004f4 BH	66	new \|= res->flags & ~PCI_BASE_ADDRESS_MEM_MASK;
45d004f4 BH	67	}
1da177e4	68
286c2378 BH	69	if (resno < PCI_ROM_RESOURCE) {
	70	reg = PCI_BASE_ADDRESS_0 + 4 * resno;
	71	} else if (resno == PCI_ROM_RESOURCE) {
0b457dde BH	72
	73	/*
	74	* Apparently some Matrox devices have ROM BARs that read
	75	* as zero when disabled, so don't update ROM BARs unless
16bbbc87 BH	76	* they're enabled. See
16bbbc87 BH	77	* https://lore.kernel.org/r/43147B3D.1030309@vc.cvut.cz/
0b457dde	78	*/
755528c8 LT	79	if (!(res->flags & IORESOURCE_ROM_ENABLE))
755528c8 LT	80	return;
286c2378 BH	81
286c2378 BH	82	reg = dev->rom_base_reg;
755528c8	83	new \|= PCI_ROM_ADDRESS_ENABLE;
286c2378 BH	84	} else
286c2378 BH	85	return;
1da177e4	86
9aac537e BH	87	/*
	88	* We can't update a 64-bit BAR atomically, so when possible,
	89	* disable decoding so that a half-updated BAR won't conflict
	90	* with another device.
	91	*/
	92	disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on;
	93	if (disable) {
	94	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	95	pci_write_config_word(dev, PCI_COMMAND,
	96	cmd & ~PCI_COMMAND_MEMORY);
	97	}
	98
1da177e4 LT	99	pci_write_config_dword(dev, reg, new);
	100	pci_read_config_dword(dev, reg, &check);
	101
	102	if ((new ^ check) & mask) {
7506dc79	103	pci_err(dev, "BAR %d: error updating (%#08x != %#08x)\n",
80ccba11	104	resno, new, check);
1da177e4 LT	105	}
1da177e4 LT	106
28c6821a	107	if (res->flags & IORESOURCE_MEM_64) {
cf7bee5a	108	new = region.start >> 16 >> 16;
1da177e4 LT	109	pci_write_config_dword(dev, reg + 4, new);
	110	pci_read_config_dword(dev, reg + 4, &check);
	111	if (check != new) {
7506dc79	112	pci_err(dev, "BAR %d: error updating (high %#08x != %#08x)\n",
227f0647	113	resno, new, check);
1da177e4 LT	114	}
1da177e4 LT	115	}
9aac537e BH	116
	117	if (disable)
	118	pci_write_config_word(dev, PCI_COMMAND, cmd);
1da177e4 LT	119	}
1da177e4 LT	120
6ffa2489 BH	121	void pci_update_resource(struct pci_dev *dev, int resno)
	122	{
	123	if (resno <= PCI_ROM_RESOURCE)
	124	pci_std_update_resource(dev, resno);
	125	#ifdef CONFIG_PCI_IOV
	126	else if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
	127	pci_iov_update_resource(dev, resno);
	128	#endif
	129	}
	130
96bde06a	131	int pci_claim_resource(struct pci_dev *dev, int resource)
1da177e4 LT	132	{
1da177e4 LT	133	struct resource *res = &dev->resource[resource];
966f3a75	134	struct resource root, conflict;
1da177e4	135
29003beb	136	if (res->flags & IORESOURCE_UNSET) {
7506dc79	137	pci_info(dev, "can't claim BAR %d %pR: no address assigned\n",
29003beb BH	138	resource, res);
	139	return -EINVAL;
	140	}
	141
16d917b1 BH	142	/*
	143	* If we have a shadow copy in RAM, the PCI device doesn't respond
	144	* to the shadow range, so we don't need to claim it, and upstream
	145	* bridges don't need to route the range to the device.
	146	*/
	147	if (res->flags & IORESOURCE_ROM_SHADOW)
	148	return 0;
	149
cebd78a8	150	root = pci_find_parent_resource(dev, res);
865df576	151	if (!root) {
7506dc79	152	pci_info(dev, "can't claim BAR %d %pR: no compatible bridge window\n",
29003beb	153	resource, res);
c770cb4c	154	res->flags \|= IORESOURCE_UNSET;
865df576	155	return -EINVAL;
1da177e4 LT	156	}
1da177e4 LT	157
966f3a75 BH	158	conflict = request_resource_conflict(root, res);
966f3a75 BH	159	if (conflict) {
7506dc79	160	pci_info(dev, "can't claim BAR %d %pR: address conflict with %s %pR\n",
29003beb	161	resource, res, conflict->name, conflict);
c770cb4c	162	res->flags \|= IORESOURCE_UNSET;
966f3a75 BH	163	return -EBUSY;
966f3a75 BH	164	}
865df576	165
966f3a75	166	return 0;
1da177e4	167	}
eaa959df	168	EXPORT_SYMBOL(pci_claim_resource);
1da177e4	169
32a9a682 YS	170	void pci_disable_bridge_window(struct pci_dev *dev)
32a9a682 YS	171	{
32a9a682 YS	172	/* MMIO Base/Limit */
	173	pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
	174
	175	/* Prefetchable MMIO Base/Limit */
	176	pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
	177	pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
	178	pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
	179	}
2bbc6942	180
6535943f MS	181	/*
	182	* Generic function that returns a value indicating that the device's
	183	* original BIOS BAR address was not saved and so is not available for
	184	* reinstatement.
	185	*
	186	* Can be over-ridden by architecture specific code that implements
	187	* reinstatement functionality rather than leaving it disabled when
	188	* normal allocation attempts fail.
	189	*/
	190	resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
	191	{
	192	return 0;
	193	}
	194
f7625980	195	static int pci_revert_fw_address(struct resource res, struct pci_dev dev,
2bbc6942 RP	196	int resno, resource_size_t size)
	197	{
	198	struct resource root, conflict;
6535943f	199	resource_size_t fw_addr, start, end;
58c84eda	200
6535943f MS	201	fw_addr = pcibios_retrieve_fw_addr(dev, resno);
6535943f MS	202	if (!fw_addr)
94778835	203	return -ENOMEM;
6535943f	204
2bbc6942 RP	205	start = res->start;
2bbc6942 RP	206	end = res->end;
6535943f	207	res->start = fw_addr;
2bbc6942	208	res->end = res->start + size - 1;
0b26cd69	209	res->flags &= ~IORESOURCE_UNSET;
351fc6d1 MS	210
	211	root = pci_find_parent_resource(dev, res);
	212	if (!root) {
	213	if (res->flags & IORESOURCE_IO)
	214	root = &ioport_resource;
	215	else
	216	root = &iomem_resource;
	217	}
	218
7506dc79	219	pci_info(dev, "BAR %d: trying firmware assignment %pR\n",
2bbc6942 RP	220	resno, res);
	221	conflict = request_resource_conflict(root, res);
	222	if (conflict) {
7506dc79	223	pci_info(dev, "BAR %d: %pR conflicts with %s %pR\n",
94778835	224	resno, res, conflict->name, conflict);
2bbc6942 RP	225	res->start = start;
2bbc6942 RP	226	res->end = end;
0b26cd69	227	res->flags \|= IORESOURCE_UNSET;
94778835	228	return -EBUSY;
2bbc6942	229	}
94778835	230	return 0;
2bbc6942 RP	231	}
2bbc6942 RP	232
ecf677c8 PD	233	/*
	234	* We don't have to worry about legacy ISA devices, so nothing to do here.
	235	* This is marked as __weak because multiple architectures define it; it should
	236	* eventually go away.
	237	*/
	238	resource_size_t __weak pcibios_align_resource(void *data,
	239	const struct resource *res,
	240	resource_size_t size,
	241	resource_size_t align)
	242	{
	243	return res->start;
	244	}
	245
fe6dacdb BH	246	static int __pci_assign_resource(struct pci_bus bus, struct pci_dev dev,
	247	int resno, resource_size_t size, resource_size_t align)
	248	{
	249	struct resource *res = dev->resource + resno;
	250	resource_size_t min;
	251	int ret;
	252
	253	min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
	254
67d29b5c BH	255	/*
	256	* First, try exact prefetching match. Even if a 64-bit
	257	* prefetchable bridge window is below 4GB, we can't put a 32-bit
	258	* prefetchable resource in it because pbus_size_mem() assumes a
	259	* 64-bit window will contain no 32-bit resources. If we assign
	260	* things differently than they were sized, not everything will fit.
	261	*/
fe6dacdb	262	ret = pci_bus_alloc_resource(bus, res, size, align, min,
5b285415	263	IORESOURCE_PREFETCH \| IORESOURCE_MEM_64,
fe6dacdb	264	pcibios_align_resource, dev);
d3689df0 BH	265	if (ret == 0)
d3689df0 BH	266	return 0;
fe6dacdb	267
67d29b5c BH	268	/*
	269	* If the prefetchable window is only 32 bits wide, we can put
	270	* 64-bit prefetchable resources in it.
	271	*/
d3689df0	272	if ((res->flags & (IORESOURCE_PREFETCH \| IORESOURCE_MEM_64)) ==
5b285415	273	(IORESOURCE_PREFETCH \| IORESOURCE_MEM_64)) {
5b285415 YL	274	ret = pci_bus_alloc_resource(bus, res, size, align, min,
5b285415 YL	275	IORESOURCE_PREFETCH,
fe6dacdb	276	pcibios_align_resource, dev);
d3689df0 BH	277	if (ret == 0)
d3689df0 BH	278	return 0;
fe6dacdb	279	}
5b285415	280
67d29b5c BH	281	/*
	282	* If we didn't find a better match, we can put any memory resource
	283	* in a non-prefetchable window. If this resource is 32 bits and
	284	* non-prefetchable, the first call already tried the only possibility
	285	* so we don't need to try again.
	286	*/
	287	if (res->flags & (IORESOURCE_PREFETCH \| IORESOURCE_MEM_64))
fe6dacdb BH	288	ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
fe6dacdb BH	289	pcibios_align_resource, dev);
67d29b5c	290
fe6dacdb BH	291	return ret;
	292	}
	293
d6776e6d NR	294	static int _pci_assign_resource(struct pci_dev *dev, int resno,
d6776e6d NR	295	resource_size_t size, resource_size_t min_align)
2bbc6942	296	{
2bbc6942 RP	297	struct pci_bus *bus;
2bbc6942 RP	298	int ret;
58c84eda	299
2bbc6942 RP	300	bus = dev->bus;
	301	while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
	302	if (!bus->parent \|\| !bus->self->transparent)
	303	break;
	304	bus = bus->parent;
	305	}
	306
2bbc6942 RP	307	return ret;
	308	}
	309
d09ee968 YL	310	int pci_assign_resource(struct pci_dev *dev, int resno)
	311	{
	312	struct resource *res = dev->resource + resno;
2bbc6942	313	resource_size_t align, size;
d09ee968 YL	314	int ret;
d09ee968 YL	315
2ea4adf7 BH	316	if (res->flags & IORESOURCE_PCI_FIXED)
	317	return 0;
	318
bd064f0a	319	res->flags \|= IORESOURCE_UNSET;
6faf17f6	320	align = pci_resource_alignment(dev, res);
d09ee968	321	if (!align) {
7506dc79	322	pci_info(dev, "BAR %d: can't assign %pR (bogus alignment)\n",
227f0647	323	resno, res);
d09ee968 YL	324	return -EINVAL;
	325	}
	326
2bbc6942 RP	327	size = resource_size(res);
2bbc6942 RP	328	ret = _pci_assign_resource(dev, resno, size, align);
d09ee968	329
2bbc6942 RP	330	/*
	331	* If we failed to assign anything, let's try the address
	332	* where firmware left it. That at least has a chance of
	333	* working, which is better than just leaving it disabled.
	334	*/
64da465e	335	if (ret < 0) {
7506dc79	336	pci_info(dev, "BAR %d: no space for %pR\n", resno, res);
2bbc6942	337	ret = pci_revert_fw_address(res, dev, resno, size);
64da465e	338	}
d09ee968	339
64da465e	340	if (ret < 0) {
7506dc79	341	pci_info(dev, "BAR %d: failed to assign %pR\n", resno, res);
28f6dbe2	342	return ret;
64da465e	343	}
28f6dbe2 BH	344
	345	res->flags &= ~IORESOURCE_UNSET;
	346	res->flags &= ~IORESOURCE_STARTALIGN;
7506dc79	347	pci_info(dev, "BAR %d: assigned %pR\n", resno, res);
28f6dbe2 BH	348	if (resno < PCI_BRIDGE_RESOURCES)
	349	pci_update_resource(dev, resno);
	350
	351	return 0;
d09ee968	352	}
b7fe9434	353	EXPORT_SYMBOL(pci_assign_resource);
d09ee968	354
fe6dacdb BH	355	int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
	356	resource_size_t min_align)
	357	{
	358	struct resource *res = dev->resource + resno;
c3337708	359	unsigned long flags;
fe6dacdb BH	360	resource_size_t new_size;
	361	int ret;
	362
2ea4adf7 BH	363	if (res->flags & IORESOURCE_PCI_FIXED)
	364	return 0;
	365
c3337708	366	flags = res->flags;
bd064f0a	367	res->flags \|= IORESOURCE_UNSET;
fe6dacdb	368	if (!res->parent) {
7506dc79	369	pci_info(dev, "BAR %d: can't reassign an unassigned resource %pR\n",
227f0647	370	resno, res);
fe6dacdb BH	371	return -EINVAL;
	372	}
	373
	374	/* already aligned with min_align */
	375	new_size = resource_size(res) + addsize;
	376	ret = _pci_assign_resource(dev, resno, new_size, min_align);
28f6dbe2	377	if (ret) {
c3337708	378	res->flags = flags;
7506dc79	379	pci_info(dev, "BAR %d: %pR (failed to expand by %#llx)\n",
c3337708	380	resno, res, (unsigned long long) addsize);
28f6dbe2	381	return ret;
fe6dacdb	382	}
c3337708	383
28f6dbe2 BH	384	res->flags &= ~IORESOURCE_UNSET;
28f6dbe2 BH	385	res->flags &= ~IORESOURCE_STARTALIGN;
7506dc79	386	pci_info(dev, "BAR %d: reassigned %pR (expanded by %#llx)\n",
64da465e	387	resno, res, (unsigned long long) addsize);
28f6dbe2 BH	388	if (resno < PCI_BRIDGE_RESOURCES)
	389	pci_update_resource(dev, resno);
	390
	391	return 0;
fe6dacdb BH	392	}
fe6dacdb BH	393
8bb705e3 CK	394	void pci_release_resource(struct pci_dev *dev, int resno)
	395	{
	396	struct resource *res = dev->resource + resno;
	397
7506dc79	398	pci_info(dev, "BAR %d: releasing %pR\n", resno, res);
c37406e0 CK	399
	400	if (!res->parent)
	401	return;
	402
8bb705e3 CK	403	release_resource(res);
	404	res->end = resource_size(res) - 1;
	405	res->start = 0;
	406	res->flags \|= IORESOURCE_UNSET;
	407	}
	408	EXPORT_SYMBOL(pci_release_resource);
	409
	410	int pci_resize_resource(struct pci_dev *dev, int resno, int size)
	411	{
	412	struct resource *res = dev->resource + resno;
729e3a66	413	struct pci_host_bridge *host;
8bb705e3 CK	414	int old, ret;
	415	u32 sizes;
	416	u16 cmd;
	417
729e3a66 AB	418	/* Check if we must preserve the firmware's resource assignment */
	419	host = pci_find_host_bridge(dev->bus);
	420	if (host->preserve_config)
	421	return -ENOTSUPP;
	422
8bb705e3 CK	423	/* Make sure the resource isn't assigned before resizing it. */
	424	if (!(res->flags & IORESOURCE_UNSET))
	425	return -EBUSY;
	426
	427	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	428	if (cmd & PCI_COMMAND_MEMORY)
	429	return -EBUSY;
	430
	431	sizes = pci_rebar_get_possible_sizes(dev, resno);
	432	if (!sizes)
	433	return -ENOTSUPP;
	434
	435	if (!(sizes & BIT(size)))
	436	return -EINVAL;
	437
	438	old = pci_rebar_get_current_size(dev, resno);
	439	if (old < 0)
	440	return old;
	441
	442	ret = pci_rebar_set_size(dev, resno, size);
	443	if (ret)
	444	return ret;
	445
	446	res->end = res->start + pci_rebar_size_to_bytes(size) - 1;
	447
	448	/* Check if the new config works by trying to assign everything. */
d09ddd81 AB	449	if (dev->bus->self) {
	450	ret = pci_reassign_bridge_resources(dev->bus->self, res->flags);
	451	if (ret)
	452	goto error_resize;
	453	}
8bb705e3 CK	454	return 0;
	455
	456	error_resize:
	457	pci_rebar_set_size(dev, resno, old);
	458	res->end = res->start + pci_rebar_size_to_bytes(old) - 1;
	459	return ret;
	460	}
	461	EXPORT_SYMBOL(pci_resize_resource);
	462
842de40d BH	463	int pci_enable_resources(struct pci_dev *dev, int mask)
	464	{
	465	u16 cmd, old_cmd;
	466	int i;
	467	struct resource *r;
	468
	469	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	470	old_cmd = cmd;
	471
	472	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
	473	if (!(mask & (1 << i)))
	474	continue;
	475
	476	r = &dev->resource[i];
	477
	478	if (!(r->flags & (IORESOURCE_IO \| IORESOURCE_MEM)))
	479	continue;
	480	if ((i == PCI_ROM_RESOURCE) &&
	481	(!(r->flags & IORESOURCE_ROM_ENABLE)))
	482	continue;
	483
3cedcc36	484	if (r->flags & IORESOURCE_UNSET) {
7506dc79	485	pci_err(dev, "can't enable device: BAR %d %pR not assigned\n",
3cedcc36 BH	486	i, r);
	487	return -EINVAL;
	488	}
	489
842de40d	490	if (!r->parent) {
7506dc79	491	pci_err(dev, "can't enable device: BAR %d %pR not claimed\n",
3cedcc36	492	i, r);
842de40d BH	493	return -EINVAL;
	494	}
	495
	496	if (r->flags & IORESOURCE_IO)
	497	cmd \|= PCI_COMMAND_IO;
	498	if (r->flags & IORESOURCE_MEM)
	499	cmd \|= PCI_COMMAND_MEMORY;
	500	}
	501
	502	if (cmd != old_cmd) {
7506dc79	503	pci_info(dev, "enabling device (%04x -> %04x)\n", old_cmd, cmd);
842de40d BH	504	pci_write_config_word(dev, PCI_COMMAND, cmd);
	505	}
	506	return 0;
	507	}