[mirror_ubuntu-hirsute-kernel.git] / drivers / pci / setup-res.c

// SPDX-License-Identifier: GPL-2.0
/*
 *	drivers/pci/setup-res.c
 *
 * Extruded from code written by
 *      Dave Rusling (david.rusling@reo.mts.dec.com)
 *      David Mosberger (davidm@cs.arizona.edu)
 *	David Miller (davem@redhat.com)
 *
 * Support routines for initializing a PCI subsystem.
 */

/* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */

/*
 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
 *	     Resource sorting
 */

#include <linux/kernel.h>
#include <linux/export.h>
#include <linux/pci.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/cache.h>
#include <linux/slab.h>
#include "pci.h"

static void pci_std_update_resource(struct pci_dev *dev, int resno)
{
	struct pci_bus_region region;
	bool disable;
	u16 cmd;
	u32 new, check, mask;
	int reg;
	struct resource *res = dev->resource + resno;

	/* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */
	if (dev->is_virtfn)
		return;

	/*
	 * Ignore resources for unimplemented BARs and unused resource slots
	 * for 64 bit BARs.
	 */
	if (!res->flags)
		return;

	if (res->flags & IORESOURCE_UNSET)
		return;

	/*
	 * Ignore non-moveable resources.  This might be legacy resources for
	 * which no functional BAR register exists or another important
	 * system resource we shouldn't move around.
	 */
	if (res->flags & IORESOURCE_PCI_FIXED)
		return;

	pcibios_resource_to_bus(dev->bus, &region, res);
	new = region.start;

	if (res->flags & IORESOURCE_IO) {
		mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
		new |= res->flags & ~PCI_BASE_ADDRESS_IO_MASK;
	} else if (resno == PCI_ROM_RESOURCE) {
		mask = PCI_ROM_ADDRESS_MASK;
	} else {
		mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
		new |= res->flags & ~PCI_BASE_ADDRESS_MEM_MASK;
	}

	if (resno < PCI_ROM_RESOURCE) {
		reg = PCI_BASE_ADDRESS_0 + 4 * resno;
	} else if (resno == PCI_ROM_RESOURCE) {

		/*
		 * Apparently some Matrox devices have ROM BARs that read
		 * as zero when disabled, so don't update ROM BARs unless
		 * they're enabled.  See https://lkml.org/lkml/2005/8/30/138.
		 */
		if (!(res->flags & IORESOURCE_ROM_ENABLE))
			return;

		reg = dev->rom_base_reg;
		new |= PCI_ROM_ADDRESS_ENABLE;
	} else
		return;

	/*
	 * We can't update a 64-bit BAR atomically, so when possible,
	 * disable decoding so that a half-updated BAR won't conflict
	 * with another device.
	 */
	disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on;
	if (disable) {
		pci_read_config_word(dev, PCI_COMMAND, &cmd);
		pci_write_config_word(dev, PCI_COMMAND,
				      cmd & ~PCI_COMMAND_MEMORY);
	}

	pci_write_config_dword(dev, reg, new);
	pci_read_config_dword(dev, reg, &check);

	if ((new ^ check) & mask) {
		pci_err(dev, "BAR %d: error updating (%#08x != %#08x)\n",
			resno, new, check);
	}

	if (res->flags & IORESOURCE_MEM_64) {
		new = region.start >> 16 >> 16;
		pci_write_config_dword(dev, reg + 4, new);
		pci_read_config_dword(dev, reg + 4, &check);
		if (check != new) {
			pci_err(dev, "BAR %d: error updating (high %#08x != %#08x)\n",
				resno, new, check);
		}
	}

	if (disable)
		pci_write_config_word(dev, PCI_COMMAND, cmd);
}

void pci_update_resource(struct pci_dev *dev, int resno)
{
	if (resno <= PCI_ROM_RESOURCE)
		pci_std_update_resource(dev, resno);
#ifdef CONFIG_PCI_IOV
	else if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
		pci_iov_update_resource(dev, resno);
#endif
}

int pci_claim_resource(struct pci_dev *dev, int resource)
{
	struct resource *res = &dev->resource[resource];
	struct resource *root, *conflict;

	if (res->flags & IORESOURCE_UNSET) {
		pci_info(dev, "can't claim BAR %d %pR: no address assigned\n",
			 resource, res);
		return -EINVAL;
	}

	/*
	 * If we have a shadow copy in RAM, the PCI device doesn't respond
	 * to the shadow range, so we don't need to claim it, and upstream
	 * bridges don't need to route the range to the device.
	 */
	if (res->flags & IORESOURCE_ROM_SHADOW)
		return 0;

	root = pci_find_parent_resource(dev, res);
	if (!root) {
		pci_info(dev, "can't claim BAR %d %pR: no compatible bridge window\n",
			 resource, res);
		res->flags |= IORESOURCE_UNSET;
		return -EINVAL;
	}

	conflict = request_resource_conflict(root, res);
	if (conflict) {
		pci_info(dev, "can't claim BAR %d %pR: address conflict with %s %pR\n",
			 resource, res, conflict->name, conflict);
		res->flags |= IORESOURCE_UNSET;
		return -EBUSY;
	}

	return 0;
}
EXPORT_SYMBOL(pci_claim_resource);

void pci_disable_bridge_window(struct pci_dev *dev)
{
	pci_info(dev, "disabling bridge mem windows\n");

	/* MMIO Base/Limit */
	pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);

	/* Prefetchable MMIO Base/Limit */
	pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
	pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
	pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
}

/*
 * Generic function that returns a value indicating that the device's
 * original BIOS BAR address was not saved and so is not available for
 * reinstatement.
 *
 * Can be over-ridden by architecture specific code that implements
 * reinstatement functionality rather than leaving it disabled when
 * normal allocation attempts fail.
 */
resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
{
	return 0;
}

static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev,
		int resno, resource_size_t size)
{
	struct resource *root, *conflict;
	resource_size_t fw_addr, start, end;

	fw_addr = pcibios_retrieve_fw_addr(dev, resno);
	if (!fw_addr)
		return -ENOMEM;

	start = res->start;
	end = res->end;
	res->start = fw_addr;
	res->end = res->start + size - 1;
	res->flags &= ~IORESOURCE_UNSET;

	root = pci_find_parent_resource(dev, res);
	if (!root) {
		if (res->flags & IORESOURCE_IO)
			root = &ioport_resource;
		else
			root = &iomem_resource;
	}

	pci_info(dev, "BAR %d: trying firmware assignment %pR\n",
		 resno, res);
	conflict = request_resource_conflict(root, res);
	if (conflict) {
		pci_info(dev, "BAR %d: %pR conflicts with %s %pR\n",
			 resno, res, conflict->name, conflict);
		res->start = start;
		res->end = end;
		res->flags |= IORESOURCE_UNSET;
		return -EBUSY;
	}
	return 0;
}

/*
 * We don't have to worry about legacy ISA devices, so nothing to do here.
 * This is marked as __weak because multiple architectures define it; it should
 * eventually go away.
 */
resource_size_t __weak pcibios_align_resource(void *data,
					      const struct resource *res,
					      resource_size_t size,
					      resource_size_t align)
{
       return res->start;
}

static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
		int resno, resource_size_t size, resource_size_t align)
{
	struct resource *res = dev->resource + resno;
	resource_size_t min;
	int ret;

	min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;

	/*
	 * First, try exact prefetching match.  Even if a 64-bit
	 * prefetchable bridge window is below 4GB, we can't put a 32-bit
	 * prefetchable resource in it because pbus_size_mem() assumes a
	 * 64-bit window will contain no 32-bit resources.  If we assign
	 * things differently than they were sized, not everything will fit.
	 */
	ret = pci_bus_alloc_resource(bus, res, size, align, min,
				     IORESOURCE_PREFETCH | IORESOURCE_MEM_64,
				     pcibios_align_resource, dev);
	if (ret == 0)
		return 0;

	/*
	 * If the prefetchable window is only 32 bits wide, we can put
	 * 64-bit prefetchable resources in it.
	 */
	if ((res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) ==
	     (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) {
		ret = pci_bus_alloc_resource(bus, res, size, align, min,
					     IORESOURCE_PREFETCH,
					     pcibios_align_resource, dev);
		if (ret == 0)
			return 0;
	}

	/*
	 * If we didn't find a better match, we can put any memory resource
	 * in a non-prefetchable window.  If this resource is 32 bits and
	 * non-prefetchable, the first call already tried the only possibility
	 * so we don't need to try again.
	 */
	if (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64))
		ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
					     pcibios_align_resource, dev);

	return ret;
}

static int _pci_assign_resource(struct pci_dev *dev, int resno,
				resource_size_t size, resource_size_t min_align)
{
	struct pci_bus *bus;
	int ret;

	bus = dev->bus;
	while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
		if (!bus->parent || !bus->self->transparent)
			break;
		bus = bus->parent;
	}

	return ret;
}

int pci_assign_resource(struct pci_dev *dev, int resno)
{
	struct resource *res = dev->resource + resno;
	resource_size_t align, size;
	int ret;

	if (res->flags & IORESOURCE_PCI_FIXED)
		return 0;

	res->flags |= IORESOURCE_UNSET;
	align = pci_resource_alignment(dev, res);
	if (!align) {
		pci_info(dev, "BAR %d: can't assign %pR (bogus alignment)\n",
			 resno, res);
		return -EINVAL;
	}

	size = resource_size(res);
	ret = _pci_assign_resource(dev, resno, size, align);

	/*
	 * If we failed to assign anything, let's try the address
	 * where firmware left it.  That at least has a chance of
	 * working, which is better than just leaving it disabled.
	 */
	if (ret < 0) {
		pci_info(dev, "BAR %d: no space for %pR\n", resno, res);
		ret = pci_revert_fw_address(res, dev, resno, size);
	}

	if (ret < 0) {
		pci_info(dev, "BAR %d: failed to assign %pR\n", resno, res);
		return ret;
	}

	res->flags &= ~IORESOURCE_UNSET;
	res->flags &= ~IORESOURCE_STARTALIGN;
	pci_info(dev, "BAR %d: assigned %pR\n", resno, res);
	if (resno < PCI_BRIDGE_RESOURCES)
		pci_update_resource(dev, resno);

	return 0;
}
EXPORT_SYMBOL(pci_assign_resource);

int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
			resource_size_t min_align)
{
	struct resource *res = dev->resource + resno;
	unsigned long flags;
	resource_size_t new_size;
	int ret;

	if (res->flags & IORESOURCE_PCI_FIXED)
		return 0;

	flags = res->flags;
	res->flags |= IORESOURCE_UNSET;
	if (!res->parent) {
		pci_info(dev, "BAR %d: can't reassign an unassigned resource %pR\n",
			 resno, res);
		return -EINVAL;
	}

	/* already aligned with min_align */
	new_size = resource_size(res) + addsize;
	ret = _pci_assign_resource(dev, resno, new_size, min_align);
	if (ret) {
		res->flags = flags;
		pci_info(dev, "BAR %d: %pR (failed to expand by %#llx)\n",
			 resno, res, (unsigned long long) addsize);
		return ret;
	}

	res->flags &= ~IORESOURCE_UNSET;
	res->flags &= ~IORESOURCE_STARTALIGN;
	pci_info(dev, "BAR %d: reassigned %pR (expanded by %#llx)\n",
		 resno, res, (unsigned long long) addsize);
	if (resno < PCI_BRIDGE_RESOURCES)
		pci_update_resource(dev, resno);

	return 0;
}

void pci_release_resource(struct pci_dev *dev, int resno)
{
	struct resource *res = dev->resource + resno;

	pci_info(dev, "BAR %d: releasing %pR\n", resno, res);
	release_resource(res);
	res->end = resource_size(res) - 1;
	res->start = 0;
	res->flags |= IORESOURCE_UNSET;
}
EXPORT_SYMBOL(pci_release_resource);

int pci_resize_resource(struct pci_dev *dev, int resno, int size)
{
	struct resource *res = dev->resource + resno;
	int old, ret;
	u32 sizes;
	u16 cmd;

	/* Make sure the resource isn't assigned before resizing it. */
	if (!(res->flags & IORESOURCE_UNSET))
		return -EBUSY;

	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	if (cmd & PCI_COMMAND_MEMORY)
		return -EBUSY;

	sizes = pci_rebar_get_possible_sizes(dev, resno);
	if (!sizes)
		return -ENOTSUPP;

	if (!(sizes & BIT(size)))
		return -EINVAL;

	old = pci_rebar_get_current_size(dev, resno);
	if (old < 0)
		return old;

	ret = pci_rebar_set_size(dev, resno, size);
	if (ret)
		return ret;

	res->end = res->start + pci_rebar_size_to_bytes(size) - 1;

	/* Check if the new config works by trying to assign everything. */
	ret = pci_reassign_bridge_resources(dev->bus->self, res->flags);
	if (ret)
		goto error_resize;

	return 0;

error_resize:
	pci_rebar_set_size(dev, resno, old);
	res->end = res->start + pci_rebar_size_to_bytes(old) - 1;
	return ret;
}
EXPORT_SYMBOL(pci_resize_resource);

int pci_enable_resources(struct pci_dev *dev, int mask)
{
	u16 cmd, old_cmd;
	int i;
	struct resource *r;

	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	old_cmd = cmd;

	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
		if (!(mask & (1 << i)))
			continue;

		r = &dev->resource[i];

		if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
			continue;
		if ((i == PCI_ROM_RESOURCE) &&
				(!(r->flags & IORESOURCE_ROM_ENABLE)))
			continue;

		if (r->flags & IORESOURCE_UNSET) {
			pci_err(dev, "can't enable device: BAR %d %pR not assigned\n",
				i, r);
			return -EINVAL;
		}

		if (!r->parent) {
			pci_err(dev, "can't enable device: BAR %d %pR not claimed\n",
				i, r);
			return -EINVAL;
		}

		if (r->flags & IORESOURCE_IO)
			cmd |= PCI_COMMAND_IO;
		if (r->flags & IORESOURCE_MEM)
			cmd |= PCI_COMMAND_MEMORY;
	}

	if (cmd != old_cmd) {
		pci_info(dev, "enabling device (%04x -> %04x)\n", old_cmd, cmd);
		pci_write_config_word(dev, PCI_COMMAND, cmd);
	}
	return 0;
}
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
1da177e4 LT	2	/*
	3	* drivers/pci/setup-res.c
	4	*
	5	* Extruded from code written by
	6	* Dave Rusling (david.rusling@reo.mts.dec.com)
	7	* David Mosberger (davidm@cs.arizona.edu)
	8	* David Miller (davem@redhat.com)
	9	*
	10	* Support routines for initializing a PCI subsystem.
	11	*/
	12
	13	/* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */
	14
	15	/*
	16	* Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
	17	* Resource sorting
	18	*/
	19
1da177e4	20	#include <linux/kernel.h>
363c75db	21	#include <linux/export.h>
1da177e4 LT	22	#include <linux/pci.h>
	23	#include <linux/errno.h>
	24	#include <linux/ioport.h>
	25	#include <linux/cache.h>
	26	#include <linux/slab.h>
	27	#include "pci.h"
	28
6ffa2489	29	static void pci_std_update_resource(struct pci_dev *dev, int resno)
1da177e4 LT	30	{
1da177e4 LT	31	struct pci_bus_region region;
9aac537e BH	32	bool disable;
9aac537e BH	33	u16 cmd;
1da177e4 LT	34	u32 new, check, mask;
1da177e4 LT	35	int reg;
14add80b	36	struct resource *res = dev->resource + resno;
1da177e4	37
63880b23 BH	38	/* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */
63880b23 BH	39	if (dev->is_virtfn)
70675e0b	40	return;
70675e0b	41
fb0f2b40 RB	42	/*
	43	* Ignore resources for unimplemented BARs and unused resource slots
	44	* for 64 bit BARs.
	45	*/
cf7bee5a IK	46	if (!res->flags)
	47	return;
	48
cd8a4d36 BH	49	if (res->flags & IORESOURCE_UNSET)
	50	return;
	51
fb0f2b40 RB	52	/*
	53	* Ignore non-moveable resources. This might be legacy resources for
	54	* which no functional BAR register exists or another important
80ccba11	55	* system resource we shouldn't move around.
fb0f2b40 RB	56	*/
	57	if (res->flags & IORESOURCE_PCI_FIXED)
	58	return;
	59
fc279850	60	pcibios_resource_to_bus(dev->bus, &region, res);
45d004f4	61	new = region.start;
1da177e4	62
45d004f4	63	if (res->flags & IORESOURCE_IO) {
1da177e4	64	mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
45d004f4 BH	65	new \|= res->flags & ~PCI_BASE_ADDRESS_IO_MASK;
45d004f4 BH	66	} else if (resno == PCI_ROM_RESOURCE) {
76dc5268	67	mask = PCI_ROM_ADDRESS_MASK;
45d004f4	68	} else {
1da177e4	69	mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
45d004f4 BH	70	new \|= res->flags & ~PCI_BASE_ADDRESS_MEM_MASK;
45d004f4 BH	71	}
1da177e4	72
286c2378 BH	73	if (resno < PCI_ROM_RESOURCE) {
	74	reg = PCI_BASE_ADDRESS_0 + 4 * resno;
	75	} else if (resno == PCI_ROM_RESOURCE) {
0b457dde BH	76
	77	/*
	78	* Apparently some Matrox devices have ROM BARs that read
	79	* as zero when disabled, so don't update ROM BARs unless
	80	* they're enabled. See https://lkml.org/lkml/2005/8/30/138.
	81	*/
755528c8 LT	82	if (!(res->flags & IORESOURCE_ROM_ENABLE))
755528c8 LT	83	return;
286c2378 BH	84
286c2378 BH	85	reg = dev->rom_base_reg;
755528c8	86	new \|= PCI_ROM_ADDRESS_ENABLE;
286c2378 BH	87	} else
286c2378 BH	88	return;
1da177e4	89
9aac537e BH	90	/*
	91	* We can't update a 64-bit BAR atomically, so when possible,
	92	* disable decoding so that a half-updated BAR won't conflict
	93	* with another device.
	94	*/
	95	disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on;
	96	if (disable) {
	97	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	98	pci_write_config_word(dev, PCI_COMMAND,
	99	cmd & ~PCI_COMMAND_MEMORY);
	100	}
	101
1da177e4 LT	102	pci_write_config_dword(dev, reg, new);
	103	pci_read_config_dword(dev, reg, &check);
	104
	105	if ((new ^ check) & mask) {
7506dc79	106	pci_err(dev, "BAR %d: error updating (%#08x != %#08x)\n",
80ccba11	107	resno, new, check);
1da177e4 LT	108	}
1da177e4 LT	109
28c6821a	110	if (res->flags & IORESOURCE_MEM_64) {
cf7bee5a	111	new = region.start >> 16 >> 16;
1da177e4 LT	112	pci_write_config_dword(dev, reg + 4, new);
	113	pci_read_config_dword(dev, reg + 4, &check);
	114	if (check != new) {
7506dc79	115	pci_err(dev, "BAR %d: error updating (high %#08x != %#08x)\n",
227f0647	116	resno, new, check);
1da177e4 LT	117	}
1da177e4 LT	118	}
9aac537e BH	119
	120	if (disable)
	121	pci_write_config_word(dev, PCI_COMMAND, cmd);
1da177e4 LT	122	}
1da177e4 LT	123
6ffa2489 BH	124	void pci_update_resource(struct pci_dev *dev, int resno)
	125	{
	126	if (resno <= PCI_ROM_RESOURCE)
	127	pci_std_update_resource(dev, resno);
	128	#ifdef CONFIG_PCI_IOV
	129	else if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
	130	pci_iov_update_resource(dev, resno);
	131	#endif
	132	}
	133
96bde06a	134	int pci_claim_resource(struct pci_dev *dev, int resource)
1da177e4 LT	135	{
1da177e4 LT	136	struct resource *res = &dev->resource[resource];
966f3a75	137	struct resource root, conflict;
1da177e4	138
29003beb	139	if (res->flags & IORESOURCE_UNSET) {
7506dc79	140	pci_info(dev, "can't claim BAR %d %pR: no address assigned\n",
29003beb BH	141	resource, res);
	142	return -EINVAL;
	143	}
	144
16d917b1 BH	145	/*
	146	* If we have a shadow copy in RAM, the PCI device doesn't respond
	147	* to the shadow range, so we don't need to claim it, and upstream
	148	* bridges don't need to route the range to the device.
	149	*/
	150	if (res->flags & IORESOURCE_ROM_SHADOW)
	151	return 0;
	152
cebd78a8	153	root = pci_find_parent_resource(dev, res);
865df576	154	if (!root) {
7506dc79	155	pci_info(dev, "can't claim BAR %d %pR: no compatible bridge window\n",
29003beb	156	resource, res);
c770cb4c	157	res->flags \|= IORESOURCE_UNSET;
865df576	158	return -EINVAL;
1da177e4 LT	159	}
1da177e4 LT	160
966f3a75 BH	161	conflict = request_resource_conflict(root, res);
966f3a75 BH	162	if (conflict) {
7506dc79	163	pci_info(dev, "can't claim BAR %d %pR: address conflict with %s %pR\n",
29003beb	164	resource, res, conflict->name, conflict);
c770cb4c	165	res->flags \|= IORESOURCE_UNSET;
966f3a75 BH	166	return -EBUSY;
966f3a75 BH	167	}
865df576	168
966f3a75	169	return 0;
1da177e4	170	}
eaa959df	171	EXPORT_SYMBOL(pci_claim_resource);
1da177e4	172
32a9a682 YS	173	void pci_disable_bridge_window(struct pci_dev *dev)
32a9a682 YS	174	{
7506dc79	175	pci_info(dev, "disabling bridge mem windows\n");
32a9a682 YS	176
	177	/* MMIO Base/Limit */
	178	pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
	179
	180	/* Prefetchable MMIO Base/Limit */
	181	pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
	182	pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
	183	pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
	184	}
2bbc6942	185
6535943f MS	186	/*
	187	* Generic function that returns a value indicating that the device's
	188	* original BIOS BAR address was not saved and so is not available for
	189	* reinstatement.
	190	*
	191	* Can be over-ridden by architecture specific code that implements
	192	* reinstatement functionality rather than leaving it disabled when
	193	* normal allocation attempts fail.
	194	*/
	195	resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
	196	{
	197	return 0;
	198	}
	199
f7625980	200	static int pci_revert_fw_address(struct resource res, struct pci_dev dev,
2bbc6942 RP	201	int resno, resource_size_t size)
	202	{
	203	struct resource root, conflict;
6535943f	204	resource_size_t fw_addr, start, end;
58c84eda	205
6535943f MS	206	fw_addr = pcibios_retrieve_fw_addr(dev, resno);
6535943f MS	207	if (!fw_addr)
94778835	208	return -ENOMEM;
6535943f	209
2bbc6942 RP	210	start = res->start;
2bbc6942 RP	211	end = res->end;
6535943f	212	res->start = fw_addr;
2bbc6942	213	res->end = res->start + size - 1;
0b26cd69	214	res->flags &= ~IORESOURCE_UNSET;
351fc6d1 MS	215
	216	root = pci_find_parent_resource(dev, res);
	217	if (!root) {
	218	if (res->flags & IORESOURCE_IO)
	219	root = &ioport_resource;
	220	else
	221	root = &iomem_resource;
	222	}
	223
7506dc79	224	pci_info(dev, "BAR %d: trying firmware assignment %pR\n",
2bbc6942 RP	225	resno, res);
	226	conflict = request_resource_conflict(root, res);
	227	if (conflict) {
7506dc79	228	pci_info(dev, "BAR %d: %pR conflicts with %s %pR\n",
94778835	229	resno, res, conflict->name, conflict);
2bbc6942 RP	230	res->start = start;
2bbc6942 RP	231	res->end = end;
0b26cd69	232	res->flags \|= IORESOURCE_UNSET;
94778835	233	return -EBUSY;
2bbc6942	234	}
94778835	235	return 0;
2bbc6942 RP	236	}
2bbc6942 RP	237
ecf677c8 PD	238	/*
	239	* We don't have to worry about legacy ISA devices, so nothing to do here.
	240	* This is marked as __weak because multiple architectures define it; it should
	241	* eventually go away.
	242	*/
	243	resource_size_t __weak pcibios_align_resource(void *data,
	244	const struct resource *res,
	245	resource_size_t size,
	246	resource_size_t align)
	247	{
	248	return res->start;
	249	}
	250
fe6dacdb BH	251	static int __pci_assign_resource(struct pci_bus bus, struct pci_dev dev,
	252	int resno, resource_size_t size, resource_size_t align)
	253	{
	254	struct resource *res = dev->resource + resno;
	255	resource_size_t min;
	256	int ret;
	257
	258	min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
	259
67d29b5c BH	260	/*
	261	* First, try exact prefetching match. Even if a 64-bit
	262	* prefetchable bridge window is below 4GB, we can't put a 32-bit
	263	* prefetchable resource in it because pbus_size_mem() assumes a
	264	* 64-bit window will contain no 32-bit resources. If we assign
	265	* things differently than they were sized, not everything will fit.
	266	*/
fe6dacdb	267	ret = pci_bus_alloc_resource(bus, res, size, align, min,
5b285415	268	IORESOURCE_PREFETCH \| IORESOURCE_MEM_64,
fe6dacdb	269	pcibios_align_resource, dev);
d3689df0 BH	270	if (ret == 0)
d3689df0 BH	271	return 0;
fe6dacdb	272
67d29b5c BH	273	/*
	274	* If the prefetchable window is only 32 bits wide, we can put
	275	* 64-bit prefetchable resources in it.
	276	*/
d3689df0	277	if ((res->flags & (IORESOURCE_PREFETCH \| IORESOURCE_MEM_64)) ==
5b285415	278	(IORESOURCE_PREFETCH \| IORESOURCE_MEM_64)) {
5b285415 YL	279	ret = pci_bus_alloc_resource(bus, res, size, align, min,
5b285415 YL	280	IORESOURCE_PREFETCH,
fe6dacdb	281	pcibios_align_resource, dev);
d3689df0 BH	282	if (ret == 0)
d3689df0 BH	283	return 0;
fe6dacdb	284	}
5b285415	285
67d29b5c BH	286	/*
	287	* If we didn't find a better match, we can put any memory resource
	288	* in a non-prefetchable window. If this resource is 32 bits and
	289	* non-prefetchable, the first call already tried the only possibility
	290	* so we don't need to try again.
	291	*/
	292	if (res->flags & (IORESOURCE_PREFETCH \| IORESOURCE_MEM_64))
fe6dacdb BH	293	ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
fe6dacdb BH	294	pcibios_align_resource, dev);
67d29b5c	295
fe6dacdb BH	296	return ret;
	297	}
	298
d6776e6d NR	299	static int _pci_assign_resource(struct pci_dev *dev, int resno,
d6776e6d NR	300	resource_size_t size, resource_size_t min_align)
2bbc6942	301	{
2bbc6942 RP	302	struct pci_bus *bus;
2bbc6942 RP	303	int ret;
58c84eda	304
2bbc6942 RP	305	bus = dev->bus;
	306	while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
	307	if (!bus->parent \|\| !bus->self->transparent)
	308	break;
	309	bus = bus->parent;
	310	}
	311
2bbc6942 RP	312	return ret;
	313	}
	314
d09ee968 YL	315	int pci_assign_resource(struct pci_dev *dev, int resno)
	316	{
	317	struct resource *res = dev->resource + resno;
2bbc6942	318	resource_size_t align, size;
d09ee968 YL	319	int ret;
d09ee968 YL	320
2ea4adf7 BH	321	if (res->flags & IORESOURCE_PCI_FIXED)
	322	return 0;
	323
bd064f0a	324	res->flags \|= IORESOURCE_UNSET;
6faf17f6	325	align = pci_resource_alignment(dev, res);
d09ee968	326	if (!align) {
7506dc79	327	pci_info(dev, "BAR %d: can't assign %pR (bogus alignment)\n",
227f0647	328	resno, res);
d09ee968 YL	329	return -EINVAL;
	330	}
	331
2bbc6942 RP	332	size = resource_size(res);
2bbc6942 RP	333	ret = _pci_assign_resource(dev, resno, size, align);
d09ee968	334
2bbc6942 RP	335	/*
	336	* If we failed to assign anything, let's try the address
	337	* where firmware left it. That at least has a chance of
	338	* working, which is better than just leaving it disabled.
	339	*/
64da465e	340	if (ret < 0) {
7506dc79	341	pci_info(dev, "BAR %d: no space for %pR\n", resno, res);
2bbc6942	342	ret = pci_revert_fw_address(res, dev, resno, size);
64da465e	343	}
d09ee968	344
64da465e	345	if (ret < 0) {
7506dc79	346	pci_info(dev, "BAR %d: failed to assign %pR\n", resno, res);
28f6dbe2	347	return ret;
64da465e	348	}
28f6dbe2 BH	349
	350	res->flags &= ~IORESOURCE_UNSET;
	351	res->flags &= ~IORESOURCE_STARTALIGN;
7506dc79	352	pci_info(dev, "BAR %d: assigned %pR\n", resno, res);
28f6dbe2 BH	353	if (resno < PCI_BRIDGE_RESOURCES)
	354	pci_update_resource(dev, resno);
	355
	356	return 0;
d09ee968	357	}
b7fe9434	358	EXPORT_SYMBOL(pci_assign_resource);
d09ee968	359
fe6dacdb BH	360	int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
	361	resource_size_t min_align)
	362	{
	363	struct resource *res = dev->resource + resno;
c3337708	364	unsigned long flags;
fe6dacdb BH	365	resource_size_t new_size;
	366	int ret;
	367
2ea4adf7 BH	368	if (res->flags & IORESOURCE_PCI_FIXED)
	369	return 0;
	370
c3337708	371	flags = res->flags;
bd064f0a	372	res->flags \|= IORESOURCE_UNSET;
fe6dacdb	373	if (!res->parent) {
7506dc79	374	pci_info(dev, "BAR %d: can't reassign an unassigned resource %pR\n",
227f0647	375	resno, res);
fe6dacdb BH	376	return -EINVAL;
	377	}
	378
	379	/* already aligned with min_align */
	380	new_size = resource_size(res) + addsize;
	381	ret = _pci_assign_resource(dev, resno, new_size, min_align);
28f6dbe2	382	if (ret) {
c3337708	383	res->flags = flags;
7506dc79	384	pci_info(dev, "BAR %d: %pR (failed to expand by %#llx)\n",
c3337708	385	resno, res, (unsigned long long) addsize);
28f6dbe2	386	return ret;
fe6dacdb	387	}
c3337708	388
28f6dbe2 BH	389	res->flags &= ~IORESOURCE_UNSET;
28f6dbe2 BH	390	res->flags &= ~IORESOURCE_STARTALIGN;
7506dc79	391	pci_info(dev, "BAR %d: reassigned %pR (expanded by %#llx)\n",
64da465e	392	resno, res, (unsigned long long) addsize);
28f6dbe2 BH	393	if (resno < PCI_BRIDGE_RESOURCES)
	394	pci_update_resource(dev, resno);
	395
	396	return 0;
fe6dacdb BH	397	}
fe6dacdb BH	398
8bb705e3 CK	399	void pci_release_resource(struct pci_dev *dev, int resno)
	400	{
	401	struct resource *res = dev->resource + resno;
	402
7506dc79	403	pci_info(dev, "BAR %d: releasing %pR\n", resno, res);
8bb705e3 CK	404	release_resource(res);
	405	res->end = resource_size(res) - 1;
	406	res->start = 0;
	407	res->flags \|= IORESOURCE_UNSET;
	408	}
	409	EXPORT_SYMBOL(pci_release_resource);
	410
	411	int pci_resize_resource(struct pci_dev *dev, int resno, int size)
	412	{
	413	struct resource *res = dev->resource + resno;
	414	int old, ret;
	415	u32 sizes;
	416	u16 cmd;
	417
	418	/* Make sure the resource isn't assigned before resizing it. */
	419	if (!(res->flags & IORESOURCE_UNSET))
	420	return -EBUSY;
	421
	422	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	423	if (cmd & PCI_COMMAND_MEMORY)
	424	return -EBUSY;
	425
	426	sizes = pci_rebar_get_possible_sizes(dev, resno);
	427	if (!sizes)
	428	return -ENOTSUPP;
	429
	430	if (!(sizes & BIT(size)))
	431	return -EINVAL;
	432
	433	old = pci_rebar_get_current_size(dev, resno);
	434	if (old < 0)
	435	return old;
	436
	437	ret = pci_rebar_set_size(dev, resno, size);
	438	if (ret)
	439	return ret;
	440
	441	res->end = res->start + pci_rebar_size_to_bytes(size) - 1;
	442
	443	/* Check if the new config works by trying to assign everything. */
	444	ret = pci_reassign_bridge_resources(dev->bus->self, res->flags);
	445	if (ret)
	446	goto error_resize;
	447
	448	return 0;
	449
	450	error_resize:
	451	pci_rebar_set_size(dev, resno, old);
	452	res->end = res->start + pci_rebar_size_to_bytes(old) - 1;
	453	return ret;
	454	}
	455	EXPORT_SYMBOL(pci_resize_resource);
	456
842de40d BH	457	int pci_enable_resources(struct pci_dev *dev, int mask)
	458	{
	459	u16 cmd, old_cmd;
	460	int i;
	461	struct resource *r;
	462
	463	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	464	old_cmd = cmd;
	465
	466	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
	467	if (!(mask & (1 << i)))
	468	continue;
	469
	470	r = &dev->resource[i];
	471
	472	if (!(r->flags & (IORESOURCE_IO \| IORESOURCE_MEM)))
	473	continue;
	474	if ((i == PCI_ROM_RESOURCE) &&
	475	(!(r->flags & IORESOURCE_ROM_ENABLE)))
	476	continue;
	477
3cedcc36	478	if (r->flags & IORESOURCE_UNSET) {
7506dc79	479	pci_err(dev, "can't enable device: BAR %d %pR not assigned\n",
3cedcc36 BH	480	i, r);
	481	return -EINVAL;
	482	}
	483
842de40d	484	if (!r->parent) {
7506dc79	485	pci_err(dev, "can't enable device: BAR %d %pR not claimed\n",
3cedcc36	486	i, r);
842de40d BH	487	return -EINVAL;
	488	}
	489
	490	if (r->flags & IORESOURCE_IO)
	491	cmd \|= PCI_COMMAND_IO;
	492	if (r->flags & IORESOURCE_MEM)
	493	cmd \|= PCI_COMMAND_MEMORY;
	494	}
	495
	496	if (cmd != old_cmd) {
7506dc79	497	pci_info(dev, "enabling device (%04x -> %04x)\n", old_cmd, cmd);
842de40d BH	498	pci_write_config_word(dev, PCI_COMMAND, cmd);
	499	}
	500	return 0;
	501	}