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Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * drivers/pci/setup-res.c | |
3 | * | |
4 | * Extruded from code written by | |
5 | * Dave Rusling (david.rusling@reo.mts.dec.com) | |
6 | * David Mosberger (davidm@cs.arizona.edu) | |
7 | * David Miller (davem@redhat.com) | |
8 | * | |
9 | * Support routines for initializing a PCI subsystem. | |
10 | */ | |
11 | ||
12 | /* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */ | |
13 | ||
14 | /* | |
15 | * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> | |
16 | * Resource sorting | |
17 | */ | |
18 | ||
1da177e4 | 19 | #include <linux/kernel.h> |
363c75db | 20 | #include <linux/export.h> |
1da177e4 LT |
21 | #include <linux/pci.h> |
22 | #include <linux/errno.h> | |
23 | #include <linux/ioport.h> | |
24 | #include <linux/cache.h> | |
25 | #include <linux/slab.h> | |
26 | #include "pci.h" | |
27 | ||
6ffa2489 | 28 | static void pci_std_update_resource(struct pci_dev *dev, int resno) |
1da177e4 LT |
29 | { |
30 | struct pci_bus_region region; | |
9aac537e BH |
31 | bool disable; |
32 | u16 cmd; | |
1da177e4 LT |
33 | u32 new, check, mask; |
34 | int reg; | |
14add80b | 35 | struct resource *res = dev->resource + resno; |
1da177e4 | 36 | |
63880b23 BH |
37 | /* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */ |
38 | if (dev->is_virtfn) | |
70675e0b | 39 | return; |
70675e0b | 40 | |
fb0f2b40 RB |
41 | /* |
42 | * Ignore resources for unimplemented BARs and unused resource slots | |
43 | * for 64 bit BARs. | |
44 | */ | |
cf7bee5a IK |
45 | if (!res->flags) |
46 | return; | |
47 | ||
cd8a4d36 BH |
48 | if (res->flags & IORESOURCE_UNSET) |
49 | return; | |
50 | ||
fb0f2b40 RB |
51 | /* |
52 | * Ignore non-moveable resources. This might be legacy resources for | |
53 | * which no functional BAR register exists or another important | |
80ccba11 | 54 | * system resource we shouldn't move around. |
fb0f2b40 RB |
55 | */ |
56 | if (res->flags & IORESOURCE_PCI_FIXED) | |
57 | return; | |
58 | ||
fc279850 | 59 | pcibios_resource_to_bus(dev->bus, ®ion, res); |
45d004f4 | 60 | new = region.start; |
1da177e4 | 61 | |
45d004f4 | 62 | if (res->flags & IORESOURCE_IO) { |
1da177e4 | 63 | mask = (u32)PCI_BASE_ADDRESS_IO_MASK; |
45d004f4 BH |
64 | new |= res->flags & ~PCI_BASE_ADDRESS_IO_MASK; |
65 | } else if (resno == PCI_ROM_RESOURCE) { | |
66 | mask = (u32)PCI_ROM_ADDRESS_MASK; | |
67 | } else { | |
1da177e4 | 68 | mask = (u32)PCI_BASE_ADDRESS_MEM_MASK; |
45d004f4 BH |
69 | new |= res->flags & ~PCI_BASE_ADDRESS_MEM_MASK; |
70 | } | |
1da177e4 | 71 | |
286c2378 BH |
72 | if (resno < PCI_ROM_RESOURCE) { |
73 | reg = PCI_BASE_ADDRESS_0 + 4 * resno; | |
74 | } else if (resno == PCI_ROM_RESOURCE) { | |
0b457dde BH |
75 | |
76 | /* | |
77 | * Apparently some Matrox devices have ROM BARs that read | |
78 | * as zero when disabled, so don't update ROM BARs unless | |
79 | * they're enabled. See https://lkml.org/lkml/2005/8/30/138. | |
80 | */ | |
755528c8 LT |
81 | if (!(res->flags & IORESOURCE_ROM_ENABLE)) |
82 | return; | |
286c2378 BH |
83 | |
84 | reg = dev->rom_base_reg; | |
755528c8 | 85 | new |= PCI_ROM_ADDRESS_ENABLE; |
286c2378 BH |
86 | } else |
87 | return; | |
1da177e4 | 88 | |
9aac537e BH |
89 | /* |
90 | * We can't update a 64-bit BAR atomically, so when possible, | |
91 | * disable decoding so that a half-updated BAR won't conflict | |
92 | * with another device. | |
93 | */ | |
94 | disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on; | |
95 | if (disable) { | |
96 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
97 | pci_write_config_word(dev, PCI_COMMAND, | |
98 | cmd & ~PCI_COMMAND_MEMORY); | |
99 | } | |
100 | ||
1da177e4 LT |
101 | pci_write_config_dword(dev, reg, new); |
102 | pci_read_config_dword(dev, reg, &check); | |
103 | ||
104 | if ((new ^ check) & mask) { | |
80ccba11 BH |
105 | dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n", |
106 | resno, new, check); | |
1da177e4 LT |
107 | } |
108 | ||
28c6821a | 109 | if (res->flags & IORESOURCE_MEM_64) { |
cf7bee5a | 110 | new = region.start >> 16 >> 16; |
1da177e4 LT |
111 | pci_write_config_dword(dev, reg + 4, new); |
112 | pci_read_config_dword(dev, reg + 4, &check); | |
113 | if (check != new) { | |
227f0647 RD |
114 | dev_err(&dev->dev, "BAR %d: error updating (high %#08x != %#08x)\n", |
115 | resno, new, check); | |
1da177e4 LT |
116 | } |
117 | } | |
9aac537e BH |
118 | |
119 | if (disable) | |
120 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1da177e4 LT |
121 | } |
122 | ||
6ffa2489 BH |
123 | void pci_update_resource(struct pci_dev *dev, int resno) |
124 | { | |
125 | if (resno <= PCI_ROM_RESOURCE) | |
126 | pci_std_update_resource(dev, resno); | |
127 | #ifdef CONFIG_PCI_IOV | |
128 | else if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END) | |
129 | pci_iov_update_resource(dev, resno); | |
130 | #endif | |
131 | } | |
132 | ||
96bde06a | 133 | int pci_claim_resource(struct pci_dev *dev, int resource) |
1da177e4 LT |
134 | { |
135 | struct resource *res = &dev->resource[resource]; | |
966f3a75 | 136 | struct resource *root, *conflict; |
1da177e4 | 137 | |
29003beb BH |
138 | if (res->flags & IORESOURCE_UNSET) { |
139 | dev_info(&dev->dev, "can't claim BAR %d %pR: no address assigned\n", | |
140 | resource, res); | |
141 | return -EINVAL; | |
142 | } | |
143 | ||
16d917b1 BH |
144 | /* |
145 | * If we have a shadow copy in RAM, the PCI device doesn't respond | |
146 | * to the shadow range, so we don't need to claim it, and upstream | |
147 | * bridges don't need to route the range to the device. | |
148 | */ | |
149 | if (res->flags & IORESOURCE_ROM_SHADOW) | |
150 | return 0; | |
151 | ||
cebd78a8 | 152 | root = pci_find_parent_resource(dev, res); |
865df576 | 153 | if (!root) { |
29003beb BH |
154 | dev_info(&dev->dev, "can't claim BAR %d %pR: no compatible bridge window\n", |
155 | resource, res); | |
c770cb4c | 156 | res->flags |= IORESOURCE_UNSET; |
865df576 | 157 | return -EINVAL; |
1da177e4 LT |
158 | } |
159 | ||
966f3a75 BH |
160 | conflict = request_resource_conflict(root, res); |
161 | if (conflict) { | |
29003beb BH |
162 | dev_info(&dev->dev, "can't claim BAR %d %pR: address conflict with %s %pR\n", |
163 | resource, res, conflict->name, conflict); | |
c770cb4c | 164 | res->flags |= IORESOURCE_UNSET; |
966f3a75 BH |
165 | return -EBUSY; |
166 | } | |
865df576 | 167 | |
966f3a75 | 168 | return 0; |
1da177e4 | 169 | } |
eaa959df | 170 | EXPORT_SYMBOL(pci_claim_resource); |
1da177e4 | 171 | |
32a9a682 YS |
172 | void pci_disable_bridge_window(struct pci_dev *dev) |
173 | { | |
865df576 | 174 | dev_info(&dev->dev, "disabling bridge mem windows\n"); |
32a9a682 YS |
175 | |
176 | /* MMIO Base/Limit */ | |
177 | pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0); | |
178 | ||
179 | /* Prefetchable MMIO Base/Limit */ | |
180 | pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0); | |
181 | pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0); | |
182 | pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff); | |
183 | } | |
2bbc6942 | 184 | |
6535943f MS |
185 | /* |
186 | * Generic function that returns a value indicating that the device's | |
187 | * original BIOS BAR address was not saved and so is not available for | |
188 | * reinstatement. | |
189 | * | |
190 | * Can be over-ridden by architecture specific code that implements | |
191 | * reinstatement functionality rather than leaving it disabled when | |
192 | * normal allocation attempts fail. | |
193 | */ | |
194 | resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx) | |
195 | { | |
196 | return 0; | |
197 | } | |
198 | ||
f7625980 | 199 | static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev, |
2bbc6942 RP |
200 | int resno, resource_size_t size) |
201 | { | |
202 | struct resource *root, *conflict; | |
6535943f | 203 | resource_size_t fw_addr, start, end; |
58c84eda | 204 | |
6535943f MS |
205 | fw_addr = pcibios_retrieve_fw_addr(dev, resno); |
206 | if (!fw_addr) | |
94778835 | 207 | return -ENOMEM; |
6535943f | 208 | |
2bbc6942 RP |
209 | start = res->start; |
210 | end = res->end; | |
6535943f | 211 | res->start = fw_addr; |
2bbc6942 | 212 | res->end = res->start + size - 1; |
0b26cd69 | 213 | res->flags &= ~IORESOURCE_UNSET; |
351fc6d1 MS |
214 | |
215 | root = pci_find_parent_resource(dev, res); | |
216 | if (!root) { | |
217 | if (res->flags & IORESOURCE_IO) | |
218 | root = &ioport_resource; | |
219 | else | |
220 | root = &iomem_resource; | |
221 | } | |
222 | ||
2bbc6942 RP |
223 | dev_info(&dev->dev, "BAR %d: trying firmware assignment %pR\n", |
224 | resno, res); | |
225 | conflict = request_resource_conflict(root, res); | |
226 | if (conflict) { | |
94778835 BH |
227 | dev_info(&dev->dev, "BAR %d: %pR conflicts with %s %pR\n", |
228 | resno, res, conflict->name, conflict); | |
2bbc6942 RP |
229 | res->start = start; |
230 | res->end = end; | |
0b26cd69 | 231 | res->flags |= IORESOURCE_UNSET; |
94778835 | 232 | return -EBUSY; |
2bbc6942 | 233 | } |
94778835 | 234 | return 0; |
2bbc6942 RP |
235 | } |
236 | ||
fe6dacdb BH |
237 | static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev, |
238 | int resno, resource_size_t size, resource_size_t align) | |
239 | { | |
240 | struct resource *res = dev->resource + resno; | |
241 | resource_size_t min; | |
242 | int ret; | |
243 | ||
244 | min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM; | |
245 | ||
67d29b5c BH |
246 | /* |
247 | * First, try exact prefetching match. Even if a 64-bit | |
248 | * prefetchable bridge window is below 4GB, we can't put a 32-bit | |
249 | * prefetchable resource in it because pbus_size_mem() assumes a | |
250 | * 64-bit window will contain no 32-bit resources. If we assign | |
251 | * things differently than they were sized, not everything will fit. | |
252 | */ | |
fe6dacdb | 253 | ret = pci_bus_alloc_resource(bus, res, size, align, min, |
5b285415 | 254 | IORESOURCE_PREFETCH | IORESOURCE_MEM_64, |
fe6dacdb | 255 | pcibios_align_resource, dev); |
d3689df0 BH |
256 | if (ret == 0) |
257 | return 0; | |
fe6dacdb | 258 | |
67d29b5c BH |
259 | /* |
260 | * If the prefetchable window is only 32 bits wide, we can put | |
261 | * 64-bit prefetchable resources in it. | |
262 | */ | |
d3689df0 | 263 | if ((res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) == |
5b285415 | 264 | (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) { |
5b285415 YL |
265 | ret = pci_bus_alloc_resource(bus, res, size, align, min, |
266 | IORESOURCE_PREFETCH, | |
fe6dacdb | 267 | pcibios_align_resource, dev); |
d3689df0 BH |
268 | if (ret == 0) |
269 | return 0; | |
fe6dacdb | 270 | } |
5b285415 | 271 | |
67d29b5c BH |
272 | /* |
273 | * If we didn't find a better match, we can put any memory resource | |
274 | * in a non-prefetchable window. If this resource is 32 bits and | |
275 | * non-prefetchable, the first call already tried the only possibility | |
276 | * so we don't need to try again. | |
277 | */ | |
278 | if (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) | |
fe6dacdb BH |
279 | ret = pci_bus_alloc_resource(bus, res, size, align, min, 0, |
280 | pcibios_align_resource, dev); | |
67d29b5c | 281 | |
fe6dacdb BH |
282 | return ret; |
283 | } | |
284 | ||
d6776e6d NR |
285 | static int _pci_assign_resource(struct pci_dev *dev, int resno, |
286 | resource_size_t size, resource_size_t min_align) | |
2bbc6942 | 287 | { |
2bbc6942 RP |
288 | struct pci_bus *bus; |
289 | int ret; | |
58c84eda | 290 | |
2bbc6942 RP |
291 | bus = dev->bus; |
292 | while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) { | |
293 | if (!bus->parent || !bus->self->transparent) | |
294 | break; | |
295 | bus = bus->parent; | |
296 | } | |
297 | ||
2bbc6942 RP |
298 | return ret; |
299 | } | |
300 | ||
d09ee968 YL |
301 | int pci_assign_resource(struct pci_dev *dev, int resno) |
302 | { | |
303 | struct resource *res = dev->resource + resno; | |
2bbc6942 | 304 | resource_size_t align, size; |
d09ee968 YL |
305 | int ret; |
306 | ||
2ea4adf7 BH |
307 | if (res->flags & IORESOURCE_PCI_FIXED) |
308 | return 0; | |
309 | ||
bd064f0a | 310 | res->flags |= IORESOURCE_UNSET; |
6faf17f6 | 311 | align = pci_resource_alignment(dev, res); |
d09ee968 | 312 | if (!align) { |
227f0647 RD |
313 | dev_info(&dev->dev, "BAR %d: can't assign %pR (bogus alignment)\n", |
314 | resno, res); | |
d09ee968 YL |
315 | return -EINVAL; |
316 | } | |
317 | ||
2bbc6942 RP |
318 | size = resource_size(res); |
319 | ret = _pci_assign_resource(dev, resno, size, align); | |
d09ee968 | 320 | |
2bbc6942 RP |
321 | /* |
322 | * If we failed to assign anything, let's try the address | |
323 | * where firmware left it. That at least has a chance of | |
324 | * working, which is better than just leaving it disabled. | |
325 | */ | |
64da465e BH |
326 | if (ret < 0) { |
327 | dev_info(&dev->dev, "BAR %d: no space for %pR\n", resno, res); | |
2bbc6942 | 328 | ret = pci_revert_fw_address(res, dev, resno, size); |
64da465e | 329 | } |
d09ee968 | 330 | |
64da465e BH |
331 | if (ret < 0) { |
332 | dev_info(&dev->dev, "BAR %d: failed to assign %pR\n", resno, | |
333 | res); | |
28f6dbe2 | 334 | return ret; |
64da465e | 335 | } |
28f6dbe2 BH |
336 | |
337 | res->flags &= ~IORESOURCE_UNSET; | |
338 | res->flags &= ~IORESOURCE_STARTALIGN; | |
339 | dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res); | |
340 | if (resno < PCI_BRIDGE_RESOURCES) | |
341 | pci_update_resource(dev, resno); | |
342 | ||
343 | return 0; | |
d09ee968 | 344 | } |
b7fe9434 | 345 | EXPORT_SYMBOL(pci_assign_resource); |
d09ee968 | 346 | |
fe6dacdb BH |
347 | int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize, |
348 | resource_size_t min_align) | |
349 | { | |
350 | struct resource *res = dev->resource + resno; | |
c3337708 | 351 | unsigned long flags; |
fe6dacdb BH |
352 | resource_size_t new_size; |
353 | int ret; | |
354 | ||
2ea4adf7 BH |
355 | if (res->flags & IORESOURCE_PCI_FIXED) |
356 | return 0; | |
357 | ||
c3337708 | 358 | flags = res->flags; |
bd064f0a | 359 | res->flags |= IORESOURCE_UNSET; |
fe6dacdb | 360 | if (!res->parent) { |
227f0647 RD |
361 | dev_info(&dev->dev, "BAR %d: can't reassign an unassigned resource %pR\n", |
362 | resno, res); | |
fe6dacdb BH |
363 | return -EINVAL; |
364 | } | |
365 | ||
366 | /* already aligned with min_align */ | |
367 | new_size = resource_size(res) + addsize; | |
368 | ret = _pci_assign_resource(dev, resno, new_size, min_align); | |
28f6dbe2 | 369 | if (ret) { |
c3337708 GC |
370 | res->flags = flags; |
371 | dev_info(&dev->dev, "BAR %d: %pR (failed to expand by %#llx)\n", | |
372 | resno, res, (unsigned long long) addsize); | |
28f6dbe2 | 373 | return ret; |
fe6dacdb | 374 | } |
c3337708 | 375 | |
28f6dbe2 BH |
376 | res->flags &= ~IORESOURCE_UNSET; |
377 | res->flags &= ~IORESOURCE_STARTALIGN; | |
64da465e BH |
378 | dev_info(&dev->dev, "BAR %d: reassigned %pR (expanded by %#llx)\n", |
379 | resno, res, (unsigned long long) addsize); | |
28f6dbe2 BH |
380 | if (resno < PCI_BRIDGE_RESOURCES) |
381 | pci_update_resource(dev, resno); | |
382 | ||
383 | return 0; | |
fe6dacdb BH |
384 | } |
385 | ||
842de40d BH |
386 | int pci_enable_resources(struct pci_dev *dev, int mask) |
387 | { | |
388 | u16 cmd, old_cmd; | |
389 | int i; | |
390 | struct resource *r; | |
391 | ||
392 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
393 | old_cmd = cmd; | |
394 | ||
395 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
396 | if (!(mask & (1 << i))) | |
397 | continue; | |
398 | ||
399 | r = &dev->resource[i]; | |
400 | ||
401 | if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) | |
402 | continue; | |
403 | if ((i == PCI_ROM_RESOURCE) && | |
404 | (!(r->flags & IORESOURCE_ROM_ENABLE))) | |
405 | continue; | |
406 | ||
3cedcc36 BH |
407 | if (r->flags & IORESOURCE_UNSET) { |
408 | dev_err(&dev->dev, "can't enable device: BAR %d %pR not assigned\n", | |
409 | i, r); | |
410 | return -EINVAL; | |
411 | } | |
412 | ||
842de40d | 413 | if (!r->parent) { |
3cedcc36 BH |
414 | dev_err(&dev->dev, "can't enable device: BAR %d %pR not claimed\n", |
415 | i, r); | |
842de40d BH |
416 | return -EINVAL; |
417 | } | |
418 | ||
419 | if (r->flags & IORESOURCE_IO) | |
420 | cmd |= PCI_COMMAND_IO; | |
421 | if (r->flags & IORESOURCE_MEM) | |
422 | cmd |= PCI_COMMAND_MEMORY; | |
423 | } | |
424 | ||
425 | if (cmd != old_cmd) { | |
426 | dev_info(&dev->dev, "enabling device (%04x -> %04x)\n", | |
427 | old_cmd, cmd); | |
428 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
429 | } | |
430 | return 0; | |
431 | } |