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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * drivers/pci/setup-res.c | |
3 | * | |
4 | * Extruded from code written by | |
5 | * Dave Rusling (david.rusling@reo.mts.dec.com) | |
6 | * David Mosberger (davidm@cs.arizona.edu) | |
7 | * David Miller (davem@redhat.com) | |
8 | * | |
9 | * Support routines for initializing a PCI subsystem. | |
10 | */ | |
11 | ||
12 | /* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */ | |
13 | ||
14 | /* | |
15 | * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> | |
16 | * Resource sorting | |
17 | */ | |
18 | ||
19 | #include <linux/init.h> | |
20 | #include <linux/kernel.h> | |
363c75db | 21 | #include <linux/export.h> |
1da177e4 LT |
22 | #include <linux/pci.h> |
23 | #include <linux/errno.h> | |
24 | #include <linux/ioport.h> | |
25 | #include <linux/cache.h> | |
26 | #include <linux/slab.h> | |
27 | #include "pci.h" | |
28 | ||
29 | ||
14add80b | 30 | void pci_update_resource(struct pci_dev *dev, int resno) |
1da177e4 LT |
31 | { |
32 | struct pci_bus_region region; | |
9aac537e BH |
33 | bool disable; |
34 | u16 cmd; | |
1da177e4 LT |
35 | u32 new, check, mask; |
36 | int reg; | |
613e7ed6 | 37 | enum pci_bar_type type; |
14add80b | 38 | struct resource *res = dev->resource + resno; |
1da177e4 | 39 | |
fb0f2b40 RB |
40 | /* |
41 | * Ignore resources for unimplemented BARs and unused resource slots | |
42 | * for 64 bit BARs. | |
43 | */ | |
cf7bee5a IK |
44 | if (!res->flags) |
45 | return; | |
46 | ||
cd8a4d36 BH |
47 | if (res->flags & IORESOURCE_UNSET) |
48 | return; | |
49 | ||
fb0f2b40 RB |
50 | /* |
51 | * Ignore non-moveable resources. This might be legacy resources for | |
52 | * which no functional BAR register exists or another important | |
80ccba11 | 53 | * system resource we shouldn't move around. |
fb0f2b40 RB |
54 | */ |
55 | if (res->flags & IORESOURCE_PCI_FIXED) | |
56 | return; | |
57 | ||
fc279850 | 58 | pcibios_resource_to_bus(dev->bus, ®ion, res); |
1da177e4 | 59 | |
1da177e4 LT |
60 | new = region.start | (res->flags & PCI_REGION_FLAG_MASK); |
61 | if (res->flags & IORESOURCE_IO) | |
62 | mask = (u32)PCI_BASE_ADDRESS_IO_MASK; | |
63 | else | |
64 | mask = (u32)PCI_BASE_ADDRESS_MEM_MASK; | |
65 | ||
613e7ed6 YZ |
66 | reg = pci_resource_bar(dev, resno, &type); |
67 | if (!reg) | |
68 | return; | |
69 | if (type != pci_bar_unknown) { | |
755528c8 LT |
70 | if (!(res->flags & IORESOURCE_ROM_ENABLE)) |
71 | return; | |
72 | new |= PCI_ROM_ADDRESS_ENABLE; | |
1da177e4 LT |
73 | } |
74 | ||
9aac537e BH |
75 | /* |
76 | * We can't update a 64-bit BAR atomically, so when possible, | |
77 | * disable decoding so that a half-updated BAR won't conflict | |
78 | * with another device. | |
79 | */ | |
80 | disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on; | |
81 | if (disable) { | |
82 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
83 | pci_write_config_word(dev, PCI_COMMAND, | |
84 | cmd & ~PCI_COMMAND_MEMORY); | |
85 | } | |
86 | ||
1da177e4 LT |
87 | pci_write_config_dword(dev, reg, new); |
88 | pci_read_config_dword(dev, reg, &check); | |
89 | ||
90 | if ((new ^ check) & mask) { | |
80ccba11 BH |
91 | dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n", |
92 | resno, new, check); | |
1da177e4 LT |
93 | } |
94 | ||
28c6821a | 95 | if (res->flags & IORESOURCE_MEM_64) { |
cf7bee5a | 96 | new = region.start >> 16 >> 16; |
1da177e4 LT |
97 | pci_write_config_dword(dev, reg + 4, new); |
98 | pci_read_config_dword(dev, reg + 4, &check); | |
99 | if (check != new) { | |
80ccba11 BH |
100 | dev_err(&dev->dev, "BAR %d: error updating " |
101 | "(high %#08x != %#08x)\n", resno, new, check); | |
1da177e4 LT |
102 | } |
103 | } | |
9aac537e BH |
104 | |
105 | if (disable) | |
106 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
1da177e4 LT |
107 | } |
108 | ||
96bde06a | 109 | int pci_claim_resource(struct pci_dev *dev, int resource) |
1da177e4 LT |
110 | { |
111 | struct resource *res = &dev->resource[resource]; | |
966f3a75 | 112 | struct resource *root, *conflict; |
1da177e4 | 113 | |
cebd78a8 | 114 | root = pci_find_parent_resource(dev, res); |
865df576 | 115 | if (!root) { |
f6d440da BH |
116 | dev_info(&dev->dev, "no compatible bridge window for %pR\n", |
117 | res); | |
865df576 | 118 | return -EINVAL; |
1da177e4 LT |
119 | } |
120 | ||
966f3a75 BH |
121 | conflict = request_resource_conflict(root, res); |
122 | if (conflict) { | |
f6d440da BH |
123 | dev_info(&dev->dev, |
124 | "address space collision: %pR conflicts with %s %pR\n", | |
125 | res, conflict->name, conflict); | |
966f3a75 BH |
126 | return -EBUSY; |
127 | } | |
865df576 | 128 | |
966f3a75 | 129 | return 0; |
1da177e4 | 130 | } |
eaa959df | 131 | EXPORT_SYMBOL(pci_claim_resource); |
1da177e4 | 132 | |
32a9a682 YS |
133 | void pci_disable_bridge_window(struct pci_dev *dev) |
134 | { | |
865df576 | 135 | dev_info(&dev->dev, "disabling bridge mem windows\n"); |
32a9a682 YS |
136 | |
137 | /* MMIO Base/Limit */ | |
138 | pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0); | |
139 | ||
140 | /* Prefetchable MMIO Base/Limit */ | |
141 | pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0); | |
142 | pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0); | |
143 | pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff); | |
144 | } | |
2bbc6942 | 145 | |
6535943f MS |
146 | /* |
147 | * Generic function that returns a value indicating that the device's | |
148 | * original BIOS BAR address was not saved and so is not available for | |
149 | * reinstatement. | |
150 | * | |
151 | * Can be over-ridden by architecture specific code that implements | |
152 | * reinstatement functionality rather than leaving it disabled when | |
153 | * normal allocation attempts fail. | |
154 | */ | |
155 | resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx) | |
156 | { | |
157 | return 0; | |
158 | } | |
159 | ||
f7625980 | 160 | static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev, |
2bbc6942 RP |
161 | int resno, resource_size_t size) |
162 | { | |
163 | struct resource *root, *conflict; | |
6535943f | 164 | resource_size_t fw_addr, start, end; |
2bbc6942 | 165 | int ret = 0; |
58c84eda | 166 | |
6535943f MS |
167 | fw_addr = pcibios_retrieve_fw_addr(dev, resno); |
168 | if (!fw_addr) | |
169 | return 1; | |
170 | ||
2bbc6942 RP |
171 | start = res->start; |
172 | end = res->end; | |
6535943f | 173 | res->start = fw_addr; |
2bbc6942 | 174 | res->end = res->start + size - 1; |
351fc6d1 MS |
175 | |
176 | root = pci_find_parent_resource(dev, res); | |
177 | if (!root) { | |
178 | if (res->flags & IORESOURCE_IO) | |
179 | root = &ioport_resource; | |
180 | else | |
181 | root = &iomem_resource; | |
182 | } | |
183 | ||
2bbc6942 RP |
184 | dev_info(&dev->dev, "BAR %d: trying firmware assignment %pR\n", |
185 | resno, res); | |
186 | conflict = request_resource_conflict(root, res); | |
187 | if (conflict) { | |
188 | dev_info(&dev->dev, | |
189 | "BAR %d: %pR conflicts with %s %pR\n", resno, | |
190 | res, conflict->name, conflict); | |
191 | res->start = start; | |
192 | res->end = end; | |
193 | ret = 1; | |
194 | } | |
195 | return ret; | |
196 | } | |
197 | ||
fe6dacdb BH |
198 | static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev, |
199 | int resno, resource_size_t size, resource_size_t align) | |
200 | { | |
201 | struct resource *res = dev->resource + resno; | |
202 | resource_size_t min; | |
203 | int ret; | |
204 | ||
205 | min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM; | |
206 | ||
207 | /* First, try exact prefetching match.. */ | |
208 | ret = pci_bus_alloc_resource(bus, res, size, align, min, | |
209 | IORESOURCE_PREFETCH, | |
210 | pcibios_align_resource, dev); | |
211 | ||
212 | if (ret < 0 && (res->flags & IORESOURCE_PREFETCH)) { | |
213 | /* | |
214 | * That failed. | |
215 | * | |
216 | * But a prefetching area can handle a non-prefetching | |
217 | * window (it will just not perform as well). | |
218 | */ | |
219 | ret = pci_bus_alloc_resource(bus, res, size, align, min, 0, | |
220 | pcibios_align_resource, dev); | |
221 | } | |
222 | return ret; | |
223 | } | |
224 | ||
d6776e6d NR |
225 | static int _pci_assign_resource(struct pci_dev *dev, int resno, |
226 | resource_size_t size, resource_size_t min_align) | |
2bbc6942 RP |
227 | { |
228 | struct resource *res = dev->resource + resno; | |
229 | struct pci_bus *bus; | |
230 | int ret; | |
231 | char *type; | |
58c84eda | 232 | |
2bbc6942 RP |
233 | bus = dev->bus; |
234 | while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) { | |
235 | if (!bus->parent || !bus->self->transparent) | |
236 | break; | |
237 | bus = bus->parent; | |
238 | } | |
239 | ||
240 | if (ret) { | |
241 | if (res->flags & IORESOURCE_MEM) | |
242 | if (res->flags & IORESOURCE_PREFETCH) | |
243 | type = "mem pref"; | |
244 | else | |
245 | type = "mem"; | |
246 | else if (res->flags & IORESOURCE_IO) | |
247 | type = "io"; | |
58c84eda | 248 | else |
2bbc6942 RP |
249 | type = "unknown"; |
250 | dev_info(&dev->dev, | |
251 | "BAR %d: can't assign %s (size %#llx)\n", | |
252 | resno, type, (unsigned long long) resource_size(res)); | |
58c84eda BH |
253 | } |
254 | ||
2bbc6942 RP |
255 | return ret; |
256 | } | |
257 | ||
d09ee968 YL |
258 | int pci_assign_resource(struct pci_dev *dev, int resno) |
259 | { | |
260 | struct resource *res = dev->resource + resno; | |
2bbc6942 | 261 | resource_size_t align, size; |
d09ee968 YL |
262 | int ret; |
263 | ||
bd064f0a | 264 | res->flags |= IORESOURCE_UNSET; |
6faf17f6 | 265 | align = pci_resource_alignment(dev, res); |
d09ee968 | 266 | if (!align) { |
865df576 | 267 | dev_info(&dev->dev, "BAR %d: can't assign %pR " |
a369c791 | 268 | "(bogus alignment)\n", resno, res); |
d09ee968 YL |
269 | return -EINVAL; |
270 | } | |
271 | ||
2bbc6942 RP |
272 | size = resource_size(res); |
273 | ret = _pci_assign_resource(dev, resno, size, align); | |
d09ee968 | 274 | |
2bbc6942 RP |
275 | /* |
276 | * If we failed to assign anything, let's try the address | |
277 | * where firmware left it. That at least has a chance of | |
278 | * working, which is better than just leaving it disabled. | |
279 | */ | |
6535943f | 280 | if (ret < 0) |
2bbc6942 | 281 | ret = pci_revert_fw_address(res, dev, resno, size); |
d09ee968 | 282 | |
2bbc6942 | 283 | if (!ret) { |
bd064f0a | 284 | res->flags &= ~IORESOURCE_UNSET; |
2bbc6942 RP |
285 | res->flags &= ~IORESOURCE_STARTALIGN; |
286 | dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res); | |
287 | if (resno < PCI_BRIDGE_RESOURCES) | |
288 | pci_update_resource(dev, resno); | |
289 | } | |
d09ee968 YL |
290 | return ret; |
291 | } | |
292 | ||
fe6dacdb BH |
293 | int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize, |
294 | resource_size_t min_align) | |
295 | { | |
296 | struct resource *res = dev->resource + resno; | |
297 | resource_size_t new_size; | |
298 | int ret; | |
299 | ||
bd064f0a | 300 | res->flags |= IORESOURCE_UNSET; |
fe6dacdb BH |
301 | if (!res->parent) { |
302 | dev_info(&dev->dev, "BAR %d: can't reassign an unassigned resource %pR " | |
303 | "\n", resno, res); | |
304 | return -EINVAL; | |
305 | } | |
306 | ||
307 | /* already aligned with min_align */ | |
308 | new_size = resource_size(res) + addsize; | |
309 | ret = _pci_assign_resource(dev, resno, new_size, min_align); | |
310 | if (!ret) { | |
bd064f0a | 311 | res->flags &= ~IORESOURCE_UNSET; |
fe6dacdb BH |
312 | res->flags &= ~IORESOURCE_STARTALIGN; |
313 | dev_info(&dev->dev, "BAR %d: reassigned %pR\n", resno, res); | |
314 | if (resno < PCI_BRIDGE_RESOURCES) | |
315 | pci_update_resource(dev, resno); | |
316 | } | |
317 | return ret; | |
318 | } | |
319 | ||
842de40d BH |
320 | int pci_enable_resources(struct pci_dev *dev, int mask) |
321 | { | |
322 | u16 cmd, old_cmd; | |
323 | int i; | |
324 | struct resource *r; | |
325 | ||
326 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
327 | old_cmd = cmd; | |
328 | ||
329 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
330 | if (!(mask & (1 << i))) | |
331 | continue; | |
332 | ||
333 | r = &dev->resource[i]; | |
334 | ||
335 | if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) | |
336 | continue; | |
337 | if ((i == PCI_ROM_RESOURCE) && | |
338 | (!(r->flags & IORESOURCE_ROM_ENABLE))) | |
339 | continue; | |
340 | ||
341 | if (!r->parent) { | |
865df576 BH |
342 | dev_err(&dev->dev, "device not available " |
343 | "(can't reserve %pR)\n", r); | |
842de40d BH |
344 | return -EINVAL; |
345 | } | |
346 | ||
347 | if (r->flags & IORESOURCE_IO) | |
348 | cmd |= PCI_COMMAND_IO; | |
349 | if (r->flags & IORESOURCE_MEM) | |
350 | cmd |= PCI_COMMAND_MEMORY; | |
351 | } | |
352 | ||
353 | if (cmd != old_cmd) { | |
354 | dev_info(&dev->dev, "enabling device (%04x -> %04x)\n", | |
355 | old_cmd, cmd); | |
356 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
357 | } | |
358 | return 0; | |
359 | } |