[mirror_ubuntu-bionic-kernel.git] / drivers / pcmcia / cardbus.c

/*
 * cardbus.c -- 16-bit PCMCIA core support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * The initial developer of the original code is David A. Hinds
 * <dahinds@users.sourceforge.net>.  Portions created by David A. Hinds
 * are Copyright (C) 1999 David A. Hinds.  All Rights Reserved.
 *
 * (C) 1999		David A. Hinds
 */

/*
 * Cardbus handling has been re-written to be more of a PCI bridge thing,
 * and the PCI code basically does all the resource handling.
 *
 *		Linus, Jan 2000
 */


#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/mm.h>
#include <linux/pci.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <asm/irq.h>

#include <pcmcia/cs_types.h>
#include <pcmcia/ss.h>
#include <pcmcia/cs.h>
#include <pcmcia/cistpl.h>
#include "cs_internal.h"

/*====================================================================*/

/* Offsets in the Expansion ROM Image Header */
#define ROM_SIGNATURE		0x0000	/* 2 bytes */
#define ROM_DATA_PTR		0x0018	/* 2 bytes */

/* Offsets in the CardBus PC Card Data Structure */
#define PCDATA_SIGNATURE	0x0000	/* 4 bytes */
#define PCDATA_VPD_PTR		0x0008	/* 2 bytes */
#define PCDATA_LENGTH		0x000a	/* 2 bytes */
#define PCDATA_REVISION		0x000c
#define PCDATA_IMAGE_SZ		0x0010	/* 2 bytes */
#define PCDATA_ROM_LEVEL	0x0012	/* 2 bytes */
#define PCDATA_CODE_TYPE	0x0014
#define PCDATA_INDICATOR	0x0015

/*=====================================================================

    Expansion ROM's have a special layout, and pointers specify an
    image number and an offset within that image.  xlate_rom_addr()
    converts an image/offset address to an absolute offset from the
    ROM's base address.

=====================================================================*/

static u_int xlate_rom_addr(void __iomem *b, u_int addr)
{
	u_int img = 0, ofs = 0, sz;
	u_short data;
	while ((readb(b) == 0x55) && (readb(b + 1) == 0xaa)) {
		if (img == (addr >> 28))
			return (addr & 0x0fffffff) + ofs;
		data = readb(b + ROM_DATA_PTR) + (readb(b + ROM_DATA_PTR + 1) << 8);
		sz = 512 * (readb(b + data + PCDATA_IMAGE_SZ) +
			    (readb(b + data + PCDATA_IMAGE_SZ + 1) << 8));
		if ((sz == 0) || (readb(b + data + PCDATA_INDICATOR) & 0x80))
			break;
		b += sz;
		ofs += sz;
		img++;
	}
	return 0;
}

/*=====================================================================

    These are similar to setup_cis_mem and release_cis_mem for 16-bit
    cards.  The "result" that is used externally is the cb_cis_virt
    pointer in the struct pcmcia_socket structure.

=====================================================================*/

static void cb_release_cis_mem(struct pcmcia_socket *s)
{
	if (s->cb_cis_virt) {
		dev_dbg(&s->dev, "cb_release_cis_mem()\n");
		iounmap(s->cb_cis_virt);
		s->cb_cis_virt = NULL;
		s->cb_cis_res = NULL;
	}
}

static int cb_setup_cis_mem(struct pcmcia_socket *s, struct resource *res)
{
	unsigned int start, size;

	if (res == s->cb_cis_res)
		return 0;

	if (s->cb_cis_res)
		cb_release_cis_mem(s);

	start = res->start;
	size = res->end - start + 1;
	s->cb_cis_virt = ioremap(start, size);

	if (!s->cb_cis_virt)
		return -1;

	s->cb_cis_res = res;

	return 0;
}

/*=====================================================================

    This is used by the CIS processing code to read CIS information
    from a CardBus device.

=====================================================================*/

int read_cb_mem(struct pcmcia_socket *s, int space, u_int addr, u_int len,
		void *ptr)
{
	struct pci_dev *dev;
	struct resource *res;

	dev_dbg(&s->dev, "read_cb_mem(%d, %#x, %u)\n", space, addr, len);

	dev = pci_get_slot(s->cb_dev->subordinate, 0);
	if (!dev)
		goto fail;

	/* Config space? */
	if (space == 0) {
		if (addr + len > 0x100)
			goto failput;
		for (; len; addr++, ptr++, len--)
			pci_read_config_byte(dev, addr, ptr);
		return 0;
	}

	res = dev->resource + space - 1;

	pci_dev_put(dev);

	if (!res->flags)
		goto fail;

	if (cb_setup_cis_mem(s, res) != 0)
		goto fail;

	if (space == 7) {
		addr = xlate_rom_addr(s->cb_cis_virt, addr);
		if (addr == 0)
			goto fail;
	}

	if (addr + len > res->end - res->start)
		goto fail;

	memcpy_fromio(ptr, s->cb_cis_virt + addr, len);
	return 0;

failput:
	pci_dev_put(dev);
fail:
	memset(ptr, 0xff, len);
	return -1;
}

/*=====================================================================

    cb_alloc() and cb_free() allocate and free the kernel data
    structures for a Cardbus device, and handle the lowest level PCI
    device setup issues.

=====================================================================*/

static void cardbus_config_irq_and_cls(struct pci_bus *bus, int irq)
{
	struct pci_dev *dev;

	list_for_each_entry(dev, &bus->devices, bus_list) {
		u8 irq_pin;

		/*
		 * Since there is only one interrupt available to
		 * CardBus devices, all devices downstream of this
		 * device must be using this IRQ.
		 */
		pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq_pin);
		if (irq_pin) {
			dev->irq = irq;
			pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
		}

		/*
		 * Some controllers transfer very slowly with 0 CLS.
		 * Configure it.  This may fail as CLS configuration
		 * is mandatory only for MWI.
		 */
		pci_set_cacheline_size(dev);

		if (dev->subordinate)
			cardbus_config_irq_and_cls(dev->subordinate, irq);
	}
}

int __ref cb_alloc(struct pcmcia_socket *s)
{
	struct pci_bus *bus = s->cb_dev->subordinate;
	struct pci_dev *dev;
	unsigned int max, pass;

	s->functions = pci_scan_slot(bus, PCI_DEVFN(0, 0));
	pci_fixup_cardbus(bus); 

	max = bus->secondary;
	for (pass = 0; pass < 2; pass++)
		list_for_each_entry(dev, &bus->devices, bus_list)
			if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
			    dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
				max = pci_scan_bridge(bus, dev, max, pass);

	/*
	 * Size all resources below the CardBus controller.
	 */
	pci_bus_size_bridges(bus);
	pci_bus_assign_resources(bus);
	cardbus_config_irq_and_cls(bus, s->pci_irq);

	/* socket specific tune function */
	if (s->tune_bridge)
		s->tune_bridge(s, bus);

	pci_enable_bridges(bus);
	pci_bus_add_devices(bus);

	s->irq.AssignedIRQ = s->pci_irq;
	return 0;
}

void cb_free(struct pcmcia_socket *s)
{
	struct pci_dev *bridge = s->cb_dev;

	cb_release_cis_mem(s);

	if (bridge)
		pci_remove_behind_bridge(bridge);
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* cardbus.c -- 16-bit PCMCIA core support
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* The initial developer of the original code is David A. Hinds
	9	* <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
	10	* are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
	11	*
	12	* (C) 1999 David A. Hinds
	13	*/
	14
	15	/*
	16	* Cardbus handling has been re-written to be more of a PCI bridge thing,
	17	* and the PCI code basically does all the resource handling.
	18	*
	19	* Linus, Jan 2000
	20	*/
	21
	22
	23	#include <linux/module.h>
	24	#include <linux/kernel.h>
	25	#include <linux/string.h>
	26	#include <linux/slab.h>
	27	#include <linux/mm.h>
	28	#include <linux/pci.h>
	29	#include <linux/ioport.h>
9fea84f4	30	#include <linux/io.h>
1da177e4	31	#include <asm/irq.h>
1da177e4	32
1da177e4 LT	33	#include <pcmcia/cs_types.h>
	34	#include <pcmcia/ss.h>
	35	#include <pcmcia/cs.h>
1da177e4 LT	36	#include <pcmcia/cistpl.h>
	37	#include "cs_internal.h"
	38
	39	/====================================================================/
	40
1da177e4 LT	41	/* Offsets in the Expansion ROM Image Header */
	42	#define ROM_SIGNATURE 0x0000 /* 2 bytes */
	43	#define ROM_DATA_PTR 0x0018 /* 2 bytes */
	44
	45	/* Offsets in the CardBus PC Card Data Structure */
	46	#define PCDATA_SIGNATURE 0x0000 /* 4 bytes */
	47	#define PCDATA_VPD_PTR 0x0008 /* 2 bytes */
	48	#define PCDATA_LENGTH 0x000a /* 2 bytes */
	49	#define PCDATA_REVISION 0x000c
	50	#define PCDATA_IMAGE_SZ 0x0010 /* 2 bytes */
	51	#define PCDATA_ROM_LEVEL 0x0012 /* 2 bytes */
	52	#define PCDATA_CODE_TYPE 0x0014
	53	#define PCDATA_INDICATOR 0x0015
	54
	55	/*=====================================================================
	56
	57	Expansion ROM's have a special layout, and pointers specify an
	58	image number and an offset within that image. xlate_rom_addr()
	59	converts an image/offset address to an absolute offset from the
	60	ROM's base address.
9fea84f4	61
1da177e4 LT	62	=====================================================================*/
	63
	64	static u_int xlate_rom_addr(void __iomem *b, u_int addr)
	65	{
	66	u_int img = 0, ofs = 0, sz;
	67	u_short data;
	68	while ((readb(b) == 0x55) && (readb(b + 1) == 0xaa)) {
	69	if (img == (addr >> 28))
	70	return (addr & 0x0fffffff) + ofs;
	71	data = readb(b + ROM_DATA_PTR) + (readb(b + ROM_DATA_PTR + 1) << 8);
	72	sz = 512 * (readb(b + data + PCDATA_IMAGE_SZ) +
	73	(readb(b + data + PCDATA_IMAGE_SZ + 1) << 8));
	74	if ((sz == 0) \|\| (readb(b + data + PCDATA_INDICATOR) & 0x80))
	75	break;
	76	b += sz;
	77	ofs += sz;
	78	img++;
	79	}
	80	return 0;
	81	}
	82
	83	/*=====================================================================
	84
	85	These are similar to setup_cis_mem and release_cis_mem for 16-bit
	86	cards. The "result" that is used externally is the cb_cis_virt
	87	pointer in the struct pcmcia_socket structure.
9fea84f4	88
1da177e4 LT	89	=====================================================================*/
1da177e4 LT	90
9fea84f4	91	static void cb_release_cis_mem(struct pcmcia_socket *s)
1da177e4 LT	92	{
1da177e4 LT	93	if (s->cb_cis_virt) {
d50dbec3	94	dev_dbg(&s->dev, "cb_release_cis_mem()\n");
1da177e4 LT	95	iounmap(s->cb_cis_virt);
	96	s->cb_cis_virt = NULL;
	97	s->cb_cis_res = NULL;
	98	}
	99	}
	100
9fea84f4	101	static int cb_setup_cis_mem(struct pcmcia_socket s, struct resource res)
1da177e4 LT	102	{
	103	unsigned int start, size;
	104
	105	if (res == s->cb_cis_res)
	106	return 0;
	107
	108	if (s->cb_cis_res)
	109	cb_release_cis_mem(s);
	110
	111	start = res->start;
	112	size = res->end - start + 1;
	113	s->cb_cis_virt = ioremap(start, size);
	114
	115	if (!s->cb_cis_virt)
	116	return -1;
	117
	118	s->cb_cis_res = res;
	119
	120	return 0;
	121	}
	122
	123	/*=====================================================================
	124
	125	This is used by the CIS processing code to read CIS information
	126	from a CardBus device.
9fea84f4	127
1da177e4 LT	128	=====================================================================*/
1da177e4 LT	129
9fea84f4 DB	130	int read_cb_mem(struct pcmcia_socket *s, int space, u_int addr, u_int len,
9fea84f4 DB	131	void *ptr)
1da177e4 LT	132	{
	133	struct pci_dev *dev;
	134	struct resource *res;
	135
d50dbec3	136	dev_dbg(&s->dev, "read_cb_mem(%d, %#x, %u)\n", space, addr, len);
1da177e4	137
74ae3221	138	dev = pci_get_slot(s->cb_dev->subordinate, 0);
1da177e4 LT	139	if (!dev)
	140	goto fail;
	141
	142	/* Config space? */
	143	if (space == 0) {
	144	if (addr + len > 0x100)
1523508d	145	goto failput;
1da177e4 LT	146	for (; len; addr++, ptr++, len--)
	147	pci_read_config_byte(dev, addr, ptr);
	148	return 0;
	149	}
	150
	151	res = dev->resource + space - 1;
74ae3221 AC	152
	153	pci_dev_put(dev);
	154
1da177e4 LT	155	if (!res->flags)
	156	goto fail;
	157
	158	if (cb_setup_cis_mem(s, res) != 0)
	159	goto fail;
	160
	161	if (space == 7) {
	162	addr = xlate_rom_addr(s->cb_cis_virt, addr);
	163	if (addr == 0)
	164	goto fail;
	165	}
	166
	167	if (addr + len > res->end - res->start)
	168	goto fail;
	169
	170	memcpy_fromio(ptr, s->cb_cis_virt + addr, len);
	171	return 0;
	172
1523508d JL	173	failput:
1523508d JL	174	pci_dev_put(dev);
1da177e4 LT	175	fail:
	176	memset(ptr, 0xff, len);
	177	return -1;
	178	}
	179
	180	/*=====================================================================
	181
	182	cb_alloc() and cb_free() allocate and free the kernel data
	183	structures for a Cardbus device, and handle the lowest level PCI
	184	device setup issues.
9fea84f4	185
1da177e4 LT	186	=====================================================================*/
1da177e4 LT	187
15ea76d4	188	static void cardbus_config_irq_and_cls(struct pci_bus *bus, int irq)
1da177e4 LT	189	{
	190	struct pci_dev *dev;
	191
	192	list_for_each_entry(dev, &bus->devices, bus_list) {
	193	u8 irq_pin;
	194
15ea76d4 TH	195	/*
	196	* Since there is only one interrupt available to
	197	* CardBus devices, all devices downstream of this
	198	* device must be using this IRQ.
	199	*/
1da177e4 LT	200	pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq_pin);
	201	if (irq_pin) {
	202	dev->irq = irq;
	203	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
	204	}
	205
15ea76d4 TH	206	/*
	207	* Some controllers transfer very slowly with 0 CLS.
	208	* Configure it. This may fail as CLS configuration
	209	* is mandatory only for MWI.
	210	*/
	211	pci_set_cacheline_size(dev);
	212
1da177e4	213	if (dev->subordinate)
15ea76d4	214	cardbus_config_irq_and_cls(dev->subordinate, irq);
1da177e4 LT	215	}
	216	}
	217
9fea84f4	218	int __ref cb_alloc(struct pcmcia_socket *s)
1da177e4 LT	219	{
	220	struct pci_bus *bus = s->cb_dev->subordinate;
	221	struct pci_dev *dev;
	222	unsigned int max, pass;
	223
	224	s->functions = pci_scan_slot(bus, PCI_DEVFN(0, 0));
2d1c8618	225	pci_fixup_cardbus(bus);
1da177e4 LT	226
	227	max = bus->secondary;
	228	for (pass = 0; pass < 2; pass++)
	229	list_for_each_entry(dev, &bus->devices, bus_list)
	230	if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE \|\|
	231	dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
	232	max = pci_scan_bridge(bus, dev, max, pass);
	233
	234	/*
	235	* Size all resources below the CardBus controller.
	236	*/
	237	pci_bus_size_bridges(bus);
	238	pci_bus_assign_resources(bus);
15ea76d4	239	cardbus_config_irq_and_cls(bus, s->pci_irq);
8c3520d4 DR	240
	241	/* socket specific tune function */
	242	if (s->tune_bridge)
	243	s->tune_bridge(s, bus);
	244
1da177e4 LT	245	pci_enable_bridges(bus);
	246	pci_bus_add_devices(bus);
	247
	248	s->irq.AssignedIRQ = s->pci_irq;
4c89e88b	249	return 0;
1da177e4 LT	250	}
1da177e4 LT	251
9fea84f4	252	void cb_free(struct pcmcia_socket *s)
1da177e4 LT	253	{
	254	struct pci_dev *bridge = s->cb_dev;
	255
	256	cb_release_cis_mem(s);
	257
	258	if (bridge)
	259	pci_remove_behind_bridge(bridge);
	260	}