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Commit | Line | Data |
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09c434b8 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
4839879f | 2 | /* |
1da177e4 LT |
3 | * Driver for Intel I82092AA PCI-PCMCIA bridge. |
4 | * | |
5 | * (C) 2001 Red Hat, Inc. | |
6 | * | |
7 | * Author: Arjan Van De Ven <arjanv@redhat.com> | |
8 | * Loosly based on i82365.c from the pcmcia-cs package | |
1da177e4 LT |
9 | */ |
10 | ||
11 | #include <linux/kernel.h> | |
1da177e4 LT |
12 | #include <linux/module.h> |
13 | #include <linux/pci.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/workqueue.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/device.h> | |
18 | ||
1da177e4 | 19 | #include <pcmcia/ss.h> |
1da177e4 | 20 | |
ac5af877 | 21 | #include <linux/io.h> |
1da177e4 LT |
22 | |
23 | #include "i82092aa.h" | |
24 | #include "i82365.h" | |
25 | ||
26 | MODULE_LICENSE("GPL"); | |
27 | ||
28 | /* PCI core routines */ | |
0178a7a5 | 29 | static const struct pci_device_id i82092aa_pci_ids[] = { |
2b2c5d8c AL |
30 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82092AA_0) }, |
31 | { } | |
1da177e4 LT |
32 | }; |
33 | MODULE_DEVICE_TABLE(pci, i82092aa_pci_ids); | |
34 | ||
ba66ddfa | 35 | static struct pci_driver i82092aa_pci_driver = { |
4839879f SG |
36 | .name = "i82092aa", |
37 | .id_table = i82092aa_pci_ids, | |
38 | .probe = i82092aa_pci_probe, | |
39 | .remove = i82092aa_pci_remove, | |
1da177e4 LT |
40 | }; |
41 | ||
42 | ||
43 | /* the pccard structure and its functions */ | |
44 | static struct pccard_operations i82092aa_operations = { | |
4839879f | 45 | .init = i82092aa_init, |
1da177e4 | 46 | .get_status = i82092aa_get_status, |
1da177e4 LT |
47 | .set_socket = i82092aa_set_socket, |
48 | .set_io_map = i82092aa_set_io_map, | |
49 | .set_mem_map = i82092aa_set_mem_map, | |
50 | }; | |
51 | ||
25985edc | 52 | /* The card can do up to 4 sockets, allocate a structure for each of them */ |
1da177e4 LT |
53 | |
54 | struct socket_info { | |
55 | int number; | |
4839879f SG |
56 | int card_state; |
57 | /* 0 = no socket, | |
58 | * 1 = empty socket, | |
59 | * 2 = card but not initialized, | |
60 | * 3 = operational card | |
61 | */ | |
62 | unsigned int io_base; /* base io address of the socket */ | |
63 | ||
1da177e4 LT |
64 | struct pcmcia_socket socket; |
65 | struct pci_dev *dev; /* The PCI device for the socket */ | |
66 | }; | |
67 | ||
68 | #define MAX_SOCKETS 4 | |
69 | static struct socket_info sockets[MAX_SOCKETS]; | |
4839879f | 70 | static int socket_count; /* shortcut */ |
1da177e4 LT |
71 | |
72 | ||
152b4bb5 SG |
73 | static int i82092aa_pci_probe(struct pci_dev *dev, |
74 | const struct pci_device_id *id) | |
1da177e4 LT |
75 | { |
76 | unsigned char configbyte; | |
77 | int i, ret; | |
4839879f | 78 | |
90886464 SG |
79 | ret = pci_enable_device(dev); |
80 | if (ret) | |
1da177e4 | 81 | return ret; |
4839879f | 82 | |
152b4bb5 SG |
83 | /* PCI Configuration Control */ |
84 | pci_read_config_byte(dev, 0x40, &configbyte); | |
85 | ||
4839879f | 86 | switch (configbyte&6) { |
6aaf8ff3 SG |
87 | case 0: |
88 | socket_count = 2; | |
89 | break; | |
90 | case 2: | |
91 | socket_count = 1; | |
92 | break; | |
93 | case 4: | |
94 | case 6: | |
95 | socket_count = 4; | |
96 | break; | |
97 | ||
98 | default: | |
99 | dev_err(&dev->dev, | |
100 | "Oops, you did something we didn't think of.\n"); | |
101 | ret = -EIO; | |
102 | goto err_out_disable; | |
1da177e4 | 103 | } |
26a0a104 SG |
104 | dev_info(&dev->dev, "configured as a %d socket device.\n", |
105 | socket_count); | |
1da177e4 LT |
106 | |
107 | if (!request_region(pci_resource_start(dev, 0), 2, "i82092aa")) { | |
108 | ret = -EBUSY; | |
109 | goto err_out_disable; | |
110 | } | |
4839879f SG |
111 | |
112 | for (i = 0; i < socket_count; i++) { | |
1da177e4 LT |
113 | sockets[i].card_state = 1; /* 1 = present but empty */ |
114 | sockets[i].io_base = pci_resource_start(dev, 0); | |
e39cdacf | 115 | sockets[i].dev = dev; |
1da177e4 LT |
116 | sockets[i].socket.features |= SS_CAP_PCCARD; |
117 | sockets[i].socket.map_size = 0x1000; | |
118 | sockets[i].socket.irq_mask = 0; | |
119 | sockets[i].socket.pci_irq = dev->irq; | |
7a96e87d | 120 | sockets[i].socket.cb_dev = dev; |
1da177e4 LT |
121 | sockets[i].socket.owner = THIS_MODULE; |
122 | ||
123 | sockets[i].number = i; | |
4839879f | 124 | |
1da177e4 LT |
125 | if (card_present(i)) { |
126 | sockets[i].card_state = 3; | |
26a0a104 | 127 | dev_dbg(&dev->dev, "slot %i is occupied\n", i); |
1da177e4 | 128 | } else { |
26a0a104 | 129 | dev_dbg(&dev->dev, "slot %i is vacant\n", i); |
1da177e4 LT |
130 | } |
131 | } | |
4839879f | 132 | |
152b4bb5 SG |
133 | /* Now, specifiy that all interrupts are to be done as PCI interrupts |
134 | * bitmask, one bit per event, 1 = PCI interrupt, 0 = ISA interrupt | |
135 | */ | |
136 | configbyte = 0xFF; | |
137 | ||
138 | /* PCI Interrupt Routing Register */ | |
139 | pci_write_config_byte(dev, 0x50, configbyte); | |
1da177e4 LT |
140 | |
141 | /* Register the interrupt handler */ | |
836e9494 | 142 | dev_dbg(&dev->dev, "Requesting interrupt %i\n", dev->irq); |
90886464 SG |
143 | ret = request_irq(dev->irq, i82092aa_interrupt, IRQF_SHARED, |
144 | "i82092aa", i82092aa_interrupt); | |
145 | if (ret) { | |
26a0a104 SG |
146 | dev_err(&dev->dev, "Failed to register IRQ %d, aborting\n", |
147 | dev->irq); | |
1da177e4 LT |
148 | goto err_out_free_res; |
149 | } | |
150 | ||
4839879f | 151 | for (i = 0; i < socket_count; i++) { |
87373318 | 152 | sockets[i].socket.dev.parent = &dev->dev; |
1da177e4 LT |
153 | sockets[i].socket.ops = &i82092aa_operations; |
154 | sockets[i].socket.resource_ops = &pccard_nonstatic_ops; | |
155 | ret = pcmcia_register_socket(&sockets[i].socket); | |
ae1f62c5 | 156 | if (ret) |
1da177e4 | 157 | goto err_out_free_sockets; |
1da177e4 LT |
158 | } |
159 | ||
1da177e4 LT |
160 | return 0; |
161 | ||
162 | err_out_free_sockets: | |
163 | if (i) { | |
ae1f62c5 | 164 | for (i--; i >= 0; i--) |
1da177e4 | 165 | pcmcia_unregister_socket(&sockets[i].socket); |
1da177e4 LT |
166 | } |
167 | free_irq(dev->irq, i82092aa_interrupt); | |
168 | err_out_free_res: | |
169 | release_region(pci_resource_start(dev, 0), 2); | |
170 | err_out_disable: | |
171 | pci_disable_device(dev); | |
4839879f | 172 | return ret; |
1da177e4 LT |
173 | } |
174 | ||
e765a02c | 175 | static void i82092aa_pci_remove(struct pci_dev *dev) |
1da177e4 | 176 | { |
36c286d5 | 177 | int i; |
1da177e4 | 178 | |
1da177e4 LT |
179 | free_irq(dev->irq, i82092aa_interrupt); |
180 | ||
36c286d5 DC |
181 | for (i = 0; i < socket_count; i++) |
182 | pcmcia_unregister_socket(&sockets[i].socket); | |
1da177e4 LT |
183 | } |
184 | ||
185 | static DEFINE_SPINLOCK(port_lock); | |
186 | ||
187 | /* basic value read/write functions */ | |
188 | ||
189 | static unsigned char indirect_read(int socket, unsigned short reg) | |
190 | { | |
191 | unsigned short int port; | |
192 | unsigned char val; | |
193 | unsigned long flags; | |
4ae66dd7 | 194 | |
4839879f | 195 | spin_lock_irqsave(&port_lock, flags); |
1da177e4 LT |
196 | reg += socket * 0x40; |
197 | port = sockets[socket].io_base; | |
4839879f | 198 | outb(reg, port); |
1da177e4 | 199 | val = inb(port+1); |
4839879f | 200 | spin_unlock_irqrestore(&port_lock, flags); |
1da177e4 LT |
201 | return val; |
202 | } | |
203 | ||
1da177e4 LT |
204 | static void indirect_write(int socket, unsigned short reg, unsigned char value) |
205 | { | |
206 | unsigned short int port; | |
207 | unsigned long flags; | |
4ae66dd7 | 208 | |
4839879f | 209 | spin_lock_irqsave(&port_lock, flags); |
1da177e4 | 210 | reg = reg + socket * 0x40; |
4839879f SG |
211 | port = sockets[socket].io_base; |
212 | outb(reg, port); | |
213 | outb(value, port+1); | |
214 | spin_unlock_irqrestore(&port_lock, flags); | |
1da177e4 LT |
215 | } |
216 | ||
217 | static void indirect_setbit(int socket, unsigned short reg, unsigned char mask) | |
218 | { | |
219 | unsigned short int port; | |
220 | unsigned char val; | |
221 | unsigned long flags; | |
4ae66dd7 | 222 | |
4839879f | 223 | spin_lock_irqsave(&port_lock, flags); |
1da177e4 | 224 | reg = reg + socket * 0x40; |
4839879f SG |
225 | port = sockets[socket].io_base; |
226 | outb(reg, port); | |
1da177e4 LT |
227 | val = inb(port+1); |
228 | val |= mask; | |
4839879f SG |
229 | outb(reg, port); |
230 | outb(val, port+1); | |
231 | spin_unlock_irqrestore(&port_lock, flags); | |
1da177e4 LT |
232 | } |
233 | ||
234 | ||
152b4bb5 SG |
235 | static void indirect_resetbit(int socket, |
236 | unsigned short reg, unsigned char mask) | |
1da177e4 LT |
237 | { |
238 | unsigned short int port; | |
239 | unsigned char val; | |
240 | unsigned long flags; | |
4ae66dd7 | 241 | |
4839879f | 242 | spin_lock_irqsave(&port_lock, flags); |
1da177e4 | 243 | reg = reg + socket * 0x40; |
4839879f SG |
244 | port = sockets[socket].io_base; |
245 | outb(reg, port); | |
1da177e4 LT |
246 | val = inb(port+1); |
247 | val &= ~mask; | |
4839879f SG |
248 | outb(reg, port); |
249 | outb(val, port+1); | |
250 | spin_unlock_irqrestore(&port_lock, flags); | |
1da177e4 LT |
251 | } |
252 | ||
152b4bb5 SG |
253 | static void indirect_write16(int socket, |
254 | unsigned short reg, unsigned short value) | |
1da177e4 LT |
255 | { |
256 | unsigned short int port; | |
257 | unsigned char val; | |
258 | unsigned long flags; | |
4ae66dd7 | 259 | |
4839879f | 260 | spin_lock_irqsave(&port_lock, flags); |
1da177e4 | 261 | reg = reg + socket * 0x40; |
4839879f SG |
262 | port = sockets[socket].io_base; |
263 | ||
264 | outb(reg, port); | |
1da177e4 | 265 | val = value & 255; |
4839879f SG |
266 | outb(val, port+1); |
267 | ||
1da177e4 | 268 | reg++; |
4839879f SG |
269 | |
270 | outb(reg, port); | |
1da177e4 | 271 | val = value>>8; |
4839879f SG |
272 | outb(val, port+1); |
273 | spin_unlock_irqrestore(&port_lock, flags); | |
1da177e4 LT |
274 | } |
275 | ||
276 | /* simple helper functions */ | |
277 | /* External clock time, in nanoseconds. 120 ns = 8.33 MHz */ | |
278 | static int cycle_time = 120; | |
279 | ||
280 | static int to_cycles(int ns) | |
281 | { | |
4839879f | 282 | if (cycle_time != 0) |
1da177e4 LT |
283 | return ns/cycle_time; |
284 | else | |
285 | return 0; | |
286 | } | |
4839879f | 287 | |
1da177e4 LT |
288 | |
289 | /* Interrupt handler functionality */ | |
290 | ||
7d12e780 | 291 | static irqreturn_t i82092aa_interrupt(int irq, void *dev) |
1da177e4 LT |
292 | { |
293 | int i; | |
294 | int loopcount = 0; | |
295 | int handled = 0; | |
296 | ||
4839879f SG |
297 | unsigned int events, active = 0; |
298 | ||
1da177e4 LT |
299 | while (1) { |
300 | loopcount++; | |
4839879f | 301 | if (loopcount > 20) { |
26a0a104 | 302 | pr_err("i82092aa: infinite eventloop in interrupt\n"); |
1da177e4 LT |
303 | break; |
304 | } | |
4839879f | 305 | |
1da177e4 | 306 | active = 0; |
4839879f SG |
307 | |
308 | for (i = 0; i < socket_count; i++) { | |
1da177e4 | 309 | int csc; |
4ae66dd7 | 310 | |
152b4bb5 SG |
311 | /* Inactive socket, should not happen */ |
312 | if (sockets[i].card_state == 0) | |
4839879f SG |
313 | continue; |
314 | ||
152b4bb5 SG |
315 | /* card status change register */ |
316 | csc = indirect_read(i, I365_CSC); | |
4839879f SG |
317 | |
318 | if (csc == 0) /* no events on this socket */ | |
1da177e4 | 319 | continue; |
1da177e4 LT |
320 | handled = 1; |
321 | events = 0; | |
4839879f | 322 | |
1da177e4 LT |
323 | if (csc & I365_CSC_DETECT) { |
324 | events |= SS_DETECT; | |
26a0a104 SG |
325 | dev_info(&sockets[i].dev->dev, |
326 | "Card detected in socket %i!\n", i); | |
4839879f SG |
327 | } |
328 | ||
329 | if (indirect_read(i, I365_INTCTL) & I365_PC_IOCARD) { | |
1da177e4 | 330 | /* For IO/CARDS, bit 0 means "read the card" */ |
152b4bb5 SG |
331 | if (csc & I365_CSC_STSCHG) |
332 | events |= SS_STSCHG; | |
1da177e4 LT |
333 | } else { |
334 | /* Check for battery/ready events */ | |
152b4bb5 SG |
335 | if (csc & I365_CSC_BVD1) |
336 | events |= SS_BATDEAD; | |
337 | if (csc & I365_CSC_BVD2) | |
338 | events |= SS_BATWARN; | |
339 | if (csc & I365_CSC_READY) | |
340 | events |= SS_READY; | |
1da177e4 | 341 | } |
4839879f | 342 | |
ae1f62c5 | 343 | if (events) |
1da177e4 | 344 | pcmcia_parse_events(&sockets[i].socket, events); |
1da177e4 LT |
345 | active |= events; |
346 | } | |
4839879f SG |
347 | |
348 | if (active == 0) /* no more events to handle */ | |
349 | break; | |
1da177e4 LT |
350 | } |
351 | return IRQ_RETVAL(handled); | |
1da177e4 LT |
352 | } |
353 | ||
354 | ||
355 | ||
356 | /* socket functions */ | |
357 | ||
358 | static int card_present(int socketno) | |
4839879f | 359 | { |
1da177e4 | 360 | unsigned int val; |
4ae66dd7 | 361 | |
4839879f | 362 | if ((socketno < 0) || (socketno >= MAX_SOCKETS)) |
1da177e4 LT |
363 | return 0; |
364 | if (sockets[socketno].io_base == 0) | |
365 | return 0; | |
366 | ||
4839879f | 367 | |
1da177e4 | 368 | val = indirect_read(socketno, 1); /* Interface status register */ |
52739f06 | 369 | if ((val&12) == 12) |
1da177e4 | 370 | return 1; |
4839879f | 371 | |
1da177e4 LT |
372 | return 0; |
373 | } | |
374 | ||
375 | static void set_bridge_state(int sock) | |
376 | { | |
4839879f SG |
377 | indirect_write(sock, I365_GBLCTL, 0x00); |
378 | indirect_write(sock, I365_GENCTL, 0x00); | |
379 | ||
380 | indirect_setbit(sock, I365_INTCTL, 0x08); | |
1da177e4 LT |
381 | } |
382 | ||
383 | ||
1da177e4 LT |
384 | static int i82092aa_init(struct pcmcia_socket *sock) |
385 | { | |
386 | int i; | |
387 | struct resource res = { .start = 0, .end = 0x0fff }; | |
4839879f | 388 | pccard_io_map io = { 0, 0, 0, 0, 1 }; |
1da177e4 | 389 | pccard_mem_map mem = { .res = &res, }; |
4839879f | 390 | |
4839879f SG |
391 | for (i = 0; i < 2; i++) { |
392 | io.map = i; | |
393 | i82092aa_set_io_map(sock, &io); | |
1da177e4 | 394 | } |
4839879f SG |
395 | for (i = 0; i < 5; i++) { |
396 | mem.map = i; | |
397 | i82092aa_set_mem_map(sock, &mem); | |
1da177e4 | 398 | } |
52739f06 | 399 | |
1da177e4 LT |
400 | return 0; |
401 | } | |
4839879f | 402 | |
1da177e4 LT |
403 | static int i82092aa_get_status(struct pcmcia_socket *socket, u_int *value) |
404 | { | |
152b4bb5 SG |
405 | unsigned int sock = container_of(socket, |
406 | struct socket_info, socket)->number; | |
1da177e4 | 407 | unsigned int status; |
152b4bb5 SG |
408 | |
409 | /* Interface Status Register */ | |
410 | status = indirect_read(sock, I365_STATUS); | |
411 | ||
1da177e4 | 412 | *value = 0; |
4839879f | 413 | |
ae1f62c5 | 414 | if ((status & I365_CS_DETECT) == I365_CS_DETECT) |
1da177e4 | 415 | *value |= SS_DETECT; |
4839879f | 416 | |
1da177e4 LT |
417 | /* IO cards have a different meaning of bits 0,1 */ |
418 | /* Also notice the inverse-logic on the bits */ | |
4839879f | 419 | if (indirect_read(sock, I365_INTCTL) & I365_PC_IOCARD) { |
84182fc7 CIK |
420 | /* IO card */ |
421 | if (!(status & I365_CS_STSCHG)) | |
422 | *value |= SS_STSCHG; | |
423 | } else { /* non I/O card */ | |
424 | if (!(status & I365_CS_BVD1)) | |
425 | *value |= SS_BATDEAD; | |
426 | if (!(status & I365_CS_BVD2)) | |
427 | *value |= SS_BATWARN; | |
428 | } | |
4839879f | 429 | |
84182fc7 CIK |
430 | if (status & I365_CS_WRPROT) |
431 | (*value) |= SS_WRPROT; /* card is write protected */ | |
4839879f | 432 | |
84182fc7 CIK |
433 | if (status & I365_CS_READY) |
434 | (*value) |= SS_READY; /* card is not busy */ | |
4839879f | 435 | |
84182fc7 CIK |
436 | if (status & I365_CS_POWERON) |
437 | (*value) |= SS_POWERON; /* power is applied to the card */ | |
1da177e4 | 438 | |
1da177e4 LT |
439 | return 0; |
440 | } | |
441 | ||
442 | ||
152b4bb5 SG |
443 | static int i82092aa_set_socket(struct pcmcia_socket *socket, |
444 | socket_state_t *state) | |
1da177e4 | 445 | { |
26a0a104 SG |
446 | struct socket_info *sock_info = container_of(socket, struct socket_info, |
447 | socket); | |
448 | unsigned int sock = sock_info->number; | |
1da177e4 | 449 | unsigned char reg; |
4839879f | 450 | |
1da177e4 | 451 | /* First, set the global controller options */ |
4839879f | 452 | |
1da177e4 | 453 | set_bridge_state(sock); |
4839879f | 454 | |
1da177e4 | 455 | /* Values for the IGENC register */ |
4839879f | 456 | |
1da177e4 | 457 | reg = 0; |
152b4bb5 SG |
458 | |
459 | /* The reset bit has "inverse" logic */ | |
460 | if (!(state->flags & SS_RESET)) | |
4839879f SG |
461 | reg = reg | I365_PC_RESET; |
462 | if (state->flags & SS_IOCARD) | |
1da177e4 | 463 | reg = reg | I365_PC_IOCARD; |
4839879f | 464 | |
152b4bb5 SG |
465 | /* IGENC, Interrupt and General Control Register */ |
466 | indirect_write(sock, I365_INTCTL, reg); | |
4839879f | 467 | |
1da177e4 | 468 | /* Power registers */ |
4839879f | 469 | |
1da177e4 | 470 | reg = I365_PWR_NORESET; /* default: disable resetdrv on resume */ |
4839879f | 471 | |
1da177e4 | 472 | if (state->flags & SS_PWR_AUTO) { |
26a0a104 | 473 | dev_info(&sock_info->dev->dev, "Auto power\n"); |
1da177e4 LT |
474 | reg |= I365_PWR_AUTO; /* automatic power mngmnt */ |
475 | } | |
476 | if (state->flags & SS_OUTPUT_ENA) { | |
26a0a104 | 477 | dev_info(&sock_info->dev->dev, "Power Enabled\n"); |
1da177e4 LT |
478 | reg |= I365_PWR_OUT; /* enable power */ |
479 | } | |
4839879f | 480 | |
1da177e4 | 481 | switch (state->Vcc) { |
6aaf8ff3 SG |
482 | case 0: |
483 | break; | |
484 | case 50: | |
485 | dev_info(&sock_info->dev->dev, | |
486 | "setting voltage to Vcc to 5V on socket %i\n", | |
487 | sock); | |
488 | reg |= I365_VCC_5V; | |
489 | break; | |
490 | default: | |
491 | dev_err(&sock_info->dev->dev, | |
492 | "%s called with invalid VCC power value: %i", | |
493 | __func__, state->Vcc); | |
6aaf8ff3 | 494 | return -EINVAL; |
1da177e4 | 495 | } |
4839879f | 496 | |
1da177e4 | 497 | switch (state->Vpp) { |
6aaf8ff3 SG |
498 | case 0: |
499 | dev_info(&sock_info->dev->dev, | |
500 | "not setting Vpp on socket %i\n", sock); | |
501 | break; | |
502 | case 50: | |
503 | dev_info(&sock_info->dev->dev, | |
504 | "setting Vpp to 5.0 for socket %i\n", sock); | |
505 | reg |= I365_VPP1_5V | I365_VPP2_5V; | |
506 | break; | |
507 | case 120: | |
508 | dev_info(&sock_info->dev->dev, "setting Vpp to 12.0\n"); | |
509 | reg |= I365_VPP1_12V | I365_VPP2_12V; | |
510 | break; | |
511 | default: | |
512 | dev_err(&sock_info->dev->dev, | |
513 | "%s called with invalid VPP power value: %i", | |
514 | __func__, state->Vcc); | |
6aaf8ff3 | 515 | return -EINVAL; |
1da177e4 | 516 | } |
4839879f SG |
517 | |
518 | if (reg != indirect_read(sock, I365_POWER)) /* only write if changed */ | |
519 | indirect_write(sock, I365_POWER, reg); | |
520 | ||
1da177e4 | 521 | /* Enable specific interrupt events */ |
4839879f | 522 | |
1da177e4 | 523 | reg = 0x00; |
ae1f62c5 | 524 | if (state->csc_mask & SS_DETECT) |
1da177e4 | 525 | reg |= I365_CSC_DETECT; |
1da177e4 LT |
526 | if (state->flags & SS_IOCARD) { |
527 | if (state->csc_mask & SS_STSCHG) | |
528 | reg |= I365_CSC_STSCHG; | |
529 | } else { | |
4839879f | 530 | if (state->csc_mask & SS_BATDEAD) |
1da177e4 | 531 | reg |= I365_CSC_BVD1; |
4839879f | 532 | if (state->csc_mask & SS_BATWARN) |
1da177e4 | 533 | reg |= I365_CSC_BVD2; |
4839879f SG |
534 | if (state->csc_mask & SS_READY) |
535 | reg |= I365_CSC_READY; | |
536 | ||
1da177e4 | 537 | } |
4839879f | 538 | |
152b4bb5 SG |
539 | /* now write the value and clear the (probably bogus) pending stuff |
540 | * by doing a dummy read | |
541 | */ | |
4839879f SG |
542 | |
543 | indirect_write(sock, I365_CSCINT, reg); | |
544 | (void)indirect_read(sock, I365_CSC); | |
1da177e4 | 545 | |
1da177e4 LT |
546 | return 0; |
547 | } | |
548 | ||
152b4bb5 SG |
549 | static int i82092aa_set_io_map(struct pcmcia_socket *socket, |
550 | struct pccard_io_map *io) | |
1da177e4 | 551 | { |
26a0a104 SG |
552 | struct socket_info *sock_info = container_of(socket, struct socket_info, |
553 | socket); | |
554 | unsigned int sock = sock_info->number; | |
1da177e4 | 555 | unsigned char map, ioctl; |
4839879f | 556 | |
1da177e4 | 557 | map = io->map; |
4839879f SG |
558 | |
559 | /* Check error conditions */ | |
52739f06 | 560 | if (map > 1) |
1da177e4 | 561 | return -EINVAL; |
52739f06 | 562 | |
152b4bb5 | 563 | if ((io->start > 0xffff) || (io->stop > 0xffff) |
52739f06 | 564 | || (io->stop < io->start)) |
1da177e4 | 565 | return -EINVAL; |
1da177e4 | 566 | |
4839879f | 567 | /* Turn off the window before changing anything */ |
1da177e4 LT |
568 | if (indirect_read(sock, I365_ADDRWIN) & I365_ENA_IO(map)) |
569 | indirect_resetbit(sock, I365_ADDRWIN, I365_ENA_IO(map)); | |
570 | ||
1da177e4 | 571 | /* write the new values */ |
4839879f SG |
572 | indirect_write16(sock, I365_IO(map)+I365_W_START, io->start); |
573 | indirect_write16(sock, I365_IO(map)+I365_W_STOP, io->stop); | |
574 | ||
575 | ioctl = indirect_read(sock, I365_IOCTL) & ~I365_IOCTL_MASK(map); | |
576 | ||
1da177e4 LT |
577 | if (io->flags & (MAP_16BIT|MAP_AUTOSZ)) |
578 | ioctl |= I365_IOCTL_16BIT(map); | |
4839879f SG |
579 | |
580 | indirect_write(sock, I365_IOCTL, ioctl); | |
581 | ||
1da177e4 LT |
582 | /* Turn the window back on if needed */ |
583 | if (io->flags & MAP_ACTIVE) | |
4839879f SG |
584 | indirect_setbit(sock, I365_ADDRWIN, I365_ENA_IO(map)); |
585 | ||
1da177e4 LT |
586 | return 0; |
587 | } | |
588 | ||
152b4bb5 SG |
589 | static int i82092aa_set_mem_map(struct pcmcia_socket *socket, |
590 | struct pccard_mem_map *mem) | |
1da177e4 | 591 | { |
152b4bb5 SG |
592 | struct socket_info *sock_info = container_of(socket, struct socket_info, |
593 | socket); | |
1da177e4 LT |
594 | unsigned int sock = sock_info->number; |
595 | struct pci_bus_region region; | |
596 | unsigned short base, i; | |
597 | unsigned char map; | |
4839879f | 598 | |
fc279850 | 599 | pcibios_resource_to_bus(sock_info->dev->bus, ®ion, mem->res); |
4839879f | 600 | |
1da177e4 | 601 | map = mem->map; |
52739f06 | 602 | if (map > 4) |
1da177e4 | 603 | return -EINVAL; |
4839879f SG |
604 | |
605 | if ((mem->card_start > 0x3ffffff) || (region.start > region.end) || | |
606 | (mem->speed > 1000)) { | |
26a0a104 | 607 | dev_err(&sock_info->dev->dev, |
152b4bb5 | 608 | "invalid mem map for socket %i: %llx to %llx with a start of %x\n", |
f96ee7a4 AM |
609 | sock, |
610 | (unsigned long long)region.start, | |
611 | (unsigned long long)region.end, | |
612 | mem->card_start); | |
1da177e4 LT |
613 | return -EINVAL; |
614 | } | |
4839879f | 615 | |
1da177e4 LT |
616 | /* Turn off the window before changing anything */ |
617 | if (indirect_read(sock, I365_ADDRWIN) & I365_ENA_MEM(map)) | |
4839879f SG |
618 | indirect_resetbit(sock, I365_ADDRWIN, I365_ENA_MEM(map)); |
619 | ||
1da177e4 LT |
620 | /* write the start address */ |
621 | base = I365_MEM(map); | |
622 | i = (region.start >> 12) & 0x0fff; | |
4839879f | 623 | if (mem->flags & MAP_16BIT) |
1da177e4 LT |
624 | i |= I365_MEM_16BIT; |
625 | if (mem->flags & MAP_0WS) | |
4839879f SG |
626 | i |= I365_MEM_0WS; |
627 | indirect_write16(sock, base+I365_W_START, i); | |
628 | ||
1da177e4 | 629 | /* write the stop address */ |
4839879f SG |
630 | |
631 | i = (region.end >> 12) & 0x0fff; | |
1da177e4 | 632 | switch (to_cycles(mem->speed)) { |
6aaf8ff3 SG |
633 | case 0: |
634 | break; | |
635 | case 1: | |
636 | i |= I365_MEM_WS0; | |
637 | break; | |
638 | case 2: | |
639 | i |= I365_MEM_WS1; | |
640 | break; | |
641 | default: | |
642 | i |= I365_MEM_WS1 | I365_MEM_WS0; | |
643 | break; | |
1da177e4 | 644 | } |
4839879f SG |
645 | |
646 | indirect_write16(sock, base+I365_W_STOP, i); | |
647 | ||
1da177e4 | 648 | /* card start */ |
4839879f | 649 | |
1da177e4 LT |
650 | i = ((mem->card_start - region.start) >> 12) & 0x3fff; |
651 | if (mem->flags & MAP_WRPROT) | |
652 | i |= I365_MEM_WRPROT; | |
26a0a104 | 653 | if (mem->flags & MAP_ATTRIB) |
1da177e4 | 654 | i |= I365_MEM_REG; |
4839879f SG |
655 | indirect_write16(sock, base+I365_W_OFF, i); |
656 | ||
1da177e4 LT |
657 | /* Enable the window if necessary */ |
658 | if (mem->flags & MAP_ACTIVE) | |
659 | indirect_setbit(sock, I365_ADDRWIN, I365_ENA_MEM(map)); | |
4839879f | 660 | |
1da177e4 LT |
661 | return 0; |
662 | } | |
663 | ||
664 | static int i82092aa_module_init(void) | |
665 | { | |
ba66ddfa | 666 | return pci_register_driver(&i82092aa_pci_driver); |
1da177e4 LT |
667 | } |
668 | ||
669 | static void i82092aa_module_exit(void) | |
670 | { | |
ba66ddfa | 671 | pci_unregister_driver(&i82092aa_pci_driver); |
4839879f | 672 | if (sockets[0].io_base > 0) |
6aaf8ff3 | 673 | release_region(sockets[0].io_base, 2); |
1da177e4 LT |
674 | } |
675 | ||
676 | module_init(i82092aa_module_init); | |
677 | module_exit(i82092aa_module_exit); | |
678 |