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1da177e4 LT |
1 | /* |
2 | * Driver for Intel I82092AA PCI-PCMCIA bridge. | |
3 | * | |
4 | * (C) 2001 Red Hat, Inc. | |
5 | * | |
6 | * Author: Arjan Van De Ven <arjanv@redhat.com> | |
7 | * Loosly based on i82365.c from the pcmcia-cs package | |
1da177e4 LT |
8 | */ |
9 | ||
10 | #include <linux/kernel.h> | |
1da177e4 LT |
11 | #include <linux/module.h> |
12 | #include <linux/pci.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/workqueue.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/device.h> | |
17 | ||
18 | #include <pcmcia/cs_types.h> | |
19 | #include <pcmcia/ss.h> | |
20 | #include <pcmcia/cs.h> | |
21 | ||
22 | #include <asm/system.h> | |
23 | #include <asm/io.h> | |
24 | ||
25 | #include "i82092aa.h" | |
26 | #include "i82365.h" | |
27 | ||
28 | MODULE_LICENSE("GPL"); | |
29 | ||
30 | /* PCI core routines */ | |
31 | static struct pci_device_id i82092aa_pci_ids[] = { | |
32 | { | |
33 | .vendor = PCI_VENDOR_ID_INTEL, | |
34 | .device = PCI_DEVICE_ID_INTEL_82092AA_0, | |
35 | .subvendor = PCI_ANY_ID, | |
36 | .subdevice = PCI_ANY_ID, | |
37 | }, | |
38 | {} | |
39 | }; | |
40 | MODULE_DEVICE_TABLE(pci, i82092aa_pci_ids); | |
41 | ||
ba66ddfa | 42 | static struct pci_driver i82092aa_pci_driver = { |
1da177e4 LT |
43 | .name = "i82092aa", |
44 | .id_table = i82092aa_pci_ids, | |
45 | .probe = i82092aa_pci_probe, | |
46 | .remove = __devexit_p(i82092aa_pci_remove), | |
1da177e4 LT |
47 | }; |
48 | ||
49 | ||
50 | /* the pccard structure and its functions */ | |
51 | static struct pccard_operations i82092aa_operations = { | |
52 | .init = i82092aa_init, | |
53 | .get_status = i82092aa_get_status, | |
1da177e4 LT |
54 | .set_socket = i82092aa_set_socket, |
55 | .set_io_map = i82092aa_set_io_map, | |
56 | .set_mem_map = i82092aa_set_mem_map, | |
57 | }; | |
58 | ||
59 | /* The card can do upto 4 sockets, allocate a structure for each of them */ | |
60 | ||
61 | struct socket_info { | |
62 | int number; | |
63 | int card_state; /* 0 = no socket, | |
64 | 1 = empty socket, | |
65 | 2 = card but not initialized, | |
66 | 3 = operational card */ | |
906da809 | 67 | unsigned int io_base; /* base io address of the socket */ |
1da177e4 LT |
68 | |
69 | struct pcmcia_socket socket; | |
70 | struct pci_dev *dev; /* The PCI device for the socket */ | |
71 | }; | |
72 | ||
73 | #define MAX_SOCKETS 4 | |
74 | static struct socket_info sockets[MAX_SOCKETS]; | |
75 | static int socket_count; /* shortcut */ | |
76 | ||
77 | ||
78 | static int __devinit i82092aa_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) | |
79 | { | |
80 | unsigned char configbyte; | |
81 | int i, ret; | |
82 | ||
83 | enter("i82092aa_pci_probe"); | |
84 | ||
85 | if ((ret = pci_enable_device(dev))) | |
86 | return ret; | |
87 | ||
88 | pci_read_config_byte(dev, 0x40, &configbyte); /* PCI Configuration Control */ | |
89 | switch(configbyte&6) { | |
90 | case 0: | |
91 | socket_count = 2; | |
92 | break; | |
93 | case 2: | |
94 | socket_count = 1; | |
95 | break; | |
96 | case 4: | |
97 | case 6: | |
98 | socket_count = 4; | |
99 | break; | |
100 | ||
101 | default: | |
102 | printk(KERN_ERR "i82092aa: Oops, you did something we didn't think of.\n"); | |
103 | ret = -EIO; | |
104 | goto err_out_disable; | |
105 | } | |
106 | printk(KERN_INFO "i82092aa: configured as a %d socket device.\n", socket_count); | |
107 | ||
108 | if (!request_region(pci_resource_start(dev, 0), 2, "i82092aa")) { | |
109 | ret = -EBUSY; | |
110 | goto err_out_disable; | |
111 | } | |
112 | ||
113 | for (i = 0;i<socket_count;i++) { | |
114 | sockets[i].card_state = 1; /* 1 = present but empty */ | |
115 | sockets[i].io_base = pci_resource_start(dev, 0); | |
116 | sockets[i].socket.features |= SS_CAP_PCCARD; | |
117 | sockets[i].socket.map_size = 0x1000; | |
118 | sockets[i].socket.irq_mask = 0; | |
119 | sockets[i].socket.pci_irq = dev->irq; | |
7a96e87d | 120 | sockets[i].socket.cb_dev = dev; |
1da177e4 LT |
121 | sockets[i].socket.owner = THIS_MODULE; |
122 | ||
123 | sockets[i].number = i; | |
124 | ||
125 | if (card_present(i)) { | |
126 | sockets[i].card_state = 3; | |
127 | dprintk(KERN_DEBUG "i82092aa: slot %i is occupied\n",i); | |
128 | } else { | |
129 | dprintk(KERN_DEBUG "i82092aa: slot %i is vacant\n",i); | |
130 | } | |
131 | } | |
132 | ||
133 | /* Now, specifiy that all interrupts are to be done as PCI interrupts */ | |
134 | configbyte = 0xFF; /* bitmask, one bit per event, 1 = PCI interrupt, 0 = ISA interrupt */ | |
135 | pci_write_config_byte(dev, 0x50, configbyte); /* PCI Interrupt Routing Register */ | |
136 | ||
137 | /* Register the interrupt handler */ | |
138 | dprintk(KERN_DEBUG "Requesting interrupt %i \n",dev->irq); | |
dace1453 | 139 | if ((ret = request_irq(dev->irq, i82092aa_interrupt, IRQF_SHARED, "i82092aa", i82092aa_interrupt))) { |
1da177e4 LT |
140 | printk(KERN_ERR "i82092aa: Failed to register IRQ %d, aborting\n", dev->irq); |
141 | goto err_out_free_res; | |
142 | } | |
143 | ||
144 | pci_set_drvdata(dev, &sockets[i].socket); | |
145 | ||
146 | for (i = 0; i<socket_count; i++) { | |
87373318 | 147 | sockets[i].socket.dev.parent = &dev->dev; |
1da177e4 LT |
148 | sockets[i].socket.ops = &i82092aa_operations; |
149 | sockets[i].socket.resource_ops = &pccard_nonstatic_ops; | |
150 | ret = pcmcia_register_socket(&sockets[i].socket); | |
151 | if (ret) { | |
152 | goto err_out_free_sockets; | |
153 | } | |
154 | } | |
155 | ||
156 | leave("i82092aa_pci_probe"); | |
157 | return 0; | |
158 | ||
159 | err_out_free_sockets: | |
160 | if (i) { | |
161 | for (i--;i>=0;i--) { | |
162 | pcmcia_unregister_socket(&sockets[i].socket); | |
163 | } | |
164 | } | |
165 | free_irq(dev->irq, i82092aa_interrupt); | |
166 | err_out_free_res: | |
167 | release_region(pci_resource_start(dev, 0), 2); | |
168 | err_out_disable: | |
169 | pci_disable_device(dev); | |
170 | return ret; | |
171 | } | |
172 | ||
173 | static void __devexit i82092aa_pci_remove(struct pci_dev *dev) | |
174 | { | |
175 | struct pcmcia_socket *socket = pci_get_drvdata(dev); | |
176 | ||
177 | enter("i82092aa_pci_remove"); | |
178 | ||
179 | free_irq(dev->irq, i82092aa_interrupt); | |
180 | ||
181 | if (socket) | |
182 | pcmcia_unregister_socket(socket); | |
183 | ||
184 | leave("i82092aa_pci_remove"); | |
185 | } | |
186 | ||
187 | static DEFINE_SPINLOCK(port_lock); | |
188 | ||
189 | /* basic value read/write functions */ | |
190 | ||
191 | static unsigned char indirect_read(int socket, unsigned short reg) | |
192 | { | |
193 | unsigned short int port; | |
194 | unsigned char val; | |
195 | unsigned long flags; | |
196 | spin_lock_irqsave(&port_lock,flags); | |
197 | reg += socket * 0x40; | |
198 | port = sockets[socket].io_base; | |
199 | outb(reg,port); | |
200 | val = inb(port+1); | |
201 | spin_unlock_irqrestore(&port_lock,flags); | |
202 | return val; | |
203 | } | |
204 | ||
205 | #if 0 | |
206 | static unsigned short indirect_read16(int socket, unsigned short reg) | |
207 | { | |
208 | unsigned short int port; | |
209 | unsigned short tmp; | |
210 | unsigned long flags; | |
211 | spin_lock_irqsave(&port_lock,flags); | |
212 | reg = reg + socket * 0x40; | |
213 | port = sockets[socket].io_base; | |
214 | outb(reg,port); | |
215 | tmp = inb(port+1); | |
216 | reg++; | |
217 | outb(reg,port); | |
218 | tmp = tmp | (inb(port+1)<<8); | |
219 | spin_unlock_irqrestore(&port_lock,flags); | |
220 | return tmp; | |
221 | } | |
222 | #endif | |
223 | ||
224 | static void indirect_write(int socket, unsigned short reg, unsigned char value) | |
225 | { | |
226 | unsigned short int port; | |
227 | unsigned long flags; | |
228 | spin_lock_irqsave(&port_lock,flags); | |
229 | reg = reg + socket * 0x40; | |
230 | port = sockets[socket].io_base; | |
231 | outb(reg,port); | |
232 | outb(value,port+1); | |
233 | spin_unlock_irqrestore(&port_lock,flags); | |
234 | } | |
235 | ||
236 | static void indirect_setbit(int socket, unsigned short reg, unsigned char mask) | |
237 | { | |
238 | unsigned short int port; | |
239 | unsigned char val; | |
240 | unsigned long flags; | |
241 | spin_lock_irqsave(&port_lock,flags); | |
242 | reg = reg + socket * 0x40; | |
243 | port = sockets[socket].io_base; | |
244 | outb(reg,port); | |
245 | val = inb(port+1); | |
246 | val |= mask; | |
247 | outb(reg,port); | |
248 | outb(val,port+1); | |
249 | spin_unlock_irqrestore(&port_lock,flags); | |
250 | } | |
251 | ||
252 | ||
253 | static void indirect_resetbit(int socket, unsigned short reg, unsigned char mask) | |
254 | { | |
255 | unsigned short int port; | |
256 | unsigned char val; | |
257 | unsigned long flags; | |
258 | spin_lock_irqsave(&port_lock,flags); | |
259 | reg = reg + socket * 0x40; | |
260 | port = sockets[socket].io_base; | |
261 | outb(reg,port); | |
262 | val = inb(port+1); | |
263 | val &= ~mask; | |
264 | outb(reg,port); | |
265 | outb(val,port+1); | |
266 | spin_unlock_irqrestore(&port_lock,flags); | |
267 | } | |
268 | ||
269 | static void indirect_write16(int socket, unsigned short reg, unsigned short value) | |
270 | { | |
271 | unsigned short int port; | |
272 | unsigned char val; | |
273 | unsigned long flags; | |
274 | spin_lock_irqsave(&port_lock,flags); | |
275 | reg = reg + socket * 0x40; | |
276 | port = sockets[socket].io_base; | |
277 | ||
278 | outb(reg,port); | |
279 | val = value & 255; | |
280 | outb(val,port+1); | |
281 | ||
282 | reg++; | |
283 | ||
284 | outb(reg,port); | |
285 | val = value>>8; | |
286 | outb(val,port+1); | |
287 | spin_unlock_irqrestore(&port_lock,flags); | |
288 | } | |
289 | ||
290 | /* simple helper functions */ | |
291 | /* External clock time, in nanoseconds. 120 ns = 8.33 MHz */ | |
292 | static int cycle_time = 120; | |
293 | ||
294 | static int to_cycles(int ns) | |
295 | { | |
296 | if (cycle_time!=0) | |
297 | return ns/cycle_time; | |
298 | else | |
299 | return 0; | |
300 | } | |
301 | ||
302 | ||
303 | /* Interrupt handler functionality */ | |
304 | ||
7d12e780 | 305 | static irqreturn_t i82092aa_interrupt(int irq, void *dev) |
1da177e4 LT |
306 | { |
307 | int i; | |
308 | int loopcount = 0; | |
309 | int handled = 0; | |
310 | ||
311 | unsigned int events, active=0; | |
312 | ||
313 | /* enter("i82092aa_interrupt");*/ | |
314 | ||
315 | while (1) { | |
316 | loopcount++; | |
317 | if (loopcount>20) { | |
318 | printk(KERN_ERR "i82092aa: infinite eventloop in interrupt \n"); | |
319 | break; | |
320 | } | |
321 | ||
322 | active = 0; | |
323 | ||
324 | for (i=0;i<socket_count;i++) { | |
325 | int csc; | |
326 | if (sockets[i].card_state==0) /* Inactive socket, should not happen */ | |
327 | continue; | |
328 | ||
329 | csc = indirect_read(i,I365_CSC); /* card status change register */ | |
330 | ||
331 | if (csc==0) /* no events on this socket */ | |
332 | continue; | |
333 | handled = 1; | |
334 | events = 0; | |
335 | ||
336 | if (csc & I365_CSC_DETECT) { | |
337 | events |= SS_DETECT; | |
338 | printk("Card detected in socket %i!\n",i); | |
339 | } | |
340 | ||
341 | if (indirect_read(i,I365_INTCTL) & I365_PC_IOCARD) { | |
342 | /* For IO/CARDS, bit 0 means "read the card" */ | |
343 | events |= (csc & I365_CSC_STSCHG) ? SS_STSCHG : 0; | |
344 | } else { | |
345 | /* Check for battery/ready events */ | |
346 | events |= (csc & I365_CSC_BVD1) ? SS_BATDEAD : 0; | |
347 | events |= (csc & I365_CSC_BVD2) ? SS_BATWARN : 0; | |
348 | events |= (csc & I365_CSC_READY) ? SS_READY : 0; | |
349 | } | |
350 | ||
351 | if (events) { | |
352 | pcmcia_parse_events(&sockets[i].socket, events); | |
353 | } | |
354 | active |= events; | |
355 | } | |
356 | ||
357 | if (active==0) /* no more events to handle */ | |
358 | break; | |
359 | ||
360 | } | |
361 | return IRQ_RETVAL(handled); | |
362 | /* leave("i82092aa_interrupt");*/ | |
363 | } | |
364 | ||
365 | ||
366 | ||
367 | /* socket functions */ | |
368 | ||
369 | static int card_present(int socketno) | |
370 | { | |
371 | unsigned int val; | |
372 | enter("card_present"); | |
373 | ||
374 | if ((socketno<0) || (socketno >= MAX_SOCKETS)) | |
375 | return 0; | |
376 | if (sockets[socketno].io_base == 0) | |
377 | return 0; | |
378 | ||
379 | ||
380 | val = indirect_read(socketno, 1); /* Interface status register */ | |
381 | if ((val&12)==12) { | |
382 | leave("card_present 1"); | |
383 | return 1; | |
384 | } | |
385 | ||
386 | leave("card_present 0"); | |
387 | return 0; | |
388 | } | |
389 | ||
390 | static void set_bridge_state(int sock) | |
391 | { | |
392 | enter("set_bridge_state"); | |
393 | indirect_write(sock, I365_GBLCTL,0x00); | |
394 | indirect_write(sock, I365_GENCTL,0x00); | |
395 | ||
396 | indirect_setbit(sock, I365_INTCTL,0x08); | |
397 | leave("set_bridge_state"); | |
398 | } | |
399 | ||
400 | ||
401 | ||
402 | ||
403 | ||
404 | ||
405 | static int i82092aa_init(struct pcmcia_socket *sock) | |
406 | { | |
407 | int i; | |
408 | struct resource res = { .start = 0, .end = 0x0fff }; | |
409 | pccard_io_map io = { 0, 0, 0, 0, 1 }; | |
410 | pccard_mem_map mem = { .res = &res, }; | |
411 | ||
412 | enter("i82092aa_init"); | |
413 | ||
414 | for (i = 0; i < 2; i++) { | |
415 | io.map = i; | |
416 | i82092aa_set_io_map(sock, &io); | |
417 | } | |
418 | for (i = 0; i < 5; i++) { | |
419 | mem.map = i; | |
420 | i82092aa_set_mem_map(sock, &mem); | |
421 | } | |
422 | ||
423 | leave("i82092aa_init"); | |
424 | return 0; | |
425 | } | |
426 | ||
427 | static int i82092aa_get_status(struct pcmcia_socket *socket, u_int *value) | |
428 | { | |
429 | unsigned int sock = container_of(socket, struct socket_info, socket)->number; | |
430 | unsigned int status; | |
431 | ||
432 | enter("i82092aa_get_status"); | |
433 | ||
434 | status = indirect_read(sock,I365_STATUS); /* Interface Status Register */ | |
435 | *value = 0; | |
436 | ||
437 | if ((status & I365_CS_DETECT) == I365_CS_DETECT) { | |
438 | *value |= SS_DETECT; | |
439 | } | |
440 | ||
441 | /* IO cards have a different meaning of bits 0,1 */ | |
442 | /* Also notice the inverse-logic on the bits */ | |
443 | if (indirect_read(sock, I365_INTCTL) & I365_PC_IOCARD) { | |
444 | /* IO card */ | |
445 | if (!(status & I365_CS_STSCHG)) | |
446 | *value |= SS_STSCHG; | |
447 | } else { /* non I/O card */ | |
448 | if (!(status & I365_CS_BVD1)) | |
449 | *value |= SS_BATDEAD; | |
450 | if (!(status & I365_CS_BVD2)) | |
451 | *value |= SS_BATWARN; | |
452 | ||
453 | } | |
454 | ||
455 | if (status & I365_CS_WRPROT) | |
456 | (*value) |= SS_WRPROT; /* card is write protected */ | |
457 | ||
458 | if (status & I365_CS_READY) | |
459 | (*value) |= SS_READY; /* card is not busy */ | |
460 | ||
461 | if (status & I365_CS_POWERON) | |
462 | (*value) |= SS_POWERON; /* power is applied to the card */ | |
463 | ||
464 | ||
465 | leave("i82092aa_get_status"); | |
466 | return 0; | |
467 | } | |
468 | ||
469 | ||
1da177e4 LT |
470 | static int i82092aa_set_socket(struct pcmcia_socket *socket, socket_state_t *state) |
471 | { | |
472 | unsigned int sock = container_of(socket, struct socket_info, socket)->number; | |
473 | unsigned char reg; | |
474 | ||
475 | enter("i82092aa_set_socket"); | |
476 | ||
477 | /* First, set the global controller options */ | |
478 | ||
479 | set_bridge_state(sock); | |
480 | ||
481 | /* Values for the IGENC register */ | |
482 | ||
483 | reg = 0; | |
484 | if (!(state->flags & SS_RESET)) /* The reset bit has "inverse" logic */ | |
485 | reg = reg | I365_PC_RESET; | |
486 | if (state->flags & SS_IOCARD) | |
487 | reg = reg | I365_PC_IOCARD; | |
488 | ||
489 | indirect_write(sock,I365_INTCTL,reg); /* IGENC, Interrupt and General Control Register */ | |
490 | ||
491 | /* Power registers */ | |
492 | ||
493 | reg = I365_PWR_NORESET; /* default: disable resetdrv on resume */ | |
494 | ||
495 | if (state->flags & SS_PWR_AUTO) { | |
496 | printk("Auto power\n"); | |
497 | reg |= I365_PWR_AUTO; /* automatic power mngmnt */ | |
498 | } | |
499 | if (state->flags & SS_OUTPUT_ENA) { | |
500 | printk("Power Enabled \n"); | |
501 | reg |= I365_PWR_OUT; /* enable power */ | |
502 | } | |
503 | ||
504 | switch (state->Vcc) { | |
505 | case 0: | |
506 | break; | |
507 | case 50: | |
508 | printk("setting voltage to Vcc to 5V on socket %i\n",sock); | |
509 | reg |= I365_VCC_5V; | |
510 | break; | |
511 | default: | |
512 | printk("i82092aa: i82092aa_set_socket called with invalid VCC power value: %i ", state->Vcc); | |
513 | leave("i82092aa_set_socket"); | |
514 | return -EINVAL; | |
515 | } | |
516 | ||
517 | ||
518 | switch (state->Vpp) { | |
519 | case 0: | |
520 | printk("not setting Vpp on socket %i\n",sock); | |
521 | break; | |
522 | case 50: | |
523 | printk("setting Vpp to 5.0 for socket %i\n",sock); | |
524 | reg |= I365_VPP1_5V | I365_VPP2_5V; | |
525 | break; | |
526 | case 120: | |
527 | printk("setting Vpp to 12.0\n"); | |
528 | reg |= I365_VPP1_12V | I365_VPP2_12V; | |
529 | break; | |
530 | default: | |
531 | printk("i82092aa: i82092aa_set_socket called with invalid VPP power value: %i ", state->Vcc); | |
532 | leave("i82092aa_set_socket"); | |
533 | return -EINVAL; | |
534 | } | |
535 | ||
536 | if (reg != indirect_read(sock,I365_POWER)) /* only write if changed */ | |
537 | indirect_write(sock,I365_POWER,reg); | |
538 | ||
539 | /* Enable specific interrupt events */ | |
540 | ||
541 | reg = 0x00; | |
542 | if (state->csc_mask & SS_DETECT) { | |
543 | reg |= I365_CSC_DETECT; | |
544 | } | |
545 | if (state->flags & SS_IOCARD) { | |
546 | if (state->csc_mask & SS_STSCHG) | |
547 | reg |= I365_CSC_STSCHG; | |
548 | } else { | |
549 | if (state->csc_mask & SS_BATDEAD) | |
550 | reg |= I365_CSC_BVD1; | |
551 | if (state->csc_mask & SS_BATWARN) | |
552 | reg |= I365_CSC_BVD2; | |
553 | if (state->csc_mask & SS_READY) | |
554 | reg |= I365_CSC_READY; | |
555 | ||
556 | } | |
557 | ||
558 | /* now write the value and clear the (probably bogus) pending stuff by doing a dummy read*/ | |
559 | ||
560 | indirect_write(sock,I365_CSCINT,reg); | |
561 | (void)indirect_read(sock,I365_CSC); | |
562 | ||
563 | leave("i82092aa_set_socket"); | |
564 | return 0; | |
565 | } | |
566 | ||
567 | static int i82092aa_set_io_map(struct pcmcia_socket *socket, struct pccard_io_map *io) | |
568 | { | |
569 | unsigned int sock = container_of(socket, struct socket_info, socket)->number; | |
570 | unsigned char map, ioctl; | |
571 | ||
572 | enter("i82092aa_set_io_map"); | |
573 | ||
574 | map = io->map; | |
575 | ||
576 | /* Check error conditions */ | |
577 | if (map > 1) { | |
578 | leave("i82092aa_set_io_map with invalid map"); | |
579 | return -EINVAL; | |
580 | } | |
581 | if ((io->start > 0xffff) || (io->stop > 0xffff) || (io->stop < io->start)){ | |
582 | leave("i82092aa_set_io_map with invalid io"); | |
583 | return -EINVAL; | |
584 | } | |
585 | ||
586 | /* Turn off the window before changing anything */ | |
587 | if (indirect_read(sock, I365_ADDRWIN) & I365_ENA_IO(map)) | |
588 | indirect_resetbit(sock, I365_ADDRWIN, I365_ENA_IO(map)); | |
589 | ||
590 | /* printk("set_io_map: Setting range to %x - %x \n",io->start,io->stop); */ | |
591 | ||
592 | /* write the new values */ | |
593 | indirect_write16(sock,I365_IO(map)+I365_W_START,io->start); | |
594 | indirect_write16(sock,I365_IO(map)+I365_W_STOP,io->stop); | |
595 | ||
596 | ioctl = indirect_read(sock,I365_IOCTL) & ~I365_IOCTL_MASK(map); | |
597 | ||
598 | if (io->flags & (MAP_16BIT|MAP_AUTOSZ)) | |
599 | ioctl |= I365_IOCTL_16BIT(map); | |
600 | ||
601 | indirect_write(sock,I365_IOCTL,ioctl); | |
602 | ||
603 | /* Turn the window back on if needed */ | |
604 | if (io->flags & MAP_ACTIVE) | |
605 | indirect_setbit(sock,I365_ADDRWIN,I365_ENA_IO(map)); | |
606 | ||
607 | leave("i82092aa_set_io_map"); | |
608 | return 0; | |
609 | } | |
610 | ||
611 | static int i82092aa_set_mem_map(struct pcmcia_socket *socket, struct pccard_mem_map *mem) | |
612 | { | |
613 | struct socket_info *sock_info = container_of(socket, struct socket_info, socket); | |
614 | unsigned int sock = sock_info->number; | |
615 | struct pci_bus_region region; | |
616 | unsigned short base, i; | |
617 | unsigned char map; | |
618 | ||
619 | enter("i82092aa_set_mem_map"); | |
620 | ||
621 | pcibios_resource_to_bus(sock_info->dev, ®ion, mem->res); | |
622 | ||
623 | map = mem->map; | |
624 | if (map > 4) { | |
625 | leave("i82092aa_set_mem_map: invalid map"); | |
626 | return -EINVAL; | |
627 | } | |
628 | ||
629 | ||
630 | if ( (mem->card_start > 0x3ffffff) || (region.start > region.end) || | |
631 | (mem->speed > 1000) ) { | |
632 | leave("i82092aa_set_mem_map: invalid address / speed"); | |
f96ee7a4 AM |
633 | printk("invalid mem map for socket %i: %llx to %llx with a " |
634 | "start of %x\n", | |
635 | sock, | |
636 | (unsigned long long)region.start, | |
637 | (unsigned long long)region.end, | |
638 | mem->card_start); | |
1da177e4 LT |
639 | return -EINVAL; |
640 | } | |
641 | ||
642 | /* Turn off the window before changing anything */ | |
643 | if (indirect_read(sock, I365_ADDRWIN) & I365_ENA_MEM(map)) | |
644 | indirect_resetbit(sock, I365_ADDRWIN, I365_ENA_MEM(map)); | |
645 | ||
646 | ||
647 | /* printk("set_mem_map: Setting map %i range to %x - %x on socket %i, speed is %i, active = %i \n",map, region.start,region.end,sock,mem->speed,mem->flags & MAP_ACTIVE); */ | |
648 | ||
649 | /* write the start address */ | |
650 | base = I365_MEM(map); | |
651 | i = (region.start >> 12) & 0x0fff; | |
652 | if (mem->flags & MAP_16BIT) | |
653 | i |= I365_MEM_16BIT; | |
654 | if (mem->flags & MAP_0WS) | |
655 | i |= I365_MEM_0WS; | |
656 | indirect_write16(sock,base+I365_W_START,i); | |
657 | ||
658 | /* write the stop address */ | |
659 | ||
660 | i= (region.end >> 12) & 0x0fff; | |
661 | switch (to_cycles(mem->speed)) { | |
662 | case 0: | |
663 | break; | |
664 | case 1: | |
665 | i |= I365_MEM_WS0; | |
666 | break; | |
667 | case 2: | |
668 | i |= I365_MEM_WS1; | |
669 | break; | |
670 | default: | |
671 | i |= I365_MEM_WS1 | I365_MEM_WS0; | |
672 | break; | |
673 | } | |
674 | ||
675 | indirect_write16(sock,base+I365_W_STOP,i); | |
676 | ||
677 | /* card start */ | |
678 | ||
679 | i = ((mem->card_start - region.start) >> 12) & 0x3fff; | |
680 | if (mem->flags & MAP_WRPROT) | |
681 | i |= I365_MEM_WRPROT; | |
682 | if (mem->flags & MAP_ATTRIB) { | |
683 | /* printk("requesting attribute memory for socket %i\n",sock);*/ | |
684 | i |= I365_MEM_REG; | |
685 | } else { | |
686 | /* printk("requesting normal memory for socket %i\n",sock);*/ | |
687 | } | |
688 | indirect_write16(sock,base+I365_W_OFF,i); | |
689 | ||
690 | /* Enable the window if necessary */ | |
691 | if (mem->flags & MAP_ACTIVE) | |
692 | indirect_setbit(sock, I365_ADDRWIN, I365_ENA_MEM(map)); | |
693 | ||
694 | leave("i82092aa_set_mem_map"); | |
695 | return 0; | |
696 | } | |
697 | ||
698 | static int i82092aa_module_init(void) | |
699 | { | |
ba66ddfa | 700 | return pci_register_driver(&i82092aa_pci_driver); |
1da177e4 LT |
701 | } |
702 | ||
703 | static void i82092aa_module_exit(void) | |
704 | { | |
705 | enter("i82092aa_module_exit"); | |
ba66ddfa | 706 | pci_unregister_driver(&i82092aa_pci_driver); |
1da177e4 LT |
707 | if (sockets[0].io_base>0) |
708 | release_region(sockets[0].io_base, 2); | |
709 | leave("i82092aa_module_exit"); | |
710 | } | |
711 | ||
712 | module_init(i82092aa_module_init); | |
713 | module_exit(i82092aa_module_exit); | |
714 |